WO2018125249A1

WO2018125249A1 - Systems, methods, and apparatuses for implementing opc model enhancement for ntd processes by including polymer compaction of photoresists

Info

Publication number: WO2018125249A1
Application number: PCT/US2016/069639
Authority: WO
Inventors: Ramon CALDERER; Gemma COMELLAS; Robert M. Bigwood; Harsha GRUNES; Seongtae Jeong; Seungmin HONG; Hyungjin MA
Original assignee: Intel Corporation
Priority date: 2016-12-31
Filing date: 2016-12-31
Publication date: 2018-07-05

Abstract

In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing Optical Proximity Correction (OPC) model enhancement for Negative Tone Development (NTD) processes by including polymer compaction of photoresists. For instance, there is in accordance with one embodiment means for reducing Optical Proximity Correction (OPC) model error, by fabricating a physical silicon wafer from a photolithographic mask via a Negative Tone Development (NTD) photolithography processes, the physical silicon wafer having a plurality of features embodied therein as defined by the photolithographic mask; capturing measurements of the features embodied within the physical silicon wafer from Scanning Electron Microscope (SEM) images of the physical silicon wafer; creating an OPC model of the photolithographic mask using physical parameters of the NTD photolithography process, the OPC model specifying contours of the plurality of features of the mask; calibrating the OPC model based on the measurements of the features of the physical silicon wafer captured from the SEM images by solving for an equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in a photoresist of the physical silicon wafer in a two-dimensional (2D) plane; and applying OPC model corrections to the photolithographic mask based on the calibrating of the OPC model. Other related embodiments are disclosed.

Description

SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING OPC MODEL ENHANCEMENT FOR NTD PROCESSES BY INCLUDING POLYMER COMPACTION OF PHOTORESISTS

CLAIM OF PRIORITY

None.

COPYRIGHT NOTICE

A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.

TECHNICAL FIELD

The subject matter described herein relates generally to the field of semiconductor and electronics manufacturing, and more particularly, to systems, methods, and apparatuses for implementing Optical Proximity Correction (OPC) model enhancement for Negative Tone Development (NTD) processes by including polymer compaction of photoresists.

BACKGROUND

The subject matter discussed in the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches, which in and of themselves may also correspond to embodiments of the claimed subject matter.

Conventional techniques utilizing Optical Proximity Correction (OPC) models are not sufficiently accurate as semiconductor manufacturing techniques necessitate increasingly strict tolerances and smaller physical dimensions.

For advanced process nodes in semiconductor manufacturing, one of the major challenges is to control defects and yield to a level that is viable for high volume manufacturing (HVM). To maintain the density scaling and reduce cell footprint, process margins are tightening which in turn causes systematic and random process variations resulting in the processes being more prone to defects. One such source of process variation is the result of insufficiently accurate model prediction of lithographic and post-lithographic processes including NTD processes, each of which affect optical proximity correction (OPC) of mask design.

The accuracy of these measurements and the accuracy of the model is of utmost importance because any variation of the OPC model translates to a variation of dimensions on the final semiconductor chips produced.

When the physical dimensions of the manufactured semiconductors were greater, such inaccuracies and uncertainty were manageable due to the greater margins. However, as the physical size of these manufactured semiconductors is reduced further into the nanometer realm of manufacturing, it becomes necessary to operate using increasingly accurate models if manufacturing yields are to remain economically viable.

The present state of the art may therefore benefit from the systems, methods, and apparatuses for implementing Optical Proximity Correction (OPC) model enhancement for Negative Tone Development (NTD) processes by including polymer compaction of photoresists as described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are illustrated by way of example, and not by way of limitation, and will be more fully understood with reference to the following detailed description when considered in connection with the figures in which:

Figure 1 depicts an exemplary process flow in accordance with described embodiments;

Figure 2A depicts a results comparison of OPC model contours before and after elastic deformation on the left and OPC model contours overlaid upon a CD-SEM image on the right in accordance with described embodiments;

Figure 2B depicts an OPC corrected and uncorrected pattern comparison for an OPC model in accordance with described embodiments;

Figure 3 depicts a shrinkage comparison of FEM2D vs FEM3D modeling in accordance with described embodiments;

Figure 4 is a flow diagram illustrating a method for implementing Optical Proximity Correction (OPC) model enhancement for Negative Tone Development (NTD) processes by including polymer compaction of photoresists in accordance with described embodiments;

Figure 5 is a schematic of a computer system in accordance with described embodiments;

Figure 6 illustrates a semiconductor device (or an interposer) that includes one or more described embodiments; and Figure 7 illustrates a computing device in accordance with one implementation of the invention.

DETAILED DESCRIPTION

Described herein are systems, methods, and apparatuses for implementing Optical

Proximity Correction (OPC) model enhancement for Negative Tone Development (NTD) processes by including polymer compaction of photoresists. For instance, there is in accordance with one embodiment means for reducing Optical Proximity Correction (OPC) model error, by fabricating a physical silicon wafer from a photolithographic mask via a Negative Tone

Development (NTD) photolithography processes, the physical silicon wafer having a plurality of features embodied therein as defined by the photolithographic mask; capturing measurements of the features embodied within the physical silicon wafer from Scanning Electron Microscope (SEM) images of the physical silicon wafer; creating an OPC model of the photolithographic mask using physical parameters of the NTD photolithography process, the OPC model specifying contours of the plurality of features of the mask; calibrating the OPC model based on the measurements of the features of the physical silicon wafer captured from the SEM images by solving for an equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in a photoresist of the physical silicon wafer in a two-dimensional (2D) plane; and applying OPC model corrections to the photolithographic mask based on the calibrating of the OPC model.

Optical Proximity Correction (OPC) models require accurate mask layout dimensions as input parameters. The greater the accuracy, the more useful and accurate the resulting model will be for the semiconductor manufacturing processes. OPC modeling provides a predictive model for lithographic and post-lithographic processes including NTD processes. Such models are then relied upon for applying corrections to the masks so as to ensure correct pattern fidelity and correct dimensions of features on the manufactured silicon wafers.

The methodologies described herein provide improvements to OPC model accuracy which may then be applied to a variety of lithographic and post lithographic processes including NTD processes.

As circuit feature sizes shrink to enable continued Moore's Law scaling, the accuracy requirements for the placement and size of individual wafer features continue to tighten. A critical determiner of this wafer feature scaling is lithography fidelity, which is a direct result of proper feature sizing on the product photomasks. The size of mask features is directly

determined by the OPC (Optical Proximity Correction) as determined by the OPC lithography model. As the Edge Placement Error (EPE) requirements tighten for next generation node manufacturing, such as 10-nanometer (nm) node and beyond, significant improvements are required in OPC modeling capability to enable both efficient process development cycles, and ultimately to enable correct feature sizes on product wafers to so as to attain proper circuit function.

Through the process of lithographic and post-lithographic patterning, it has been observed that a significant portion of Critical Dimension (CD) variations are systematically correlated with surrounding geometric information. Due to the lack of an efficient and accurate way of capturing and utilizing two-dimensional geometric information, mask corrections using previously known techniques are insufficient for next generation wafer fabrication.

Optical Proximity Correction (OPC) models require highly accurate model predictions to properly correct critical features. Such OPC models are usually obtained by fitting experimental critical dimensions (CDs) measured in CD Scanning Electron Microscope (SEM) images after development.

In the case of Negative Tone Development (NTD) processes, the exposed photoresist areas are retained after development, leading to additional challenges in the modeling accuracy due to polymer compaction of the photoresist material.

According to described embodiments, a linear elastic mechanical deformation model is therefore applied to compensate for polymer compaction in the input critical dimensions for NTD processes prior to calibrating an OPC model.

The methodologies illustrated here as well as the systems and apparatuses which implement or embody such methodologies are utilized to further enhance OPC Model prediction beyond currently known techniques. According to described embodiments, such OPC models begin with a semi-physical lithography model as well as linear elastic mechanical representations that mimic physical and chemical process steps such as photoresist shrinkage due to polymer compaction which are then provided as inputs into for use with Optical Proximity Correction

(OPC) techniques so as to satisfy lithographic and post-lithographic stage requirements in terms of predictive accuracy.

The techniques described herein are demonstrated to produce more accurate lithographic and post-lithographic models than conventional OPC models with an acceptable increase in computational cost and are therefore economically viable for manufacturing.

The existing modeling software for OPC is deficient in terms of accuracy for new lithographic systems and next generation fabrication post lithographic processes which require significantly tighter margins and dimensions. Conventional modeling software for OPC therefore results in unworkable errors inhibiting the newer technologies from being successfully scaled to high volume manufacturing. Conventional OPC models simply cannot predict with sufficient accuracy and precision to the smaller feature size and feature geometries associated new technologies.

Improvements to the existing OPC models are needed such that the OPC models which drive manufacturing may be successfully utilized to attain sufficiently accurate pattern fidelity on the mask and on the manufactured silicon wafers.

Use of the conventional models has been demonstrated to result in unacceptable yields from the silicon wafer fabrication process due to the degree of uncertainty of such models, resulting in the features actually printed failing within the layers due to the size of the features as printed which is a direct result of the inaccurate models. The position and size of the features of the mask are critical to the functioning of the circuit produced and on the scale of nanometers the margin for error becomes incredibly small, thus necessitating model outputs with a greater degree of precision. Printing deviances of tens of nanometers in the process which are not accounted for in the design will render an entire silicon wafer inoperable. Such a circuit simply will not work and will not function like a processor because such deviations cause joins and shorts which are not part of the circuit design.

The conventional OPC models need further adjustment and correction and improved contour correction or shifting means so as to move these printed features into the correct position with a greater degree of precision. Such improvements ensure functionally operable silicon and thus improve manufacturing yields and profitability for any given product.

In the following description, numerous specific details are set forth such as examples of specific systems, languages, components, etc., in order to provide a thorough understanding of the various embodiments. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the embodiments disclosed herein. In other instances, well known materials or methods have not been described in detail in order to avoid

unnecessarily obscuring the disclosed embodiments.

In addition to various hardware components depicted in the figures and described herein, embodiments further include various operations which are described below. The operations described in accordance with such embodiments may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general- purpose or special -purpose processor programmed with the instructions to perform the operations. Alternatively, the operations may be performed by a combination of hardware and software.

Any of the disclosed embodiments may be used alone or together with one another in any combination. Although various embodiments may have been partially motivated by deficiencies with conventional techniques and approaches, some of which are described or alluded to within the specification, the embodiments need not necessarily address or solve any of these deficiencies, but rather, may address only some of the deficiencies, address none of the deficiencies, or be directed toward different deficiencies and problems which are not directly discussed.

Implementations of embodiments of the invention may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present invention.

A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors

(MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the invention, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the invention may also be carried out using nonplanar transistors.

Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used. The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

In some implementations, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some implementations of the invention, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

Figure 1 depicts an exemplary process flow 100 in accordance with described

embodiments.

In particular, on the left there is depicted a process of retrieving a target wafer pattern 105 for a physical silicon wafer to be fabricated, followed by application of an OPC corrected layout 110, for instance, to an OPC model or a semi -physical model representing the target wafer pattern. Processing then continues to mask manufacturing 115 which is finely aligned via an OPC corrected reticle subsequent to which actual fabrication processes such as application of the lithography process and etch processing 125 in which an imager or other light source exposes the mask as corrected according to the OPC model adjustments followed by a chemical etch or other post lithographic processes which then result in the final pattern 130 in the physical silicon wafer.

On the right there is further depicted the various OPC corrections 135 which are introduced into the process flow 100 on the left in between operations 105 with the selection of the target wafer pattern and application of the OPC corrected layout 110 in which the OPC corrections 135 will be utilized.

Specifically, within the OPC correction 135 sub-process flow there is depicted starting from the far right an in sample CD-SEM (Critical Dimension (CD) Scanning Electron Microscope (SEM)) measurements 140 which are then provided to block 145 where calibration of the OPC model with 2D FEM (Finite Element Method) is applied and subjected to multiple iterations of out of sample model validation with additional CD-SEM measurements from block 146 until the calibration phase at block 145 is complete.

Lastly, at block 150, OPC model correction is applied using the calibrated OPC model with

2D FEM from block 145 resulting in an OPC correction 135 ready for use with the OPC corrected layout at block 110.

According to described embodiments, converting from a 3D solution to a 2D solution includes the introduction of a linear spring term to allow for the assumption that a top surface of the resist behaves independently of anything below the top surface. However, because in reality there are stresses below the top surface of the resist, the linear spring term uniformly distributes those sub-surface stresses across the 2D planar surface of the resist, thus permitting the reduction from 3D space to 2D space while incorporating those sub-surface stresses.

In such a way, the linear spring term (or hook and spring) provides a sufficiently accurate mathematical approximation or a simulation of the stresses below the top surface of the resist when solving for only the top 2D planar surface of the resist in 2D space rather than fully solving for the polymer compaction problem in 3D space.

According to described embodiments, the calibration of the OPC model with 2D FEM 145 solves for the simplified 2D equations and outputs the predicted deformation of the resist subsequent to the lithographic processes and the output predicted deformation is then utilized for the OPC correction of the OPC model with the 2D FEM 150 solution.

The OPC model provides a forward function which connects what is on the mask to what is on the wafer. Software algorithms provide a basic physics solution to this problem, but the solution requires many approximations which thus operate as a source of inaccuracies. Described embodiments therefore reformulate the problem in such a way that a in-sample CD-SEM measurements 140 and out of sample model validation with CD-SEM measurements 146 may be utilized to calibrate the OPC model using 2D FEM processes as depicted at block 145.

Through such validation and calibration base on the CD-SEM measurement inputs, the OPC model derives an OPC correction to account for necessary adaptations to conform the base OPC model predictions to known physical models as represented by both the in sample and out of sample CD-SEM measurements. These adaptations are output as OPC corrections 135 so as to provide both the OPC corrected layout 110 and the OPC corrected reticle 120 of a target wafer pattern 105 prior to actual lithographic exposure and chemical etch processing 125 of the actual physical silicon wafer undergoing the process of manufacture and fabrication.

Because the OPC model, the structures, the features, and the mask is so complex it simply is not practical to manually determine what function or adaptations to the incoming base OPC model are necessary to conform that model to the reality as observed in the CD-SEM imagery measurements taken from fabricated silicon wafers fabricated utilizing the (uncorrected) base OPC model. Application of the calibration technique for the OPC model using 2D FEM processes therefore provides a significant advantage to overcome such complexities such that the OPC corrections 135 may be applied to account for the required adaptations.

A so called finite element method (FEM) provides a numerical technique for finding approximate solutions to boundary value problems for partial differential equations by subdividing a larger problem into smaller, simpler parts referred to as the finite elements. Simple equations which model the finite elements are then assembled into a larger system of equations that models the entire problem.

In accordance with certain embodiments, application of the calibration of the OPC model utilizing the 2D FEM processes provides a deterministic model error or process driven changes to the critical dimensions (CDs) for the size and position of features represented within the OPC model and as embodied within the physical silicon wafer fabricated using an uncorrected mask based on the target wafer pattern.

Over the past decade there have been significant improvements to the processes utilized for lithography patterning which in turn enable significantly greater fidelity and detailed patterning of silicon wafers. However, with such improvements, the more detailed patterning on the wafers become more susceptible to model error, with a significant contributor to such error being attributable to changes in the resists during lithographic and post lithographic processes which are not fully accounted for within current OPC modeling strategies.

For instance, with Negative Tone Development (NTD) processes in which resist portions are retained after the development of the resist, there is an extra challenge for current OPC modeling strategies versus conventional positive tone exposure and development processes in which exposed regions of the resist are then etched away rather than retained.

A key challenge with Negative Tone Development (NTD) lithographic processes is that the retained portions of the resist will subsequently be affected by polymer compaction during post lithographic processes such as Post Exposure Bake (PEB) and current OPC modeling strategies simply fail to account for these physical changes to the size, contour, and dimensions of the features and geometries within the resist. Stated differently, the physical realities of the resist subsequent to lithographic and post lithographic processes do not match the predicted results by the OPC models, thus necessitating a calibration and correction phase as described herein so as to realign the OPC model output with the physical changes and actually observed within the fabricated silicon wafers. Ordinarily, solving for the polymer compaction problem would be performed in three- dimensional (3D) space which is the most accurate and precise method by which to solve the problem. Unfortunately, solving for the polymer compaction in 3D space is also the most computationally burdensome process which translates into the longest time to completion, rendering such an approach undesirable for full chip modeling in a production environment.

Described embodiments therefore convert the 3D problem into a two-dimensional (2D) problem such that the polymer compaction problem may be solved in 2D space by reducing the complexity of the problem on the basis of several assumptions which are described in greater detail below. These assumptions have been evaluated experimentally by solving the same polymer compaction problems in both 3D and 2D space for the sake of comparison and the results, though not identical, exhibit very good agreement, sufficient for use in calibrating and correcting the OPC model output for use with lithographic processes 125 for a final pattern 130 in the wafer which is sufficiently accurate and precise to meet manufacturing yield targets.

Converting the 3D problem into a 3D problem additionally reduces costs due to the reduction in computational resources needed to solve the equations within an acceptable period of time. Such equations may be referred to as elastic compaction problems, elastic deformation equations, or equilibrium problems. According to certain embodiments, turn-key equilibrium problem solvers may be utilized in which the OPC model simply provides inputs to the turn-key equilibrium problem solver and then accepts outputs for use with OPC model calibration and OPC model layout corrections.

According to certain embodiments, reduction of the complexity of the 3D problem is achieved by assuming that the exposed resist exceeds a threshold height such that changes near the top surface are non-dependent upon the length of the resist. In such a way, it is possible to assume the resist is a 2D plane and solve for only surface changes on a 2D plane within a 2D space without concern for sub-surface behaviors which reside within the 3D space.

With regard to the use of a turn-key equilibrium problem solver, because the actual changes in the resist occur very slowly, it is in accordance with certain embodiments that transient and temporal terms are ignored, effectively treating the equilibrium problem as a static equitation, which also greatly simplifies the equations and therefore reduces the computational burden.

Still further, additional embodiments simplify the equilibrium problem by assuming that the resist material exhibits strictly linear properties and therefore, Hooke's law may be followed by enforcing a constraint on the equations that any stresses are proportional to their

corresponding change in deformation.

In accordance with other embodiments, the equilibrium problem is further simplified by assuming that the resist material is an isotropic material and therefore exhibits identical values in all directions, thus negating the need to solve for changes to the resist in 3D space and solving only for changes to the resist in the 2D plane.

Figure 2A depicts a results comparison 200 of OPC model contours before and after elastic deformation on the left and OPC model contours overlaid upon a CD-SEM image on the right.

More particularly, it may be observed within the OPC model contours on the left at element 205 that there are two contours depicted, represented by thin black lines 215 and thick black lines 220. The grid pattern on the left represents the OPC uncorrected pattern 250 upon which the OPC model contour lines 215 and 220 are overlaid. The OPC uncorrected pattern 250 depicts the selected OPC target pattern before calibration or adjustment.

The innermost thick black line 220 represents the OPC model contours prior to elastic deformation whereas the thin black line 215 represents the OPC model contours after elastic deformation.

Further depicted on the right is a CD-SEM image 210 having contours from the OPC model overlaid thereupon. The white dot pattern represents the CD-SEM contours as measured whereas the hashing area in the middle depicts a 4X Edge Placement Error (EPE) between the top and bottom features of the CD-SEM image.

It has been observed that polymer deformation in NTD resists are correlated to elastic mechanical deformation and therefore predictions may be rendered to estimate total resist height compaction in ID features. According to described embodiments, use of a 3D elastic

deformation model to correct OPC model contours and profiles yields significantly improved OPC model accuracy when compared to previously known techniques.

According to certain embodiments, a previously calibrated NTD OPC model is utilized from which to derive contours and an intensity map as predicted by the previously calibrated NTD OPC model, for instance, using a forward transfer function to extract the contours and intensity map from the previously calibrated NTD semi-physical OPC model. The contours and intensity map is then utilized as an input for simulations in which a FEM (Finite Element Method) solver applies 3D isotropic linear elasticity theory algorithms.

Laboratory experimentation reveals a strong qualitative agreement with the trends of the model error as exhibited by the OPC model 205 on the left and the CD-SEM imagery 210 for a corresponding physical silicon wafer exposed utilizing the target mask as depicted on the right.

With the above noted assumptions (e.g., static, linear behavior, isotropic material, length vs. height non-dependence, etc.), there is an acceptable tradeoff between the greater precision of the more rigorous and complete 3D equilibrium problem solutions for predicting the final state of polymer compaction of the resist when compared with the reduced complexity 2D solutions for the same equilibrium problem which is less precise but significantly less computationally burdensome.

However, even with such a tradeoff, the reduced complexity 2D solutions have been experimentally demonstrated to yield far better results when compared with the uncorrected OPC model. Specifically, the reduced complexity 2D solutions more accurately predict the final contours after elastic deformation 215 of the various features and geometries within the physical silicon wafer when compared with use of the uncorrected OPC model, thus permitting calibration and corrections to the OPC model which better align with observed realities when the OPC model contours are compared with actual CD-SEM imagery 210 measurements.

According to certain embodiments, experimental datasets are not required for calibration of the OPC model using 2D FEM whereas in other embodiments experimental datasets may be utilized to further refine and improve the final calibration.

Figure 2B depicts an OPC corrected and uncorrected pattern comparison 201 for an OPC model in accordance with described embodiments.

In particular, the OPC model 205 now depicts both the OPC corrected pattern 255 as well as the previously shown OPC uncorrected pattern 250. The OPC corrected pattern 255 subsequent to calibration will account for the elastic deformation exhibited such that the contours and features of the physical silicon wafer end up in the correct location with the appropriate design contours and after the predicted elastic deformation due to the post lithographic Negative Tone Development (NTD) and Post Exposure Bake (PEB) processes.

In particular, given that the contour prior to elastic deformation 220 is known to change via the NTD and post lithographic processes to the position of the depicted contour after the elastic deformation 215, the calibration and correction of the OPC model will render an OPC corrected layout (see element 110 of Figure 1) and an OPC corrected reticle (see element 120 of Figure 1) such that subsequent lithographic and etch processing (see element 125 of Figure 1) will result in the correct final pattern (see element 130 of Figure 1) being formed into the physical silicon wafer.

Figure 3 depicts a shrinkage comparison 300 of FEM2D vs FEM3D modeling. In particular, the graph depicts Finite Element Methods (FEM) modeling in two-dimensional (2D) space at element 305 on the vertical axis and depicts FEM modeling in three-dimensional (3D) space at element 310 on the horizontal axis with the depicted linear fit 320 revealing extremely strong correspondence between the two modeling approaches.

Optical Proximity Correction (OPC) models require highly accurate model predictions to properly correct critical features with corrections to such models typically obtained by fitting experimental critical dimensions (CDs) measured in the CD-SEM images after development.

Because Negative Tone Development (NTD) processes retain the exposed resist areas after development additional challenges are presented with respect to achieving modeling accuracy due to polymer compaction of the photoresist. Techniques which model polymer compaction by solving for a linear elastic mechanical deformation equation finite element method in three dimensions (3D) with appropriate boundary conditions at the top of the resist surface and bottom of the resist surface are rigorous, conceptually straightforward, and provide very good prediction results by which to correct the OPC models. Unfortunately, solving for linear elastic mechanical deformation in three dimensions, even when utilizing 3D Finite Element Methods (FEM) are so computationally intensive that the modeling runs far too slow to be economically viable for full chip modeling in a High Volume Manufacturing (HVM) environment.

Consequently, improvements are needed which yield sufficiently accurate modeling assumptions while reducing the total computational burden and therefore reducing the time to perform such modeling of elastic mechanical deformation for full chip implementations.

[0001] It is therefore in accordance with described embodiments that the three- dimensional elastic mechanical deformation modeling is reduced to a two-dimensional modeling problem which vastly reduces the computational burden required to complete the modeling and improves the time to completion for a full chip modeling implementation by 10 fold.

Laboratory experimentation demonstrates that OPC Model contours of negative-tone development (NTD) resists adjusted using a finite element model to solve polymer compaction in 2D space exhibit very good agreement with 3D FEM code developed to solve the same problem in a 3D space, thus enabling scalability of the 2D FEM version for full chip modeling corrections in a production HVM environment.

According to such an embodiment, the FEM model evaluates mechanical deformation of the resist in a two-dimensional space with two explicitly configured assumptions. First, the FEM model assumes that stresses were induced to the resist during the resist Post Exposure Bake (PEB) and development. Secondly, the FEM model assumes that regions exposed with higher intensity become softer (e.g., exhibit a lower elasticity modulus) than those areas exposed with lower intensity.

For instance, described embodiments reduce the 3D FEM modeling problem to a 2D version of the same FEM modeling problem in support of scaling to production ready full-chip OPC corrections by restraining the 2D FEM modeling of linear elastic mechanical deformation with a first requirement that, where the resist is sufficiently thick, in excess of a configurable threshold thickness, then deformation near a top surface is made to be non-dependent upon the z- coordinate, representing a so called "plane stress hypothesis." However, because plane stress hypothesis is not strictly true in reality, meaning that deformation at a top surface is at least partially dependent upon thickness of the resist, a second requirement is additionally applied to the 2D FEM modeling of the linear elastic mechanical deformation so as to counteract the first constraint. Namely, the 2D FRM modeling is forced to account for the contribution of other resist regions by assuming a linear elastic footing force in the modeling.

With these two constraints, comparison of the experimental simulation results between the 2D FEM modeling and the 3D FEM modeling result in the shrinkage comparison 300 plot depicted here with sufficient agreement to permit use of the 2D FEM modeling for production chip correction.

Laboratory experimentation reveals that OPC model contours computed by measuring the difference between the original uncorrected OPC model contour and the corrected OPC model contour after applying the 2D FEM simulation result in both improved contour fit from the OPC model predictions to actual CD-SEM imagery measurements of corresponding feature contours as well as reduction Root-Mean- Square Error (RMSE) for the calibrated OPC models.

Application of the 2D FEM methodologies for calibration of the OPC model improves

RET (Resolution Enhancement Technology) by reducing total OPC model error for Negative Tone Development (NTD) processes specifically by correcting correct experimental critical dimensions measured from CD-SEM imagery prior to the OPC model calibration for NTD resists.

According to other embodiments, the 2D FEM modeling is additionally restricted to a temporally static problem to improve its computational efficiency and so as to further reduce time to completion of the 2D FEM modeling for any full chip modeling problem. For instance, according to one embodiment the 2D FEM model is forced to ignore all transitive and temporal terms when solving for linear elastic mechanical deformation.

According to one embodiment, the 2D FEM model implements Hooke's law to force the assumption that deformation is linear and therefore proportional to its distances, regardless of whether or not the assumption is literally true as experimental data shows that such a simplification reduces the computational burden and reduces time to completion for the 2D FEM modeling while yielding very good agreement with the more comprehensive 3D FEM version of the modeling.

With the above simplifications to the 2D FEM modeling the model is forced to assume simple material properties which perform the same in all directions, yet yields sufficiently accurate results for calibration and correction of the OPC model contours and OPC model reticle while permitting a sufficiently short time to completion due to the reduced computational burden of the simplified model. According to yet another embodiment, the 2D FEM model is forced to assume the height of the chip or silicon wafer under manufacture is much taller or has a far greater height than it does have in reality. In so doing, the 2D FEM model having been given an excessive height for the chip, uses a linear spring term to convert from the 3D to a 2D space, causing vertical coordinates below the chip surface to become effectively zero, such that material property behaviors at the surface at the chip are identical to material property behaviors immediately below the surface of the chip, thus flatting the more complex 3D problem to a 2D problem.

Application of the 2D Finite Element Methods (FEM) solver then yields predictions by which the OPC model may be compensated or adjusted with far greater precision than previously possible.

When comparing actual regional model error based on CD-SEM image measurements with counteracting adjustments through the simulated or predicted changes to the resist due to polymer compaction there is a strong agreement between the predicted deformation and the predicted deformation of the resist for the same mask.

Such agreement therefore leads to the conclusion that the reductions in complexity based on the introduced assumptions when converting the 3D solutions the simplified 2D solutions are reasonable for the purposes of calibrating and correcting the OPC model to adjust for expected changes to the resist.

Moreover, experimental results demonstrate a Root-Mean- Square Error (RMSE) improvement of approximately 27% and a nearly perfect linear fit 320 when solving the same problem with the 3D and 2D FEM models, thus reinforcing the conclusion that the 2D FEM code provides a significant and valuable improvement over conventional OPC modeling results.

While solving every full chip implementation in full 3D space for the elastic deformation would be ideal, the economic reality of having to produce the product in a manufacturing environment simply render the 3D solution impractical. Yet, the endless pursuit of Moore's law also demands greater precision and smaller design tolerances, thus necessitating ever improved OPC model predictions if the features and geometries of the fabricated silicon wafers are to be sufficiently precisely aligned and positioned so as to permit fully functional chips at acceptable manufacturing yields.

The simplified 2D FEM solution 305 therefore provides the computational savings which make full chip modeling economically viable while simultaneously providing the needed increase in OPC modeling precision.

Figure 4 is a flow diagram illustrating a method 400 for implementing Optical Proximity Correction (OPC) model enhancement for Negative Tone Development (NTD) processes by including polymer compaction of photoresists in accordance with described embodiments. Some of the blocks and/or operations listed below are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur.

Additionally, operations from flow 400 may be utilized in a variety of combinations.

At block 405 the method 400 begins with reducing Optical Proximity Correction (OPC) model error by the following operations.

At block 410 the method includes fabricating a physical silicon wafer from a

photolithographic mask via a Negative Tone Development (NTD) photolithography processes, the physical silicon wafer having a plurality of features embodied therein as defined by the photolithographic mask.

At block 415 the method includes capturing measurements of the features embodied within the physical silicon wafer from Scanning Electron Microscope (SEM) images of the physical silicon wafer.

At block 420 the method includes creating an OPC model of the photolithographic mask using physical parameters of the NTD photolithography process, the OPC model specifying contours of the plurality of features of the mask.

At block 425 the method includes calibrating the OPC model based on the measurements of the features of the physical silicon wafer captured from the SEM images by solving for an equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in a photoresist of the physical silicon wafer in a two-dimensional (2D) plane.

At block 430 the method includes applying OPC model corrections to the

photolithographic mask based on the calibrating of the OPC model.

Figure 5 is a schematic of a computer system 500 in accordance with described embodiments. The computer system 500 (also referred to as the electronic system 500) as depicted can embody means for implementing Optical Proximity Correction (OPC) model enhancement for Negative Tone Development (NTD) processes by including polymer compaction of photoresists, according to any of the several disclosed embodiments and their equivalents as set forth in this disclosure. The computer system 500 may be a mobile device such as a net-book computer. The computer system 500 may be a mobile device such as a wireless smartphone or tablet. The computer system 500 may be a desktop computer. The computer system 500 may be a hand-held reader. The computer system 500 may be a server system. The computer system 500 may be a supercomputer or high-performance computing system.

In accordance with one embodiment, the electronic system 500 is a computer system that includes a system bus 520 to electrically couple the various components of the electronic system 500. The system bus 520 is a single bus or any combination of busses according to various embodiments. The electronic system 500 includes a voltage source 530 that provides power to the integrated circuit 510. In some embodiments, the voltage source 530 supplies current to the integrated circuit 510 through the system bus 520.

Such an integrated circuit 510 is electrically coupled to the system bus 520 and includes any circuit, or combination of circuits according to an embodiment. In an embodiment, the integrated circuit 510 includes a processor 512 that can be of any type. As used herein, the processor 512 may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, the processor 512 includes, or is coupled with, electrical devices having gradient encapsulant protection, as disclosed herein.

In accordance with one embodiment, SRAM embodiments are found in memory caches of the processor. Other types of circuits that can be included in the integrated circuit 510 are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit 514 for use in wireless devices such as cellular telephones, smart phones, pagers, portable computers, two-way radios, and similar electronic systems, or a communications circuit for servers. In an embodiment, the integrated circuit 510 includes on-die memory 516 such as static random-access memory (SRAM). In an embodiment, the integrated circuit 510 includes embedded on-die memory 516 such as embedded dynamic random-access memory (eDRAM).

In accordance with one embodiment, the integrated circuit 510 is complemented with a subsequent integrated circuit 511. Useful embodiments include a dual processor 513 and a dual communications circuit 515 and dual on-die memory 517 such as SRAM. In accordance with one embodiment, the dual integrated circuit 510 includes embedded on-die memory 517 such as eDRAM.

In one embodiment, the electronic system 500 also includes an external memory 540 that in turn may include one or more memory elements suitable to the particular application, such as a main memory 542 in the form of RAM, one or more hard drives 544, and/or one or more drives that handle removable media 546, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. The external memory 540 may also be embedded memory 548 such as the first die in a die stack, according to an embodiment.

In accordance with one embodiment, the electronic system 500 also includes a display device 550 and an audio output 560. In one embodiment, the electronic system 500 includes an input device 570 such as a controller that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system 500. In an embodiment, an input device 570 is a camera. In an embodiment, an input device 570 is a digital sound recorder. In an embodiment, an input device 570 is a camera and a digital sound recorder.

As shown herein, the integrated circuit 510 can be implemented in a number of different embodiments, including means for implementing Optical Proximity Correction (OPC) model enhancement for Negative Tone Development (NTD) processes by including polymer compaction of photoresists, according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes means for implementing Optical Proximity Correction (OPC) model enhancement for Negative Tone Development (NTD) processes by including polymer compaction of photoresists, according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including array contact count, array contact configuration for a microelectronic die embedded in a processor mounting substrate according to any of the several disclosed package substrates and means for implementing Optical Proximity Correction (OPC) model enhancement for Negative Tone Development (NTD) processes by including polymer compaction of photoresists embodiments and their equivalents. A foundation substrate 598 may be included, as represented by the dashed line of Figure 5. Passive devices 599 may also be included, as is also depicted in Figure 5.

Figure 6 illustrates a semiconductor device 600 (or an interposer) that includes one or more described embodiments. The interposer 600 is an intervening substrate used to bridge a first substrate 602 to a second substrate 604. The first substrate 602 may be, for instance, an integrated circuit die. The second substrate 604 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 600 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 600 may couple an integrated circuit die to a ball grid array (BGA) 606 that can subsequently be coupled to the second substrate 604. In some embodiments, the first and second substrates 602/604 are attached to opposing sides of the interposer 600. In other embodiments, the first and second substrates 602/604 are attached to the same side of the interposer 600. And in further embodiments, three or more substrates are interconnected by way of the interposer 600.

The interposer 600 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects 608 and vias 610, including but not limited to through-silicon vias (TSVs) 612. The interposer 600 may further include embedded devices 614, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 600. In accordance with described embodiments, apparatuses or processes disclosed herein may be used in the fabrication of interposer 600.

Figure 7 illustrates a computing device 700 in accordance with one implementation of the invention. The computing device 700 houses a board 702. The board 702 may include a number of components, including but not limited to a processor 704 and at least one communication chip 706. The processor 704 is physically and electrically coupled to the board 702. In some implementations the at least one communication chip 706 is also physically and electrically coupled to the board 702. In further implementations, the communication chip 706 is part of the processor 704.

Depending on its applications, computing device 700 may include other components that may or may not be physically and electrically coupled to the board 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 706 enables wireless communications for the transfer of data to and from the computing device 700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 700 may include a plurality of communication chips 706. For instance, a first communication chip 706 may be dedicated to shorter range wireless

communications such as Wi-Fi and Bluetooth and a second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704. In some implementations of the invention, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 706 also includes an integrated circuit die packaged within the communication chip 706. In accordance with another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices, such as MOS- FET transistors built in accordance with implementations of the invention.

In further implementations, another component housed within the computing device 700 may contain an integrated circuit die that includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention.

In various implementations, the computing device 700 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 700 may be any other electronic device that processes data.

While the subject matter disclosed herein has been described by way of example and in terms of the specific embodiments, it is to be understood that the claimed embodiments are not limited to the explicitly enumerated embodiments disclosed. To the contrary, the disclosure is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the disclosed subject matter is therefore to be determined in reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. It is therefore in accordance with the described embodiments, that:

According to one embodiment there is a method for reducing Optical Proximity Correction (OPC) model error, by fabricating a physical silicon wafer from a photolithographic mask via a Negative Tone Development (NTD) photolithography processes, the physical silicon wafer having a plurality of features embodied therein as defined by the photolithographic mask;

capturing measurements of the features embodied within the physical silicon wafer from

Scanning Electron Microscope (SEM) images of the physical silicon wafer; creating an OPC model of the photolithographic mask using physical parameters of the NTD photolithography process, the OPC model specifying contours of the plurality of features of the mask; calibrating the OPC model based on the measurements of the features of the physical silicon wafer captured from the SEM images by solving for an equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in a photoresist of the physical silicon wafer in a two- dimensional (2D) plane; and applying OPC model corrections to the photolithographic mask based on the calibrating of the OPC model.

According to another embodiment of the method, solving for the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in the photoresist of the physical silicon wafer in the two-dimensional (2D) plane includes: constraining the equilibrium problem solving for polymer compaction of the photoresist at a top 2D surface plane of the photoresist without regard to any sub-surface deformation of the photoresist.

According to another embodiment of the method, constraining the equilibrium problem solving for polymer compaction of the photoresist at the top 2D surface plane of the photoresist without regard to any sub-surface deformation of the photoresist further includes applying a linear spring term at the top 2D surface plane of the photoresist to mathematically isolate deformation behavior at the top 2D surface plane of the photoresist from any deformation of the photoresist below the top 2D surface plane of the photoresist such that the solving for the equilibrium problem in the 2D plane assumes the top 2D surface plane behaves independently of any material properties exhibited below the top 2D surface plane.

According to another embodiment of the method, solving for the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in the photoresist of the physical silicon wafer in the two-dimensional (2D) plane includes: constraining the equilibrium problem solving for polymer compaction of the photoresist at a top 2D surface plane of the photoresist and applying a linear spring term at the top 2D surface plane of the photoresist to mathematically approximate sub-surface stresses within the photoresist below the top 2D surface plane.

According to another embodiment of the method, solving for the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in the photoresist of the physical silicon wafer in the two-dimensional (2D) plane includes: constraining the equilibrium problem solving for polymer compaction of the photoresist at a top 2D surface plane to assume that all deformation of the photoresist is linear and therefore assume that all stresses in the photoresist are proportional to their corresponding change in deformation distance.

According to another embodiment of the method, solving for the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in the photoresist of the physical silicon wafer in the two-dimensional (2D) plane includes: constraining the equilibrium problem solving for polymer compaction of the photoresist at a top 2D surface plane to treat the photoresist an isotropic material which exhibits identical material property values in all directions to negate the need to solve for the polymer compaction of the photoresist in a three- dimensional space.

According to another embodiment of the method, solving for the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in the photoresist of the physical silicon wafer in the two-dimensional (3D) plane includes: constraining the equilibrium problem solving for polymer compaction of the photoresist at a top 2D surface plane to treat the photoresist as having a height that exceeds a configurable threshold distance which is greater than an actual height of the photoresist such that vertical coordinates below the top 2D surface plane are mathematically treated as zero negating the need to solve for the polymer compaction of the photoresist in a three-dimensional (3D) space.

According to another embodiment of the method, solving for the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in the photoresist of the physical silicon wafer in the two-dimensional (3D) plane includes: constraining the equilibrium problem solving for polymer compaction of the photoresist at a top 2D surface plane to treat the photoresist as having a height that exceeds a configurable threshold distance which is greater than an actual height of the photoresist such that deformation at the top 2D surface plane operates independently of a length of the photoresist.

According to another embodiment of the method, solving for the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in the photoresist of the physical silicon wafer in the two-dimensional (3D) plane includes: constraining the equilibrium problem solving for polymer compaction of the photoresist at a top 2D surface plane to treat polymer deformation of the photoresist as static by ignoring all transient and temporal terms when solving for the equilibrium problem.

According to another embodiment of the method, capturing the measurements of the features embodied within the physical silicon wafer includes capturing Critical Dimension (CD) measurements from CD-SEM images of the plurality of features as embodied within the physical silicon wafer after exposed to the photolithographic mask via Negative Tone Development (NTD) photolithography processing.

According to another embodiment of the method, capturing the CD measurements from CD-SEM images is performed subsequent to NTD processing and Post Exposure Bake (PEB) processing of the physical silicon wafer.

According to another embodiment of the method, capturing measurements of the features embodied within the physical silicon wafer from the SEM images of the physical silicon wafer includes: collecting experimental data by extracting the measurements from Critical Dimension Scanning Electron Microscope (CD-SEM) images; and in which the experimental data includes at least critical dimension measurements of the CD-SEM images and features within the CD- SEM images having contours corresponding to contours of the features as specified by the OPC model of the photolithographic mask.

According to another embodiment of the method, applying the OPC model corrections to the photolithographic mask based on the calibrating of the OPC model includes: adjusting the contours of the OPC model based on the calibrating to more accurately match the measurements of the features embodied within the physical silicon wafer as captured from the SEM images of the physical silicon wafer.

According to another embodiment of the method, solving for the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction of the photoresist of the physical silicon wafer in the 2D plane further includes outputting adjusted contours as predictions for the polymer compaction of the photoresist; and in which applying the OPC model corrections to the photolithographic mask based on the calibrating of the OPC model includes applying the predictions for the polymer compaction of the photoresist to adjust the contours of the OPC model.

According to another embodiment of the method, the adjustment to the contours of the OPC model yield an OPC corrected layout from which a new photolithographic mask is manufactured.

According to another embodiment of the method, a third party black box software solution implements the equilibrium problem; and in which the equilibrium problem of the third party black box software solution is constrained to solving the equilibrium problem in the 2D plane by modifying the equations solved by the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction of the photoresist by constraining the equations to assume one or more of the following: (a) a top 2D surface plane of the photoresist exhibits deformation independent to deformation at any sub-surface region of the photoresist; (b) all deformation of the photoresist is linear and therefore all stresses in the photoresist are proportional to their corresponding change in deformation distance; (c) a linear spring term is applied to the equation to approximate stresses in the sub-surface region of the photoresist at the top 2D surface plane of the photoresist; (d) the photoresist an isotropic material which exhibits identical material property values in all directions; (e) the photoresist is specified to have a height that exceeds a configurable threshold distance which is greater than an actual height of the photoresist such that vertical coordinates below the top 2D surface plane are mathematically treated as zero; and (f) equilibrium of the polymer deformation is static such that all transient and temporal terms of the equation are ignored.

According to another embodiment, the method further includes: validating predictions output by the calibrating of the OPC model; in which the validating uses new measurements captured of the features embodied within a new physical silicon wafer fabricated using an OPC corrected layout after applying the OPC model corrections to the photolithographic mask.

According to another embodiment of the method, the new physical silicon wafer is fabricated using a new photolithographic mask manufactured using the OPC corrected layout subsequent to the calibrating of the OPC model.

According to another embodiment of the method, the measurements captured of the features embodied within the physical silicon wafer from SEM images of the physical silicon wafer represent a sample experimental data set; in which the new measurements captured of the features embodied within the new physical silicon wafer fabricated using the OPC corrected layout represent a different set of measurements of different features not included within the sample experimental data set; and in which the new measurements are validated by comparing the new measurements with the predictions output by the calibrated OPC model.

According to another embodiment of the method, the predictions output by the calibrating of the OPC model based are validated and acceptable when the Edge Placement Error (EPE) of the contours of the calibrated OPC model are less than corresponding EPE of the contours of the uncorrected OPC model.

In accordance with yet another embodiment there is a system to reduce Optical Proximity Correction (OPC) model error, in which the system includes: a physical silicon wafer fabricated from a photolithographic mask via a Negative Tone Development (NTD) photolithography processes, the physical silicon wafer having a plurality of features embodied therein as defined by the photolithographic mask; a non-transitory storage device to store measurements of the features embodied within the physical silicon wafer from Scanning Electron Microscope (SEM) images of the physical silicon wafer; an analysis unit to create an OPC model of the

photolithographic mask using physical parameters of the NTD photolithography process, the OPC model specifying contours of the plurality of features of the photolithographic mask; the analysis unit to calibrate the OPC model based on the measurements of the features of the physical silicon wafer captured from the SEM images by solving for an equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in a photoresist of the physical silicon wafer in a two-dimensional (2D) plane; and the analysis unit to apply OPC model corrections to the photolithographic mask based on the calibrating of the OPC model.

According to another embodiment of the system, there is a third party black box software solution to implement the equilibrium problem; and in which the equilibrium problem of the third party black box software solution is constrained to solving the equilibrium problem in the 2D plane by modifying the equations solved by the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction of the photoresist by constraining the equations to assume one or more of the following: a top 2D surface plane of the photoresist exhibits deformation independent to deformation at any sub-surface region of the photoresist; all deformation of the photoresist is linear and therefore all stresses in the photoresist are proportional to their corresponding change in deformation distance; a linear spring term is applied to the equation to approximate stresses in the sub-surface region of the photoresist at the top 2D surface plane of the photoresist; the photoresist an isotropic material which exhibits identical material property values in all directions; the photoresist is specified to have a height that exceeds a configurable threshold distance which is greater than an actual height of the photoresist such that vertical coordinates below the top 2D surface plane are mathematically treated as zero; and equilibrium of the polymer deformation is static such that all transient and temporal terms of the equation are ignored.

According to another embodiment, the system further includes: the analysis unit to validate predictions output by the calibrating of the OPC model; in which the analysis unit to validate the predictions includes the analysis unit to use new measurements captured of the features embodied within a new physical silicon wafer fabricated using an OPC corrected layout after applying the OPC model corrections to the photolithographic mask; in which the new physical silicon wafer is fabricated using a new photolithographic mask manufactured using the OPC corrected layout subsequent to the calibrating of the OPC model.

According to a particular embodiment there is a non-transitory computer readable storage media having instructions stored thereupon that, when executed by a processor, the instructions cause the processor to perform operations for reducing Optical Proximity Correction (OPC) model error, in which operations include: fabricating a physical silicon wafer from a

photolithographic mask via a Negative Tone Development (NTD) photolithography processes, the physical silicon wafer having a plurality of features embodied therein as defined by the photolithographic mask; capturing measurements of the features embodied within the physical silicon wafer from Scanning Electron Microscope (SEM) images of the physical silicon wafer; creating an OPC model of the photolithographic mask using physical parameters of the NTD photolithography process, the OPC model specifying contours of the plurality of features of the photolithographic mask; calibrating the OPC model based on the measurements of the features of the physical silicon wafer captured from the SEM images by solving for an equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in a photoresist of the physical silicon wafer in a two-dimensional (2D) plane; and applying OPC model corrections to the photolithographic mask based on the calibrating of the OPC model.

According to another embodiment of the non-transitory computer readable media, there is a third party black box software solution implements the equilibrium problem; and in which the equilibrium problem of the third party black box software solution is constrained to solving the equilibrium problem in the 2D plane by modifying the equations solved by the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction of the photoresist by constraining the equations to assume one or more of the following: a top 2D surface plane of the photoresist exhibits deformation independent to deformation at any subsurface region of the photoresist; all deformation of the photoresist is linear and therefore all stresses in the photoresist are proportional to their corresponding change in deformation distance; a linear spring term is applied to the equation to approximate stresses in the sub-surface region of the photoresist at the top 2D surface plane of the photoresist; the photoresist an isotropic material which exhibits identical material property values in all directions; the photoresist is specified to have a height that exceeds a configurable threshold distance which is greater than an actual height of the photoresist such that vertical coordinates below the top 2D surface plane are mathematically treated as zero; and equilibrium of the polymer deformation is static such that all transient and temporal terms of the equation are ignored.

According to yet another embodiment, the instructions of the non-transitory computer readable media cause the processor to perform operations further including: validating predictions output by the calibrating of the OPC model; in which the validating uses new measurements captured of the features embodied within a new physical silicon wafer fabricated using an OPC corrected layout after applying the OPC model corrections to the

photolithographic mask; in which the new physical silicon wafer is fabricated using a new photolithographic mask manufactured using the OPC corrected layout subsequent to the calibrating of the OPC model; in which the measurements captured of the features embodied within the physical silicon wafer from SEM images of the physical silicon wafer represent a sample experimental data set; in which the new measurements captured of the features embodied within the new physical silicon wafer fabricated using the OPC corrected layout represent a different set of measurements of different features not included within the sample experimental data set; and in which the new measurements are validated by comparing the new measurements with the predictions output by the calibrated OPC model.

Claims

CLAIMS What is claimed is:

1. A method for reducing Optical Proximity Correction (OPC) model error, comprising:

fabricating a physical silicon wafer from a photolithographic mask via a Negative Tone

Development (NTD) photolithography processes, the physical silicon wafer having a plurality of features embodied therein as defined by the photolithographic mask;

Scanning Electron Microscope (SEM) images of the physical silicon wafer;

creating an OPC model of the photolithographic mask using physical parameters of the NTD photolithography process, the OPC model specifying contours of the plurality of features of the photolithographic mask;

calibrating the OPC model based on the measurements of the features of the physical silicon wafer captured from the SEM images by solving for an equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in a photoresist of the physical silicon wafer in a two-dimensional (2D) plane; and

applying OPC model corrections to the photolithographic mask based on the calibrating of the OPC model.

2. The method of claim 1, wherein solving for the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in the photoresist of the physical silicon wafer in the two-dimensional (2D) plane comprises:

constraining the equilibrium problem solving for polymer compaction of the photoresist at a top 2D surface plane of the photoresist without regard to any sub-surface deformation of the photoresist.

3. The method of claim 2, wherein constraining the equilibrium problem solving for polymer compaction of the photoresist at the top 2D surface plane of the photoresist without regard to any sub-surface deformation of the photoresist further comprises applying a linear spring term at the top 2D surface plane of the photoresist to mathematically isolate deformation behavior at the top 2D surface plane of the photoresist from any deformation of the photoresist below the top 2D surface plane of the photoresist such that the solving for the equilibrium problem in the 2D plane assumes the top 2D surface plane behaves independently of any material properties exhibited below the top 2D surface plane.

4. The method of claim 1, wherein solving for the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in the photoresist of the physical silicon wafer in the two-dimensional (2D) plane comprises: constraining the equilibrium problem solving for polymer compaction of the photoresist at a top 2D surface plane of the photoresist and applying a linear spring term at the top 2D surface plane of the photoresist to mathematically approximate sub-surface stresses within the photoresist below the top 2D surface plane.

5. The method of claim 1, wherein solving for the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in the photoresist of the physical silicon wafer in the two-dimensional (2D) plane comprises:

constraining the equilibrium problem solving for polymer compaction of the photoresist at a top 2D surface plane to assume that all deformation of the photoresist is linear and therefore assume that all stresses in the photoresist are proportional to their corresponding change in deformation distance.

6. The method of claim 1, wherein solving for the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in the photoresist of the physical silicon wafer in the two-dimensional (2D) plane comprises:

constraining the equilibrium problem solving for polymer compaction of the photoresist at a top 2D surface plane to treat the photoresist an isotropic material which exhibits identical material property values in all directions to negate the need to solve for the polymer compaction of the photoresist in a three-dimensional space.

7. The method of claim 1, wherein solving for the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in the photoresist of the physical silicon wafer in the two-dimensional (3D) plane comprises:

constraining the equilibrium problem solving for polymer compaction of the photoresist at a top 2D surface plane to treat the photoresist as having a height that exceeds a configurable threshold distance which is greater than an actual height of the photoresist such that vertical coordinates below the top 2D surface plane are mathematically treated as zero negating the need to solve for the polymer compaction of the photoresist in a three- dimensional (3D) space.

8. The method of claim 1, wherein solving for the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in the photoresist of the physical silicon wafer in the two-dimensional (3D) plane comprises:

constraining the equilibrium problem solving for polymer compaction of the photoresist at a top 2D surface plane to treat the photoresist as having a height that exceeds a configurable threshold distance which is greater than an actual height of the photoresist such that deformation at the top 2D surface plane operates independently of a length of the photoresist.

9. The method of claim 1, wherein solving for the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in the photoresist of the physical silicon wafer in the two-dimensional (3D) plane comprises:

constraining the equilibrium problem solving for polymer compaction of the photoresist at a top 2D surface plane to treat polymer deformation of the photoresist as static by ignoring all transient and temporal terms when solving for the equilibrium problem.

10. The method of claim 1, wherein capturing the measurements of the features embodied within the physical silicon wafer comprises capturing Critical Dimension (CD) measurements from CD-SEM images of the plurality of features as embodied within the physical silicon wafer after exposed to the photolithographic mask via Negative Tone Development (NTD) photolithography processing.

11. The method of claim 10, wherein capturing the CD measurements from CD-SEM images is performed subsequent to NTD processing and Post Exposure Bake (PEB) processing of the physical silicon wafer.

12. The method of claim 1, wherein capturing measurements of the features embodied within the physical silicon wafer from the SEM images of the physical silicon wafer comprises: collecting experimental data by extracting the measurements from Critical Dimension Scanning

Electron Microscope (CD-SEM) images; and

wherein the experimental data comprises at least critical dimension measurements of the CD- SEM images and features within the CD-SEM images having contours corresponding to contours of the features as specified by the OPC model of the photolithographic mask.

13. The method of claim 1, wherein applying the OPC model corrections to the

photolithographic mask based on the calibrating of the OPC model comprises:

adjusting the contours of the OPC model based on the calibrating to more accurately match the measurements of the features embodied within the physical silicon wafer as captured from the SEM images of the physical silicon wafer.

14. The method of claim 1 :

wherein the solving for the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction of the photoresist of the physical silicon wafer in the 2D plane further comprises outputting adjusted contours as predictions for the polymer compaction of the photoresist; and

wherein applying the OPC model corrections to the photolithographic mask based on the

calibrating of the OPC model comprises applying the predictions for the polymer compaction of the photoresist to adjust the contours of the OPC model.

15. The method of claim 14, wherein the adjustment to the contours of the OPC model yield an OPC corrected layout from which a new photolithographic mask is manufactured.

16. The method of claim 1 :

wherein a third party black box software solution implements the equilibrium problem; and wherein the equilibrium problem of the third party black box software solution is constrained to solving the equilibrium problem in the 2D plane by modifying the equations solved by the equilibrium problem to adjust the contours specified by the OPC model for polymer compaction of the photoresist by constraining the equations to assume one or more of the following:

a top 2D surface plane of the photoresist exhibits deformation independent to deformation at any sub-surface region of the photoresist;

all deformation of the photoresist is linear and therefore all stresses in the photoresist are

proportional to their corresponding change in deformation distance;

a linear spring term is applied to the equation to approximate stresses in the sub-surface region of the photoresist at the top 2D surface plane of the photoresist;

the photoresist an isotropic material which exhibits identical material property values in all

directions;

the photoresist is specified to have a height that exceeds a configurable threshold distance which is greater than an actual height of the photoresist such that vertical coordinates below the top 2D surface plane are mathematically treated as zero; and

equilibrium of the polymer deformation is static such that all transient and temporal terms of the equation are ignored.

17. The method of claim 1, further comprising:

validating predictions output by the calibrating of the OPC model;

wherein the validating uses new measurements captured of the features embodied within a new physical silicon wafer fabricated using an OPC corrected layout after applying the OPC model corrections to the photolithographic mask.

18. The method of claim 17, wherein the new physical silicon wafer is fabricated using a new photolithographic mask manufactured using the OPC corrected layout subsequent to the calibrating of the OPC model.

19. The method of claim 17:

wherein the measurements captured of the features embodied within the physical silicon wafer from SEM images of the physical silicon wafer represent a sample experimental data set; wherein the new measurements captured of the features embodied within the new physical

silicon wafer fabricated using the OPC corrected layout represent a different set of measurements of different features not included within the sample experimental data set; and

wherein the new measurements are validated by comparing the new measurements with the predictions output by the calibrated OPC model.

20. The method of claim 19, wherein the predictions output by the calibrating of the OPC model based are validated and acceptable when the Edge Placement Error (EPE) of the contours of the calibrated OPC model are less than corresponding EPE of the contours of the uncorrected OPC model.

21. A system to reduce Optical Proximity Correction (OPC) model error, wherein the system comprises:

a physical silicon wafer fabricated from a photolithographic mask via a Negative Tone

a non-transitory storage device to store measurements of the features embodied within the

physical silicon wafer from Scanning Electron Microscope (SEM) images of the physical silicon wafer;

an analysis unit to create an OPC model of the photolithographic mask using physical parameters of the NTD photolithography process, the OPC model specifying contours of the plurality of features of the photolithographic mask;

the analysis unit to calibrate the OPC model based on the measurements of the features of the physical silicon wafer captured from the SEM images by solving for an equilibrium problem to adjust the contours specified by the OPC model for polymer compaction in a photoresist of the physical silicon wafer in a two-dimensional (2D) plane; and

the analysis unit to apply OPC model corrections to the photolithographic mask based on the calibrating of the OPC model.

22. The system of claim 21 :

proportional to their corresponding change in deformation distance; a linear spring term is applied to the equation to approximate stresses in the sub-surface region of the photoresist at the top 2D surface plane of the photoresist;

directions;

23. The system of claim 21, further comprising:

the analysis unit to validate predictions output by the calibrating of the OPC model;

wherein the analysis unit to validate the predictions comprises the analysis unit to use new

measurements captured of the features embodied within a new physical silicon wafer fabricated using an OPC corrected layout after applying the OPC model corrections to the photolithographic mask;

wherein the new physical silicon wafer is fabricated using a new photolithographic mask

manufactured using the OPC corrected layout subsequent to the calibrating of the OPC model.

24. Non-transitory computer readable storage media having instructions stored thereupon that, when executed by a processor, the instructions cause the processor to perform operations for reducing Optical Proximity Correction (OPC) model error, wherein operations comprise:

Scanning Electron Microscope (SEM) images of the physical silicon wafer;

25. The non-transitory computer readable media of claim 24:

proportional to their corresponding change in deformation distance;

directions;

26. The non-transitory computer readable media of claim 24, wherein the instructions cause the processor to perform operations further comprising:

validating predictions output by the calibrating of the OPC model;

wherein the validating uses new measurements captured of the features embodied within a new physical silicon wafer fabricated using an OPC corrected layout after applying the OPC model corrections to the photolithographic mask;

manufactured using the OPC corrected layout subsequent to the calibrating of the OPC model;