WO2019062532A1 - 电压调节系统、驱动电路、显示装置和电压调节方法 - Google Patents

电压调节系统、驱动电路、显示装置和电压调节方法 Download PDF

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Publication number
WO2019062532A1
WO2019062532A1 PCT/CN2018/104851 CN2018104851W WO2019062532A1 WO 2019062532 A1 WO2019062532 A1 WO 2019062532A1 CN 2018104851 W CN2018104851 W CN 2018104851W WO 2019062532 A1 WO2019062532 A1 WO 2019062532A1
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Prior art keywords
voltage
resistor
circuit
operational amplifier
output
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PCT/CN2018/104851
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English (en)
French (fr)
Inventor
刘媛媛
刘帅
袁先锋
陈泽君
汪敏
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/329,823 priority Critical patent/US11282418B2/en
Publication of WO2019062532A1 publication Critical patent/WO2019062532A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • Embodiments of the present disclosure relate to a voltage regulation system, a drive circuit, a display device, and a voltage adjustment method.
  • the timing controller is an important component of the display panel driving circuit. It can convert the signal input from the front-end system into the control signal required by the display panel through data processing.
  • the timing controller generates two kinds of voltages: the core voltage and the I/O (input/output) voltage.
  • the core voltage refers to the voltage of the core chip of the timing controller.
  • the I/O voltage refers to the driver I. /O circuit voltage.
  • the timing controller has strict requirements on the voltage and current of the core voltage. If the core voltage is abnormal, the timing controller will not work properly. Due to the importance of the timing controller to the display panel, if the core voltage is abnormal, the display panel may be abnormally turned on, repeatedly turned on and off, and the screen is abnormally displayed. Therefore, it is very important to ensure the stability of the core voltage, to improve the stability of the display panel drive circuit, and to prevent the display panel from being abnormally displayed.
  • At least one embodiment of the present disclosure provides a voltage regulation system for an electronic device including a power supply circuit, a determination circuit, and an adjustment circuit.
  • the power supply circuit is coupled to the adjustment circuit and configured to provide a reference voltage and provide a first voltage input to the electronic device;
  • the determination circuit is coupled to the power supply circuit and configured to be based on the reference a voltage and the first voltage output compensation voltage;
  • the adjustment circuit is coupled to the determination circuit to receive the compensation voltage, and configured to be based on the compensation voltage when the compensation voltage is not within a preset range
  • the second voltage outputs a third voltage;
  • the power supply circuit is further configured to provide the first voltage according to the third voltage, the second voltage being the reference voltage or a voltage obtained based on the change of the reference voltage .
  • the determination circuit is configured to perform a difference processing on the reference voltage and the first voltage to obtain the compensation voltage.
  • the second voltage is equal to the reference voltage.
  • a voltage regulation system further includes a voltage feedback circuit connected to the adjustment circuit, configured to be configured according to the reference when the adjustment circuit outputs the third voltage The voltage and the third voltage obtain the second voltage and provide to the conditioning circuit.
  • the determination circuit includes: a first operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor.
  • the first end of the first resistor is configured to receive the first voltage, the second end of the first resistor is coupled to an inverting input of the first operational amplifier; the first of the second resistor An end is coupled to an inverting input of the first operational amplifier, a second end of the second resistor is coupled to an output of the first operational amplifier; a first end of the third resistor is configured to receive a reference voltage, a second end of the third resistor is coupled to the non-inverting input of the first operational amplifier; a first end of the fourth resistor is coupled to a non-inverting input of the first operational amplifier, A second end of the fourth resistor is coupled to ground; an output of the first operational amplifier is configured to output the compensation voltage.
  • the adjustment circuit includes: a second operational amplifier, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor.
  • a first end of the fifth resistor is configured to receive the second voltage, a second end of the fifth resistor is coupled to an inverting input of the second operational amplifier; a first of the sixth resistor The end is configured to receive the compensation voltage, the second end of the sixth resistor is coupled to the inverting input of the second operational amplifier; the first end of the seventh resistor and the second operational amplifier Connected to the non-inverting input, the second end of the seventh resistor is grounded; the first end of the eighth resistor is coupled to the inverting input of the second operational amplifier, and the second end of the eighth resistor is An output of the second operational amplifier is coupled; an output of the second operational amplifier is configured to output the third voltage.
  • the eighth resistor is a variable resistor
  • the eighth resistor includes N resistors and N first switches
  • the adjustment circuit further includes a first process. Circuit.
  • the N resistors are in one-to-one correspondence with the N first switches; the first end of each of the N resistors passes through an inverting input of the corresponding first switch and the second operational amplifier An end connection, a second end of each of the N resistors being coupled to an output of the second operational amplifier; the first processing circuit and the determining circuit and the eighth resistor N first switches are connected, and configured to control each of the N first switches in the eighth resistor to open or close when the compensation voltage is not within a preset range; N is greater than 1 The integer.
  • the adjustment circuit further includes a second switch and a second processing circuit.
  • the second switch is coupled to the first end of the sixth resistor and the second processing circuit; the second processing circuit is coupled to the determining circuit and configured to control the second switch to be turned off or closure.
  • the eighth resistor is a variable resistor
  • the eighth resistor includes N resistors and N first switches
  • the adjustment circuit further includes a processing circuit and The second switch.
  • the N resistors are in one-to-one correspondence with the N first switches; the first end of each of the N resistors passes through an inverting input of the corresponding first switch and the second operational amplifier End connection, a second end of each of the N resistors is coupled to an output of the second operational amplifier; a second end of the second switch and the sixth resistor and the processing circuit are coupled
  • the processing circuit is coupled to the second switch, the determining circuit, and the N first switches, and configured to control the N first switches when the compensation voltage is not within a preset range Each of the ones are open or closed, and the second switch is controlled to open or close; N is an integer greater than one.
  • the power supply circuit is disposed in a power control chip.
  • the adjustment circuit is disposed in the power control chip.
  • At least one embodiment of the present disclosure also provides a voltage adjustment method of any voltage regulation system according to an embodiment of the present disclosure, including: causing the power supply circuit to provide the reference voltage and the first voltage; The determining circuit obtains the compensation voltage according to the reference voltage and the first voltage; when the compensation voltage is not within a preset range, causing the adjustment circuit to obtain the according to the compensation voltage and the second voltage a third voltage; and causing the power supply circuit to provide the first voltage according to the third voltage.
  • causing the determination circuit to obtain the compensation voltage according to the reference voltage and the first voltage includes: causing the determination circuit to compare the reference voltage The first voltage is subjected to a difference process to obtain the compensation voltage.
  • the voltage adjustment method further includes: re-sampling the third voltage output by the adjustment circuit Provided to the regulation circuit and as a second voltage.
  • the adjustment circuit is caused to be based on the compensation voltage and the The obtaining the third voltage by the second voltage comprises: the processing circuit closing the second switch when determining that the compensation voltage is not within a preset range, so that the compensation voltage is input to the second operational amplifier.
  • the adjustment circuit in a case where the voltage regulation system includes an eighth resistor and the eighth resistor is a variable resistor, the adjustment circuit is caused to be based on the compensation voltage and The obtaining the third voltage by the second voltage further includes: adjusting a voltage value of the third voltage output by the adjustment circuit by adjusting a resistance of the eighth resistor.
  • the causing the adjustment circuit to obtain the third voltage according to the compensation voltage and the second voltage includes: if the compensation voltage is greater than the preset range a maximum value that increases a voltage value of the third voltage output by the adjustment circuit; and if the compensation voltage is less than a minimum value of the preset range, reducing the third voltage output by the adjustment circuit Voltage value.
  • the power supply circuit is disposed in a power control chip.
  • At least one embodiment of the present disclosure also provides a driving circuit for driving a timing controller including a power control chip and a determining circuit.
  • the timing controller includes a core voltage input terminal;
  • the determining circuit includes a first operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor;
  • the power control chip includes a reference voltage output terminal and a compensation voltage An input terminal, a second voltage input terminal, a third voltage output terminal, a processing circuit, a second operational amplifier, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a second switch;
  • One end is connected to the core voltage input end, and the second end of the first resistor is connected to an inverting input end of the first operational amplifier;
  • the first end of the second resistor is opposite to the first operational amplifier
  • the inverting input is connected, the second end of the second resistor is connected to the output of the first operational amplifier;
  • the first end of the third resistor is
  • the eighth resistor is a variable resistor
  • the eighth resistor includes N resistors and N first switches; the N resistors and the N resistors a first switch corresponding to each other; a first end of each of the N resistors is connected to an inverting input end of the second operational amplifier through a corresponding first switch, wherein the N resistors A second end of each resistor is coupled to an output of the second operational amplifier; N is an integer greater than one.
  • At least one embodiment of the present disclosure further provides a display device including any of the voltage regulation system, the timing controller, and the display panel provided by the embodiments of the present disclosure; the voltage regulation system is configured to drive the timing controller, The timing controller is configured to provide a control signal to the display panel.
  • the voltage regulation system is configured to provide a core voltage to the timing controller.
  • FIG. 1A is a schematic diagram of a voltage regulation system according to an embodiment of the present disclosure
  • FIG. 1B is a schematic diagram of another voltage regulation system according to an embodiment of the present disclosure.
  • FIG. 2 is a circuit diagram of a determination circuit according to an embodiment of the present disclosure
  • FIG. 3 is a circuit diagram of a first adjustment circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a circuit diagram of a second adjustment circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a circuit diagram of a third adjustment circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a circuit diagram of a fourth adjustment circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a voltage adjustment method according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of another voltage adjustment method according to an embodiment of the present disclosure.
  • FIG. 9 is a circuit diagram of a driving circuit according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the core voltage required by the timing controller provides more current than the voltage required by other devices. Therefore, in order to ensure the stability of the core voltage of the timing controller, high requirements are placed on the printed circuit board layout (PCB Layout).
  • PCB Layout the printed circuit board layout
  • the core voltage is generated by the power control chip.
  • the stability of the core voltage is ensured by increasing the line width of the printed circuit board to reduce the line loss, thereby ensuring the timing.
  • the stability of the core voltage received by the controller ensures that the timing controller can continue to work normally, thus making the display panel work normally.
  • the timing controller generally uses a Quad Flat No-lead Package (QFN).
  • QFN Quad Flat No-lead Package
  • the wiring of the package in the design of the printed circuit board does not need to pass through an IC (integrated circuit) to make the wiring space. Large, so increasing the line width is achievable, and the implementation is simple and low cost.
  • the resolution and refresh frequency of the display panel are gradually increasing, and the number of pins of the timing controller is gradually increasing.
  • the timing controller of the QFN package cannot meet the demand, and the pin grid array packaging technology is insufficient.
  • the (Pin Grid Array Package, PGA) package has gradually replaced the QFN package.
  • the PGA package pins are under the IC, the pitch between the two pins is limited, the wiring space is limited, and the trace width is also limited, which leads to the stability of the core voltage by increasing the line width.
  • the method is not feasible and the effectiveness cannot be guaranteed.
  • the display panel is in different operating environments or as the running time is lengthened, the power consumption will increase, the current of the core voltage will also increase, and the line loss will increase. Therefore, in addition to the limitations of the package, this situation also reduces the effectiveness of the method of ensuring the stability of the core voltage by increasing the line width.
  • the stability of the core voltage input to the timing controller is ensured by increasing the line width, the resolution and the refresh rate of the display panel cannot be satisfied in the process of packaging the timing controller using the QFN technology.
  • the feasibility of using PGA technology to package the timing controller is not high, and the effectiveness is not guaranteed.
  • the operating environment and running time of the display panel also limit the core voltage supplied to the timing controller.
  • the stability and effectiveness of the core voltage ultimately provided to the timing controller is reduced. Therefore, by increasing the line width, the stability of the core voltage input to the timing controller cannot be ensured, resulting in a decrease in the stability of the display panel driving circuit, and an abnormal display may occur on the display panel.
  • At least one embodiment of the present disclosure provides a voltage regulation system for an electronic device that can self-adjust a voltage supplied to an electronic device, thereby improving stability of the electronic device. At least one embodiment of the present disclosure also provides a driving circuit and a voltage adjusting method corresponding to the above voltage regulating system.
  • One embodiment of the present disclosure provides a voltage regulation system for use in an electronic device 20 as shown in FIG. 1A, the voltage regulation system including a power supply circuit 10, a determination circuit 30, and an adjustment circuit 40.
  • the reference voltage V C can be provided to the decision circuit 30 for subsequent processing.
  • the first voltage V B input to the electronic device 20 may be the core voltage of the electronic device 20, for example, the core voltage is the voltage of the core chip that drives the electronic device 20.
  • the first voltage V B in the embodiment of the present disclosure represents the voltage input to the electronic device 20, such as the voltage input to the core chip in the electronic device 20, that is, It is said that the first voltage V B is a voltage close to the side of the electronic device 20, that is, the receiving voltage received by the electronic device 20, instead of the output voltage near the side of the power supply circuit 10, the receiving voltage and the output voltage are due to the voltage of the wire itself.
  • the drop may be different.
  • the power supply circuit 10 can be disposed in a power control chip.
  • the determination circuit 30 is connected to the power supply circuit 10 and the adjustment circuit 40, and is configured to output a compensation voltage V D according to the reference voltage V C and the first voltage V B .
  • the determination circuit 30 can directly receive the reference voltage V C supplied from the power supply circuit 10.
  • the judging circuit 30 can acquire the first voltage V B supplied from the power supply circuit 10 to the electronic device 20 on the side close to the electronic device 20.
  • the determination circuit 30 may process the reference voltage V C and the first voltage V B to output a compensation voltage V D , for example, the compensation voltage V D may be supplied to the adjustment circuit. 40 for subsequent processing.
  • the decision circuit 30 is configured to perform a difference process on the reference voltage V C and the first voltage V B to obtain a compensation voltage V D , that is, the compensation voltage V D may be the reference voltage V C and the first The difference between the voltages V B .
  • the adjustment circuit 40 is connected to the determination circuit 30 to receive the compensation voltage V D , and is configured to output the third voltage according to the compensation voltage V D and the additionally received second voltage V E when the compensation voltage V D is not within the preset range. V A .
  • the third voltage V A output by the adjustment circuit 40 may be supplied to the power supply circuit 10, and the power supply circuit 10 adjusts the output voltage based on the third voltage V A .
  • the adjustment circuit 40 can be disposed in the same integrated circuit or chip as the power supply circuit 10.
  • the adjustment circuit 40 can also be disposed on the power control chip. In order to simplify the circuit structure.
  • the power supply circuit 10 is further configured to generate or adjust the supplied first voltage V B according to the third voltage V A .
  • a wire may be disposed between the power supply circuit 10 and the electronic device 20 (eg, a core chip in the electronic device 20), and the power supply circuit 10 may directly output a third voltage V A , the third voltage V A is transmitted to the electronic device 20 through the above-described wires, and becomes the first voltage V B input to the electronic device 20, that is, the power supply circuit 10 supplies the first voltage V B according to the third voltage V A .
  • the third voltage V A has a voltage drop during transmission, which may cause the first voltage V B input to the electronic device 20 to be less than the third voltage V A .
  • the second voltage V E is the reference voltage V C , ie, the second voltage V E is equal to the reference voltage V C .
  • the adjustment circuit 40 can be connected to the power supply circuit 10 so that the reference voltage V C supplied from the power supply circuit 10 can be received as the second voltage V E .
  • the adjustment circuit 40 can output the third voltage V A according to the reference voltage V C and the compensation voltage V D .
  • the second voltage V E may also be a voltage obtained based on a change in the reference voltage V C .
  • the adjustment circuit 40 outputs the third voltage V A according to the reference voltage V C and the compensation voltage V D ; then, in the n+1th voltage adjustment, the adjustment circuit 40 can be the nth time
  • the third voltage V A outputted in the voltage regulation is used as the second voltage V E required for the n+1th voltage adjustment; for example, in each subsequent voltage adjustment, the adjustment circuit 40 can output the last voltage adjustment.
  • the third voltage V A serves as the second voltage V E required for the current voltage regulation.
  • n is an integer greater than zero.
  • the voltage regulation system further includes a voltage feedback circuit 50.
  • the voltage feedback circuit 50 is connected to the adjustment circuit 40 and configured to obtain the second voltage V E according to the reference voltage V C and the third voltage V A and to supply to the adjustment circuit 40 when the adjustment circuit 40 outputs the third voltage V A .
  • the adjustment circuit 40 outputs the third voltage V A, V A and the third voltage may be provided to the voltage feedback circuit 50, while the voltage feedback circuit 50 may also receive a reference voltage supply circuit 10 is provided V C ; Then, in the n+1th voltage regulation, the voltage feedback circuit 50 can obtain the second voltage V E according to the reference voltage V C and the third voltage V A and supply it to the adjustment circuit 40 for voltage regulation.
  • the second voltage V E obtained by the adjustment circuit 40 in the n+1th voltage adjustment is equal to the third voltage V A outputted in the nth voltage adjustment.
  • voltage feedback circuit 50 can include an analog to digital conversion circuit and a voltage conversion circuit. For example, after receiving the third voltage V A , the voltage feedback circuit 50 can convert the third voltage V A into a corresponding digital signal by using an analog-to-digital conversion circuit, and the digital signal can be stored, for example, in a memory or a register, and then The voltage conversion circuit may generate the second voltage V E according to the digital signal and the reference voltage V C and make the second voltage V E and the third voltage V A equal.
  • the voltage regulation system can adjust and stabilize the first voltage V B input to the electronic device 20 such that the core voltage obtained by the electronic device 20 remains stable.
  • the stable core voltage required by the electronic device 20 is 1.2V
  • the preset range of the compensation voltage V D is set to be -0.2V to 0.2V, when the power supply circuit 10 is provided to the electronic device 20
  • the first voltage V B is in the range of 1 V to 1.4 V
  • the reference voltage V C supplied from the power supply circuit 10 can also be made 1.2V.
  • the power supply circuit 10 supplies the third voltage V A and the reference voltage V C , for example, the third voltage V A and the reference voltage V C are both 1.2. V.
  • the first voltage V B input to the electronic device 20 is smaller than the third voltage V A due to the voltage drop of the wire, for example, the first voltage V B becomes 0.9V, that is, on the wire.
  • the pressure drop is 0.3V.
  • the adjustment circuit 40 first determines that the compensation voltage V D is not within the preset range of -0.2V to 0.2V, and then according to the compensation voltage V D and the second voltage V E (in this example The second voltage V E is the reference voltage V C ) outputting the third voltage V A , for example, the compensation voltage V D (0.3V) and the second voltage V E (1.2V) are summed to obtain the third voltage V A . 1.5V. Then, the third voltage V A is directly supplied to the power supply circuit 10, and the power supply circuit 10 outputs the third voltage V A . Assuming that the voltage drop on the wire is still 0.3 V at this time, the third voltage V A is transmitted to the electronic device. After 20, it becomes 1.2V, that is, the first voltage V B supplied from the power supply circuit 10 to the electronic device 20 after the voltage adjustment is 1.2V.
  • the first voltage V B supplied from the power supply circuit 10 can be made to satisfy the requirement by one adjustment.
  • the adjustment circuit 40 employs the reference voltage V C as the second voltage V E , so the voltage feedback circuit 50 shown in FIG. 1B may not be provided.
  • the adjusted first voltage V B provided by the power supply circuit 10 may change. For example, if the voltage drop across the wire changes from 0.3V to 0.7V, the first voltage V B provided by the power supply circuit 10 will drop from 1.2V to 0.8V, whereby the voltage received by the electronic device 20 no longer satisfies the electron.
  • the core voltage required by device 20 is required to continue the second voltage regulation.
  • the reference voltage V C supplied from the power supply circuit 10 remains unchanged at 1.2 V, and the determination circuit 30 can perform a difference processing on the reference voltage V C (1.2 V) and the first voltage V B (0.8 V) to obtain compensation.
  • the voltage V D that is, the compensation voltage V D is 0.4V.
  • the adjustment circuit 40 first determines that the compensation voltage V D is not within the preset range of -0.2V to 0.2V, and then according to the compensation voltage V D and the second voltage V E (in this example The second voltage V E is the third voltage V A outputted by the regulating circuit 40 in the first voltage adjustment, that is, 1.5V), and outputs the third voltage V A , for example, the compensation voltage V D (0.4V) and the second voltage V E (1.5 V) is summed to obtain a third voltage V A of 1.9V. Then, the third voltage V A is directly supplied to the power supply circuit 10, and the power supply circuit 10 outputs the third voltage V A .
  • the third voltage V A is transmitted to the electronic device. After 20, it becomes 1.2V, that is, the first voltage V B supplied from the power supply circuit 10 to the electronic device 20 is 1.2V.
  • the voltage regulation system can still adjust the first voltage V B to satisfy the electronic device 20 Core voltage requirements.
  • the voltage feedback circuit 50 shown in FIG. 1B needs to be set.
  • the two independent loops can respectively generate the third voltage V A and the reference voltage V C , and the two independent loops are independent of each other. They are not affected by each other.
  • the manner in which the power supply circuit 10 generates the third voltage V A includes, but is not limited to, some or all of the following:
  • a circuit such as a buck circuit or a boost converter circuit.
  • the third voltage V A and the reference voltage V C output by the power supply circuit 10 can be made equal to the core voltage required by the electronic device 20, for example, 1.2. V. Then, in subsequent voltage regulation, the power supply circuit 10 can receive the third voltage V A output by the adjustment circuit 40 and directly output the third voltage V A to provide a first voltage input to the electronic device 20.
  • the voltage supplied to the electronic device (for example, the core voltage required by the electronic device) can be adjusted and stabilized, thereby improving the stability of the electronic device.
  • the power supply circuit 10 can be disposed in a power control chip, and the electronic device 20 is a timing controller in the display panel driving circuit. Improving the stability of the timing controller can improve the stability of the display panel driving circuit. This prevents an abnormal display from appearing on the display panel.
  • the first voltage V B input to the electronic device 20 is provided by the power supply circuit 10.
  • the current of the third voltage V A output from the power supply circuit 10 is large, and there is a large line loss during transmission, so the first voltage V B input to the electronic device 20 is smaller than the third voltage V A . Based on this, when the first voltage V B input to the electronic device 20 is acquired, the acquisition can be performed on the side close to the electronic device 20.
  • the third voltage V A output from the power supply circuit 10 is 1.2 V
  • the magnitude of the first voltage V B input to the electronic device 20 is 0.9 V due to the transmission wire loss.
  • Embodiments of the present disclosure acquire a first voltage V B input to the electronic device 20 on the core voltage input side of the electronic device 20 .
  • the judging circuit 30 includes a first operational amplifier OA1, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.
  • the first end of the first resistor R1 is configured to receive the first voltage V B , and the second end of the first resistor R1 is coupled to the inverting input of the first operational amplifier OA1.
  • the first end of the second resistor R2 is connected to the inverting input terminal of the first operational amplifier OA1, and the second end of the second resistor R2 is connected to the output terminal of the first operational amplifier OA1.
  • the first end of the third resistor R3 is configured to receive the reference voltage V C , and the second end of the third resistor R3 is coupled to the non-inverting input of the first operational amplifier OA1.
  • the first end of the fourth resistor R4 is connected to the non-inverting input of the first operational amplifier OA1, and the second end of the fourth resistor R4 is grounded.
  • the output of the first operational amplifier OA1 is coupled to the regulation circuit 40 and is configured to output a compensation voltage V D .
  • the first voltage V B obtained near the side of the electronic device 20 is input to the inverting input terminal of the first operational amplifier OA1 through the first resistor R1, and the reference voltage V output from the power supply circuit 10 is used.
  • C is input to the non-inverting input terminal of the first operational amplifier OA1 through the third resistor R3, so that when the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 satisfy certain conditions, the first operational amplifier OA1 passes through The output voltage is the difference between the two voltages input.
  • the current of the third voltage V A outputted by the power supply circuit 10 is large, and there is a large line loss during transmission, so the first voltage V B input to the first operational amplifier OA1 is higher than the third voltage V A small.
  • the third voltage V A output from the power supply circuit 10 is 1.2 V
  • the magnitude of the first voltage V B input to the first operational amplifier OA1 may be 0.9 V due to the influence of the line loss.
  • the inverting input of the first operational amplifier OA1 is brought close to the core voltage input of the electronic device 20 during the layout of the printed circuit board.
  • the reference voltage V C output from the power supply circuit 10 is 1.2V.
  • the current of the reference voltage V C outputted by the power supply circuit 10 is small, so that when the printed circuit board wiring is reasonable, the line loss of the reference voltage V C during transmission is negligible, and is transmitted to the non-inverting input terminal of the first operational amplifier OA1.
  • the power supply circuit 10 includes a loop that outputs a reference voltage V C , and the loop is completely independent from other voltages.
  • the compensation voltage V D outputted by the first operational amplifier OA1 can be determined by the following formula:
  • V D (R4/(R3+R4))*((R1+R2)/R1)*V C -(R2/R1)*V B
  • the difference between the reference voltage V C output by the power supply circuit 10 and the first voltage V B input to the electronic device 20, that is, the compensation voltage V can be accurately calculated by the first operational amplifier OA1. D.
  • circuit diagram shown in FIG. 2 is only an example, and any circuit capable of determining the difference between the reference voltage V C output from the power supply circuit 10 and the first voltage V B input to the electronic device 20 through the operational amplifier is Suitable for embodiments of the present disclosure.
  • the adjustment circuit 40 includes: a second operational amplifier OA2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth Resistor R8.
  • the first end of the fifth resistor R5 is configured to receive the second voltage V E , and the second end of the fifth resistor R5 is coupled to the inverting input of the second operational amplifier OA2.
  • the first end of the sixth resistor R6 is configured to receive the compensation voltage V D , and the second end of the sixth resistor R6 is coupled to the inverting input of the second operational amplifier OA2.
  • the first end of the seventh resistor R7 is connected to the non-inverting input of the second operational amplifier OA2, and the second end of the seventh resistor R7 is grounded.
  • the first end of the eighth resistor R8 is coupled to the inverting input of the second operational amplifier OA2, and the second end of the eighth resistor R8 is coupled to the output of the second operational amplifier OA2.
  • the output of the second operational amplifier OA2 is configured to output a third voltage V A , for example, the third voltage V A can be transmitted to the power supply circuit 10 such that the power supply circuit 10 can provide the first voltage V according to the third voltage V A B.
  • the compensation voltage V D is the voltage output from the first operational amplifier OA1 in the determination circuit 30 (ie, the reference voltage V C output from the power supply circuit 10 determined by the determination circuit 30 and the input to the electronic device 20
  • the difference between the voltage V B and the second voltage V E is the reference voltage V C output from the power supply circuit 10 or the voltage output from the voltage feedback circuit 50.
  • the resistors R5, R6, R7, and R8 are resistors of a fixed resistance.
  • the adjustment circuit 40 determines that the received compensation voltage V D is not within the preset range, the adjustment circuit 40
  • the compensation voltage V D and the second voltage V E may be processed to output a third voltage V A , and the output third voltage V A may be transmitted to the power supply circuit 10, for example, and the third voltage V A is output through the power supply circuit 10, and finally It is input to the electronic device 20.
  • the third voltage V A outputted by the second operational amplifier OA2 can be determined by the following formula:
  • V A R8*(V D /R6+V E /R5)
  • the compensation voltage V D and the second voltage V E are processed by the adjustment circuit 40 to output the third voltage V A , which ensures that the first voltage V B transmitted to the electronic device 20 is in a stable range.
  • the adjustment circuit 40 receives the third voltage V A , and the third voltage V A , and the third voltage V A , which ensures that the first voltage V B transmitted to the electronic device 20 is in a stable range.
  • an abnormal display of the display panel during operation can be avoided.
  • the eighth resistor R8 is a variable resistor, and the eighth resistor R8 includes: N resistors R and N first switches K1; the adjustment circuit 40 further includes The first processing circuit 41.
  • the N resistors R and the N first switches K1 are in one-to-one correspondence.
  • the first end of each of the N resistors R is connected to the inverting input terminal of the second operational amplifier OA2 through the corresponding first switch K1, and the second end and the second operation of each of the N resistors R
  • the output of amplifier OA2 is connected.
  • the first processing circuit 41 is connected to the N first switches K1 of the determination circuit 30 and the eighth resistor R8, and is configured to control N first of the eighth resistors R8 when the compensation voltage V D is not within the preset range.
  • Each of the switches K1 is opened or closed.
  • N is an integer greater than one.
  • the eighth resistor R8 includes two and/or two or more resistors R, and the number of resistors R in the eighth resistor R8 and the resistance of each resistor R can be determined experimentally according to application scenarios, requirements, and the like.
  • the determination circuit 30 inputs the difference between the reference voltage V C output from the power supply circuit 10 and the first voltage V B input from the power supply circuit 10 to the electronic device 20, that is, the compensation voltage V D , to the adjustment circuit 40.
  • the first processing circuit 41 determines whether the compensation voltage V D is within a preset range according to the value of the received compensation voltage V D . If the compensation voltage V D is not within the preset range, the first processing is performed.
  • the circuit 41 can control the N first switches K1 of the eighth resistor R8 to close one or more of the N first switches K1 of the eighth resistor R8, so that the resistance of the eighth resistor R8 can be performed.
  • the third voltage V A outputted by the second operational amplifier OA2 is adjusted, and the output third voltage V A can be outputted, for example, through the power supply circuit 10, and finally input to the electronic device 20.
  • the resistance of the eighth resistor R8 can be changed by adjusting the state of the plurality of first switches K1 in the eighth resistor R8, thereby achieving the adjustment.
  • the purpose of the three voltages V A is such that the first voltage V B ultimately transmitted into the electronic device 20 is within a stable range.
  • the adjustment circuit 40 in the voltage regulation system further includes a second switch K2 and a second processing circuit 42.
  • the first switch K2 and the first end of the sixth resistor R6 are coupled to the second processing circuit 42; the second processing circuit 42 is coupled to the decision circuit 30 and is configured to control the second switch K2 to open or close.
  • the second processing circuit 42 when the second processing circuit 42 receives the compensation voltage V D and determines that the compensation voltage V D is within a preset range, the second processing circuit 42 can control the second switch K2.
  • the second switch K2 is placed in an off state.
  • the inverting input terminal of the second operational amplifier OA2 receives only the second voltage V E input through the fifth resistor R5; when the second processing circuit 42 determines that the compensation voltage V D is not present
  • the second processing circuit 42 can control the second switch K2 to make the second switch K2 in a closed state.
  • the inverting input terminal of the second operational amplifier OA2 can receive the input through the fifth resistor R5 at the same time.
  • the second voltage V E and the compensation voltage V D input through the sixth resistor R6.
  • the second processing circuit 42 controls the second switch K2 to close.
  • the compensation voltage V D does not exceed the preset range, that is, when the first voltage V B input to the electronic device 20 is in a stable range, the load of the circuit can be lowered, so that the power consumption of the circuit can be reduced.
  • the eighth resistor R8 is a variable resistor, the eighth resistor R8 includes N resistors R and N first switches K1; and the adjustment circuit 40 further includes processing Circuit 43 and second switch K2.
  • the N resistors R and the N first switches K1 are in one-to-one correspondence.
  • a first end of each of the N resistors R is connected to an inverting input terminal of the second operational amplifier OA2 through a corresponding first switch K1, and a second end of each of the N resistors R
  • the output terminals of the two operational amplifiers OA2 are connected.
  • the first end of the second switch K2 and the sixth resistor R6 are connected to the processing circuit 43.
  • the processing circuit 43 is connected to the second switch K2, the determination circuit 30, and the N first switches K1, and is configured to control each of the N first switches K1 to be disconnected when the compensation voltage V D is not within the preset range Closing, and controlling the second switch K2 to open or close.
  • N is an integer greater than one.
  • the processing circuit 43 in the adjustment circuit 40 is connected to both the N first switches K1 and the second switch K2 in the eighth resistor R8.
  • the processing circuit 43 in the adjusting circuit 40 receives the compensation voltage V D outputted by the determining circuit 30, it first determines whether the compensation voltage V D is within a preset range, and then the processing circuit 43 can control the eighth resistor R8 according to the determination result.
  • the opening or closing of the N first switches K1 can also control the opening or closing of the second switch K2.
  • the processing circuit 43 may control one or more of the resistors R8 to be closed while controlling the second switch K2 to close.
  • the opening or closing of the N first switches K1 and the second switch K2 in the eighth resistor R8 is simultaneously controlled by a processing circuit 43 so that the compensation voltage V D outputted by the first operational amplifier OA1 can be While inputting to the second operational amplifier OA2, the resistance of the eighth resistor R8 can also be adjusted, so that the third voltage V A outputted by the second operational amplifier OA2 can be ensured.
  • the power supply circuit 10 is disposed in a power control chip; the electronic device 20 is a timing controller.
  • the adjustment circuit 40 may also be disposed in the power control chip, thereby simplifying the circuit structure and improving the integrity of the voltage regulation system.
  • the power control chip can provide the first voltage V B input to the electronic device 20 and the reference voltage V C ;
  • the electronic device 20 is a timing controller, and the timing controller can Receiving the first voltage V B and acting as a core voltage, the timing controller can output a control signal for the display panel under the driving of the core voltage, thereby controlling the display panel to perform a normal display operation.
  • embodiments of the present disclosure also provide a voltage regulation method that can be used in a voltage regulation system provided by any of the embodiments of the present disclosure. It should be noted that, since the system corresponding to the method is a system for voltage regulation provided by an embodiment of the present disclosure, and the principle of the method for solving the problem is similar to the system, the implementation of the method can be referred to the foregoing regarding the voltage regulation system. Implementation, repetition will not be repeated.
  • Step 400 The power supply circuit 10 is caused to provide the reference voltage V C and the first voltage V B ; the first voltage V B is the voltage input to the electronic device 20, and the description about the first voltage V B can be referred to the above regarding the voltage regulation system. The corresponding description will not be repeated here.
  • Step 401 The determination circuit 30 is caused to obtain the compensation voltage V D according to the reference voltage V C and the first voltage V B ; for example, in one example, the determination circuit 30 can be caused to perform the difference between the reference voltage V C and the first voltage V B Processing to obtain a compensation voltage V D .
  • Step 402 When the compensation voltage V D is not within the preset range, the adjustment circuit 40 is caused to obtain the third voltage V A according to the compensation voltage V D and the second voltage V E ; it should be noted that the second voltage V E can be referred to The above description of the voltage regulation system will not be repeated here. as well as
  • Step 403 The power supply circuit 10 is caused to provide the first voltage V B according to the third voltage V A .
  • the voltage adjustment method provided by the embodiment of the present disclosure further includes: providing the third voltage V A output by the adjustment circuit 40 to the adjustment circuit 40 again. As the second voltage V E .
  • the adjustment circuit 40 outputs the third voltage V A, V A and the third voltage may be provided to the voltage feedback circuit 50, while the voltage feedback circuit 50 may also receive a reference voltage supply circuit 10 is provided V C ; Then, in the n+1th voltage regulation, the voltage feedback circuit 50 can obtain the second voltage V E according to the reference voltage V C and the third voltage V A and supply it to the adjustment circuit 40 for voltage regulation.
  • the second voltage V E obtained by the adjustment circuit 40 in the n+1th voltage adjustment is equal to the third voltage V A outputted in the nth voltage adjustment.
  • the above step 402 may include the following operations:
  • the processing circuit 43 closes the second switch K2 when it is determined that the compensation voltage V D is not within the preset range, so that the compensation voltage V D is input to the second operational amplifier OA2.
  • step 402 may include the following operations:
  • the voltage value of the third voltage V A output from the adjustment circuit 40 is adjusted by adjusting the resistance of the eighth resistor R8.
  • the above step 402 may include the following operations.
  • the compensation voltage V D is less than the minimum value of the preset range, the voltage value of the third voltage V A output by the adjustment circuit 40 is decreased.
  • the preset range is -0.2V to 0.2V
  • the compensation voltage V D outputted by the determination circuit 30 is 0.3V
  • the compensation voltage V D is not within the preset range, and is greater than the preset range.
  • the maximum value increases the voltage value of the third voltage V A output from the adjustment circuit 40.
  • the eighth resistor R8 is a variable resistor
  • the voltage value of the third voltage V A output from the regulator circuit 40 can be increased by increasing the resistance value of the eighth resistor R8.
  • the preset range is -0.2V to 0.2V
  • the compensation voltage V D outputted by the determination circuit is -0.3V
  • the compensation voltage V D is not within the preset range, and is less than the preset range.
  • the minimum value reduces the voltage value of the third voltage V A output from the adjustment circuit 40.
  • the eighth resistor R8 is a variable resistor
  • the voltage value of the third voltage V A output from the regulator circuit 40 can be reduced by reducing the resistance value of the eighth resistor R8.
  • the adjustment circuit 40 determines whether the compensation voltage V D is within a preset range, and then adjusts the first voltage V B input to the electronic device 20 provided by the power supply circuit 10 according to the determination result, It is ensured that the compensation voltage V D is within a preset range, so that the first voltage V B input to the electronic device 20 remains stable, so that, for example, the risk of abnormal display of the display panel can be reduced.
  • an embodiment of the present disclosure further provides a voltage adjustment method, the method comprising the following operations.
  • Step 500 The determining circuit 30 acquires the first voltage V B input to the timing controller
  • Step 501 The determining circuit 30 obtains the reference voltage V C output by the power control chip
  • Step 502 The determining circuit 30 performs a difference processing on the reference voltage V C and the first voltage V B to obtain a compensation voltage V D ;
  • Step 503 The processing circuit 43 determines whether the compensation voltage V D is within a preset range. If it is within the preset range, step 500 is performed; otherwise, step 504 is performed.
  • the processing circuit 43 is a circuit provided in the adjustment circuit 40.
  • Step 504 If the compensation voltage V D is not within the preset range, the adjustment circuit 40 is triggered to perform adjustment;
  • Step 505 After receiving the trigger of the processing circuit 43, the adjustment circuit 40 closes a switch for connecting a path between the output end of the first operational amplifier OA1 and the inverting input terminal of the second operational amplifier OA2; for example, the switch is a diagram 5 or the second switch K2 in FIG.
  • Step 506 The adjustment circuit 40 adjusts the voltage input to the timing controller provided by the power control chip through the second operational amplifier OA2.
  • the voltage adjustment method provided in this embodiment can improve the stability of the timing controller, so that the stability of the display panel functioning by the timing controller can be improved, so that abnormal display of the display panel can be avoided.
  • an embodiment of the present disclosure further provides a driving circuit for driving a timing controller 71, which includes a power control chip 70 and a determining circuit 30.
  • the timing controller 71 includes a core voltage input terminal IV, for example, the core voltage input terminal IV for receiving the first voltage V B and using the first voltage V B as a core voltage for driving the core chip of the timing controller 71
  • the judgment circuit 30 includes a first operational amplifier OA1, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.
  • the power control chip 70 includes a reference voltage output terminal VCO, a compensation voltage input terminal VDI, a second voltage input terminal VEI, a third voltage output terminal VAO, a processing circuit 43, a second operational amplifier OA2, a fifth resistor R5, and a sixth resistor R6. a seventh resistor R7, an eighth resistor R8, and a second switch K2.
  • the first end of the first resistor R1 is connected to the core voltage input terminal IV to receive the first voltage V B , the second end of the first resistor R1 is connected to the inverting input end of the first operational amplifier OA1; the second resistor R2 is One end is connected to the inverting input terminal of the first operational amplifier OA1, the second end of the second resistor R2 is connected to the output end of the first operational amplifier OA1, and the first end of the third resistor R3 is connected to the reference voltage output terminal VCO.
  • the second end of the third resistor R3 is connected to the non-inverting input end of the first operational amplifier OA; the first end of the fourth resistor R4 is connected to the non-inverting input end of the first operational amplifier OA1, and the fourth resistor R4 The second terminal is grounded; the output of the first operational amplifier OA1 is coupled to the compensation voltage input terminal VDI of the power control chip 70 for providing the compensation voltage V D to the power control chip 70.
  • the processing circuit 43 is connected to the compensation voltage input terminal VDI and the second switch K2; the second switch K2 is also connected to the first terminal of the sixth resistor R6; the second terminal of the sixth resistor R6 is opposite to the inverting input of the second operational amplifier OA2
  • the first end of the fifth resistor R5 is connected to the second voltage input terminal VEI to receive the second voltage V E , and the second end of the fifth resistor R5 is connected to the inverting input end of the second operational amplifier OA2;
  • the first end of the resistor R7 is connected to the non-inverting input terminal of the second operational amplifier OA2, the second end of the seventh resistor R7 is grounded, and the first end of the eighth resistor R8 is connected to the inverting input end of the second operational amplifier OA2,
  • the second end of the eight resistor R8 is connected to the output of the second operational amplifier OA2; the output of the second operational amplifier OA2 is connected to the third voltage output terminal VAO of the power control chip 70 for out
  • the type of the eighth resistor R8 is not limited.
  • the eighth resistor R8 may be a resistor of a fixed resistance; for example, as shown in FIG. 9, the eighth resistor R8 is variable. resistance.
  • the eighth resistor R8 is a variable resistor, and the eighth resistor R8 includes N resistors R and N first switches K1.
  • the N resistors R and the N first switches K1 are in one-to-one correspondence; the first end of each of the N resistors R is connected to the inverting input terminal of the second operational amplifier OA2 through the corresponding first switch K1, N A second end of each of the resistors R is coupled to an output of the second operational amplifier OA2.
  • the eighth resistor R8 includes four resistors R, but is not limited to four in practical applications, and the number of resistors R and the magnitude of the resistors in the eighth resistor R8 can be set according to actual conditions.
  • An embodiment of the present disclosure further provides a display device 1 including any of the voltage regulation system 100, the timing controller 71, and the display panel 200 provided by the embodiments of the present disclosure.
  • the voltage regulation system 100 is configured to drive the timing controller 71, for example, in one example, the voltage regulation system 100 is configured to provide a stable core voltage to the timing controller 71, such as the core of the drive timing controller 71.
  • the voltage of the chip is configured to provide a stable core voltage to the timing controller 71, such as the core of the drive timing controller 71. The voltage of the chip.
  • the timing controller 71 is configured to provide a control signal to the display panel 200.
  • the display device 1 may further include a gate driving circuit 300 and a data driving circuit 400, and the timing controller 71 and the gate driving circuit, respectively. 300 and data drive circuit 400 are coupled to provide a control signal.
  • the display device 1 includes a display panel 200 in which a pixel array composed of a plurality of sub-pixel units 210 is disposed.
  • the output terminals of each stage of the shift register unit in the gate driving circuit 300 are electrically connected to the sub-pixel units 210 of different rows, for example, the gate driving circuit 300 is electrically connected to the sub-pixel unit 210 through the gate line GL.
  • the gate driving circuit 300 is for providing a driving signal to the pixel array, for example, the driving signal can drive the scanning transistor in the sub-pixel unit 210.
  • data drive circuit 400 is used to provide a data signal to a pixel array.
  • the data driving circuit 400 is electrically connected to the sub-pixel unit 210 through the data line DL.
  • the display device 1 in this embodiment may be: a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigation device, etc. Functional product or part.
  • the display device 1 may further include other conventional components such as a display panel, and embodiments of the present disclosure are not limited thereto.
  • the display device 1 provided by the embodiment of the present disclosure can adjust and stabilize the voltage supplied to the timing controller 71 by the voltage regulation system 100, thereby improving the stability of the timing controller 71 during operation, thereby improving the display panel 200 (display device) 1) Stability during operation to avoid abnormal display of the display panel 200 (display device 1).
  • the present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, systems (devices), and computer program products according to embodiments of the present disclosure. It will be understood that each flow and/or block of the flowcharts and/or FIG.
  • the computer program instructions can be provided to a processing circuit of a general purpose computer, a special purpose computer, an embedded processor, or other programmable data processing system to produce a machine instruction that is executed by a processing circuit of a computer or other programmable data processing system A method for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing system to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing system to perform a series of operational steps on a computer or other programmable system to produce computer-implemented processing for execution on a computer or other programmable system.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

一种电压调节系统、驱动电路、显示装置和电压调节方法。该电压调节系统用于一电子设备(20)，包括供电电路(10)、判断电路(30)和调节电路(40)。供电电路(10)与调节电路(40)连接，且被配置为提供基准电压(V C)并提供输入到电子设备(20)的第一电压(V B)；判断电路(30)与供电电路(10)连接，且被配置为根据基准电压(V C)和第一电压(V B)输出补偿电压(V D)；调节电路(40)与判断电路(30)连接以接收补偿电压(V D)，且被配置为在补偿电压(V D)不在预设范围内时，根据补偿电压(V D)以及第二电压(V E)输出第三电压(V A)；供电电路(10)还被配置为根据第三电压(V A)提供第一电压(V B)，第二电压(V E)为基准电压(V C)或基于基准电压(V C)变化而获得的电压。该电压调节系统可以自我调节提供至电子设备的电压，从而提高该电子设备的稳定性。

Description

电压调节系统、驱动电路、显示装置和电压调节方法
本申请要求于2017年9月29日递交的中国专利申请第201710908807.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种电压调节系统、驱动电路、显示装置和电压调节方法。
背景技术
时序控制器是显示面板驱动电路的重要元器件，它能将前端系统输入的信号通过数据处理转换为显示面板所需要的控制信号。时序控制器产生控制信号一般需要两种电压：内核电压和I/O(input/output，输入/输出)电压，内核电压是指驱动时序控制器核心芯片的电压，I/O电压是指驱动I/O电路的电压。时序控制器对内核电压的电压和电流的要求非常严格，如果内核电压异常，则时序控制器不能正常工作。而由于时序控制器对显示面板的重要性，如果内核电压异常，显示面板可能会出现不能正常开机、反复开关机、花屏等异常显示的情况。因此保证内核电压的稳定性，对于提升显示面板驱动电路的稳定性，防止显示面板出现异常显示是非常重要的。
发明内容
本公开的至少一实施例提供一种电压调节系统，用于一电子设备，包括供电电路、判断电路和调节电路。所述供电电路与所述调节电路连接，且被配置为提供基准电压并提供输入到所述电子设备的第一电压；所述判断电路与所述供电电路连接，且被配置为根据所述基准电压和所述第一电压输出补偿电压；所述调节电路与所述判断电路连接以接收所述补偿电压，且被配置为在所述补偿电压不在预设范围内时，根据所述补偿电压以及第二电压输出第三电压；所述供电电路还被配置为根据所述第三电压提供所述第一电压， 所述第二电压为所述基准电压或基于所述基准电压变化而获得的电压。
例如，在本公开一实施例提供的电压调节系统中，所述判断电路被配置为对所述基准电压和所述第一电压进行求差处理以获得所述补偿电压。
例如，在本公开一实施例提供的电压调节系统中，所述第二电压与所述基准电压相等。
例如，本公开一实施例提供的电压调节系统还包括电压反馈电路，所述电压反馈电路与所述调节电路连接，被配置为在所述调节电路输出所述第三电压时，根据所述基准电压和所述第三电压获得所述第二电压并提供至所述调节电路。
例如，在本公开一实施例提供的电压调节系统中，所述判断电路包括：第一运算放大器、第一电阻、第二电阻、第三电阻和第四电阻。所述第一电阻的第一端被配置为接收所述第一电压，所述第一电阻的第二端与所述第一运算放大器的反相输入端连接；所述第二电阻的第一端与所述第一运算放大器的反相输入端连接，所述第二电阻的第二端与所述第一运算放大器的输出端连接；所述第三电阻的第一端被配置为接收所述基准电压，所述第三电阻的第二端与所述第一运算放大器的同相输入端连接；所述第四电阻的第一端与所述第一运算放大器的同相输入端连接，所述第四电阻的第二端接地；所述第一运算放大器的输出端被配置为输出所述补偿电压。
例如，在本公开一实施例提供的电压调节系统中，所述调节电路包括：第二运算放大器、第五电阻、第六电阻、第七电阻和第八电阻。所述第五电阻的第一端被配置为接收所述第二电压，所述第五电阻的第二端与所述第二运算放大器的反相输入端连接；所述第六电阻的第一端被配置为接收所述补偿电压，所述第六电阻的第二端与所述第二运算放大器的反相输入端连接；所述第七电阻的第一端与所述第二运算放大器的同相输入端连接，所述第七电阻的第二端接地；所述第八电阻的第一端与所述第二运算放大器的反相输入端连接，所述第八电阻的第二端与所述第二运算放大器的输出端连接；所述第二运算放大器的输出端被配置为输出所述第三电压。
例如，在本公开一实施例提供的电压调节系统中，所述第八电阻为可变电阻，所述第八电阻包括N个电阻和N个第一开关，所述调节电路还包括第一处理电路。所述N个电阻和所述N个第一开关一一对应；所述N个电阻中的每一个电阻的第一端通过对应的所述第一开关与所述第二运算放大 器的反相输入端连接，所述N个电阻中的每一个电阻的第二端与所述第二运算放大器的输出端连接；所述第一处理电路与所述判断电路以及所述第八电阻中的所述N个第一开关连接，且被配置为在所述补偿电压不在预设范围内时控制所述第八电阻中的所述N个第一开关中的每一个断开或闭合；N为大于1的整数。
例如，在本公开一实施例提供的电压调节系统中，所述调节电路还包括第二开关和第二处理电路。所述第二开关和所述第六电阻的第一端以及所述第二处理电路连接；所述第二处理电路与所述判断电路连接，且被配置为控制所述第二开关断开或闭合。
例如，在本公开一实施例提供的电压调节系统中，所述第八电阻为可变电阻，所述第八电阻包括N个电阻和N个第一开关，所述调节电路还包括处理电路和第二开关。所述N个电阻和所述N个第一开关一一对应；所述N个电阻中的每一个电阻的第一端通过对应的所述第一开关与所述第二运算放大器的反相输入端连接，所述N个电阻中的每一个电阻的第二端与所述第二运算放大器的输出端连接；所述第二开关和所述第六电阻的第一端以及所述处理电路连接；所述处理电路与所述第二开关、所述判断电路以及所述N个第一开关连接，且被配置为在所述补偿电压不在预设范围内时控制所述N个第一开关中的每一个断开或闭合，以及控制所述第二开关断开或闭合；N为大于1的整数。
例如，在本公开一实施例提供的电压调节系统中，所述供电电路设置在电源控制芯片中。
例如，在本公开一实施例提供的电压调节系统中，所述调节电路设置在所述电源控制芯片中。
本公开至少一实施例还提供一种如本公开的实施例提供的任一电压调节系统的电压调节方法，包括：使得所述供电电路提供所述基准电压和所述第一电压；使得所述判断电路根据所述基准电压和所述第一电压获得所述补偿电压；在所述补偿电压不在预设范围内时，使得所述调节电路根据所述补偿电压和所述第二电压获得所述第三电压；以及使得所述供电电路根据所述第三电压提供所述第一电压。
例如，在本公开一实施例提供的电压调节方法中，使得所述判断电路根据所述基准电压和所述第一电压获得所述补偿电压包括：使得所述判断电路 对所述基准电压和所述第一电压进行求差处理以获得所述补偿电压。
例如，在本公开一实施例提供的电压调节方法中，在所述电压调节系统包括电压反馈电路的情形下，所述电压调节方法还包括：将所述调节电路输出的所述第三电压再提供至所述调节电路并作为第二电压。
例如，在本公开一实施例提供的电压调节方法中，在所述电压调节系统包括第二开关、处理电路以及第二运算放大器的情形下，使得所述调节电路根据所述补偿电压和所述第二电压获得所述第三电压包括：所述处理电路在确定所述补偿电压不在预设范围内时，闭合所述第二开关，以使得所述补偿电压输入至所述第二运算放大器。
例如，在本公开一实施例提供的电压调节方法中，在所述电压调节系统包括第八电阻且所述第八电阻为可变电阻的情形下，使得所述调节电路根据所述补偿电压和所述第二电压获得所述第三电压还包括：通过调整所述第八电阻的阻值调节所述调节电路输出的所述第三电压的电压值。
例如，在本公开一实施例提供的电压调节方法中，所述使得所述调节电路根据所述补偿电压和所述第二电压获得所述第三电压包括：若补偿电压大于所述预设范围的最大值，则增大所述调节电路输出的所述第三电压的电压值；以及若补偿电压小于所述预设范围的最小值，则减小所述调节电路输出的所述第三电压的电压值。
例如，在本公开一实施例提供的电压调节方法中，所述供电电路设置在电源控制芯片中。
本公开的至少一实施例还提供一种驱动电路，用于驱动一时序控制器，包括电源控制芯片和判断电路。所述时序控制器包括内核电压输入端；所述判断电路包括第一运算放大器、第一电阻、第二电阻、第三电阻和第四电阻；所述电源控制芯片包括基准电压输出端、补偿电压输入端、第二电压输入端、第三电压输出端、处理电路、第二运算放大器、第五电阻、第六电阻、第七电阻、第八电阻和第二开关；所述第一电阻的第一端与所述内核电压输入端连接，所述第一电阻的第二端与所述第一运算放大器的反相输入端连接；所述第二电阻的第一端与所述第一运算放大器的反相输入端连接，所述第二电阻的第二端与所述第一运算放大器的输出端连接；所述第三电阻的第一端与所述基准电压输出端连接，所述第三电阻的第二端与所述第一运算放大器的同相输入端连接；所述第四电阻的第一端与所述第一运算放大器的同相输入 端连接，所述第四电阻的第二端接地；所述第一运算放大器的输出端与所述补偿电压输入端连接；所述处理电路与所述补偿电压输入端以及所述第二开关连接；所述第二开关还与所述第六电阻的第一端连接；所述第六电阻的第二端与第二运算放大器的反相输入端连接；所述第五电阻的第一端与所述第二电压输入端连接，所述第五电阻的第二端与所述第二运算放大器的反相输入端连接；所述第七电阻的第一端与所述第二运算放大器的同相输入端连接，所述第七电阻的第二端接地；所述第八电阻的第一端与所述第二运算放大器的反相输入端连接，所述第八电阻的第二端与所述第二运算放大器的输出端连接；所述第二运算放大器的输出端与所述第三电压输出端连接。
例如，在本公开一实施例提供的驱动电路中，所述第八电阻为可变电阻，所述第八电阻包括N个电阻和N个第一开关；所述N个电阻和所述N个第一开关一一对应；所述N个电阻中的每一个电阻的第一端通过对应的所述第一开关与所述第二运算放大器的反相输入端连接，所述N个电阻中的每一个电阻的第二端与所述第二运算放大器的输出端连接；N为大于1的整数。
本公开至少一实施例还提供一种显示装置，包括本公开的实施例提供的任一电压调节系统、时序控制器和显示面板；所述电压调节系统被配置为驱动所述时序控制器，所述时序控制器被配置为向所述显示面板提供控制信号。
例如，在本公开一实施例提供的显示装置中，所述电压调节系统被配置为向所述时序控制器提供内核电压。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A为本公开的实施例提供的一种电压调节系统的示意图；
图1B为本公开的实施例提供的另一种电压调节系统的示意图；
图2为本公开的实施例提供的一种判断电路的电路图；
图3为本公开的实施例提供的第一种调节电路的电路图；
图4为本公开的实施例提供的第二种调节电路的电路图；
图5为本公开的实施例提供的第三种调节电路的电路图；
图6为本公开的实施例提供的第四种调节电路的电路图；
图7为本公开的实施例提供的一种电压调节方法的示意图；
图8为本公开的实施例提供的另一种电压调节方法的示意图；
图9为本公开的实施例提供的一种驱动电路的电路图；以及
图10为本公开的实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
通常时序控制器所需的内核电压提供的电流相比其他器件所需的电压提供的电流要大。因此，为保证时序控制器的内核电压的稳定，对印刷电路板设计(Printed circuit board Layout，PCB Layout)提出了较高的要求。一般而言，在显示面板驱动电路中，内核电压由电源控制芯片产生，在一种设计中，通过增大印刷电路板的线宽以减小线损来保证内核电压的稳定性，进而保证时序控制器接收到的内核电压的稳定性，保证时序控制器可以持续正常工作，因此使得显示面板可以正常工作。
时序控制器一般使用方形扁平无引脚封装(Quad Flat No-lead Package， QFN)，这种封装在印刷电路板设计时的走线不需要经过IC(integrated circuit，集成电路)内部，使得布线空间大，因此增加线宽是可实现的，且实现方式简单、成本低。但是，随着显示面板行业的发展，显示面板的分辨率及刷新频率逐渐提高，时序控制器的引脚数量也逐渐增加，QFN封装的时序控制器已经不能满足需求，插针网格阵列封装技术(Pin Grid Array Package，PGA)封装逐渐取代了QFN封装。
在PCB之上，PGA封装引脚在IC下方，两个引脚间距有限，布线空间受到了限制，因此走线宽度也受到了限制，这导致通过增大线宽来保证内核电压的稳定性的方法可行性不高，且有效性也不能保证。与此同时，显示面板在不同的运行环境或者随着运行时间的加长，功耗会增大，内核电压的电流也会随之提升，线损随之提升。因此，除了封装的限制，此种情况也会使通过增大线宽来保证内核电压的稳定性的方法的有效性降低。
综上所述，在通过增大线宽来保证输入到时序控制器的内核电压的稳定性时，在使用QFN技术对时序控制器进行封装的过程中，不能满足显示面板的分辨率及刷新频率的要求；同时，采用PGA技术对时序控制器进行封装的可行性不高，有效性得不到保证；另外，显示面板的运行环境和运行时间也限制了提供至时序控制器的内核电压，使最终提供至时序控制器的内核电压的稳定性及有效性降低。因此通过增大线宽无法保证输入到时序控制器的内核电压的稳定性，从而导致显示面板驱动电路的稳定性降低，显示面板可能会出现异常显示。
本公开至少一实施例提供一种电压调节系统，用于一电子设备，该电压调节系统可以自我调节提供至电子设备的电压，从而提高了该电子设备的稳定性。本公开至少一实施例还提供对应于上述电压调节系统的驱动电路和电压调节方法。
下面结合附图对本公开的实施例进行详细说明。
本公开的一个实施例提供一种电压调节系统，如图1A所示，该电压调节系统用于一电子设备20，该电压调节系统包括供电电路10、判断电路30和调节电路40。
该供电电路10与电子设备20、判断电路30以及调节电路40连接，且被配置为提供输入到判断电路30的基准电压V C并提供输入到电子设备20的第一电压V B。例如，在一个示例中，基准电压V C可以提供至判断电路30 中以用于后续处理。例如，输入到电子设备20的第一电压V B可以作为电子设备20的内核电压，例如，该内核电压为驱动电子设备20的核心芯片的电压。
需要说明的是，在下面的表述中，本公开的实施例中的第一电压V B表示输入到电子设备20的电压，该电压例如为输入到电子设备20中的核心芯片的电压，也就是说，第一电压V B是靠近电子设备20一侧的电压，即电子设备20接收到的接收电压，而不是靠近供电电路10一侧的输出电压，该接收电压和输出电压由于导线本身的压降而可能不同。
例如，在一个示例中，供电电路10可以设置在电源控制芯片中。
该判断电路30与供电电路10以及调节电路40连接，且被配置为根据基准电压V C和第一电压V B输出补偿电压V D。例如，判断电路30可以直接接收供电电路10提供的基准电压V C。例如，判断电路30可以在靠近电子设备20一侧获取供电电路10提供至电子设备20的第一电压V B。判断电路30在获取基准电压V C和第一电压V B后，可以对基准电压V C和第一电压V B进行处理以输出补偿电压V D，例如，该补偿电压V D可以提供至调节电路40以用于后续处理。
例如，在一个示例中，判断电路30被配置为对基准电压V C和第一电压V B进行求差处理，以获得补偿电压V D，即补偿电压V D可以是基准电压V C和第一电压V B的差值。
该调节电路40与判断电路30连接以接收补偿电压V D，且被配置为在补偿电压V D不在预设范围内时，根据补偿电压V D以及另外接收的第二电压V E输出第三电压V A。例如，调节电路40输出的第三电压V A可以被提供至供电电路10，供电电路10基于该第三电压V A以调整输出的电压。例如，在一些实施例中，调节电路40可以与供电电路10设置在同一集成电路或芯片之中，例如当供电电路10设置在电源控制芯片中时，调节电路40也可以设置在该电源控制芯片中，从而可以简化电路结构。
例如，供电电路10还被配置为根据第三电压V A产生或调整提供的第一电压V B。例如，在一个示例中，可以在供电电路10和电子设备20(例如电子设备20中的核心芯片)之间设置一根导线，供电电路10可以将第三电压V A直接输出，该第三电压V A通过上述导线传输至电子设备20，变为输入到电子设备20的第一电压V B，即供电电路10根据第三电压V A提供第一电压 V B。例如，当该导线上的电流较大时，第三电压V A在传输时会有压降，从而会导致输入到电子设备20的第一电压V B小于第三电压V A。
例如，在一个示例中，第二电压V E为基准电压V C，即第二电压V E与基准电压V C相等。例如，调节电路40可以和供电电路10连接，从而可以接收供电电路10提供的基准电压V C并作为第二电压V E。例如，在第一次电压调节中，调节电路40可以根据该基准电压V C和补偿电压V D输出第三电压V A。
又例如，在另一个示例中，第二电压V E还可以为基于基准电压V C变化而获得的电压。例如，在第n次电压调节中，调节电路40根据基准电压V C和补偿电压V D输出第三电压V A；然后，在第n+1次电压调节中，调节电路40可以将第n次电压调节中输出的第三电压V A作为第n+1次电压调节所需的第二电压V E；例如，在此后的每一次电压调节中，调节电路40都可以将上一次电压调节中输出的第三电压V A作为本次电压调节所需的第二电压V E。n为大于零的整数。
在本公开的一个实施例提供的电压调节系统中，如图1B所示，电压调节系统还包括电压反馈电路50。电压反馈电路50与调节电路40连接，被配置为在调节电路40输出第三电压V A时，根据基准电压V C和第三电压V A获得第二电压V E并提供至调节电路40。例如，在第n次电压调节中，调节电路40输出第三电压V A，该第三电压V A可以提供至电压反馈电路50，同时，电压反馈电路50还可以接收供电电路10提供的基准电压V C；然后，在第n+1次电压调节中，电压反馈电路50可以根据基准电压V C和第三电压V A获得第二电压V E并提供至调节电路40以用于电压调节。例如，调节电路40在第n+1次电压调节中获得的第二电压V E和在第n次电压调节中输出的第三电压V A相等。
例如，在一个示例中，电压反馈电路50可以包括模数转换电路和电压转换电路。例如，电压反馈电路50接收到第三电压V A后，可以采用模数转换电路将该第三电压V A转换为对应的数字信号，该数字信号例如可以被存储在存储器或寄存器之中，然后电压转换电路可以根据该数字信号以及基准电压V C生成第二电压V E，并使得第二电压V E和第三电压V A相等。
采用本公开的实施例提供的电压调节系统可以调节并稳定输入到电子设备20的第一电压V B，使得电子设备20所获得的内核电压保持稳定。例如， 在一个实施例中，电子设备20所需要的稳定的内核电压为1.2V，补偿电压V D的预设范围定为-0.2V～0.2V，则当供电电路10提供至电子设备20的第一电压V B处于1V～1.4V范围内时，即认为可使得电子设备20获得的内核电压保持稳定。例如，可以使得供电电路10提供的基准电压V C也为1.2V。
下面以图1B所示的实施例为例详细描述电压调节系统的工作过程。
例如，在第一次电压调节中，在如图1B所示的实施例中，供电电路10提供第三电压V A和基准电压V C，例如第三电压V A和基准电压V C都为1.2V。第三电压V A经过导线的传输后，由于导线存在压降，使得输入到电子设备20的第一电压V B小于第三电压V A，例如第一电压V B变为0.9V，即导线上的压降为0.3V。例如，判断电路30可以对基准电压V C和第一电压V B进行求差处理以获得补偿电压V D，即补偿电压V D为1.2V-0.9V＝0.3V。例如，调节电路40在接收补偿电压V D后，首先判定补偿电压V D不在上述-0.2V～0.2V的预设范围内，然后根据补偿电压V D和第二电压V E(在该示例中，第二电压V E为基准电压V C)输出第三电压V A，例如将补偿电压V D(0.3V)和第二电压V E(1.2V)进行求和处理得到第三电压V A为1.5V。然后，直接将第三电压V A提供至供电电路10，供电电路10将该第三电压V A输出，假设此时导线上的压降仍然为0.3V，则第三电压V A传输至电子设备20后变为1.2V，即经过电压调节后供电电路10提供至电子设备20的第一电压V B为1.2V。
如上所述，采用电压调节系统，通过一次调节即可以使得供电电路10提供的第一电压V B满足要求。在本示例中，调节电路40采用基准电压V C作为第二电压V E，所以可以不设置图1B中所示的电压反馈电路50。
例如，当电路参数(例如导线压降、电阻阻值等)发生变化或者环境参数(例如温度)发生变化时，之前供电电路10提供的调节好的第一电压V B可能会发生变化。例如，导线上的压降从之前的0.3V变为0.7V，则供电电路10提供的第一电压V B会从1.2V下降为0.8V，由此电子设备20接收到的电压不再满足电子设备20所需要的内核电压的要求，这时需要继续进行第二次电压调节。例如，供电电路10提供的基准电压V C保持不变，仍然为1.2V，判断电路30可以对基准电压V C(1.2V)和第一电压V B(0.8V)进行求差处理以获得补偿电压V D，即补偿电压V D为0.4V。例如，调节电路40在接收补偿电压V D后，首先判定补偿电压V D不在上述-0.2V～0.2V的预设范围内，然后根据补偿电压V D和第二电压V E(在该示例中，第二电压V E为第一次 电压调节中调节电路40输出的第三电压V A，即1.5V)输出第三电压V A，例如将补偿电压V D(0.4V)和第二电压V E(1.5V)进行求和处理得到第三电压V A为1.9V。然后，直接将第三电压V A提供至供电电路10，供电电路10将该第三电压V A输出，假设此时导线上的压降仍然为0.7V，则第三电压V A传输至电子设备20后变为1.2V，即供电电路10提供至电子设备20的第一电压V B为1.2V。
如上所述，在完成第一次电压调节后，当电路发生变化而导致第一电压V B不满足要求时，电压调节系统仍然可以对第一电压V B进行调节，使其满足电子设备20的内核电压的要求。在本示例中，需要设置图1B中所示的电压反馈电路50。
需要说明的是，例如在供电电路10中存在两个独立的回路，该两个独立的回路可以分别产生第三电压V A和基准电压V C，且该两个独立的回路彼此之间是独立的，相互之间不受影响。
供电电路10产生第三电压V A的方式包括但不限于下列方式中的部分或全部：
降压式变换(Buck)电路、升压式变换(Boost)电路等电路。
例如，在电压调节系统开始工作时，即在第一次电压调节中，可以使得供电电路10输出的第三电压V A以及基准电压V C都和电子设备20需要的内核电压相等，例如为1.2V。然后，在后续电压调节中，供电电路10可以接收调节电路40输出的第三电压V A，并将该第三电压V A直接输出以提供输入到电子设备20的第一电压。
综上，采用本公开的实施例提供的电压调节系统，可以调节并稳定提供至电子设备的电压(例如电子设备所需的内核电压)，从而提高该电子设备的稳定性。例如，在一个实施例中，供电电路10可以设置在电源控制芯片中，电子设备20为显示面板驱动电路中的时序控制器，提高时序控制器的稳定性可以提高显示面板驱动电路的稳定性，从而可以避免显示面板出现异常显示。
输入到电子设备20的第一电压V B是由供电电路10提供的。供电电路10输出的第三电压V A的电流较大，在传输过程中有较大的线损，因此输入到电子设备20的第一电压V B要比第三电压V A小。基于此，在获取输入到电子设备20的第一电压V B时，可以在靠近电子设备20的一侧进行获取。
在如图2所示的实施例中，例如，供电电路10输出的第三电压V A为1.2V，由于传输导线有线损，输入到电子设备20的第一电压V B的大小为0.9V。本公开的实施例在电子设备20的内核电压输入端一侧获取输入到电子设备20的第一电压V B。
例如，如图2所示，判断电路30包括：第一运算放大器OA1、第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4。
第一电阻R1的第一端被配置为接收第一电压V B，第一电阻R1的第二端与所述第一运算放大器OA1的反相输入端连接。
第二电阻R2的第一端与第一运算放大器OA1的反相输入端连接，第二电阻R2的第二端与第一运算放大器OA1的输出端连接。
第三电阻R3的第一端被配置为接收基准电压V C，第三电阻R3的第二端与第一运算放大器OA1的同相输入端连接。
第四电阻R4的第一端与第一运算放大器OA1的同相输入端连接，第四电阻R4的第二端接地。
第一运算放大器OA1的输出端与调节电路40连接，且被配置为输出补偿电压V D。
在图2所示的电路中，将靠近电子设备20一侧获得的第一电压V B通过第一电阻R1输入到第一运算放大器OA1的反相输入端，将供电电路10输出的基准电压V C通过第三电阻R3输入到第一运算放大器OA1的同相输入端，这样在第一电阻R1、第二电阻R2、第三电阻R3以及第四电阻R4满足一定条件时，经过第一运算放大器OA1输出的电压就是输入的两个电压的差值。
例如，供电电路10输出的第三电压V A的电流较大，在传输过程中有较大的线损，因此输入到第一运算放大器OA1中的第一电压V B要比第三电压V A小。
例如，供电电路10输出的第三电压V A为1.2V，由于线损的影响，输入到第一运算放大器OA1中的第一电压V B的大小可能为0.9V。例如，在印刷电路板布局时将第一运算放大器OA1的反相输入端靠近电子设备20的内核电压输入端。
例如，供电电路10输出的基准电压V C为1.2V。
例如，供电电路10输出的基准电压V C的电流较小，因此在印刷电路板 布线合理时，基准电压V C在传输过程中的线损可以忽略不计，传输到第一运算放大器OA1同相输入端的电压值的大小不变，仍为基准电压V C＝1.2V。
例如，供电电路10中包括输出基准电压V C的回路，且此回路完全独立，不受其他电压的影响。
在图2所示的电路中，第一运算放大器OA1输出的补偿电压V D可以通过下列公式确定：
V D＝(R4/(R3+R4))*((R1+R2)/R1)*V C-(R2/R1)*V B
例如，为了保证判断电路30输出的补偿电压V D的精确度，在一个实施例中，可以设置第一电阻R1与第三电阻R3的阻值相等，第二电阻R2与第四电阻R4的阻值相等，则上述公式可以简化为：V D＝(R2/R1)*(V C-V B)。又例如，还可以进一步使得第一电阻R1与第二电阻R2的阻值相等，则上述公式可以进一步简化为V D＝V C-V B；即判断电路30输出的补偿电压V D为基准电压V C与第一电压V B的差值。
在本公开的实施例中，通过第一运算放大器OA1可以准确的计算出供电电路10输出的基准电压V C和输入到电子设备20的第一电压V B之间的差值，即补偿电压V D。
需要说明的是，图2所示的电路图只是举例说明，任何能够通过运算放大器确定供电电路10输出的基准电压V C和输入到电子设备20的第一电压V B之间的差值的电路都适用于本公开的实施例。
例如，如图3所示，在本公开的一个实施例提供的电压调节系统中，调节电路40包括：第二运算放大器OA2、第五电阻R5、第六电阻R6、第七电阻R7和第八电阻R8。
第五电阻R5的第一端被配置为接收第二电压V E，第五电阻R5的第二端与第二运算放大器OA2的反相输入端连接。
第六电阻R6的第一端被配置为接收补偿电压V D，第六电阻R6的第二端与第二运算放大器OA2的反相输入端连接。
第七电阻R7的第一端与第二运算放大器OA2的同相输入端连接，第七电阻R7的第二端接地。
第八电阻R8的第一端与第二运算放大器OA2的反相输入端连接，第八电阻R8的第二端与第二运算放大器OA2的输出端连接。
第二运算放大器OA2的输出端被配置为输出第三电压V A，例如该第三 电压V A可以传输至供电电路10，以使得供电电路10可以根据该第三电压V A提供第一电压V B。
例如，如图3所示，补偿电压V D为判断电路30中的第一运算放大器OA1输出的电压(即判断电路30确定的供电电路10输出的基准电压V C和输入到电子设备20的第一电压V B的差值)，第二电压V E为供电电路10输出的基准电压V C或者电压反馈电路50输出的电压。
例如，如图3所示，在一个示例中，电阻R5、R6、R7和R8为固定阻值的电阻，当调节电路40判断收到的补偿电压V D不在预设范围内时，调节电路40可以对补偿电压V D和第二电压V E进行处理从而输出第三电压V A，输出的第三电压V A例如可以传输至供电电路10，通过供电电路10将第三电压V A输出，最终输入到电子设备20中。
在图3所示的电路中，第二运算放大器OA2输出的第三电压V A可以通过下列公式确定：
V A＝R8*(V D/R6+V E/R5)
例如，在一个实施例中，可以设置电阻R5＝R6＝R8，则上述公式可以简化为：V A＝V D+V E。
在本实施例中，通过调节电路40对补偿电压V D和第二电压V E进行处理以输出第三电压V A，保证了传输到电子设备20的第一电压V B在稳定的范围内，从而例如可以避免显示面板在工作时出现异常显示。
例如，如图4所示，在本公开的另一个实施例中，第八电阻R8为可变电阻，第八电阻R8包括：N个电阻R和N个第一开关K1；调节电路40还包括第一处理电路41。
N个电阻R和N个第一开关K1一一对应。N个电阻中的每一个电阻R的第一端通过对应的第一开关K1与第二运算放大器OA2的反相输入端连接，N个电阻中的每一个电阻R的第二端与第二运算放大器OA2的输出端连接。
第一处理电路41与判断电路30以及第八电阻R8中的N个第一开关K1连接，且被配置为在补偿电压V D不在预设范围内时控制第八电阻R8中的N个第一开关K1中的每一个断开或闭合。N为大于1的整数。
例如，第八电阻R8中包括两个和/或两个以上电阻R，且第八电阻R8中电阻R的数量和各个电阻R的阻值可以根据应用场景、需求等采用实验手 段确定。
例如，判断电路30将供电电路10输出的基准电压V C和供电电路10提供的输入到电子设备20的第一电压V B之间的差值即补偿电压V D，输入到调节电路40中的第一处理电路41，第一处理电路41根据接收到的补偿电压V D的值判断出补偿电压V D是否在预设范围内，若补偿电压V D不在预设范围内，此时第一处理电路41可以控制第八电阻R8中的N个第一开关K1，将第八电阻R8中的N个第一开关K1中的一个或多个闭合，这样就可以对第八电阻R8的阻值进行调节，进而调节了第二运算放大器OA2输出的第三电压V A，输出的第三电压V A例如可以通过供电电路10输出，最终输入到电子设备20中。
在本公开的实施例中，在第八电阻R8为可变电阻时，可以通过调整第八电阻R8中的多个第一开关K1的状态来改变第八电阻R8的阻值，从而达到调节第三电压V A的目的，使最终传输到电子设备20中的第一电压V B在稳定范围内。
例如，如图5所示，在本公开的另一个实施例中，电压调节系统中的调节电路40还包括第二开关K2和第二处理电路42。
第二开关K2和第六电阻R6的第一端以及第二处理电路42连接；第二处理电路42与判断电路30连接，且被配置为控制第二开关K2断开或闭合。
例如，在图5所示的电路中，当第二处理电路42接收到补偿电压V D并判定补偿电压V D在预设范围内时，第二处理电路42可以对第二开关K2进行控制，使第二开关K2处于断开状态，此时，第二运算放大器OA2的反相输入端仅接收通过第五电阻R5输入的第二电压V E；当第二处理电路42判定补偿电压V D不在预设范围内时，第二处理电路42可以对第二开关K2进行控制，使第二开关K2处于闭合状态，此时第二运算放大器OA2的反相输入端可以同时接收通过第五电阻R5输入的第二电压V E以及通过第六电阻R6输入的补偿电压V D。
在图5所示的实施例中，通过在判断电路30和第六电阻R6之间设置第二处理电路42和第二开关K2，当补偿电压V D不在预设范围内时，第二处理电路42控制第二开关K2闭合。采用这种方式可以使得当补偿电压V D未超出预设范围时，即当输入到电子设备20的第一电压V B处于稳定范围时，可以降低电路的负载，从而可以降低电路的功耗。
例如，如图6所示，在本公开的另一个实施例中，第八电阻R8为可变电阻，第八电阻R8包括N个电阻R和N个第一开关K1；调节电路40还包括处理电路43和第二开关K2。
N个电阻R和N个第一开关K1一一对应。N个电阻R中的每一个电阻R的第一端通过对应的第一开关K1与第二运算放大器OA2的反相输入端连接，N个电阻R中的每一个电阻R的第二端与第二运算放大器OA2的输出端连接。第二开关K2和第六电阻R6的第一端以及处理电路43连接。
处理电路43与第二开关K2、判断电路30以及N个第一开关K1连接，且被配置为在补偿电压V D不在预设范围内时控制N个第一开关K1中的每一个断开或闭合，以及控制第二开关K2断开或闭合。N为大于1的整数。
例如，如图6所示，调节电路40中的处理电路43既与第八电阻R8中的N个第一开关K1连接，又与第二开关K2连接。当调节电路40中的处理电路43接收到判断电路30输出的补偿电压V D后，首先判断补偿电压V D是否在预设范围内，然后处理电路43可以根据判断结果控制第八电阻R8中的N个第一开关K1的断开或闭合，同时还可以控制第二开关K2的断开或闭合。例如，当补偿电压V D不在预设范围内时，处理电路43可以控制第八电阻R8中的一个或多个电阻R闭合，同时控制第二开关K2使其闭合。
在本实施例中，通过一个处理电路43同时控制第八电阻R8中的N个第一开关K1与第二开关K2的断开或闭合，在使得第一运算放大器OA1输出的补偿电压V D可以输入到第二运算放大器OA2的同时，还可以调节第八电阻R8的阻值，从而可以保证第二运算放大器OA2输出的第三电压V A可以满足要求。
例如，在一些实施例中，供电电路10设置在电源控制芯片中；电子设备20为时序控制器。
又例如，在一些实施例中，在供电电路10设置在电源控制芯片中的情形下，调节电路40也可以设置在电源控制芯片中，从而可以简化电路结构，提高电压调节系统的整体性。
例如，当供电电路10设置在电源控制芯片中时，电源控制芯片可以提供输入到电子设备20的第一电压V B以及基准电压V C；例如，电子设备20为时序控制器，时序控制器可以接收第一电压V B并作为内核电压，时序控制器在该内核电压的驱动下可以输出用于显示面板的控制信号，从而控制显 示面板进行正常显示操作。
基于同一构思，本公开的实施例还提供了一种电压调节方法，该电压调节方法可以用于本公开的任一实施例提供的电压调节系统。需要说明的是，由于该方法对应的系统是本公开的实施例提供的进行电压调节的系统，并且该方法解决问题的原理与该系统相似，因此该方法的实施可以参见上述关于电压调节系统的实施，重复之处不再赘述。
如图7所示，在本公开的实施例提供的一种电压调节方法中，包括如下操作步骤。
步骤400：使得供电电路10提供基准电压V C和第一电压V B；第一电压V B为输入到电子设备20的电压，关于第一电压V B的描述可以参考上述关于电压调节系统中的相应描述，这里不再赘述。
步骤401：使得判断电路30根据基准电压V C和第一电压V B获得补偿电压V D；例如，在一个示例中，可以使得判断电路30对基准电压V C和第一电压V B进行求差处理以获得补偿电压V D。
步骤402：在补偿电压V D不在预设范围内时，使得调节电路40根据补偿电压V D和第二电压V E获得第三电压V A；需要说明的是，关于第二电压V E可以参考上述关于电压调节系统中的相应描述，这里不再赘述。以及
步骤403：使得供电电路10根据第三电压V A提供第一电压V B。
如图3所示，在电压调节系统包括电压反馈电路50的情形下，本公开的实施例提供的电压调节方法还包括：将调节电路40输出的第三电压V A再提供至调节电路40并作为第二电压V E。
例如，在第n次电压调节中，调节电路40输出第三电压V A，该第三电压V A可以提供至电压反馈电路50，同时，电压反馈电路50还可以接收供电电路10提供的基准电压V C；然后，在第n+1次电压调节中，电压反馈电路50可以根据基准电压V C和第三电压V A获得第二电压V E并提供至调节电路40以用于电压调节。例如，调节电路40在第n+1次电压调节中获得的第二电压V E和在第n次电压调节中输出的第三电压V A相等。
如图6所示，在电压调节系统包括第二开关K2、处理电路43以及第二运算放大器OA2的情形下，上述步骤402可以包括如下操作：
处理电路43在确定补偿电压V D不在预设范围内时，闭合第二开关K2，以使得补偿电压V D输入至第二运算放大器OA2。
如图5和图6所示，在电压调节系统包括第八电阻R8且第八电阻R8为可变电阻的情形下，上述步骤402可以包括如下操作：
通过调整第八电阻R8的阻值调节调节电路40输出的第三电压V A的电压值。
例如，在本公开的一个实施例提供的电压调节方法中，上述步骤402可以包括如下操作。
若补偿电压V D大于预设范围的最大值，则增大调节电路40输出的第三电压V A的电压值；以及
若补偿电压V D小于预设范围的最小值，则减小调节电路40输出的第三电压V A的电压值。
例如，在一个实施例中，预设范围为-0.2V～0.2V，而判断电路30输出的补偿电压V D为0.3V，该补偿电压V D不在预设范围内，且大于预设范围的最大值，此时，增大调节电路40输出的第三电压V A的电压值。例如，在第八电阻R8为可变电阻时，可以通过增大第八电阻R8的电阻值来增大调节电路40输出的第三电压V A的电压值。
例如，在一个实施例中，预设范围为-0.2V～0.2V，而判断电路输出的补偿电压V D为-0.3V，该补偿电压V D不在预设范围内，且小于预设范围的最小值，此时，减小调节电路40输出的第三电压V A的电压值。例如，在第八电阻R8为可变电阻时，可以通过减小第八电阻R8的电阻值来减小调节电路40输出的第三电压V A的电压值。
在本公开的实施例中，调节电路40通过判断补偿电压V D是否在预设范围内，然后根据判断结果对供电电路10提供的输入到电子设备20的第一电压V B进行相应的调整，以保证补偿电压V D在预设范围内，从而使得输入到电子设备20的第一电压V B保持稳定，从而例如可以降低显示面板出现异常显示的风险。
如图8所示，本公开的一个实施例还提供一种电压调节方法，该方法包括如下操作。
步骤500：判断电路30获取输入到时序控制器的第一电压V B；
步骤501：判断电路30获取电源控制芯片输出的基准电压V C；
步骤502：判断电路30对基准电压V C和第一电压V B进行求差处理获得补偿电压V D；
步骤503：处理电路43判断补偿电压V D是否在预设范围内，如果在预设范围内，则执行步骤500；否则执行步骤504。例如，如图6所示，处理电路43为设置在调节电路40中的电路。
步骤504：如果补偿电压V D不在预设范围内则触发调节电路40进行调节；
步骤505：调节电路40接收到处理电路43的触发后，闭合用于连通第一运算放大器OA1的输出端和第二运算放大器OA2的反相输入端之间通路的开关；例如，该开关为图5或图6中的第二开关K2。
步骤506：调节电路40通过第二运算放大器OA2对电源控制芯片提供的输入到时序控制器的电压进行调整。
本实施例提供的电压调节方法可以提高时序控制器的稳定性，从而可以提高该时序控制器作用的显示面板的稳定性，从而可以避免该显示面板出现异常显示。
如图9所示，本公开的一个实施例还提供了一种驱动电路，该驱动电路用于驱动一时序控制器71，该驱动电路包括电源控制芯片70和判断电路30。
时序控制器71包括内核电压输入端IV，例如该内核电压输入端IV用于接收第一电压V B，并将该第一电压V B用作内核电压以用于驱动时序控制器71的核心芯片；判断电路30包括第一运算放大器OA1、第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4。
电源控制芯片70包括基准电压输出端VCO、补偿电压输入端VDI、第二电压输入端VEI、第三电压输出端VAO、处理电路43、第二运算放大器OA2、第五电阻R5、第六电阻R6、第七电阻R7、第八电阻R8和第二开关K2。
第一电阻R1的第一端与内核电压输入端IV连接以接收第一电压V B，第一电阻R1的第二端与第一运算放大器OA1的反相输入端连接；第二电阻R2的第一端与第一运算放大器OA1的反相输入端连接，第二电阻R2的第二端与第一运算放大器OA1的输出端连接；第三电阻R3的第一端与基准电压输出端VCO连接以接收基准电压V C，第三电阻R3的第二端与第一运算放大器OA的同相输入端连接；第四电阻R4的第一端与第一运算放大器OA1的同相输入端连接，第四电阻R4的第二端接地；第一运算放大器OA1的输出端与电源控制芯片70的补偿电压输入端VDI连接，以 用于向电源控制芯片70提供补偿电压V D。
处理电路43与补偿电压输入端VDI以及第二开关K2连接；第二开关K2还与第六电阻R6的第一端连接；第六电阻R6的第二端与第二运算放大器OA2的反相输入端连接；第五电阻R5的第一端与第二电压输入端VEI连接以接收第二电压V E，第五电阻R5的第二端与第二运算放大器OA2的反相输入端连接；第七电阻R7的第一端与第二运算放大器OA2的同相输入端连接，第七电阻R7的第二端接地；第八电阻R8的第一端与第二运算放大器OA2的反相输入端连接，第八电阻R8的第二端与第二运算放大器OA2的输出端连接；第二运算放大器OA2的输出端与电源控制芯片70的第三电压输出端VAO连接以用于输出第三电压V A。
需要说明的是，在本实施例中，对第八电阻R8的类型不作限定，例如第八电阻R8可以为固定阻值的电阻；又例如，如图9所示，第八电阻R8为可变电阻。
例如，如图9所示，在一个示例中，第八电阻R8为可变电阻，第八电阻R8包括N个电阻R和N个第一开关K1。N个电阻R和N个第一开关K1一一对应；N个电阻R中的每一个电阻R的第一端通过对应的第一开关K1与第二运算放大器OA2的反相输入端连接，N个电阻R中的每一个电阻R的第二端与第二运算放大器OA2的输出端连接。
如图9所示，第八电阻R8包括4个电阻R，但在实际应用中不限于4个，且第八电阻R8中的电阻R的数量及阻值大小可以根据实际情况进行设定。
本公开的实施例还提供一种显示装置1，该显示装置1包括本公开实施例提供的任一电压调节系统100、时序控制器71和显示面板200。
电压调节系统100被配置为驱动时序控制器71，例如，在一个示例中，电压调节系统100被配置为向时序控制器71提供稳定的内核电压，该内核电压例如为驱动时序控制器71的核心芯片的电压。
时序控制器71被配置为向显示面板200提供控制信号，例如，如图10所示，显示装置1还可以包括栅极驱动电路300和数据驱动电路400，时序控制器71分别和栅极驱动电路300以及数据驱动电路400连接以提供控制信号。
如图10所示，该显示装置1包括显示面板200，在显示面板200中设置 有多个子像素单元210构成的像素阵列。
例如，栅极驱动电路300中的每一级移位寄存器单元的输出端分别和不同行的子像素单元210电连接，例如，栅极驱动电路300通过栅线GL与子像素单元210电连接。栅极驱动电路300用于提供驱动信号至像素阵列，例如该驱动信号可以驱动子像素单元210中的扫描晶体管。
例如，数据驱动电路400用于提供数据信号至像素阵列。例如，数据驱动电路400通过数据线DL与子像素单元210电连接。
需要说明的是，本实施例中的显示装置1可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置1还可以包括显示面板等其他常规部件，本公开的实施例对此不作限制。
本公开的实施例提供的显示装置1，通过电压调节系统100可以调节并稳定提供至时序控制器71的电压，从而提高时序控制器71工作时的稳定性，进而可以提高显示面板200(显示装置1)工作时的稳定性，避免显示面板200(显示装置1)出现异常显示。
本公开是参照根据本公开实施例的方法、系统(设备)、和计算机程序产品的流程图和/或方框图来描述的。应理解，可以由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理系统的处理电路，以产生一个机器指令，使得通过计算机或其他可编程数据处理系统的处理电路执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的方法。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理系统以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理系统上，使得在计算机或其他可编程系统上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程系统上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的 步骤。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例做出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (22)

  1. 一种电压调节系统，用于一电子设备，包括供电电路、判断电路和调节电路；其中，
    所述供电电路与所述调节电路连接，且被配置为提供基准电压并提供输入到所述电子设备的第一电压；
    所述判断电路与所述供电电路连接，且被配置为根据所述基准电压和所述第一电压输出补偿电压；
    所述调节电路与所述判断电路连接以接收所述补偿电压，且被配置为在所述补偿电压不在预设范围内时，根据所述补偿电压以及第二电压输出第三电压；
    所述供电电路还被配置为根据所述第三电压提供所述第一电压，其中，
    所述第二电压为所述基准电压或基于所述基准电压变化而获得的电压。
  2. 如权利要求1所述的电压调节系统，还包括电压反馈电路，其中，所述电压反馈电路与所述调节电路连接，被配置为在所述调节电路输出所述第三电压时，根据所述基准电压和所述第三电压获得所述第二电压并提供至所述调节电路。
  3. 如权利要求1或2所述的电压调节系统，其中，所述判断电路被配置为对所述基准电压和所述第一电压进行求差处理以获得所述补偿电压。
  4. 如权利要求1-3任一所述的电压调节系统，其中，所述第二电压与所述基准电压相等。
  5. 如权利要求1-4任一所述的电压调节系统，其中，所述判断电路包括：第一运算放大器、第一电阻、第二电阻、第三电阻和第四电阻；其中，
    所述第一电阻的第一端被配置为接收所述第一电压，所述第一电阻的第二端与所述第一运算放大器的反相输入端连接；
    所述第二电阻的第一端与所述第一运算放大器的反相输入端连接，所述第二电阻的第二端与所述第一运算放大器的输出端连接；
    所述第三电阻的第一端被配置为接收所述基准电压，所述第三电阻的 第二端与所述第一运算放大器的同相输入端连接；
    所述第四电阻的第一端与所述第一运算放大器的同相输入端连接，所述第四电阻的第二端接地；
    所述第一运算放大器的输出端被配置为输出所述补偿电压。
  6. 如权利要求1-5任一所述的电压调节系统，其中，所述调节电路包括：第二运算放大器、第五电阻、第六电阻、第七电阻和第八电阻；
    所述第五电阻的第一端与被配置为接收所述第二电压，所述第五电阻的第二端与所述第二运算放大器的反相输入端连接；
    所述第六电阻的第一端被配置为接收所述补偿电压，所述第六电阻的第二端与所述第二运算放大器的反相输入端连接；
    所述第七电阻的第一端与所述第二运算放大器的同相输入端连接，所述第七电阻的第二端接地；
    所述第八电阻的第一端与所述第二运算放大器的反相输入端连接，所述第八电阻的第二端与所述第二运算放大器的输出端连接；
    所述第二运算放大器的输出端被配置为输出所述第三电压。
  7. 如权利要求6所述的电压调节系统，其中，所述第八电阻为可变电阻，所述第八电阻包括N个电阻和N个第一开关，所述调节电路还包括第一处理电路；其中，
    所述N个电阻和所述N个第一开关一一对应；
    所述N个电阻中的每一个电阻的第一端通过对应的所述的第一开关与所述第二运算放大器的反相输入端连接，所述N个电阻中的每一个电阻的第二端与所述第二运算放大器的输出端连接；
    所述第一处理电路与所述判断电路以及所述第八电阻中的所述N个第一开关连接，且被配置为在所述补偿电压不在预设范围内时控制所述第八电阻中的所述N个第一开关中的每一个断开或闭合；
    N为大于1的整数。
  8. 如权利要求7所述的电压调节系统，其中，所述调节电路还包括第二开关和第二处理电路；其中，
    所述第二开关和所述第六电阻的第一端以及所述第二处理电路连接；
    所述第二处理电路与所述判断电路连接，且被配置为控制所述第二开关断开或闭合。
  9. 如权利要求6所述的电压调节系统，其中，所述第八电阻为可变电阻，所述第八电阻包括N个电阻和N个第一开关，所述调节电路还包括处理电路和第二开关；其中，
    所述N个电阻和所述N个第一开关一一对应；
    所述N个电阻中的每一个电阻的第一端通过对应的所述第一开关与所述第二运算放大器的反相输入端连接，所述N个电阻中的每一个电阻的第二端与所述第二运算放大器的输出端连接；
    所述第二开关和所述第六电阻的第一端以及所述处理电路连接；
    所述处理电路与所述第二开关、所述判断电路以及所述N个第一开关连接，且被配置为在所述补偿电压不在预设范围内时控制所述N个第一开关中的每一个断开或闭合，以及控制所述第二开关断开或闭合；
    N为大于1的整数。
  10. 如权利要求1-9任一所述的电压调节系统，其中，所述供电电路设置在电源控制芯片中。
  11. 如权利要求10所述的电压调节系统，其中，所述调节电路设置在所述电源控制芯片中。
  12. 一种如权利要求1-11任一电压调节系统的电压调节方法，包括：
    使得所述供电电路提供所述基准电压和所述第一电压；
    使得所述判断电路根据所述基准电压和所述第一电压获得所述补偿电压；
    在所述补偿电压不在预设范围内时，使得所述调节电路根据所述补偿电压和所述第二电压获得所述第三电压；以及
    使得所述供电电路根据所述第三电压提供所述第一电压。
  13. 如权利要求12所述的电压调节方法，其中，使得所述判断电路根据所述基准电压和所述第一电压获得所述补偿电压包括：
    使得所述判断电路对所述基准电压和所述第一电压进行求差处理以获得所述补偿电压。
  14. 如权利要求12或13所述的电压调节方法，其中，在所述电压调节系统包括电压反馈电路的情形下，所述电压调节方法还包括：
    将所述调节电路输出的所述第三电压再提供至所述调节电路并作为第二电压。
  15. 如权利要求12-14任一所述的电压调节方法，其中，在所述电压调节系统包括第二开关、处理电路以及第二运算放大器的情形下，使得所述调节电路根据所述补偿电压和所述第二电压获得所述第三电压包括：
    所述处理电路在确定所述补偿电压不在预设范围内时，闭合所述第二开关，以使得所述补偿电压输入至所述第二运算放大器。
  16. 如权利要求12-15任一所述的电压调节方法，其中，在所述电压调节系统包括第八电阻且所述第八电阻为可变电阻的情形下，使得所述调节电路根据所述补偿电压和所述第二电压获得所述第三电压包括：
    通过调整所述第八电阻的阻值调节所述调节电路输出的所述第三电压的电压值。
  17. 如权利要求12-16任一所述的电压调节方法，其中，使得所述调节电路根据所述补偿电压和所述第二电压获得所述第三电压包括：
    若补偿电压大于所述预设范围的最大值，则增大所述调节电路输出的所述第三电压的电压值；或者
    若补偿电压小于所述预设范围的最小值，则减小所述调节电路输出的所述第三电压的电压值。
  18. 如权利要求12-17任一所述的电压调节方法，其中，所述供电电路设置在电源控制芯片中。
  19. 一种驱动电路，用于驱动一时序控制器，包括电源控制芯片和判断电路；其中，
    所述时序控制器包括内核电压输入端；所述判断电路包括第一运算放大器、第一电阻、第二电阻、第三电阻和第四电阻；
    所述电源控制芯片包括基准电压输出端、补偿电压输入端、第二电压输入端、第三电压输出端、处理电路、第二运算放大器、第五电阻、第六电阻、第七电阻、第八电阻和第二开关；其中，
    所述第一电阻的第一端与所述内核电压输入端连接，所述第一电阻的第二端与所述第一运算放大器的反相输入端连接；所述第二电阻的第一端与所述第一运算放大器的反相输入端连接，所述第二电阻的第二端与所述第一运算放大器的输出端连接；所述第三电阻的第一端与所述基准电压输出端连接，所述第三电阻的第二端与所述第一运算放大器的同相输入端连接；所述第四电阻的第一端与所述第一运算放大器的同相输入端连接，所 述第四电阻的第二端接地；所述第一运算放大器的输出端与所述补偿电压输入端连接；
    所述处理电路与所述补偿电压输入端以及所述第二开关连接；所述第二开关还与所述第六电阻的第一端连接；所述第六电阻的第二端与第二运算放大器的反相输入端连接；所述第五电阻的第一端与所述第二电压输入端连接，所述第五电阻的第二端与所述第二运算放大器的反相输入端连接；所述第七电阻的第一端与所述第二运算放大器的同相输入端连接，所述第七电阻的第二端接地；所述第八电阻的第一端与所述第二运算放大器的反相输入端连接，所述第八电阻的第二端与所述第二运算放大器的输出端连接；所述第二运算放大器的输出端与所述第三电压输出端连接。
  20. 如权利要求19所述的驱动电路，其中，所述第八电阻为可变电阻，所述第八电阻包括N个电阻和N个第一开关；
    所述N个电阻和所述N个第一开关一一对应；
    所述N个电阻中的每一个电阻的第一端通过对应的所述第一开关与所述第二运算放大器的反相输入端连接，所述N个电阻中的每一个电阻的第二端与所述第二运算放大器的输出端连接；
    N为大于1的整数。
  21. 一种显示装置，包括如权利要求1-11任一所述的电压调节系统、时序控制器和显示面板；其中，
    所述电压调节系统被配置为驱动所述时序控制器，所述时序控制器被配置为向所述显示面板提供控制信号。
  22. 如权利要求21所述的显示装置，其中，所述电压调节系统被配置为向所述时序控制器提供内核电压。
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