WO2019051930A1 - Thin film transistor and manufacturing method therefor, and display panel - Google Patents
Thin film transistor and manufacturing method therefor, and display panel Download PDFInfo
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- WO2019051930A1 WO2019051930A1 PCT/CN2017/107049 CN2017107049W WO2019051930A1 WO 2019051930 A1 WO2019051930 A1 WO 2019051930A1 CN 2017107049 W CN2017107049 W CN 2017107049W WO 2019051930 A1 WO2019051930 A1 WO 2019051930A1
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- H01L29/78636—
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- H01L29/66969—
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- H01L29/7869—
Definitions
- the present invention relates to the field of display technologies, and in particular to a thin film transistor, a method of fabricating the same, and a display panel having the same.
- IGZO Indium Gallium Zinc Oxide
- the active layer is located at a portion of the source pattern and the drain pattern to form a channel of the TFT. Since IGZO is a material with extremely sensitive electrical properties, the channel is easily damaged during the manufacturing process of the LCD. For example, in etching the source pattern and the drain pattern of the TFT, the etching liquid is easily damaged. The channel, which affects the electrical properties of the channel.
- the present invention provides a thin film transistor, a method of manufacturing the same, and a display panel, which can be advantageously prevented from damaging the channel and ensuring electrical properties of the channel.
- the source pattern is covered in one of the contact holes and connected to the semiconductor pattern, and the drain pattern is covered in the other contact hole and connected to the semiconductor pattern;
- a passivation layer covering the source pattern and the drain pattern is formed on the second protective layer.
- the deposition power of the second protective layer is greater than the deposition power of the first protective layer, wherein the first protective layer and the second protective layer are both open through the first protective layer and the second Two contact holes of the protective layer, the two contact holes are spaced apart and both expose the surface of the semiconductor pattern;
- the source pattern is covered in one of the contact holes and connected to the semiconductor pattern
- the drain pattern is covered in the other contact hole and connected to the semiconductor pattern
- the deposition power of the second protective layer is greater than the deposition power of the first protective layer, wherein the first protective layer and the second protective layer are both open through the first protective layer and the second Two contact holes of the protective layer, the two contact holes are spaced apart and both expose the surface of the semiconductor pattern;
- the source pattern is covered in one of the contact holes and connected to the semiconductor pattern
- the drain pattern is covered in the other contact hole and connected to the semiconductor pattern
- the ESL (Etch Stop Layer) of the TFT channel of the present invention is a first protective layer and at least a second protective layer sequentially formed on the semiconductor pattern, since the first layer is directly formed on the channel
- the deposition power of the protective layer is small, so that the bombardment effect of the plasma on the channel can be reduced in the process of forming the first protective layer, thereby facilitating the damage of the channel and ensuring the electrical performance of the channel.
- FIG. 1 is a flow chart showing a method of manufacturing a thin film transistor according to an embodiment of the present invention
- FIG. 2 is a schematic view of a process for fabricating a thin film transistor based on the method shown in FIG. 1;
- Fig. 3 is a cross-sectional view showing the structure of an embodiment of the display panel of the present invention.
- FIG. 1 is a flow chart showing a method of manufacturing a thin film transistor according to an embodiment of the present invention.
- a method of manufacturing a thin film transistor of this embodiment includes steps S11 to S17.
- S11 forming a gate pattern and an insulating layer covering the gate pattern on the substrate substrate.
- the substrate substrate 20 may be a light-transmitting substrate such as a glass substrate, a transparent plastic substrate, or a flexible substrate.
- the substrate substrate 20 of the present embodiment may also be provided with a passivation protective layer.
- the substrate substrate 20 may include a substrate and a passivation protective layer formed on the substrate, and the substrate may be a glass substrate or a transparent plastic base.
- a transparent substrate such as a material or a flexible substrate.
- the material of the passivation protective layer includes, but is not limited to, a silicon nitride compound, such as Si 3 N 4 (tetrazinc silicon nitride, referred to as silicon nitride), to improve the substrate base. Structural stability of the surface of the material 20.
- This embodiment can form a predetermined gate pattern 21 on the substrate substrate 20 by a yellow light process.
- the substrate substrate 20 is first cleaned and dried, and then a metal layer can be formed on the substrate substrate 20 by a PVD (Physical Vapor Deposition) method.
- the thickness of the metal layer can be for
- the material includes, but is not limited to, an alloy of any one or more of Mo (molybdenum), Al (aluminum), Cu (copper), Ti (titanium), and then a full-surface photoresist layer is coated on the metal layer.
- the photoresist layer is exposed and developed by using a photomask, the fully exposed photoresist is removed by the developer, and the unexposed photoresist is retained, and further, etching is performed to remove the metal not covered by the remaining photoresist layer.
- the layer, which in turn removes the remaining photoresist layer, is the gate pattern 21 that is ultimately retained.
- the insulating layer 22 is also referred to as a Gate Insulation Layer (GI), which may be a full-surface structure formed on the substrate substrate 20 by a CVD (Chemical Vapor Deposition) method, and the upper surface thereof is a plane, and the thickness can be
- the material of the insulating layer 22 may be a silicon oxide compound (SiO x ), or the insulating layer 22 may also include a silicon oxide compound layer and a silicon nitride compound (SiN x ) sequentially formed on the gate pattern 21.
- SiO 2 (silicon dioxide) and Si 3 N 4 (silicon nitride) make the insulating layer 22 have higher wear resistance and better insulating properties.
- the present embodiment can form a predetermined semiconductor pattern 23 on the insulating layer 22 by a CVD method, and the semiconductor pattern 23 is located directly above the gate pattern 21.
- the thickness of the semiconductor pattern 23 can be The material thereof includes, but is not limited to, IGZO (Indium Gallium Zinc Oxide), IZTO (Indium Zinc Tin Oxide), and IGZTO (Indium Gallium Zinc Tin Oxide).
- the present embodiment can select the corresponding method to form the semiconductor pattern 23 on the insulating layer 22.
- S14 forming at least one second protective layer covering the first protective layer, wherein a deposition power of the second protective layer is greater than a deposition power of the first protective layer.
- the main purpose of this embodiment is to limit the deposition power of the second protective layer to be greater than the deposition power of the first protective layer, and does not limit which process is specifically employed when forming the first protective layer and the second protective layer. Also, the present embodiment can form the first protective layer and the second protective layer by the same film forming process, such as a CVD process.
- a first protective layer 241 is formed on the layer 22 and the semiconductor pattern 23.
- the second protective layer 242 is formed.
- the present embodiment can control the deposition power of the first protective layer 241 by adjusting parameters such as gas inlet rate, temperature, and the like which affect the progress of the gas phase reaction.
- the deposition power of the first protective layer 242 is small, the deposition rate is slow, the film formation density is good, and the plasma formed by the dissociation of the plasma (also called the plasma) has a small bombardment effect on the upper surface of the semiconductor pattern 23, which is favorable for reducing the semiconductor.
- the physical damage of the upper surface of the pattern 23 makes it less rigid and reduces the trapping effect on electrons, thereby facilitating the electrical performance of the channel.
- the deposition power of the second protective layer 242 may be the same as the deposition power of the existing ESL or channel protective layer.
- the thickness of the first protective layer 241 is smaller than the thickness of the second protective layer 242, and the upper surface of the second protective layer 242 is a flat surface.
- the materials of the first protective layer 241 and the second protective layer 242 may be the same, for example, all of them are silicon oxide compounds.
- each of the second protective layers 242 may be a silicon oxide compound layer and a silicon nitride compound alternately formed on the first protective layer 241 in order, so that the second protective layer 242 has a higher Wear resistance and better insulation properties.
- the first protective layer 241 and the second protective layer 242 may be formed according to different materials.
- the present embodiment can form the contact hole 243 and the contact hole 244 by an etching process. Specifically, first, a full-surface photoresist layer can be formed on the second protective layer 242 by using a CVD method, and then the photoresist layer is exposed and developed by using a photomask, and the fully exposed photoresist is removed by the developer, and is not exposed. The photoresist is retained to remove the photoresist layer directly above the contact hole 243 and the contact hole 244, and then the first protective layer 241 and the second protective layer 242 are etched and covered by the photoresist layer.
- a protective layer 241 and a second protective layer 242 are retained, and the remaining first protective layer 241 and second protective layer 242 are etched away to form contact holes 243 and contact holes 244, and finally the remaining lithography is removed by ashing. Adhesive layer.
- S16 forming a source pattern and a drain pattern on the second protective layer, the source pattern is covered in one of the contact holes and connected to the semiconductor pattern, and the drain pattern is covered in the other contact hole and connected to the semiconductor pattern.
- the source pattern 251 and the drain pattern 252 can be formed by a yellow light process.
- the principle and process can be referred to the prior art.
- the thickness of the source pattern 251 and the drain pattern 252 may be equal, for example, both
- the materials of the two may be the same, for example, all of them are alloys of any one or several of Mo, Al, Cu, and Ti.
- a passivation layer (Passivation, PV layer) 26 can be formed by a CVD method, and the passivation layer 26 is a one-sided structure having via holes 261 for protecting the source pattern 251 and the drain pattern 252.
- the thickness of the passivation layer 26 can be Materials include, but are not limited to, SiO x and/or SiN x .
- the via 261 can be used to achieve electrical connection between the drain pattern 252 and the pixel electrode pattern.
- the present embodiment can produce a desired thin film transistor.
- the first protective layer 241 and the second protective layer 242 can be regarded as the ESL of the TFT channel, which can avoid damage of the semiconductor pattern 23 (channel) by the etching liquid in the subsequent etching process, and Since the deposition power of the first protective layer 241 directly formed on the channel is small, the bombardment effect of the Plasma on the channel can be reduced in the process of forming the first protective layer 241, thereby facilitating the damage of the channel and ensuring the groove.
- the electrical properties of the road can be regarded as the ESL of the TFT channel, which can avoid damage of the semiconductor pattern 23 (channel) by the etching liquid in the subsequent etching process, and Since the deposition power of the first protective layer 241 directly formed on the channel is small, the bombardment effect of the Plasma on the channel can be reduced in the process of forming the first protective layer 241, thereby facilitating the damage of the channel and ensuring the groove.
- the electrical properties of the road can be regarded as the ESL of the TFT channel, which can avoid damage of the semiconductor pattern 23
- the present invention further provides a display panel according to an embodiment.
- the liquid crystal display panel 30 can include a first substrate 31 and a second substrate 32.
- the thin film transistor can be formed on the first substrate 31 or the second substrate 32. . Therefore, the display panel 30 also has the above-described advantageous effects.
- the display panel 30 includes, but is not limited to, a liquid crystal display panel, an AMOLED (Active-Matrix Organic Light Emitting Diode), or an active matrix organic light emitting diode (Active Matrix Organic Light Emitting Diode).
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- Thin Film Transistor (AREA)
Abstract
Provided are a thin film transistor and a manufacturing method therefor, and a display panel. The method comprises: (S13) forming a first protective layer (241) covering a semiconductor pattern (23); (S14) forming at least one second protective layer (242) covering the first protective layer, wherein the deposition power of the second protective layer is greater than the deposition power of the first protective layer; and (S16) forming, on the second protective layer, a source electrode pattern (251) and a drain electrode pattern (252) both connected to the semiconductor pattern. The method is beneficial for avoiding damaging a channel and ensuring the electrical performance of the channel.
Description
本发明涉及显示技术领域，具体而言涉及一种薄膜晶体管及其制造方法、以及具有该薄膜晶体管的显示面板。The present invention relates to the field of display technologies, and in particular to a thin film transistor, a method of fabricating the same, and a display panel having the same.
随着人们对显示面板的大尺寸和清晰度的要求越来越高，具有较大电子迁移率的TFT(Thin Film Transistor，薄膜晶体管)结构已崭露头角并表现出巨大的市场应用前景。当前，业界普遍采用IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)来制备TFT的半导体图案(有源层)，并且该有源层位于源极图案和漏极图案的部分形成TFT的沟道，由于IGZO是一种电学性能极其敏感的材料，因此在LCD的制造过程中沟道容易受到损伤，例如在刻蚀形成TFT的源极图案和漏极图案的过程中，刻蚀液极易损伤沟道，从而影响沟道的电学性能。With the increasing demand for large size and definition of display panels, TFT (Thin Film Transistor) structures with large electron mobility have emerged and have shown great market application prospects. Currently, IGZO (Indium Gallium Zinc Oxide) is commonly used in the industry to prepare a semiconductor pattern (active layer) of a TFT, and the active layer is located at a portion of the source pattern and the drain pattern to form a channel of the TFT. Since IGZO is a material with extremely sensitive electrical properties, the channel is easily damaged during the manufacturing process of the LCD. For example, in etching the source pattern and the drain pattern of the TFT, the etching liquid is easily damaged. The channel, which affects the electrical properties of the channel.
【发明内容】[Summary of the Invention]
鉴于此，本发明提供一种薄膜晶体管及其制造方法、显示面板，能够有利于避免损伤沟道，确保沟道的电学性能。In view of this, the present invention provides a thin film transistor, a method of manufacturing the same, and a display panel, which can be advantageously prevented from damaging the channel and ensuring electrical properties of the channel.
本发明一实施例的薄膜晶体管的制造方法，包括：A method of manufacturing a thin film transistor according to an embodiment of the present invention includes:
在衬底基材上形成栅极图案及覆盖栅极图案的绝缘层；Forming a gate pattern and an insulating layer covering the gate pattern on the substrate substrate;
在绝缘层上形成半导体图案；Forming a semiconductor pattern on the insulating layer;
在绝缘层上形成覆盖半导体图案的第一保护层；Forming a first protective layer covering the semiconductor pattern on the insulating layer;
形成覆盖第一保护层的至少一第二保护层，其中第二保护层的沉积功率大于第一保护层的沉积功率；Forming at least one second protective layer covering the first protective layer, wherein a deposition power of the second protective layer is greater than a deposition power of the first protective layer;
形成均贯穿第一保护层和第二保护层的两个接触孔，两个接触孔间隔设置且均暴露半导体图案的表面；Forming two contact holes each penetrating through the first protective layer and the second protective layer, the two contact holes being spaced apart and exposing the surface of the semiconductor pattern;
在第二保护层上形成源极图案和漏极图案，源极图案覆盖于其中一个接触孔中并与半导体图案连接，漏极图案覆盖于另一个接触孔中并与半导体图案连接；
Forming a source pattern and a drain pattern on the second protective layer, the source pattern is covered in one of the contact holes and connected to the semiconductor pattern, and the drain pattern is covered in the other contact hole and connected to the semiconductor pattern;
在第二保护层上形成覆盖源极图案和漏极图案的钝化层。A passivation layer covering the source pattern and the drain pattern is formed on the second protective layer.
本发明一实施例的薄膜晶体管包括：A thin film transistor according to an embodiment of the present invention includes:
衬底基材；Substrate substrate;
位于衬底基材上的栅极图案及覆盖栅极图案的绝缘层；a gate pattern on the substrate substrate and an insulating layer covering the gate pattern;
位于绝缘层上且覆盖半导体图案的第一保护层；a first protective layer on the insulating layer and covering the semiconductor pattern;
覆盖第一保护层的至少一第二保护层，第二保护层的沉积功率大于第一保护层的沉积功率，其中第一保护层和第二保护层开设有均贯穿第一保护层和第二保护层的两个接触孔，两个接触孔间隔设置且均暴露半导体图案的表面；Covering at least one second protective layer of the first protective layer, the deposition power of the second protective layer is greater than the deposition power of the first protective layer, wherein the first protective layer and the second protective layer are both open through the first protective layer and the second Two contact holes of the protective layer, the two contact holes are spaced apart and both expose the surface of the semiconductor pattern;
位于第二保护层上的源极图案和漏极图案，源极图案覆盖于其中一个接触孔中并与半导体图案连接，漏极图案覆盖于另一个接触孔中并与半导体图案连接；a source pattern and a drain pattern on the second protective layer, the source pattern is covered in one of the contact holes and connected to the semiconductor pattern, and the drain pattern is covered in the other contact hole and connected to the semiconductor pattern;
位于第二保护层上且覆盖源极图案和漏极图案的钝化层。A passivation layer on the second protective layer covering the source pattern and the drain pattern.
本发明一实施例的显示面板，其薄膜晶体管包括：A display panel according to an embodiment of the invention includes a thin film transistor including:
衬底基材；Substrate substrate;
位于衬底基材上的栅极图案及覆盖栅极图案的绝缘层；a gate pattern on the substrate substrate and an insulating layer covering the gate pattern;
位于绝缘层上且覆盖半导体图案的第一保护层；a first protective layer on the insulating layer and covering the semiconductor pattern;
覆盖第一保护层的至少一第二保护层，第二保护层的沉积功率大于第一保护层的沉积功率，其中第一保护层和第二保护层开设有均贯穿第一保护层和第二保护层的两个接触孔，两个接触孔间隔设置且均暴露半导体图案的表面；Covering at least one second protective layer of the first protective layer, the deposition power of the second protective layer is greater than the deposition power of the first protective layer, wherein the first protective layer and the second protective layer are both open through the first protective layer and the second Two contact holes of the protective layer, the two contact holes are spaced apart and both expose the surface of the semiconductor pattern;
位于第二保护层上的源极图案和漏极图案，源极图案覆盖于其中一个接触孔中并与半导体图案连接，漏极图案覆盖于另一个接触孔中并与半导体图案连接；a source pattern and a drain pattern on the second protective layer, the source pattern is covered in one of the contact holes and connected to the semiconductor pattern, and the drain pattern is covered in the other contact hole and connected to the semiconductor pattern;
位于第二保护层上且覆盖源极图案和漏极图案的钝化层。A passivation layer on the second protective layer covering the source pattern and the drain pattern.
有益效果：本发明设计TFT沟道的ESL(Etch Stop Layer，刻蚀阻挡层)为依次形成于半导体图案上的第一保护层和至少一第二保护层，由于直接形成于沟道上的第一保护层的沉积功率较小，因此在形成第一保护层的过程中能够减少Plasma(等离子体)对沟道的轰击作用，从而有利于避免损伤沟道，确保沟道的电学性能。
[Advantageous Effects] The ESL (Etch Stop Layer) of the TFT channel of the present invention is a first protective layer and at least a second protective layer sequentially formed on the semiconductor pattern, since the first layer is directly formed on the channel The deposition power of the protective layer is small, so that the bombardment effect of the plasma on the channel can be reduced in the process of forming the first protective layer, thereby facilitating the damage of the channel and ensuring the electrical performance of the channel.
图1是本发明一实施例的薄膜晶体管的制造方法的流程示意图；1 is a flow chart showing a method of manufacturing a thin film transistor according to an embodiment of the present invention;
图2是基于图1所示方法制造薄膜晶体管的场景示意图；2 is a schematic view of a process for fabricating a thin film transistor based on the method shown in FIG. 1;
图3是本发明的显示面板一实施例的结构剖面示意图。Fig. 3 is a cross-sectional view showing the structure of an embodiment of the display panel of the present invention.
下面结合附图对本发明的各个实施例的技术方案进行清楚、完整地描述。在不冲突的情况下，下述实施例及其技术特征可以相互组合。并且，以下全文所采用的方向性术语，例如“上”、“下”等，均是为了更好的描述各个实施例，并非用于限制本发明的保护范围。The technical solutions of the various embodiments of the present invention are clearly and completely described below with reference to the accompanying drawings. The following embodiments and their technical features can be combined with each other without conflict. In addition, the directional terms used in the following text, such as "upper", "lower", etc., are used to better describe the various embodiments and are not intended to limit the scope of the invention.
图1是本发明一实施例的薄膜晶体管的制造方法的流程示意图。请参阅图1，本实施例的薄膜晶体管的制造方法包括步骤S11～S17。1 is a flow chart showing a method of manufacturing a thin film transistor according to an embodiment of the present invention. Referring to FIG. 1, a method of manufacturing a thin film transistor of this embodiment includes steps S11 to S17.
S11：在衬底基材上形成栅极图案及覆盖栅极图案的绝缘层。S11: forming a gate pattern and an insulating layer covering the gate pattern on the substrate substrate.
结合图2所示，衬底基材20可以为玻璃基材、透明塑料基材、可挠式基材等透光基材。当然，本实施例的衬底基材20也可以设置有钝化保护层，例如衬底基材20可以包括基板和形成于基板上的钝化保护层，基板可以为玻璃基材、透明塑料基材、可挠式基材等透光基材，钝化保护层的材料包括但不限于硅氮化合物，例如Si3N4(四氮化三硅，简称氮化硅)，以提高衬底基材20表面的结构稳定性。As shown in FIG. 2, the substrate substrate 20 may be a light-transmitting substrate such as a glass substrate, a transparent plastic substrate, or a flexible substrate. Of course, the substrate substrate 20 of the present embodiment may also be provided with a passivation protective layer. For example, the substrate substrate 20 may include a substrate and a passivation protective layer formed on the substrate, and the substrate may be a glass substrate or a transparent plastic base. A transparent substrate such as a material or a flexible substrate. The material of the passivation protective layer includes, but is not limited to, a silicon nitride compound, such as Si 3 N 4 (tetrazinc silicon nitride, referred to as silicon nitride), to improve the substrate base. Structural stability of the surface of the material 20.
本实施例可以通过一道黄光制程在衬底基材20上形成预定的栅极图案21。具体而言，首先对衬底基材20进行清洗及烘干处理，然后可以采用PVD(Physical Vapor Deposition，物理气相沉积)方法在衬底基材20上形成一金属层，该金属层的厚度可以为
其材料包括但不限于Mo(钼)、Al(铝)、Cu(铜)、Ti(钛)中的任一种或几种的合金，接着在金属层上涂布一整面光刻胶层，再采用光罩对光刻胶层进行曝光显影，完全曝光的光刻胶被显影液去除，而未曝光的光刻胶被保留，进一步，刻蚀去除未被剩余光刻胶层遮盖的金属层，继而去除剩余光刻胶层，最终保留的金属层即为栅极图案21。This embodiment can form a predetermined gate pattern 21 on the substrate substrate 20 by a yellow light process. Specifically, the substrate substrate 20 is first cleaned and dried, and then a metal layer can be formed on the substrate substrate 20 by a PVD (Physical Vapor Deposition) method. The thickness of the metal layer can be for The material includes, but is not limited to, an alloy of any one or more of Mo (molybdenum), Al (aluminum), Cu (copper), Ti (titanium), and then a full-surface photoresist layer is coated on the metal layer. Then, the photoresist layer is exposed and developed by using a photomask, the fully exposed photoresist is removed by the developer, and the unexposed photoresist is retained, and further, etching is performed to remove the metal not covered by the remaining photoresist layer. The layer, which in turn removes the remaining photoresist layer, is the gate pattern 21 that is ultimately retained.
绝缘层22又称栅极绝缘层(Gate Insulation Layer，GI)，其可以为采用
CVD(Chemical Vapor Deposition，化学气相沉积)方法形成于衬底基材20上的一整面结构，其上表面为一平面，且厚度可以为
在本实施例中，绝缘层22的材质可以为硅氧化合物(SiOx)，或者，绝缘层22也可以包括依次形成于栅极图案21上的硅氧化合物层和硅氮化合物(SiNx)，例如SiO2(二氧化硅)和Si3N4(三氮化硅)，从而使得绝缘层22具有较高的耐磨损能力和较佳的绝缘性能。The insulating layer 22 is also referred to as a Gate Insulation Layer (GI), which may be a full-surface structure formed on the substrate substrate 20 by a CVD (Chemical Vapor Deposition) method, and the upper surface thereof is a plane, and the thickness can be In this embodiment, the material of the insulating layer 22 may be a silicon oxide compound (SiO x ), or the insulating layer 22 may also include a silicon oxide compound layer and a silicon nitride compound (SiN x ) sequentially formed on the gate pattern 21. For example, SiO 2 (silicon dioxide) and Si 3 N 4 (silicon nitride) make the insulating layer 22 have higher wear resistance and better insulating properties.
S12：在绝缘层上形成半导体图案。S12: forming a semiconductor pattern on the insulating layer.
继续参阅图2，本实施例可以采用CVD方法在绝缘层22上形成预定的半导体图案23，该半导体图案23位于栅极图案21的正上方。其中，半导体图案23的厚度可以为
其材质包括但不限于IGZO(铟镓锌氧化物)、IZTO(铟锌锡氧化物)、以及IGZTO(铟镓锌锡氧化物)中的任一种。另外，根据材质的不同，本实施例可以选取相对应的方法在绝缘层22上形成上述半导体图案23。With continued reference to FIG. 2, the present embodiment can form a predetermined semiconductor pattern 23 on the insulating layer 22 by a CVD method, and the semiconductor pattern 23 is located directly above the gate pattern 21. Wherein, the thickness of the semiconductor pattern 23 can be The material thereof includes, but is not limited to, IGZO (Indium Gallium Zinc Oxide), IZTO (Indium Zinc Tin Oxide), and IGZTO (Indium Gallium Zinc Tin Oxide). In addition, according to different materials, the present embodiment can select the corresponding method to form the semiconductor pattern 23 on the insulating layer 22.
S13：在绝缘层上形成覆盖半导体图案的第一保护层。S13: forming a first protective layer covering the semiconductor pattern on the insulating layer.
S14：形成覆盖第一保护层的至少一第二保护层，其中第二保护层的沉积功率大于第一保护层的沉积功率。S14: forming at least one second protective layer covering the first protective layer, wherein a deposition power of the second protective layer is greater than a deposition power of the first protective layer.
本实施例的主要目的是限制第二保护层的沉积功率大于第一保护层的沉积功率，而并不限制形成第一保护层和第二保护层时具体采用哪一种工艺。并且，本实施例可以通过相同的成膜工艺，例如CVD工艺，形成第一保护层和第二保护层。The main purpose of this embodiment is to limit the deposition power of the second protective layer to be greater than the deposition power of the first protective layer, and does not limit which process is specifically employed when forming the first protective layer and the second protective layer. Also, the present embodiment can form the first protective layer and the second protective layer by the same film forming process, such as a CVD process.
以CVD工艺为例，在高温环境下，将含有构成第一保护层的气态反应剂或液态反应剂的蒸汽及反应所需其它气体引入反应室，并在反应室中发生气相反应，从而在绝缘层22和半导体图案23上沉积生成第一保护层241。同理形成第二保护层242。Taking a CVD process as an example, in a high temperature environment, steam containing a gaseous reactant or a liquid reactant constituting the first protective layer and other gases required for the reaction are introduced into the reaction chamber, and a gas phase reaction occurs in the reaction chamber, thereby insulating A first protective layer 241 is formed on the layer 22 and the semiconductor pattern 23. Similarly, the second protective layer 242 is formed.
在CVD工艺的整个过程中，本实施例可以通过调整气体通入速率、温度等影响气相反应进程的参数来控制第一保护层241的沉积功率。第一保护层242的沉积功率较小，沉积速率慢，成膜致密性好，气体解离后形成的Plasma(又称电浆体)对半导体图案23上表面的轰击作用小，有利于减少半导体图案23上表面的物理损伤，使其粗糙度较小，降低对电子的束缚(trap)作用，从而有利于确保沟道的电学性能。并且，半导体图案23上
表面受到的轰击作用小，有利于避免沟道表面的氧离子被轰击掉，进一步确保沟道的电学性能。而第二保护层242的沉积功率可以与现有ESL或沟道保护层的沉积功率相同。In the entire process of the CVD process, the present embodiment can control the deposition power of the first protective layer 241 by adjusting parameters such as gas inlet rate, temperature, and the like which affect the progress of the gas phase reaction. The deposition power of the first protective layer 242 is small, the deposition rate is slow, the film formation density is good, and the plasma formed by the dissociation of the plasma (also called the plasma) has a small bombardment effect on the upper surface of the semiconductor pattern 23, which is favorable for reducing the semiconductor. The physical damage of the upper surface of the pattern 23 makes it less rigid and reduces the trapping effect on electrons, thereby facilitating the electrical performance of the channel. And, on the semiconductor pattern 23
The impact of the surface is small, which helps to avoid the bombardment of oxygen ions on the surface of the channel, further ensuring the electrical properties of the channel. The deposition power of the second protective layer 242 may be the same as the deposition power of the existing ESL or channel protective layer.
其中，第一保护层241的厚度小于第二保护层242的厚度，且第二保护层242的上表面为一平面。另外，第一保护层241和第二保护层242的材质可以相同，例如均为硅氧化合物。在形成多个第二保护层242的场景中，各个第二保护层242可以为依次交替形成于第一保护层241上的硅氧化合物层和硅氮化合物，使得第二保护层242具有较高的耐磨损能力和较佳的绝缘性能。本实施例可以根据材质的不同选取相对应的方法形成所述第一保护层241和第二保护层242。The thickness of the first protective layer 241 is smaller than the thickness of the second protective layer 242, and the upper surface of the second protective layer 242 is a flat surface. In addition, the materials of the first protective layer 241 and the second protective layer 242 may be the same, for example, all of them are silicon oxide compounds. In the scene in which the plurality of second protective layers 242 are formed, each of the second protective layers 242 may be a silicon oxide compound layer and a silicon nitride compound alternately formed on the first protective layer 241 in order, so that the second protective layer 242 has a higher Wear resistance and better insulation properties. In this embodiment, the first protective layer 241 and the second protective layer 242 may be formed according to different materials.
S15：形成均贯穿第一保护层和第二保护层的两个接触孔，两个接触孔间隔设置且均暴露半导体图案的表面。S15: forming two contact holes each penetrating through the first protective layer and the second protective layer, the two contact holes being spaced apart and exposing the surface of the semiconductor pattern.
继续参阅图2，本实施例可以通过刻蚀工艺形成接触孔243和接触孔244。具体地，首先可以采用CVD方法在第二保护层242上形成一整面光刻胶层，再采用光罩对光刻胶层进行曝光显影，完全曝光的光刻胶被显影液去除，未曝光的光刻胶被保留，从而去除位于接触孔243和接触孔244正上方的光刻胶层，接着对第一保护层241和第二保护层242进行刻蚀，被光刻胶层遮盖的第一保护层241和第二保护层242被保留，其余的第一保护层241和第二保护层242被刻蚀去除，从而形成接触孔243和接触孔244，最后通过灰化处理去除剩余光刻胶层。Continuing to refer to FIG. 2, the present embodiment can form the contact hole 243 and the contact hole 244 by an etching process. Specifically, first, a full-surface photoresist layer can be formed on the second protective layer 242 by using a CVD method, and then the photoresist layer is exposed and developed by using a photomask, and the fully exposed photoresist is removed by the developer, and is not exposed. The photoresist is retained to remove the photoresist layer directly above the contact hole 243 and the contact hole 244, and then the first protective layer 241 and the second protective layer 242 are etched and covered by the photoresist layer. A protective layer 241 and a second protective layer 242 are retained, and the remaining first protective layer 241 and second protective layer 242 are etched away to form contact holes 243 and contact holes 244, and finally the remaining lithography is removed by ashing. Adhesive layer.
S16：在第二保护层上形成源极图案和漏极图案，源极图案覆盖于其中一个接触孔中并与半导体图案连接，漏极图案覆盖于另一个接触孔中并与半导体图案连接。S16: forming a source pattern and a drain pattern on the second protective layer, the source pattern is covered in one of the contact holes and connected to the semiconductor pattern, and the drain pattern is covered in the other contact hole and connected to the semiconductor pattern.
本实施例可以通过一道黄光制程形成源极图案251和漏极图案252，其原理及过程可参阅现有技术。源极图案251和漏极图案252的厚度可以相等，例如均为
两者的材料也可以相同，例如均为Mo、Al、Cu、Ti中的任一种或几种的合金。In this embodiment, the source pattern 251 and the drain pattern 252 can be formed by a yellow light process. The principle and process can be referred to the prior art. The thickness of the source pattern 251 and the drain pattern 252 may be equal, for example, both The materials of the two may be the same, for example, all of them are alloys of any one or several of Mo, Al, Cu, and Ti.
S17：在第二保护层上形成覆盖源极图案和漏极图案的钝化层。S17: forming a passivation layer covering the source pattern and the drain pattern on the second protective layer.
本实施例可以采用CVD方法形成钝化层(Passivation，PV层)26，该钝化层26为具有过孔261的一整面结构，用于保护源极图案251和漏极图
案252。钝化层26的厚度可以为
其材料包括但不限于SiOx和/或SiNx。其中，过孔261可用于实现漏极图案252与像素电极图案的电性连接。In this embodiment, a passivation layer (Passivation, PV layer) 26 can be formed by a CVD method, and the passivation layer 26 is a one-sided structure having via holes 261 for protecting the source pattern 251 and the drain pattern 252. The thickness of the passivation layer 26 can be Materials include, but are not limited to, SiO x and/or SiN x . The via 261 can be used to achieve electrical connection between the drain pattern 252 and the pixel electrode pattern.
通过上述方式，本实施例即可制得所需要的薄膜晶体管。In the above manner, the present embodiment can produce a desired thin film transistor.
在本实施例中，第一保护层241和第二保护层242可视为TFT沟道的ESL，该ESL能够避免后续刻蚀制程中刻蚀液对半导体图案23(沟道)的损伤，并且，由于直接形成于沟道上的第一保护层241的沉积功率较小，因此在形成第一保护层241的过程中能够减少Plasma对沟道的轰击作用，从而有利于避免损伤沟道，确保沟道的电学性能。In the present embodiment, the first protective layer 241 and the second protective layer 242 can be regarded as the ESL of the TFT channel, which can avoid damage of the semiconductor pattern 23 (channel) by the etching liquid in the subsequent etching process, and Since the deposition power of the first protective layer 241 directly formed on the channel is small, the bombardment effect of the Plasma on the channel can be reduced in the process of forming the first protective layer 241, thereby facilitating the damage of the channel and ensuring the groove. The electrical properties of the road.
本发明还提供一实施例的显示面板，如图3所示，该液晶显示面板30可以包括第一基板31和第二基板32，上述薄膜晶体管可形成于第一基板31或第二基板32上。因此，该显示面板30也具有上述有益效果。该显示面板30包括但不限于液晶显示面板、AMOLED(Active-matrix organic light emitting diode，有源矩阵有机发光二极体或主动矩阵有机发光二极体)等类型的显示面板。The present invention further provides a display panel according to an embodiment. As shown in FIG. 3, the liquid crystal display panel 30 can include a first substrate 31 and a second substrate 32. The thin film transistor can be formed on the first substrate 31 or the second substrate 32. . Therefore, the display panel 30 also has the above-described advantageous effects. The display panel 30 includes, but is not limited to, a liquid crystal display panel, an AMOLED (Active-Matrix Organic Light Emitting Diode), or an active matrix organic light emitting diode (Active Matrix Organic Light Emitting Diode).
应理解，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。
It should be understood that the above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention, the equivalent structure or equivalent process transformations, such as the techniques between the embodiments, using the present specification and the drawings. The combination of features, or directly or indirectly, in other related technical fields, is equally included in the scope of patent protection of the present invention.
Claims (13)
- 一种薄膜晶体管的制造方法，其中，所述方法包括：A method of fabricating a thin film transistor, wherein the method comprises:在衬底基材上形成栅极图案及覆盖所述栅极图案的绝缘层；Forming a gate pattern on the substrate substrate and an insulating layer covering the gate pattern;在所述绝缘层上形成半导体图案；Forming a semiconductor pattern on the insulating layer;在所述绝缘层上形成覆盖所述半导体图案的第一保护层；Forming a first protective layer covering the semiconductor pattern on the insulating layer;形成覆盖所述第一保护层的至少一第二保护层，其中所述第二保护层的沉积功率大于所述第一保护层的沉积功率；Forming at least one second protective layer covering the first protective layer, wherein a deposition power of the second protective layer is greater than a deposition power of the first protective layer;形成均贯穿所述第一保护层和第二保护层的两个接触孔，所述两个接触孔间隔设置且均暴露所述半导体图案的表面；Forming two contact holes each penetrating the first protective layer and the second protective layer, the two contact holes being spaced apart and exposing surfaces of the semiconductor pattern;在所述第二保护层上形成源极图案和漏极图案，所述源极图案覆盖于其中一个接触孔中并与所述半导体图案连接，所述漏极图案覆盖于另一个接触孔中并与所述半导体图案连接；Forming a source pattern and a drain pattern on the second protective layer, the source pattern covering one of the contact holes and being connected to the semiconductor pattern, the drain pattern covering the other contact hole and Connecting with the semiconductor pattern;在所述第二保护层上形成覆盖所述源极图案和漏极图案的钝化层。A passivation layer covering the source pattern and the drain pattern is formed on the second protective layer.
- 根据权利要求1所述的方法，其中，通过相同的成膜工艺形成所述第一保护层和所述第二保护层。The method of claim 1, wherein the first protective layer and the second protective layer are formed by the same film forming process.
- 根据权利要求1所述的方法，其中，通过化学气相沉积CVD工艺形成所述第一保护层和第二保护层中的至少一者。The method of claim 1, wherein at least one of the first protective layer and the second protective layer is formed by a chemical vapor deposition CVD process.
- 根据权利要求1所述的方法，其中，采用相同的材质形成所述第一保护层和所述第二保护层。The method of claim 1 wherein the first protective layer and the second protective layer are formed using the same material.
- 根据权利要求1所述的方法，其中，所述第一保护层的厚度小于所述第二保护层的厚度。The method of claim 1 wherein the thickness of the first protective layer is less than the thickness of the second protective layer.
- 一种薄膜晶体管，其中，所述薄膜晶体管包括：A thin film transistor, wherein the thin film transistor comprises:衬底基材；Substrate substrate;位于所述衬底基材上的栅极图案及覆盖所述栅极图案的绝缘层；a gate pattern on the substrate substrate and an insulating layer covering the gate pattern;位于所述绝缘层上且覆盖所述半导体图案的第一保护层；a first protective layer on the insulating layer and covering the semiconductor pattern;覆盖所述第一保护层的至少一第二保护层，所述第二保护层的沉积功率大于所述第一保护层的沉积功率，其中所述第一保护层和第二保护层开设有均贯穿所述第一保护层和第二保护层的两个接触孔，所述两个接触孔间隔设置且均暴露所述半导体图案的表面； Covering at least one second protective layer of the first protective layer, the deposition power of the second protective layer is greater than the deposition power of the first protective layer, wherein the first protective layer and the second protective layer are both open Through the two contact holes of the first protective layer and the second protective layer, the two contact holes are spaced apart and both expose the surface of the semiconductor pattern;位于所述第二保护层上的源极图案和漏极图案，所述源极图案覆盖于其中一个接触孔中并与所述半导体图案连接，所述漏极图案覆盖于另一个接触孔中并与所述半导体图案连接；a source pattern and a drain pattern on the second protective layer, the source pattern covering one of the contact holes and connected to the semiconductor pattern, the drain pattern covering the other contact hole and Connecting with the semiconductor pattern;位于所述第二保护层上且覆盖所述源极图案和漏极图案的钝化层。a passivation layer on the second protective layer covering the source pattern and the drain pattern.
- 根据权利要求6所述的薄膜晶体管，其中，所述第一保护层和所述第二保护层的材质相同。The thin film transistor according to claim 6, wherein the first protective layer and the second protective layer are made of the same material.
- 根据权利要求6所述的薄膜晶体管，其中，所述第一保护层的材质包括硅氧化合物。The thin film transistor according to claim 6, wherein the material of the first protective layer comprises a silicon oxide compound.
- 根据权利要求6所述的薄膜晶体管，其中，所述第一保护层的厚度小于所述第二保护层的厚度。The thin film transistor according to claim 6, wherein the thickness of the first protective layer is smaller than the thickness of the second protective layer.
- 一种显示面板，其中，所述显示面板的薄膜晶体管包括：A display panel, wherein the thin film transistor of the display panel comprises:衬底基材；Substrate substrate;位于所述衬底基材上的栅极图案及覆盖所述栅极图案的绝缘层；a gate pattern on the substrate substrate and an insulating layer covering the gate pattern;位于所述绝缘层上且覆盖所述半导体图案的第一保护层；a first protective layer on the insulating layer and covering the semiconductor pattern;覆盖所述第一保护层的至少一第二保护层，所述第二保护层的沉积功率大于所述第一保护层的沉积功率，其中所述第一保护层和第二保护层开设有均贯穿所述第一保护层和第二保护层的两个接触孔，所述两个接触孔间隔设置且均暴露所述半导体图案的表面；Covering at least one second protective layer of the first protective layer, the deposition power of the second protective layer is greater than the deposition power of the first protective layer, wherein the first protective layer and the second protective layer are both open Through the two contact holes of the first protective layer and the second protective layer, the two contact holes are spaced apart and both expose the surface of the semiconductor pattern;位于所述第二保护层上的源极图案和漏极图案，所述源极图案覆盖于其中一个接触孔中并与所述半导体图案连接，所述漏极图案覆盖于另一个接触孔中并与所述半导体图案连接；a source pattern and a drain pattern on the second protective layer, the source pattern covering one of the contact holes and connected to the semiconductor pattern, the drain pattern covering the other contact hole and Connecting with the semiconductor pattern;位于所述第二保护层上且覆盖所述源极图案和漏极图案的钝化层。a passivation layer on the second protective layer covering the source pattern and the drain pattern.
- 根据权利要求10所述的显示面板，其中，所述第一保护层和所述第二保护层的材质相同。The display panel according to claim 10, wherein the first protective layer and the second protective layer are made of the same material.
- 根据权利要求10所述的显示面板，其中，所述第一保护层的材质包括硅氧化合物。The display panel according to claim 10, wherein the material of the first protective layer comprises a silicon oxide compound.
- 根据权利要求10所述的显示面板，其中，所述第一保护层的厚度小于所述第二保护层的厚度。 The display panel according to claim 10, wherein the thickness of the first protective layer is smaller than the thickness of the second protective layer.
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| CN102437194A (en) * | 2011-11-22 | 2012-05-02 | 上海中科高等研究院 | Metal oxide thin film transistor and preparation method thereof |
| US20130242220A1 (en) * | 2012-03-15 | 2013-09-19 | Wintek Corporation | Thin-film transistor, method of manufacturing the same and active matrix display panel using the same |
| CN103887343A (en) * | 2012-12-21 | 2014-06-25 | 北京京东方光电科技有限公司 | Thin film transistor and manufacturing method thereof, array substrate and display device |
| CN104167447A (en) * | 2014-07-22 | 2014-11-26 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method thereof, display substrate and display device |
| CN105097902A (en) * | 2015-06-11 | 2015-11-25 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate, preparation method therefor, and display device |
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| CN102437194A (en) * | 2011-11-22 | 2012-05-02 | 上海中科高等研究院 | Metal oxide thin film transistor and preparation method thereof |
| US20130242220A1 (en) * | 2012-03-15 | 2013-09-19 | Wintek Corporation | Thin-film transistor, method of manufacturing the same and active matrix display panel using the same |
| CN103887343A (en) * | 2012-12-21 | 2014-06-25 | 北京京东方光电科技有限公司 | Thin film transistor and manufacturing method thereof, array substrate and display device |
| CN104167447A (en) * | 2014-07-22 | 2014-11-26 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method thereof, display substrate and display device |
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