WO2019047329A1 - 一种低温多晶硅面板 - Google Patents

一种低温多晶硅面板 Download PDF

Info

Publication number
WO2019047329A1
WO2019047329A1 PCT/CN2017/105821 CN2017105821W WO2019047329A1 WO 2019047329 A1 WO2019047329 A1 WO 2019047329A1 CN 2017105821 W CN2017105821 W CN 2017105821W WO 2019047329 A1 WO2019047329 A1 WO 2019047329A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
film layer
thin film
opening
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/105821
Other languages
English (en)
French (fr)
Inventor
韩约白
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US15/735,543 priority Critical patent/US10784286B2/en
Publication of WO2019047329A1 publication Critical patent/WO2019047329A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/921—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a low temperature polysilicon panel.
  • Low-temperature polysilicon panels have become the star products in flat panel display products due to their high resolution, high mobility, low power consumption, etc., and are widely used in major mobile phones such as Apple, Samsung, Huawei, Huawei and Meizu. And on the tablet computer, but due to the complicated process of the low-temperature polysilicon device, the ESD (Electro-Static discharge) problem is more likely to occur in the process, and a large amount of charge accumulation may easily cause damage to the edge of the panel and the polysilicon film layer.
  • the gate and the polysilicon film layer are short-circuited, so that the gate signal is input to the polysilicon film layer, causing a defect in the spot, and this phenomenon is concentrated on the edge of the panel. How to improve the anti-ESD capability of the pixel at the edge of the panel has become One of the hot spots of panel industry engineers research.
  • the PV hole and the ILD hole are not disposed on the edge of the polysilicon panel, that is, the interlayer spacer layer (ILD layer) between the polysilicon film layer and the dummy pixel unit is not provided with an opening, thereby forming a polysilicon film layer. It is completely insulated from the dummy pixel unit, and the passivation layer (PV layer) between the dummy pixel unit and the pixel electrode is also not provided with an opening.
  • the disadvantage of this kind of scheme is that the static electricity accumulated on the polysilicon film layer in the process cannot be released when it gathers, which is easy to cause damage.
  • the PV hole and the ILD hole are simultaneously disposed on the edge of the polysilicon panel, and the virtual pixel unit is exactly the same as the real pixel unit of the display area, that is, the interlayer interval between the polysilicon film layer and the dummy pixel unit.
  • the layer (ILD layer) is provided with an opening, and the dummy pixel unit and the pixel
  • a passivation layer (PV layer) between the electrodes is provided with an opening.
  • the present invention provides a low-temperature polysilicon panel, which can guide the accumulated charges on the polysilicon film layer, avoid edge damage of the polysilicon panel, greatly improve the ESD resistance of the panel, and improve the product yield. It can prevent light leakage at the edge of the polysilicon panel.
  • the invention provides a low temperature polysilicon panel, including an edge region,
  • the edge region includes: a polysilicon film layer and an interlayer spacer layer above the polysilicon film layer; a column of dummy pixel cells is disposed on the interlayer spacer layer, and the dummy pixel unit is disposed above the column of the dummy pixel unit a first conductive film layer, the dummy pixel unit and the first conductive film layer are insulated and separated by a passivation layer;
  • the virtual pixel unit of the column comprises a column of thin film transistors, and a data line electrically connected to the thin film transistor for accessing a common signal;
  • a first opening is disposed on the interlayer spacer layer, and the polysilicon film layer is electrically connected to the data line through the first opening.
  • a gate insulating layer is further disposed between the interlayer spacer layer and the polysilicon film layer;
  • the thin film transistor includes: a gate, a drain, and a source;
  • the gate is located between the interlayer spacer layer and the gate insulating layer, and the source and the drain are located on the interlayer spacer layer;
  • the first opening is opposite to the drain and the source, and the second opening is disposed at a position where the gate insulating layer faces the first opening;
  • the data line is electrically connected to the source, and the source and the drain are connected to the polysilicon film layer through the first opening and the second opening.
  • the virtual pixel unit is a column of pixel units at the outermost side of the edge region.
  • the voltage at the input end of the data line is 0.1 to 0.4V.
  • a substrate is disposed under the polysilicon film layer, and a buffer layer is prepared between the polysilicon film layer and the substrate.
  • a flat layer is prepared on the interlayer spacer layer.
  • the buffer layer comprises SiN and/or SixOy, wherein x ⁇ 1, y ⁇ 1.
  • a second conductive thin film layer is prepared between the flat layer and the passivation layer.
  • the first conductive thin film layer is a pixel electrode
  • the second conductive thin film layer is a common electrode
  • the first conductive film layer and the second conductive film layer are both indium tin oxide semiconductor transparent conductive films.
  • the invention also provides a low temperature polysilicon panel comprising an edge region
  • the edge region includes: a polysilicon film layer and an interlayer spacer layer above the polysilicon film layer; a column of dummy pixel cells is disposed on the interlayer spacer layer, and the dummy pixel unit is disposed above the column of the dummy pixel unit a first conductive film layer, the dummy pixel unit and the first conductive film layer are insulated and separated by a passivation layer;
  • the virtual pixel unit of the column comprises a column of thin film transistors, and a data line electrically connected to the thin film transistor for accessing a common signal;
  • a first opening is disposed on the interlayer spacer layer, and the polysilicon film layer is electrically connected to the data line through the first opening;
  • a gate insulating layer is further disposed between the interlayer spacer layer and the polysilicon film layer;
  • the thin film transistor includes: a gate, a drain, and a source;
  • the gate is located between the interlayer spacer layer and the gate insulating layer, and the source and the drain are located on the interlayer spacer layer;
  • the first opening is opposite to the drain and the source, and the second opening is disposed at a position where the gate insulating layer faces the first opening;
  • the data line is electrically connected to the source, and the source and the drain are connected to the polysilicon film layer through the first opening and the second opening.
  • the virtual pixel unit is a column of pixel units at the outermost side of the edge region.
  • the voltage at the input end of the data line is 0.1 to 0.4V;
  • a substrate is disposed under the polysilicon film layer, and a buffer layer is prepared between the polysilicon film layer and the substrate;
  • a flat layer is prepared on the interlayer spacer layer.
  • the buffer layer comprises SiN and/or SixOy, wherein x ⁇ 1, y ⁇ 1;
  • a second conductive thin film layer is prepared between the flat layer and the passivation layer.
  • the first conductive film layer is a pixel electrode, and the second conductive film layer is a common electrode;
  • the first conductive thin film layer and the second conductive thin film layer are both indium tin oxide semiconductor transparent conductive films.
  • the invention also provides a low temperature polysilicon panel comprising an edge region
  • the edge region includes: a polysilicon film layer and an interlayer spacer layer above the polysilicon film layer; a column of dummy pixel cells is disposed on the interlayer spacer layer, and the dummy pixel unit is disposed above the column of the dummy pixel unit a first conductive film layer, the dummy pixel unit and the first conductive film layer are insulated and separated by a passivation layer;
  • the virtual pixel unit of the column comprises a column of thin film transistors, and a data line electrically connected to the thin film transistor for accessing a common signal;
  • a first opening is disposed on the interlayer spacer layer, and the polysilicon film layer is electrically connected to the data line through the first opening;
  • a flat layer is prepared on the interlayer spacer layer.
  • a gate insulating layer is further disposed between the interlayer spacer layer and the polysilicon film layer;
  • the thin film transistor includes: a gate, a drain, and a source;
  • the gate is located between the interlayer spacer layer and the gate insulating layer, and the source and the drain are located on the interlayer spacer layer;
  • the first opening is opposite to the drain and the source, and the second opening is disposed at a position where the gate insulating layer faces the first opening;
  • the data line is electrically connected to the source, and the source and the drain are connected to the polysilicon film layer through the first opening and the second opening.
  • the virtual pixel unit is a column of pixel units at the outermost side of the edge region
  • the voltage at the input end of the data line is 0.1 to 0.4V.
  • a substrate is disposed under the polysilicon film layer, and a buffer layer is prepared between the polysilicon film layer and the substrate;
  • the buffer layer includes SiN and/or SixOy, wherein x ⁇ 1, y ⁇ 1.
  • a second conductive thin film layer is prepared between the flat layer and the passivation layer;
  • the first conductive film layer is a pixel electrode, and the second conductive film layer is a common electrode;
  • the first conductive thin film layer and the second conductive thin film layer are both indium tin oxide semiconductor transparent conductive films.
  • the low temperature polysilicon panel provided by the present invention has an interlayer spacer between the dummy pixel unit and the polysilicon film layer on the edge region of the panel, and the polysilicon film layer and the dummy pixel are disposed.
  • the data lines on the unit are electrically connected, so that the accumulated charges on the polysilicon film layer can be guided away by the data line, thereby avoiding edge damage of the polysilicon panel, greatly improving the ESD resistance of the panel and improving the product yield.
  • the first conductive film layer is completely insulated from the dummy pixel unit to avoid the connection between the dummy pixel unit and the first conductive film layer, thereby preventing light leakage at the edge of the polysilicon panel.
  • 1a is a plan view of a virtual pixel unit at the edge of a low temperature polysilicon panel in a first design in the background art provided by the present invention.
  • 1b is a plan view of a low-temperature polysilicon panel edge dummy pixel unit in a second design in the background art provided by the present invention.
  • FIG. 2 is a cross-sectional view of an edge region of a low temperature polysilicon panel provided by the present invention.
  • FIG 3 is a plan view of an edge region virtual pixel unit of a low temperature polysilicon panel provided by the present invention.
  • FIG. 4 is a cross-sectional view showing another structure of a thin film transistor not shown in the edge region of the low temperature polysilicon panel provided by the present invention.
  • the present invention provides a low temperature polysilicon panel comprising an edge region.
  • the edge region includes: a polysilicon film layer 1 and an interlayer spacer layer 2 (ie, an ILD layer) above the polysilicon film layer 1; and a column of dummy pixel cells disposed on the interlayer spacer layer 2,
  • a first conductive thin film layer 3 is disposed above the column dummy pixel unit, and the dummy pixel unit and the first guide
  • the electrically thin film layers 3 are insulated from each other by a passivation layer 4.
  • the column of virtual pixel cells includes a column of thin film transistors, and a data line electrically connected to the thin film transistor for accessing a common signal.
  • the voltage at one end of the common signal (ie, the common signal output terminal) is close to 0V, which can be approximated as grounding, that is, equivalent to the grounding of the polysilicon film layer 1 and the charge accumulated on the polysilicon film layer 1.
  • the formed potential is higher than the end of the common signal. Therefore, the polysilicon panel provided by the present invention can conduct the charge accumulated on the polysilicon film layer 1 through the data line, thereby preventing the electric charge on the polysilicon film layer 1 from being damaged.
  • the panel's anti-ESD (Electro-Static discharge) capability improves product yield.
  • the dummy pixel unit when the dummy pixel unit is completely insulated from the first conductive film layer 3, the dummy pixel unit is not electrically connected to the first conductive film layer 3 to form a loop, and the virtual pixel unit does not receive a common signal.
  • the display of the polysilicon panel does not have any influence on the display effect of the polysilicon panel, nor does it cause light leakage at the edge of the polysilicon panel.
  • the interlayer spacer 2 is provided with a first opening 13 through which the polysilicon film layer 1 passes through the first opening 13 and the data line. Electrical connection.
  • the dummy pixel unit is insulated from the first conductive film layer 3, specifically, the passivation layer 4 is not provided with an opening.
  • a gate insulating layer 5 is further disposed between the interlayer spacer layer 2 and the polysilicon film layer 1.
  • the thin film transistor includes a gate 6, a drain 8, and a source 7.
  • the gate electrode 6 is located between the interlayer spacer layer 2 and the gate insulating layer 5, and the source electrode 7 and the drain electrode 8 are located on the interlayer spacer layer 2.
  • each thin film transistor has two first openings 13 respectively, and the two first openings 13 are opposite to the drain 8 and the source 7, respectively, and the gate insulating layer 5 and the first opening 13 A second opening 14 is provided at the opposite position.
  • the data line is electrically connected to the source 7 , and the source 7 and the drain 8 are both connected to the polysilicon film layer 1 through the first opening 13 and the second opening 14 .
  • the virtual pixel unit is a column of pixel units at the outermost side of the edge region.
  • the voltage at the input end of the data line is 0.1 to 0.4 V.
  • the input end of the data line refers to the input terminal of the common signal. Therefore, the voltage at the input end of the data line is 0.1 to 0.4 V, that is, the voltage at the output terminal of the common signal is 0.1 to 0.4 V.
  • the potential formed by the accumulated charges on the polysilicon film layer 1 is generally larger than 0.4V, therefore, the charge accumulated on the polysilicon film layer 1 can be conducted away through the data line.
  • a substrate 10 is disposed under the polysilicon film layer 1, and a buffer layer 9 is prepared between the polysilicon film layer 1 and the substrate 10.
  • the substrate 10 may be a glass substrate.
  • a flat layer 11 is prepared on the interlayer spacer 2.
  • the buffer layer 9 includes SiN and/or SixOy, wherein x ⁇ 1, y ⁇ 1.
  • a second conductive thin film layer 12 is prepared between the flat layer 11 and the passivation layer 4.
  • first conductive thin film layer 3 is a pixel electrode
  • second conductive thin film layer 12 is a common electrode
  • first conductive thin film layer 3 and the second conductive thin film layer 12 are both indium tin oxide semiconductor transparent conductive films, that is, ITO thin films.
  • the polysilicon panel also includes an effective display area, the edge area being an extension of the effective display area.
  • the effective display region includes a polysilicon film layer 1 and an interlayer spacer layer 2 above the polysilicon film layer 1, and a gate insulating layer 5 is further disposed between the interlayer spacer layer 2 and the polysilicon film layer 1;
  • a plurality of columns of real pixel units are disposed, each column of real pixel units includes a column of thin film transistors, the gate 6 of the thin film transistor is located between the interlayer spacer layer 2 and the gate insulating layer 5, and the source 7 and the drain 8 are located at the layer On the spacer layer 2.
  • a passivation layer 4 is prepared on the source 7 and the drain 8, and a pixel electrode is prepared over the passivation layer 4. Openings are formed on the gate insulating layer 5 and the interlayer spacer 2 at positions corresponding to the source 7 and the drain 8, and the source 7 and the drain 8 are electrically connected to the polysilicon film layer 1 through the openings. Further, an opening is formed in the passivation layer 4 at a position facing the drain electrode 8. The drain 8 is electrically connected to the pixel electrode through the opening, and the data line connecting the common signal is electrically connected to the source 7. After the thin film transistor is turned on and the pixel electrode is turned on, the common signal can be sent to the pixel electrode through the thin film transistor for controlling the display of the panel.
  • the low temperature polysilicon panel provided by the present invention has an interlayer spacer 2 between the dummy pixel unit and the polysilicon film layer 1 on the edge region of the panel, and the polysilicon film layer 1 and the dummy pixel unit are disposed.
  • the upper data lines are electrically connected, so that the accumulated charges on the polysilicon film layer 1 can be guided away by the data lines, thereby avoiding edge damage of the polysilicon panel, greatly improving the panel's anti-ESD capability and improving the product yield.
  • the first conductive film layer 3 is completely insulated from the dummy pixel unit to prevent the virtual pixel unit from being connected to the first conductive film layer, thereby preventing polysilicon. Light leakage occurs at the edge of the panel.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种低温多晶硅面板，该面板包括边缘区域；边缘区域包括有：多晶硅膜层(1)以及位于多晶硅膜层(1)上方的层间间隔层(2)；在层间间隔层(2)上设置有一列虚拟像素单元，在该列虚拟像素单元上方设置有第一导电薄膜层(3)，虚拟像素单元与第一导电薄膜层(3)之间通过钝化层(4)绝缘隔开；该列虚拟像素单元包含有一列薄膜晶体管，以及与薄膜晶体管电性连接的用于接入公共信号的数据线；层间间隔层(2)上设置有第一开孔(13)，多晶硅膜层(1)通过第一开孔(13)与数据线电性连接。所述低温多晶硅面板可以将多晶硅膜层(1)上聚集的电荷导走，避免多晶硅面板的边缘炸伤，还可以防止多晶硅面板边缘出现漏光。

Description

一种低温多晶硅面板
本申请要求于2017年9月5日提交中国专利局、申请号为201710791713.8、发明名称为“一种低温多晶硅面板”的中国专利申请的优先权，上述专利的全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示技术领域，尤其涉及一种低温多晶硅面板。
背景技术
低温多晶硅面板借着其高分辨率，高迁移率，低功耗等诸多优点已成为了目前平板显示产品中的明星产品，被广泛应用在例如苹果、三星、华为、小米、魅族等各大手机及平板电脑上，但由于低温多晶硅器件制程复杂，因此，制程中更容易引起ESD(Electro-Static discharge，静电释放)问题，而大量的电荷聚集会容易造成面板边缘栅极和多晶硅膜层炸伤，造成栅极和多晶硅膜层发生短路，从而将栅极信号输入到多晶硅膜层，引起点类不良，而这一现象多集中出现在面板的边缘，如何提高面板边缘像素的抗ESD能力已成为了面板行业工程师研究的热点之一。
目前，市面上大多数的多晶硅面板在边缘区域上设置有一列虚拟像素单元，其使用较多的两种设计方案如下：
1、如图1a所示，多晶硅面板的边缘上没有设置PV孔和ILD孔，即多晶硅膜层与虚拟像素单元之间的层间间隔层(ILD层)不设置开孔，从而将多晶硅膜层与虚拟像素单元之间完全绝缘隔开，且在虚拟像素单元与像素电极之间的钝化层(PV层)也没有设置开孔。该种方案的缺点是制程中多晶硅膜层上聚集的静电聚集时无法释放，容易引起炸伤。
2、如图1b所示，多晶硅面板的边缘上同时设置有PV孔和ILD孔，虚拟像素单元与显示区域的真实像素单元完全一样，即在多晶硅膜层与虚拟像素单元之间的层间间隔层(ILD层)上设置有开孔，且在虚拟像素单元与像素 电极之间的钝化层(PV层)设置有开孔。该种方案的缺点是钝化层上设置有开孔，会导致公共电极与虚拟像素单元之间接通，容易造成多晶硅面板的边缘出现漏光。
发明内容
为解决上述技术问题，本发明提供一种低温多晶硅面板，可以将多晶硅膜层上聚集的电荷导走，避免多晶硅面板的边缘炸伤，大幅度提高面板的抗ESD能力，提高产品良率，还可以防止多晶硅面板边缘出现漏光。
本发明提供一种低温多晶硅面板，包括边缘区域，
所述边缘区域包括有：多晶硅膜层以及位于所述多晶硅膜层上方的层间间隔层；在所述层间间隔层上设置有一列虚拟像素单元，在该列所述虚拟像素单元上方设置有第一导电薄膜层，所述虚拟像素单元与所述第一导电薄膜层之间通过钝化层绝缘隔开；
该列所述虚拟像素单元包含有一列薄膜晶体管，以及与所述薄膜晶体管电性连接的用于接入公共信号的数据线；
所述层间间隔层上设置有第一开孔，所述多晶硅膜层通过所述第一开孔与所述数据线电性连接。
优选地，在所述层间间隔层与所述多晶硅膜层之间还设置有栅绝缘层；
所述薄膜晶体管包括：栅极、漏极、源极；
所述栅极位于所述层间间隔层与所述栅绝缘层之间，所述源极和所述漏极位于所述层间间隔层上；
其中，所述第一开孔与所述漏极和所述源极正对，所述栅绝缘层与所述第一开孔正对的位置处设置有第二开孔；
所述数据线与所述源极电性连接，所述源极和所述漏极均穿过所述第一开孔和所述第二开孔与所述多晶硅膜层连接。
优选地，所述虚拟像素单元为所述边缘区域最外侧的一列像素单元。
优选地，所述数据线输入端的的电压为0.1～0.4V。
优选地，所述多晶硅膜层下方设置有基板，在所述多晶硅膜层与所述基板之间制备有缓冲层。
优选地，所述层间间隔层上制备有平坦层。
优选地，所述缓冲层包括有SiN和/或SixOy，其中，x≥1，y≥1。
优选地，所述平坦层与所述钝化层之间制备有第二导电薄膜层。
优选地，所述第一导电薄膜层为像素电极，所述第二导电薄膜层为公共电极。
优选地，所述第一导电薄膜层和所述第二导电薄膜层均为铟锡氧化物半导体透明导电膜。
本发明还提供一种低温多晶硅面板，包括边缘区域，
所述边缘区域包括有：多晶硅膜层以及位于所述多晶硅膜层上方的层间间隔层；在所述层间间隔层上设置有一列虚拟像素单元，在该列所述虚拟像素单元上方设置有第一导电薄膜层，所述虚拟像素单元与所述第一导电薄膜层之间通过钝化层绝缘隔开；
该列所述虚拟像素单元包含有一列薄膜晶体管，以及与所述薄膜晶体管电性连接的用于接入公共信号的数据线；
所述层间间隔层上设置有第一开孔，所述多晶硅膜层通过所述第一开孔与所述数据线电性连接；
在所述层间间隔层与所述多晶硅膜层之间还设置有栅绝缘层；
所述薄膜晶体管包括：栅极、漏极、源极；
所述栅极位于所述层间间隔层与所述栅绝缘层之间，所述源极和所述漏极位于所述层间间隔层上；
其中，所述第一开孔与所述漏极和所述源极正对，所述栅绝缘层与所述第一开孔正对的位置处设置有第二开孔；
所述数据线与所述源极电性连接，所述源极和所述漏极均穿过所述第一开孔和所述第二开孔与所述多晶硅膜层连接。
优选地，所述虚拟像素单元为所述边缘区域最外侧的一列像素单元。
优选地，所述数据线输入端的的电压为0.1～0.4V；
所述多晶硅膜层下方设置有基板，在所述多晶硅膜层与所述基板之间制备有缓冲层；
所述层间间隔层上制备有平坦层。
优选地，所述缓冲层包括有SiN和/或SixOy，其中，x≥1，y≥1；
所述平坦层与所述钝化层之间制备有第二导电薄膜层。
优选地，所述第一导电薄膜层为像素电极，所述第二导电薄膜层为公共电极；
所述第一导电薄膜层和所述第二导电薄膜层均为铟锡氧化物半导体透明导电膜。
本发明还提供一种低温多晶硅面板，包括边缘区域，
所述边缘区域包括有：多晶硅膜层以及位于所述多晶硅膜层上方的层间间隔层；在所述层间间隔层上设置有一列虚拟像素单元，在该列所述虚拟像素单元上方设置有第一导电薄膜层，所述虚拟像素单元与所述第一导电薄膜层之间通过钝化层绝缘隔开；
该列所述虚拟像素单元包含有一列薄膜晶体管，以及与所述薄膜晶体管电性连接的用于接入公共信号的数据线；
所述层间间隔层上设置有第一开孔，所述多晶硅膜层通过所述第一开孔与所述数据线电性连接；
所述层间间隔层上制备有平坦层。
优选地，在所述层间间隔层与所述多晶硅膜层之间还设置有栅绝缘层；
所述薄膜晶体管包括：栅极、漏极、源极；
所述栅极位于所述层间间隔层与所述栅绝缘层之间，所述源极和所述漏极位于所述层间间隔层上；
其中，所述第一开孔与所述漏极和所述源极正对，所述栅绝缘层与所述第一开孔正对的位置处设置有第二开孔；
所述数据线与所述源极电性连接，所述源极和所述漏极均穿过所述第一开孔和所述第二开孔与所述多晶硅膜层连接。
优选地，所述虚拟像素单元为所述边缘区域最外侧的一列像素单元；
所述数据线输入端的的电压为0.1～0.4V。
优选地，所述多晶硅膜层下方设置有基板，在所述多晶硅膜层与所述基板之间制备有缓冲层；
所述缓冲层包括有SiN和/或SixOy，其中，x≥1，y≥1。
优选地，所述平坦层与所述钝化层之间制备有第二导电薄膜层；
所述第一导电薄膜层为像素电极，所述第二导电薄膜层为公共电极；
所述第一导电薄膜层和所述第二导电薄膜层均为铟锡氧化物半导体透明导电膜。
实施本发明，具有如下有益效果：本发明提供的低温多晶硅面板，在面板的边缘区域上，将虚拟像素单元与多晶硅膜层之间的层间间隔层设置开孔，将多晶硅膜层与虚拟像素单元上的数据线电性连接，从而可以通过该数据线将多晶硅膜层上聚集的电荷导走，避免多晶硅面板的边缘炸伤，大幅度提高面板的抗ESD能力，提高产品良率。其次，还将第一导电薄膜层与虚拟像素单元之间完全绝缘隔开，避免虚拟像素单元与第一导电膜层之间接通，从而防止多晶硅面板边缘出现漏光。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a是本发明提供的背景技术中第一设计方案中低温多晶硅面板边缘虚拟像素单元的平面图。
图1b是本发明提供的背景技术中第二设计方案中低温多晶硅面板边缘虚拟像素单元的平面图。
图2是本发明提供的低温多晶硅面板的边缘区域的剖面图。
图3是本发明提供的低温多晶硅面板的边缘区域虚拟像素单元的平面图。
图4是本发明提供的低温多晶硅面板的边缘区域的另一未示出薄膜晶体管结构的剖面图。
具体实施方式
本发明提供一种低温多晶硅面板，该多晶硅面板包括边缘区域。
如图2所示，边缘区域包括有：多晶硅膜层1以及位于多晶硅膜层1上方的层间间隔层2(即ILD层)；在层间间隔层2上设置有一列虚拟像素单元，在该列虚拟像素单元上方设置有第一导电薄膜层3，虚拟像素单元与第一导 电薄膜层3之间通过钝化层4绝缘隔开。该列虚拟像素单元包含有一列薄膜晶体管，以及与薄膜晶体管电性连接的用于接入公共信号的数据线。
一般而言，提供公共信号的一端(即公共信号输出端)的电压接近0V，可以近似看成是接地，也即是相当于把多晶硅膜层1接地，而多晶硅膜层1上聚集的电荷所形成的电势会高于提供公共信号的一端，因此，本发明提供的多晶硅面板可以将多晶硅膜层1上聚集的电荷通过数据线导走，避免多晶硅膜层1上的电荷炸伤，大幅度提高面板的抗ESD(Electro-Static discharge，静电释放)能力，提高产品良率。
其次，当虚拟像素单元与第一导电薄膜层3之间完全绝缘隔开，虚拟像素单元不会与第一导电薄膜层3电性连接形成回路，虚拟像素单元也不会接收到公共信号，控制多晶硅面板的显示，因此，不会对多晶硅面板的显示效果造成任何影响，也不会引起多晶硅面板的边缘漏光。
如图3所示，多晶硅面板的边缘上没有设置ILD孔，如图4所示，即层间间隔层2上设置有第一开孔13，多晶硅膜层1通过第一开孔13与数据线电性连接。虚拟像素单元与第一导电薄膜层3之间绝缘隔开，具体而言即是钝化层4上不设置有开孔。
进一步地，继续参考图2，在层间间隔层2与多晶硅膜层1之间还设置有栅绝缘层5。
薄膜晶体管包括：栅极6、漏极8、源极7。
栅极6位于层间间隔层2与栅绝缘层5之间，源极7和漏极8位于层间间隔层2上。
其中，继续参考图4，每一薄膜晶体管对应有两个第一开孔13，两个第一开孔13分别与漏极8和源极7正对，栅绝缘层5与第一开孔13正对的位置处设置有第二开孔14。数据线与源极7电性连接，源极7和漏极8均穿过第一开孔13和第二开孔14与多晶硅膜层1连接。
进一步地，虚拟像素单元为边缘区域最外侧的一列像素单元。
进一步地，数据线输入端的电压为0.1～0.4V，这里，数据线输入端指的是公共信号的输入端。因此数据线输入端的电压为0.1～0.4V也即是公共信号输出端的电压为0.1～0.4V。多晶硅膜层1上聚集电荷形成的电势一般大于 0.4V，因此，多晶硅膜层1上聚集的电荷可以通过数据线导走。
进一步地，多晶硅膜层1下方设置有基板10，在多晶硅膜层1与基板10之间制备有缓冲层9。基板10可以是玻璃基板。
进一步地，层间间隔层2上制备有平坦层11。
进一步地，缓冲层9包括有SiN和/或SixOy，其中，x≥1，y≥1。
进一步地，平坦层11与钝化层4之间制备有第二导电薄膜层12。
进一步地，第一导电薄膜层3为像素电极，第二导电薄膜层12为公共电极。
进一步地，第一导电薄膜层3和第二导电薄膜层12均为铟锡氧化物半导体透明导电膜，即ITO薄膜。
该多晶硅面板还包括有效显示区域，边缘区域为有效显示区域的延伸部。有效显示区域包括有多晶硅膜层1以及位于多晶硅膜层1上方的层间间隔层2，在层间间隔层2与多晶硅膜层1之间还设置有栅绝缘层5；在层间间隔层2上设置有若干列真实像素单元，每一列真实像素单元都包括一列薄膜晶体管，该薄膜晶体管的栅极6位于层间间隔层2与栅绝缘层5之间，源极7和漏极8位于层间间隔层2上。
源极7和漏极8的上制备有钝化层4，在该钝化层4上方制备有像素电极。在栅绝缘层5和层间间隔层2上与源极7和漏极8对应的位置设置有开孔，源极7和漏极8通过该开孔与多晶硅膜层1电性连接。并且，在钝化层4上与漏极8正对的位置设置有开孔，漏极8通过该开孔与像素电极电性连接，接入公共信号的数据线与源极7电性连接，从而薄膜晶体管与像素电极之间导通之后，公共信号可以通过薄膜晶体管送至像素电极，用于控制面板的显示。
综上所述，本发明提供的低温多晶硅面板，在面板的边缘区域上，将虚拟像素单元与多晶硅膜层1之间的层间间隔层2设置开孔，将多晶硅膜层1与虚拟像素单元上的数据线电性连接，从而可以通过该数据线将多晶硅膜层1上聚集的电荷导走，避免多晶硅面板的边缘炸伤，大幅度提高面板的抗ESD能力，提高产品良率。其次，还将第一导电薄膜层3与虚拟像素单元之间完全绝缘隔开，避免虚拟像素单元与第一导电膜层之间接通，从而防止多晶硅 面板边缘出现漏光。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (20)

  1. 一种低温多晶硅面板，包括边缘区域，其中，
    所述边缘区域包括有：多晶硅膜层以及位于所述多晶硅膜层上方的层间间隔层；在所述层间间隔层上设置有一列虚拟像素单元，在该列所述虚拟像素单元上方设置有第一导电薄膜层，所述虚拟像素单元与所述第一导电薄膜层之间通过钝化层绝缘隔开；
    该列所述虚拟像素单元包含有一列薄膜晶体管，以及与所述薄膜晶体管电性连接的用于接入公共信号的数据线；
    所述层间间隔层上设置有第一开孔，所述多晶硅膜层通过所述第一开孔与所述数据线电性连接。
  2. 根据权利要求1所述的低温多晶硅面板，其中，在所述层间间隔层与所述多晶硅膜层之间还设置有栅绝缘层；
    所述薄膜晶体管包括：栅极、漏极、源极；
    所述栅极位于所述层间间隔层与所述栅绝缘层之间，所述源极和所述漏极位于所述层间间隔层上；
    其中，所述第一开孔与所述漏极和所述源极正对，所述栅绝缘层与所述第一开孔正对的位置处设置有第二开孔；
    所述数据线与所述源极电性连接，所述源极和所述漏极均穿过所述第一开孔和所述第二开孔与所述多晶硅膜层连接。
  3. 根据权利要求1所述的低温多晶硅面板，其中，所述虚拟像素单元为所述边缘区域最外侧的一列像素单元。
  4. 根据权利要求1所述的低温多晶硅面板，其中，所述数据线输入端的的电压为0.1～0.4V。
  5. 根据权利要求1所述的低温多晶硅面板，其中，所述多晶硅膜层下方设置有基板，在所述多晶硅膜层与所述基板之间制备有缓冲层。
  6. 根据权利要求1所述的低温多晶硅面板，其中，所述层间间隔层上制备有平坦层。
  7. 根据权利要求5所述的低温多晶硅面板，其中，所述缓冲层包括有SiN和/或SixOy，其中，x≥1，y≥1。
  8. 根据权利要求6所述的低温多晶硅面板，其中，所述平坦层与所述钝化层之间制备有第二导电薄膜层。
  9. 根据权利要求8所述的低温多晶硅面板，其中，所述第一导电薄膜层为像素电极，所述第二导电薄膜层为公共电极。
  10. 根据权利要求8所述的低温多晶硅面板，其中，所述第一导电薄膜层和所述第二导电薄膜层均为铟锡氧化物半导体透明导电膜。
  11. 一种低温多晶硅面板，包括边缘区域，其中，
    所述边缘区域包括有：多晶硅膜层以及位于所述多晶硅膜层上方的层间间隔层；在所述层间间隔层上设置有一列虚拟像素单元，在该列所述虚拟像素单元上方设置有第一导电薄膜层，所述虚拟像素单元与所述第一导电薄膜层之间通过钝化层绝缘隔开；
    该列所述虚拟像素单元包含有一列薄膜晶体管，以及与所述薄膜晶体管电性连接的用于接入公共信号的数据线；
    所述层间间隔层上设置有第一开孔，所述多晶硅膜层通过所述第一开孔与所述数据线电性连接；
    在所述层间间隔层与所述多晶硅膜层之间还设置有栅绝缘层；
    所述薄膜晶体管包括：栅极、漏极、源极；
    所述栅极位于所述层间间隔层与所述栅绝缘层之间，所述源极和所述漏极位于所述层间间隔层上；
    其中，所述第一开孔与所述漏极和所述源极正对，所述栅绝缘层与所述第一开孔正对的位置处设置有第二开孔；
    所述数据线与所述源极电性连接，所述源极和所述漏极均穿过所述第一开孔和所述第二开孔与所述多晶硅膜层连接。
  12. 根据权利要求11所述的低温多晶硅面板，其中，所述虚拟像素单元为所述边缘区域最外侧的一列像素单元。
  13. 根据权利要求11所述的低温多晶硅面板，其中，所述数据线输入端的的电压为0.1～0.4V；
    所述多晶硅膜层下方设置有基板，在所述多晶硅膜层与所述基板之间制备有缓冲层；
    所述层间间隔层上制备有平坦层。
  14. 根据权利要求13所述的低温多晶硅面板，其中，所述缓冲层包括有SiN和/或SixOy，其中，x≥1，y≥1；
    所述平坦层与所述钝化层之间制备有第二导电薄膜层。
  15. 根据权利要求14所述的低温多晶硅面板，其中，所述第一导电薄膜层为像素电极，所述第二导电薄膜层为公共电极；
    所述第一导电薄膜层和所述第二导电薄膜层均为铟锡氧化物半导体透明导电膜。
  16. 一种低温多晶硅面板，包括边缘区域，其中，
    所述边缘区域包括有：多晶硅膜层以及位于所述多晶硅膜层上方的层间间隔层；在所述层间间隔层上设置有一列虚拟像素单元，在该列所述虚拟像素单元上方设置有第一导电薄膜层，所述虚拟像素单元与所述第一导电薄膜层之间通过钝化层绝缘隔开；
    该列所述虚拟像素单元包含有一列薄膜晶体管，以及与所述薄膜晶体管电性连接的用于接入公共信号的数据线；
    所述层间间隔层上设置有第一开孔，所述多晶硅膜层通过所述第一开孔与所述数据线电性连接；
    所述层间间隔层上制备有平坦层。
  17. 根据权利要求16所述的低温多晶硅面板，其中，在所述层间间隔层与所述多晶硅膜层之间还设置有栅绝缘层；
    所述薄膜晶体管包括：栅极、漏极、源极；
    所述栅极位于所述层间间隔层与所述栅绝缘层之间，所述源极和所述漏极位于所述层间间隔层上；
    其中，所述第一开孔与所述漏极和所述源极正对，所述栅绝缘层与所述第一开孔正对的位置处设置有第二开孔；
    所述数据线与所述源极电性连接，所述源极和所述漏极均穿过所述第一开孔和所述第二开孔与所述多晶硅膜层连接。
  18. 根据权利要求16所述的低温多晶硅面板，其中，所述虚拟像素单元为所述边缘区域最外侧的一列像素单元；
    所述数据线输入端的的电压为0.1～0.4V。
  19. 根据权利要求16所述的低温多晶硅面板，其中，所述多晶硅膜层下方设置有基板，在所述多晶硅膜层与所述基板之间制备有缓冲层；
    所述缓冲层包括有SiN和/或SixOy，其中，x≥1，y≥1。
  20. 根据权利要求16所述的低温多晶硅面板，其中，所述平坦层与所述钝化层之间制备有第二导电薄膜层；
    所述第一导电薄膜层为像素电极，所述第二导电薄膜层为公共电极；
    所述第一导电薄膜层和所述第二导电薄膜层均为铟锡氧化物半导体透明导电膜。
PCT/CN2017/105821 2017-09-05 2017-10-12 一种低温多晶硅面板 Ceased WO2019047329A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/735,543 US10784286B2 (en) 2017-09-05 2017-10-12 Low temperature polysilicon panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710791713.8 2017-09-05
CN201710791713.8A CN107464806A (zh) 2017-09-05 2017-09-05 一种低温多晶硅面板

Publications (1)

Publication Number Publication Date
WO2019047329A1 true WO2019047329A1 (zh) 2019-03-14

Family

ID=60551784

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/105821 Ceased WO2019047329A1 (zh) 2017-09-05 2017-10-12 一种低温多晶硅面板

Country Status (3)

Country Link
US (1) US10784286B2 (zh)
CN (1) CN107464806A (zh)
WO (1) WO2019047329A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118119885A (zh) 2022-09-30 2024-05-31 京东方科技集团股份有限公司 显示基板和显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1152427A (ja) * 1997-08-07 1999-02-26 Sharp Corp 液晶表示装置
CN201845768U (zh) * 2010-03-30 2011-05-25 深圳华映显示科技有限公司 一种静电放电防护结构
CN104538307A (zh) * 2014-12-19 2015-04-22 深圳市华星光电技术有限公司 一种用于制作多晶硅薄膜晶体管的方法
CN106783845A (zh) * 2017-02-24 2017-05-31 武汉华星光电技术有限公司 阵列基板以及具有该阵列基板的液晶面板

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004006313A (ja) * 2002-04-18 2004-01-08 Seiko Epson Corp 電気光学装置の製造方法、電気光学装置、および電子機器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1152427A (ja) * 1997-08-07 1999-02-26 Sharp Corp 液晶表示装置
CN201845768U (zh) * 2010-03-30 2011-05-25 深圳华映显示科技有限公司 一种静电放电防护结构
CN104538307A (zh) * 2014-12-19 2015-04-22 深圳市华星光电技术有限公司 一种用于制作多晶硅薄膜晶体管的方法
CN106783845A (zh) * 2017-02-24 2017-05-31 武汉华星光电技术有限公司 阵列基板以及具有该阵列基板的液晶面板

Also Published As

Publication number Publication date
US10784286B2 (en) 2020-09-22
CN107464806A (zh) 2017-12-12
US20200035706A1 (en) 2020-01-30

Similar Documents

Publication Publication Date Title
US10324348B2 (en) Array substrate, liquid crystal display panel and liquid crystal display device
CN101706637B (zh) 高显示质量的画素电极结构
CN104656323B (zh) 显示面板
US9488881B2 (en) Array substrate and display device
CN105527767A (zh) 一种阵列基板以及液晶显示器
CN105679765A (zh) Tft阵列基板结构
WO2015039386A1 (zh) 阵列基板、液晶显示面板及显示装置
CN106356381B (zh) 一种阵列基板及其制备方法、显示面板
CN105629612A (zh) 薄膜晶体管阵列基板及其制作方法
CN103605241A (zh) 一种液晶显示面板
CN102629606A (zh) 阵列基板及其制备方法和显示装置
WO2018000810A1 (zh) 薄膜晶体管及显示装置
JP4410912B2 (ja) 静電保護回路
CN106886107A (zh) 显示面板
CN109031827A (zh) 静电释放单元、阵列基板及液晶显示面板
CN110085584B (zh) Esd防护薄膜晶体管及esd防护结构
WO2020107594A1 (zh) 显示面板及其修复方法
CN102681274B (zh) 液晶显示器阵列基板及制造方法
CN104656327A (zh) 一种阵列基板及液晶显示面板
CN102981337A (zh) Tft-lcd显示面板及显示装置
CN106125432A (zh) 显示器及其显示面板
CN103278986A (zh) 一种阵列基板、显示装置及阵列基板的制造方法
CN110047850A (zh) 一种tft阵列基板、其制备方法及其显示面板
CN103345095A (zh) 一种tft-lcd阵列基板及显示装置
TW201712420A (zh) 畫素結構

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17924400

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17924400

Country of ref document: EP

Kind code of ref document: A1