WO2019037430A1 - 供电电路及显示装置 - Google Patents

供电电路及显示装置 Download PDF

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Publication number
WO2019037430A1
WO2019037430A1 PCT/CN2018/081722 CN2018081722W WO2019037430A1 WO 2019037430 A1 WO2019037430 A1 WO 2019037430A1 CN 2018081722 W CN2018081722 W CN 2018081722W WO 2019037430 A1 WO2019037430 A1 WO 2019037430A1
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WIPO (PCT)
Prior art keywords
transistor
power
power supply
supply circuit
detecting
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PCT/CN2018/081722
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English (en)
French (fr)
Inventor
刘晓石
汪敏
刘媛媛
董慧
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/309,864 priority Critical patent/US11043180B2/en
Publication of WO2019037430A1 publication Critical patent/WO2019037430A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/36—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of semiconductors, not otherwise provided for
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a power supply circuit and a display device.
  • the liquid crystal module Due to its advantages of lightness, thinness, and low power consumption, the liquid crystal module is widely used in modern information equipment such as televisions, notebook computers, mobile phones, and personal digital assistants. At present, with the continuous development of liquid crystal module production technology, the demand for large-size, high-resolution liquid crystal modules in the market is also increasing.
  • a commonly used power supply circuit includes a power management module (PMIC) that uses a single die (chip) process, and a control portion and a MOS transistor (metal-oxide-semiconductor field effect transistor) integrated in one chip.
  • PMIC power management module
  • MOS transistor metal-oxide-semiconductor field effect transistor
  • the on-state resistance can reach hundreds of milliohms, resulting in a large loss of the power management module (PMIC), and with the enlargement of the liquid crystal module, the power management module ( The loss of the PMIC) will become larger and larger, which in turn will make the loss of the power supply circuit larger and larger.
  • PMIC power management module
  • Embodiments of the present disclosure provide a power supply circuit and a display device.
  • a power supply circuit including:
  • a power management integrated module includes a driving pin for transmitting a driving signal
  • a power transistor having a control terminal coupled to the driver pin, a first terminal coupled to the first power source and a second terminal coupled to the load for providing a voltage to the load.
  • the power management integration module further includes:
  • a detecting leg connected to the second end of the power transistor
  • a detection circuit is coupled to the detection pin for detecting a current flowing through the power transistor.
  • the detecting circuit includes a current mirror circuit, and the current mirror circuit includes:
  • a first transistor, a control end and a first end are both connected to the first power source;
  • the second transistor, the control terminal and the first terminal are both connected to the first power source.
  • the detecting circuit further includes:
  • control end is connected to the first power source, the first end is connected to the second end of the first transistor, and the second end is connected to the second power source;
  • the first end is connected to the second end of the second transistor, and the second end is connected to the current detecting end of the detecting circuit;
  • control end and the second end are both connected to the second power source, and the first end is connected to the current detecting end of the detecting circuit;
  • the first end is connected to the second end of the second transistor, and the second end is connected to the second power source;
  • control end is connected to the first end of the first transistor, the first end is connected to the voltage detecting end of the detecting circuit, and the second end is connected to the second end of the first transistor;
  • the first end is connected to the first power source, and the second end is connected to the voltage detecting end of the detecting circuit.
  • the state of the detecting circuit includes a detecting state and a waiting state
  • the first switch is turned on, and the second switch is turned off;
  • the first switch is turned off and the second switch is turned on.
  • the first transistor and the second transistor are the same size.
  • a size ratio of the third transistor to the fourth transistor is N, wherein N>0 and a width to length ratio of the third transistor and the fourth The ratio of the width to length of the transistor is determined.
  • the first transistor to the fifth transistor are both an N-type thin film transistor or a P-type thin film transistor.
  • the power transistor is an N-type power transistor or a P-type power transistor.
  • the driving signal transmitted by the driving pin is a pulse waveform with a variable duty ratio.
  • the power management integration module controls an output voltage of the second end of the power transistor by adjusting a duty ratio of the driving signal.
  • a display device comprising the power supply circuit according to any of the above.
  • FIG. 1 is a schematic diagram 1 of a power supply circuit provided in an exemplary embodiment of the present disclosure
  • FIG. 2 is a schematic diagram 2 of a power supply circuit provided in an exemplary embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a detection circuit provided in an exemplary embodiment of the present disclosure.
  • the power supply circuit may include: a power management integration module 10 and a power transistor 20, wherein:
  • the power management integrated module 10 may include a driving pin 11 for transmitting a driving signal; the power transistor 20 is disposed outside the power management integrated module 10, and the control of the power transistor 20 The terminal is connected to the driving pin 11, the first end of the power transistor 20 is connected to the first power source VSS, and the second end of the power transistor 20 is connected to the load for supplying a voltage to the load.
  • the driving signal transmitted by the driving pin 11 may be a pulse waveform with a variable duty ratio.
  • the voltage of the drive signal can be determined according to the voltage of the power transistor 20. For example, when the power transistor 20 is a low voltage power transistor of 20 V, the drive signal employs a pulse waveform having a duty ratio of 4.5 V.
  • the power management integrated module (PMIC) 10 can control the output voltage of the second terminal of the power transistor 20 by adjusting the duty cycle of the drive signal.
  • the power transistor 20 can be a power field effect transistor or a power bipolar transistor.
  • the power transistor 20 may be an enhancement transistor or a depletion transistor, which is not specifically limited in this exemplary embodiment.
  • the power transistor 20 has a control end, a first end, and a second end.
  • the control terminal of the power transistor 20 can be a gate
  • the first end of the power transistor 20 can be a source
  • the second end of the power transistor 20 can be a drain.
  • the first power source VSS outputs a low level.
  • the power transistor 20 is a P-type power transistor
  • the first power source VSS outputs a high level.
  • the P-type power transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level
  • the N-type power transistor is turned off when the gate is at a low level, and turned on when the gate is at a high level.
  • a power transistor 20 is disposed outside the power management integrated module (PMIC) 10 to replace the existing power management integrated module (PMIC).
  • PMIC power management integrated module
  • LDMOS laterally diffused metal oxide semiconductor
  • LDMOS can largely avoid the related defects of LDMOS, which can reduce the power supply loss of the power supply circuit, and thus improve the power supply efficiency of the power supply circuit.
  • the power management integrated module (PMIC) 10 may further include a detecting pin 12 and a detecting circuit. among them:
  • the detecting leg 12 is connected to the second end of the power transistor 20.
  • a current detecting terminal D1 of the detecting circuit is connected to the detecting pin 12 for detecting a current flowing through the power transistor 20.
  • the detection circuit is located in a power management integration module (PMIC) 10 and is integrated on a power management integration module (PMIC) 10.
  • PMIC power management integration module
  • PMIC power management integration module
  • the detection circuit detects the current flowing through the power transistor 20 through the detection pin 12 on the power management integrated module (PMIC) 10.
  • the detecting circuit may include a current mirror circuit, wherein the current mirror circuit may include: a first transistor M1 and a second transistor M2. among them:
  • the control end and the first end of the first transistor M1 are both connected to the first power source VSS;
  • the control terminal and the first terminal of the second transistor M2 are both connected to the first power source VSS.
  • the first transistor M1 and the second transistor M2 may be the same size such that current flowing through the first transistor M1 and flowing through the second transistor M2 is equal.
  • the first transistor M1 and the second transistor M2 may both be field effect transistors, and may also be bipolar transistors.
  • the first transistor M1 and the second transistor M2 may both be enhancement transistors, and may also be depletion transistors, which is not specifically limited in this exemplary embodiment.
  • the first transistor M1 and the second transistor M2 each have a control end, a first end, and a second end.
  • the control terminal of each transistor may be a gate
  • the first end of each transistor may be a source
  • the second end of each transistor may be a drain.
  • the first power source VSS When the first transistor M1 and the second transistor M2 are both P-type thin film transistors, the first power source VSS outputs a high level. When the first transistor M1 and the second transistor M2 are both N-type thin film transistors, the first power source VSS outputs a low level. It should be noted that the P-type thin film transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level, and the N-type thin film transistor is turned off when the gate is at a low level, and turned on when the gate is at a high level.
  • the detecting circuit may further include: a third transistor M3, a first switch S1, a fourth transistor M4, a second switch S2, a fifth transistor M5, and a resistor R. among them:
  • the control terminal of the third transistor M3 is connected to the first power source VSS, the first terminal of the third transistor M3 is connected to the second terminal of the first transistor M1, and the second terminal of the third transistor M3 is connected to the second power source VDD. connection;
  • the first end of the first switch S1 is connected to the second end of the second transistor M2, and the second end of the first switch S1 is connected to the current detecting end D1 of the detecting circuit;
  • the control terminal and the second terminal of the fourth transistor M4 are both connected to the second power source VDD, and the first terminal of the fourth transistor M4 is connected to the current detecting terminal D1 of the detecting circuit;
  • the first end of the second switch S2 is connected to the second end of the second transistor M2, and the second end of the second switch S2 is connected to the second power source VDD;
  • the control terminal of the fifth transistor M5 is connected to the first terminal of the first transistor M1, the first terminal of the fifth transistor M5 is connected to the voltage detection terminal D2 of the detection circuit, and the second terminal of the fifth transistor M5 is The second end of the first transistor M1 is connected;
  • the first end of the resistor R is connected to the first power source VSS, and the second end of the resistor R is connected to the voltage detecting terminal D2 of the detecting circuit.
  • the third to fifth transistors M3 to M5 may both be field effect transistors, and may also be bipolar transistors.
  • the third transistor M3 to the fifth transistor M5 may both be enhancement transistors, and may also be depletion transistors, which is not specifically limited in this exemplary embodiment.
  • the third transistor M3 to the fifth transistor M5 each have a control end, a first end, and a second end.
  • the control terminal of each transistor may be a gate
  • the first end of each transistor may be a source
  • the second end of each transistor may be a drain.
  • the third transistor M3 to the fifth transistor M5 may both be N-type thin film transistors, and the third to Mth transistors M3 to M5 may also be P-type thin film transistors. It should be noted that the P-type thin film transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level, and the N-type thin film transistor is turned off when the gate is at a low level, and turned on when the gate is at a high level.
  • a size ratio of the third transistor M3 to the fourth transistor M4 may be N, where N>0 and a ratio of a width to length ratio of the third transistor to a width to length ratio of the fourth transistor determine.
  • the first switch S1 and the second switch S2 may be devices having a switching function such as a diode.
  • the first switch S1 and the second switch S2 each have a first end and a second end.
  • the first end can be a cathode and the second end can be an anode.
  • the first end can be an anode and the second end can be a cathode.
  • the resistor R may be, for example, a polysilicon resistor, a metal resistor, a well resistor or an injection resistor, etc., which is not particularly limited in this exemplary embodiment.
  • the state of the detecting circuit may include a detecting state and a waiting state. Wherein, when the detection circuit is in the detection state, the first switch S1 is turned on, and the second switch S2 is turned off. When the detection circuit is in the waiting state, the first switch S1 is turned off, and the second switch S2 is turned on.
  • the first switch S1 When the detection circuit is in the detection state, the first switch S1 is turned on and the second switch S2 is turned off. At this time, the loop in which the second transistor M2 and the fourth transistor M4 are located is turned on. Since the first transistor M1 and the second transistor M2 are the same size, and the first transistor M1 and the second transistor M2 constitute a current mirror circuit, flowing through the first transistor M1 and flowing through the second The current of transistor M2 is equal.
  • the second terminal of the first transistor M1 and the voltage between the control terminal and the first terminal of the second transistor M2 are equal, the second terminal of the first transistor M1 and The voltage between the first terminals is equal to the voltage between the second end and the first end of the second transistor M2.
  • the first terminal of the first transistor M1 and the first terminal of the second transistor M2 are both connected to the first power source VSS, the voltage of the second terminal of the first transistor M1 is equal to the voltage of the second terminal of the second transistor M2.
  • the size ratio of the third transistor M3 and the fourth transistor M4 is N (ie, the third transistor M3 and the fourth transistor M4 can be regarded as two resistors of a ratio N), and the first transistor M1
  • the voltage of the second terminal is equal to the voltage of the second terminal of the second transistor M2, and therefore, the current flowing through the fourth transistor M4 is proportional to the current flowing through the fifth transistor M5.
  • the voltage of the first terminal of the fifth transistor M5 can be detected by the voltage detecting terminal D2 of the detecting circuit, and the current flowing through the fifth transistor M5 can be calculated.
  • the current flowing through the fourth transistor M4 can be calculated by combining the above ratio N. Since the first end of the fourth transistor M4 is connected to the current detecting terminal D1 of the detecting circuit, the current flowing through the power transistor 20 can be obtained by the current flowing through the fourth transistor M4.
  • the first switch S1 When the detection circuit is in the waiting state, the first switch S1 is turned off and the second switch S2 is turned on. At this time, since the circuit composed of the second transistor M2 and the fourth transistor M4 is turned off, the current flowing through the fourth transistor M4 cannot be detected, and thus the current flowing through the power transistor 20 cannot be detected.
  • the current flowing through the fourth transistor M4 can be detected by the above detection circuit, thereby obtaining a current flowing through the power transistor 20.
  • the power management integration module (PMIC) 10 can also adjust the driving signal transmitted by the driving pin 11 according to the current flowing through the power transistor 20 to keep the output voltage of the second end of the power transistor 20 stable.
  • the above detection circuit is simple in structure and easy to integrate in the power management integration module (PMIC) 10.
  • the example embodiment also provides a display device including the above-described power supply circuit.
  • the display device includes: a plurality of scan lines for providing scan signals; a plurality of data lines for providing data signals; a plurality of power supply circuits electrically connected to the scan lines and the data lines; and at least one of the power supply circuits It is included in any of the above power supply circuits in the present exemplary embodiment.
  • the display device may include, for example, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, or the like, any product or component having a display function.

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Abstract

一种供电电路及显示装置，该供电电路包括：一电源管理集成模块（10），包括一驱动脚（11），所述驱动脚（11）用于传输驱动信号；一功率晶体管（20），其控制端与所述驱动脚（11）连接，第一端与第一电源（VSS）连接，第二端与负载连接，用于向所述负载提供电压。

Description

供电电路及显示装置
交叉引用
本申请要求于2017年8月25日提交的申请号为201710742801.9、发明名称为“供电电路及显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种供电电路及显示装置。
背景技术
液晶模组因其具有轻、薄、耗电小等优点，被广泛应用于电视、笔记型本电脑、移动电话、个人数字助理等现代化信息设备。目前，随着液晶模组生产技术的不断发展，大尺寸、高分辨率的液晶模组在市场上的需求也来越多。
通常液晶模组需要一个供电电路对其供电。目前，常用的供电电路包括一电源管理模块(PMIC)，该电源管理模块(PMIC)采用单die(芯片)工艺，控制部分和MOS管(金属-氧化物-半导体场效应晶体管)集成在一个芯片上面。由于控制部分和MOS管(金属-氧化物-半导体场效应晶体管)集成在一个芯片上面，且限于当前工艺的条件，该MOS管(金属-氧化物-半导体场效应晶体管)采用LDMOS(横向扩散金属氧化物半导体)。
由于LDMOS(横向扩散金属氧化物半导体)的性能差，通态电阻可达数百毫欧，导致电源管理模块(PMIC)的损耗较大，且随着液晶模组的大型化，电源管理模块(PMIC)的损耗将越来越大，进而使得供电电路的损耗也越来越大。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的实施例提供了一种供电电路及显示装置。
根据本公开的一个方面，提供一种供电电路，包括：
一电源管理集成模块，包括一驱动脚，所述驱动脚用于传输驱动信号；
一功率晶体管，且其控制端与所述驱动脚连接，第一端与第一电源连接，第二端与负载连接，用于向所述负载提供电压。
在本公开的一种示例性实施例中，所述电源管理集成模块还包括：
一检测脚，所述检测脚与所述功率晶体管的第二端连接；
一检测电路，所述检测电路的电流检测端与所述检测脚连接，用于检测流经所述功率晶体管的电流。
在本公开的一种示例性实施例中，所述检测电路包括一电流镜电路，所述电流镜电路包括：
第一晶体管，控制端和第一端均与所述第一电源连接；
第二晶体管，控制端和第一端均与所述第一电源连接。
在本公开的一种示例性实施例中，所述检测电路还包括：
第三晶体管，控制端与所述第一电源连接，第一端与所述第一晶体管的第二端连接，第二端与第二电源连接；
第一开关，第一端与所述第二晶体管的第二端连接，第二端与所述检测电路的电流检测端连接；
第四晶体管，控制端和第二端均与所述第二电源连接，第一端与所述检测电路的电流检测端连接；
第二开关，第一端与所述第二晶体管的第二端连接，第二端与所述第二电源连接；
第五晶体管，控制端与所述第一晶体管的第一端连接，第一端与所述检测电路的电压检测端连接，第二端与所述第一晶体管的第二端连接；
电阻，第一端与所述第一电源连接，第二端与所述检测电路的电压检测端连接。
在本公开的一种示例性实施例中，所述检测电路的状态包括检测状态和等待状态；
在所述检测状态，所述第一开关接通，所述第二开关断开；
在所述等待状态，所述第一开关断开，所述第二开关接通。
在本公开的一种示例性实施例中，所述第一晶体管和所述第二晶体管的尺寸相同。
在本公开的一种示例性实施例中，所述第三晶体管与所述第四晶体管的尺寸比例为N，其中，N＞0且由所述第三晶体管的宽长比与所述第四晶体管的宽长比之比确定。
在本公开的一种示例性实施例中，所述第一晶体管至所述第五晶体管均为N型薄膜晶体管或P型薄膜晶体管。
在本公开的一种示例性实施例中，所述功率晶体管为N型功率晶体管或P型功率晶体管。
在本公开的一种示例性实施例中，所述驱动脚传输的驱动信号为占空比可变的脉冲波形。
在本公开的一种示例性实施例中，所述电源管理集成模块通过调整所述驱动信号的占空比控制所述功率晶体管的第二端的输出电压。
根据本公开的一个方面，提供一种显示装置，包括如上述任意一项所述的供电电路。
附图说明
通过参照附图来详细描述其示例性实施例，本公开的上述和其它特征及优点将变得更加明显。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1为本公开一示例性实施例中提供的供电电路的示意图一；
图2为本公开一示例性实施例中提供的供电电路的示意图二；
图3为本公开一示例性实施例中提供的检测电路的示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的实施例；相反，提供这些实施例使得本公开将全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免模糊本公开的各方面。
此外，附图仅为本公开的示意性图解，并非一定是按照比例绘制。图中相同的附图标记标识相同或相似的部分，因而将省略对它们的重复描述。
本示例实施方式中提供了一种供电电路，参照图1所示，该供电电路可以包括：电源管理集成模块10以及功率晶体管20，其中：
所述电源管理集成模块10可以包括一驱动脚11，所述驱动脚11用于传输驱动信号；所述功率晶体管20设置在所述电源管理集成模块10之外，且所述功率晶体管20的控制端与所述驱动脚11连接，所述功率晶体管20的第一端与第一电源VSS连接，所述功率晶体管20的第二端与负载连接，用于向所述负载提供电压。
在本示例性实施例中，所述驱动脚11传输的驱动信号可以为占空比可变的脉冲波形。所述驱动信号的电压可以根据功率晶体管20的电压确定。例如，在功率晶体管20为20V的低压功率晶体管时，驱动信号采用4.5V的占空比可变的脉冲波形。此外，所述电源管理集成模块(PMIC)10可以通过调整所述驱动信号的占空比控制所述功率晶体管20的第二端的输出电压。
所述功率晶体管20可以为功率场效应晶体管，还可以为功率双极晶体管。此外，所述功率晶体管20可以为增强型晶体管，还可以为耗尽型晶体管，本示例性实施例对此不作特殊限定。
所述功率晶体管20具有控制端、第一端以及第二端。举例而言，功率晶体管20的控制端可以为栅极，功率晶体管20的第一端可以为源极，功率晶体管20的第二端可以为漏极。在功率晶体管20为N型功率晶体管时，第一电源VSS输出低电平。在功率晶体管20为P型功率晶体管时，第一电源VSS输出高电平。需要说明的是，P型功率晶体管在栅极为低电平时导通，在栅极为高电平时截止；N型功率晶体管在栅极为低电平时截止，在栅极为高电平时导通。
综上所述，相比于现有技术，通过改变上述供电电路的结构，在电源管理集成模块(PMIC)10之外设置一功率晶体管20以代替现有的电源管理集成模块(PMIC)中的LDMOS(横向扩散金属氧化物半导体)，可以在很大程度上避免LDMOS的相关缺陷，从而可以降低供电电路的供电损耗，进而也提高了供电电路的供电效率。
此外，参照图2至图3所示，所述电源管理集成模块(PMIC)10还可以包括一检测脚12和一检测电路。其中：
所述检测脚12与所述功率晶体管20的第二端连接。所述检测电路的电流检测端D1与所述检测脚12连接，用于检测流经所述功率晶体管20的电流。
在本示例性实施例中，所述检测电路位于电源管理集成模块(PMIC)10中，且集成在电源管理集成模块(PMIC)10上。所述检测电路通过电源管理集成模块(PMIC)10上的检测脚12检测流经功率晶体管20的电流。
进一步的，如图3所示，所述检测电路可以包括一电流镜电路，其中，所述电流镜电路可以包括：第一晶体管M1和第二晶体管M2。其中：
第一晶体管M1的控制端和第一端均与所述第一电源VSS连接；
第二晶体管M2的控制端和第一端均与所述第一电源VSS连接。
在本示例性实施例中，所述第一晶体管M1和所述第二晶体管M2的尺寸可以相同，以使流经所述第一晶体管M1和流经所述第二晶体管M2的电流相等。
所述第一晶体管M1和所述第二晶体管M2可以均为场效应晶体管，还可以均为双极晶体管。此外，所述第一晶体管M1和所述第二晶体管M2可以均为增强型晶体管，还可以均为耗尽型晶体管，本示例性实施例对此不作特殊限定。
所述第一晶体管M1和所述第二晶体管M2均具有控制端、第一端以及第二端。举例而言，各晶体管的控制端可以为栅极，各晶体管的第一端可以为源极，各晶体管的第二端可以为漏极。
在第一晶体管M1和第二晶体管M2均为P型薄膜晶体管时，所述第一电源VSS输出高电平。在第一晶体管M1和第二晶体管M2均为N型薄膜晶体管时，所述第一电源VSS输出低电平。需要说明的是，P型薄膜晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型薄膜晶体管在栅极为低电平时截止，在栅极为高电平时导通。
进一步的，所述检测电路还可以包括：第三晶体管M3、第一开关S1、第四晶体 管M4、第二开关S2、第五晶体管M5以及电阻R。其中：
第三晶体管M3的控制端与所述第一电源VSS连接，第三晶体管M3的第一端与所述第一晶体管M1的第二端连接，第三晶体管M3的第二端与第二电源VDD连接；
第一开关S1的第一端与所述第二晶体管M2的第二端连接，第一开关S1的第二端与所述检测电路的电流检测端D1连接；
第四晶体管M4的控制端和第二端均与所述第二电源VDD连接，第四晶体管M4的第一端与所述检测电路的电流检测端D1连接；
第二开关S2的第一端与所述第二晶体管M2的第二端连接，第二开关S2的第二端与所述第二电源VDD连接；
第五晶体管M5的控制端与所述第一晶体管M1的第一端连接，第五晶体管M5的第一端与所述检测电路的电压检测端D2连接，第五晶体管M5的第二端与所述第一晶体管M1的第二端连接；
电阻R的第一端与所述第一电源VSS连接，电阻R的第二端与所述检测电路的电压检测端D2连接。
在本示例性实施例中，所述第三晶体管M3至第五晶体管M5可以均为场效应晶体管，还可以均为双极晶体管。此外，所述第三晶体管M3至第五晶体管M5可以均为增强型晶体管，还可以均为耗尽型晶体管，本示例性实施例对此不作特殊限定。
所述第三晶体管M3至第五晶体管M5均具有控制端、第一端以及第二端。举例而言，各晶体管的控制端可以为栅极，各晶体管的第一端可以为源极，各晶体管的第二端可以为漏极。
所述第三晶体管M3至所述第五晶体管M5可以均为N型薄膜晶体管，所述第三晶体管M3至所述第五晶体管M5还可以均为P型薄膜晶体管。需要说明的是，P型薄膜晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型薄膜晶体管在栅极为低电平时截止，在栅极为高电平时导通。
此外，所述第三晶体管M3与所述第四晶体管M4的尺寸比例可以为N，其中，N＞0且由所述第三晶体管的宽长比与所述第四晶体管的宽长比之比确定。
所述第一开关S1和所述第二开关S2可以为二极管等具有开关作用的器件。所述第一开关S1和所述第二开关S2均具有第一端和第二端。例如，第一端可以为阴极，第二端可以为阳极。再例如，第一端可以为阳极，第二端可以为阴极。
所述电阻R例如可以为多晶硅电阻、金属电阻、阱电阻或注入电阻等，本示例性实施例对此不作特殊限定。
进一步的，所述检测电路的状态可以包括检测状态和等待状态。其中，在检测电路处于所述检测状态时，所述第一开关S1接通，所述第二开关S2断开。在检测电路处于所述等待状态时，所述第一开关S1断开，所述第二开关S2接通。
下面，结合图3分别对检测电路的检测状态和等待状态进行说明。
在检测电路处于检测状态时，第一开关S1接通，第二开关S2断开。此时，第二晶体管M2和第四晶体管M4所在的回路导通。由于所述第一晶体管M1和所述第二晶体管M2的尺寸相同，且所述第一晶体管M1和第二晶体管M2构成电流镜电路，因此，流经所述第一晶体管M1和流经第二晶体管M2的电流相等。
在此基础上，由于第一晶体管M1的控制端和第一端之间的电压和第二晶体管M2的控制端和第一端之间的电压相等，因此，第一晶体管M1的第二端和第一端之间的电压与第二晶体管M2的第二端和第一端之间的电压相等。又由于第一晶体管M1的第一端和第二晶体管M2的第一端均连接第一电源VSS，因此，第一晶体管M1的第二端的电压与第二晶体管M2的第二端的电压相等。
在此基础上，由于第三晶体管M3与第四晶体管M4的尺寸比例为N(即可以将第三晶体管M3和第四晶体管M4看做是两个比例为N的电阻)，且第一晶体管M1的第二端的电压与第二晶体管M2的第二端的电压相等，因此，流经第四晶体管M4的电流与流经第五晶体管M5的电流成比例N。
如图3所示，通过检测电路的电压检测端D2可以检测第五晶体管M5的第一端的电压，进而可计算出流经第五晶体管M5的电流。再结合上述比例N即可计算出流经第四晶体管M4的电流。由于第四晶体管M4的第一端与检测电路的电流检测端D1连接，因此，通过流经第四晶体管M4的电流即可得到流经所述功率晶体管20的电流。
在检测电路处于等待状态时，第一开关S1断开，第二开关S2接通。此时，由于第二晶体管M2和第四晶体管M4组成的电路断开，因此无法检测到流经第四晶体管M4的电流，进而也无法检测流经所述功率晶体管20的电流。
综上所述，通过上述检测电路可以检测出流经第四晶体管M4的电流，进而得到流经所述功率晶体管20的电流。另外，所述电源管理集成模块(PMIC)10还可以根据流经所述功率晶体管20的电流调整所述驱动脚11传输的驱动信号，以使功率晶体管20的第二端的输出电压保持稳定。此外，上述检测电路结构简单且易于集成在所述电源管理集成模块(PMIC)10中。
本示例实施方式还提供一种显示装置，包括上述的供电电路。该显示装置包括：多条扫描线，用于提供扫描信号；多条数据线，用于提供数据信号；多个供电电路，电连接于上述的扫描线和数据线；其中至少之一的供电电路包括为本示例实施方式中的上述任一供电电路。所述显示装置例如可以包括手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
需要说明的是：所述显示装置中各模块单元的具体细节已经在对应的供电电路中进行了详细的描述，因此这里不再赘述。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个 或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (12)

  1. 一种供电电路，包括：
    一电源管理集成模块，包括一驱动脚，所述驱动脚用于传输驱动信号；
    一功率晶体管，其控制端与所述驱动脚连接，第一端与第一电源连接，第二端与负载连接，用于向所述负载提供电压。
  2. 根据权利要求1所述的供电电路，其中，所述电源管理集成模块还包括：
    一检测脚，所述检测脚与所述功率晶体管的第二端连接；
    一检测电路，所述检测电路的电流检测端与所述检测脚连接，用于检测流经所述功率晶体管的电流。
  3. 根据权利要求2所述的供电电路，其中，所述检测电路包括一电流镜电路，所述电流镜电路包括：
    第一晶体管，控制端和第一端均与所述第一电源连接；
    第二晶体管，控制端和第一端均与所述第一电源连接。
  4. 根据权利要求3所述的供电电路，其中，所述检测电路还包括：
    第三晶体管，控制端与所述第一电源连接，第一端与所述第一晶体管的第二端连接，第二端与第二电源连接；
    第一开关，第一端与所述第二晶体管的第二端连接，第二端与所述检测电路的电流检测端连接；
    第四晶体管，控制端和第二端均与所述第二电源连接，第一端与所述检测电路的电流检测端连接；
    第二开关，第一端与所述第二晶体管的第二端连接，第二端与所述第二电源连接；
    第五晶体管，控制端与所述第一晶体管的第一端连接，第一端与所述检测电路的电压检测端连接，第二端与所述第一晶体管的第二端连接；
    电阻，第一端与所述第一电源连接，第二端与所述检测电路的电压检测端连接。
  5. 根据权利要求4所述的供电电路，其中，所述检测电路的状态包括检测状态和等待状态；
    在所述检测状态，所述第一开关接通，所述第二开关断开；
    在所述等待状态，所述第一开关断开，所述第二开关接通。
  6. 根据权利要求3～5中任意一项所述的供电电路，其中，所述第一晶体管和所述第二晶体管的尺寸相同。
  7. 根据权利要求4～6中任意一项所述的供电电路，其中，所述第三晶体管与所述第四晶体管的尺寸比例为N，其中，N＞0且由所述第三晶体管的宽长比与所述第四晶体管的宽长比之比确定。
  8. 根据权利要求4～7中任意一项所述的供电电路，其中，所述第一晶体管至所述第 五晶体管均为N型薄膜晶体管或P型薄膜晶体管。
  9. 根据权利要求1～8中任意一项所述的供电电路，其中，所述功率晶体管为N型功率晶体管或P型功率晶体管。
  10. 根据权利要求1～9中任意一项所述的供电电路，其中，所述驱动脚传输的驱动信号为占空比可变的脉冲波形。
  11. 根据权利要求10所述的供电电路，其中，所述电源管理集成模块通过调整所述驱动信号的占空比控制所述功率晶体管的第二端的输出电压。
  12. 一种显示装置，包括如权利要求1～11中任意一项所述的供电电路。
PCT/CN2018/081722 2017-08-25 2018-04-03 供电电路及显示装置 WO2019037430A1 (zh)

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