WO2019033713A1 - 基于igzo制程的栅极驱动电路及液晶显示屏 - Google Patents

基于igzo制程的栅极驱动电路及液晶显示屏 Download PDF

Info

Publication number
WO2019033713A1
WO2019033713A1 PCT/CN2018/074101 CN2018074101W WO2019033713A1 WO 2019033713 A1 WO2019033713 A1 WO 2019033713A1 CN 2018074101 W CN2018074101 W CN 2018074101W WO 2019033713 A1 WO2019033713 A1 WO 2019033713A1
Authority
WO
WIPO (PCT)
Prior art keywords
tft
gate
port
electrically connected
circuit module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/074101
Other languages
English (en)
French (fr)
Inventor
石龙强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/060,521 priority Critical patent/US20200320947A1/en
Publication of WO2019033713A1 publication Critical patent/WO2019033713A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of terminal technologies, and in particular, to a gate driving circuit and a liquid crystal display based on an IGZO process.
  • GOA Gate Driver on Array
  • TFT Thin Film Transistor
  • the driving method has the advantages of reducing the production cost and realizing the narrow frame design of the panel, and is used by various displays.
  • the GOA circuit has two basic functions: output gate scan drive signal to drive the gate line in the panel, open the TFT in the display area, charge the pixel; shift register function, when a gate scan drive signal After the output is completed, the output of the next gate scan driving signal is performed by clock control, and is sequentially transmitted.
  • IGZO indium gallium zinc oxide
  • IGZO is an amorphous oxide containing indium, gallium and zinc. It has high mobility and stability of the device, which is beneficial to improve the line scan rate of pixels. Therefore, the GOA circuit is usually integrated using the IGZO process.
  • the technical problem to be solved by the embodiments of the present invention is to provide a gate driving circuit and a liquid crystal display screen based on the IGZO process, which can improve the output waveform of the current stage gate driving signal output by the GOA circuit, and reduce the rising edge time and the falling edge time. Also reduces circuit power consumption.
  • the embodiment of the present invention provides a gate driving circuit based on an IGZO process, including: a GOA gate driving circuit module with N stages cascaded, and each level of the GOA gate driving circuit module includes an electrical connection. GOA circuit module and amplification circuit module;
  • the GOA circuit module includes a first input port, a second input port, and a first output port, where the first input port and the second input port are respectively used to input a previous stage gate driving signal and a first clock signal;
  • the GOA circuit module is configured to maintain an output level of the first output port unchanged when the first clock signal is in a hold period, and when the first clock signal is in a gating period,
  • the upper gate drive signal is used as a current stage gate drive signal and output through the first output port;
  • the amplifying circuit module includes a third input port for inputting the current stage gate driving signal, and the amplifying circuit module for driving the current level gate driving signal Amplifying processing is performed, and a current stage gate driving amplification signal is output through the second output port.
  • the amplifying circuit module includes a first thin film transistor TFT, a second TFT, a third TFT, and a fourth TFT; a source of the first TFT and a drain of the second TFT and the a gate of the fourth TFT is electrically connected, and a gate of the second TFT is electrically connected to a first output port of the GOA circuit module and a gate of the third TFT, respectively
  • the source is electrically connected to the drain of the fourth TFT; the gate of the first TFT, the drain of the first TFT, and the drain of the third TFT are respectively connected to the first voltage source (VGH An electrical connection; a source of the second TFT and a source of the fourth TFT are electrically connected to a second voltage source (VSS), respectively.
  • the amplifying circuit module further includes a first capacitor, the first capacitor being connected across a gate and a source of the third TFT.
  • the GOA circuit module includes a pull-down maintaining circuit unit, a second capacitor, a fifth TFT, and a sixth TFT, and the pull-down maintaining circuit unit includes a first port, a second port, a third port, and a fourth port.
  • the source of the fifth TFT is electrically connected to the gates of the first port and the sixth TFT, respectively, and the source of the sixth TFT is respectively connected to the third port and the first output
  • the port and the second voltage source (VSS) are electrically connected, the gate and the drain of the fifth TFT are electrically connected to the first input port, respectively; the drain of the sixth TFT and the fourth port Electrically connected to the second input port, the second port is electrically connected to a second voltage source (VSS); the second capacitor is connected between the gate and the source of the sixth TFT .
  • the GOA circuit module further includes: a seventh TFT and an eighth TFT; a drain of the seventh TFT and a gate of the fifth TFT and a gate of the sixth TFT, respectively.
  • the gate of the seventh TFT is electrically connected to the gate of the eighth TFT
  • the drain of the eighth TFT is electrically connected to the source of the sixth TFT
  • the seventh TFT is The source and the drain of the eighth TFT are electrically connected to the second voltage source (VSS), respectively.
  • an embodiment of the present invention further discloses a liquid crystal display including a gate driving circuit based on the IGZO process as described above.
  • Embodiments of the present invention provide a gate driving circuit and a liquid crystal display screen based on an IGZO process
  • the gate driving circuit includes: a GOA gate driving circuit module cascaded with N stages, and each stage GOA gate driving
  • the circuit modules each include a GOA circuit module and an amplifying circuit module electrically connected to each other; the GOA circuit module is configured to maintain the output level unchanged when the first clock signal is in the hold period, when the first clock signal is at During the strobing period, the input upper gate driving signal is output as the current-level gate driving signal, and the amplifying circuit module is configured to perform amplification processing on the current-level gate driving signal to output the current-level gate
  • the pole drive amplifies the signal; this improves the output waveform of the GOA circuit output current gate drive signal, reduces the rising edge time and falling edge time, and reduces the circuit power consumption.
  • FIG. 1 is a schematic diagram of a connection of a GOA circuit module according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of waveforms of a GOA based circuit module according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a gate driving circuit based on an IGZO process according to an embodiment of the present invention
  • FIG. 4A and FIG. 4B are schematic diagrams showing the connection of two types of amplifying circuit modules according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of waveforms in a gate driving circuit according to an embodiment of the present invention.
  • 6A and 6B are schematic diagrams showing a gate driving circuit based on an IGZO process according to another embodiment of the present invention.
  • the GOA circuit module 100 includes four ports, which are respectively port 11 to port 14, wherein port 11 and port 13 respectively The first output port 11, the second input port 12, and an input port 13, the port 14 is the first output port 14.
  • the first input port 11 is used to input the upper stage gate drive signal G(n-1).
  • the second input port 12 inputs a first clock signal CK/XCK.
  • the input port 13 is used to input the first DC signal VSS, and may also be electrically connected to the first voltage source VSS.
  • the GOA circuit module 100 may include a pull-down maintaining unit 102, two Thin Film Transistors (TFTs), T100, T106, and a bootstrap capacitor, respectively, shown as Cb.
  • the pull-down maintaining unit 102 includes seven ports, which are illustrated as port 1 to port 7, respectively.
  • the gate and the drain of the T104 are electrically connected to the first input port 11, and the sources of the T104 are electrically connected to the gates of the ports 1, 4, and T106, respectively, and the drain and port 3 of the T106 are respectively.
  • the second input port 12 is electrically connected.
  • Port 2 is electrically connected to the source of T106, and the bootstrap capacitor Cb is connected across the gate and source of T106.
  • the sources of T106 are electrically connected to the first output port 14 and the input port 13, respectively.
  • the GOA circuit module 100 may further include two other TFTs, which are illustrated as T108 and T110.
  • T108 is electrically connected to the source of T106, and the source of T108 is electrically connected to the input port 13.
  • sexual connection The gate of T110 is electrically connected to the gate of T108, and the drain of T110 is electrically connected to the gate of T106 and the source of T104, respectively, and the source of T110 is electrically connected to the input port 13.
  • Port 5, port 6, and port 7 of the pull-down maintaining unit are electrically connected to the input port 13, respectively.
  • the GOA circuit module 100 may further have another input port 15 for inputting a next-stage gate drive signal, the input port 15 and the gate of the T110, respectively.
  • the gate of T108 is electrically connected.
  • the working principle of the GOA circuit module 100 is: when the input G(n) is a high level signal, the bootstrap capacitor Cb is charged, and the pull-down maintaining unit is used to maintain the input upper gate signal and the first clock signal.
  • the off state that is, the output of the low voltage DC signal (the first DC signal).
  • the bootstrap capacitor Cb When the input G(n) is a low level signal, the bootstrap capacitor Cb is discharged, so that the current stage gate drive signal G(n) is obtained through the first output port 14.
  • the first DC signal VSS may be a low voltage DC signal of -5V, that is, the potential is -5V.
  • FIG. 2 is a schematic diagram showing several waveforms involved in the operation of a GOA circuit module according to an embodiment of the present invention.
  • the STV is the start signal, that is, the first stage gate drive signal.
  • CK/XCK is a high-frequency AC signal with the opposite signal. These high and low potentials are 28V and -5V, respectively.
  • the first clock signal input from the third input port 13 in each adjacent two-stage GOA circuit module may be a high-frequency alternating current with the opposite signal, and the first-level GOA circuit module inputs the first clock signal as CK.
  • the first clock signal input by the current stage GOA circuit module may be XCK.
  • the gate driving circuit 10 includes: a GOA gate driving circuit module with N stages cascaded, and a GOA gate of each stage.
  • the driving circuit modules each include a GOA circuit module 100 and an amplifying circuit module 200 electrically connected to each other;
  • the GOA circuit module 100 includes a first input port 11, a second input port 12, and a first output port 14.
  • the first input port 11 and the second input port 12 are respectively used to input a previous stage gate drive signal G. (n-1) and a first clock signal CK/XCK;
  • the GOA circuit module 1000 is configured to maintain an output level of the first output port 14 when the first clock signal CK/XCK is in a hold period
  • the upper-stage gate driving signal G(n-1) is used as the current-stage gate driving signal G(n), and passes through The first output port 14 outputs;
  • the amplifying circuit module 200 includes a third input port 16 for inputting the current stage gate driving signal G(n), and a second output port 19 for The current stage gate drive signal G(n) is amplified, and the current stage gate drive amplification signal G(n)_out is output through the second output port 19.
  • the output waveform of the current stage gate driving signal output by the GOA circuit module can be improved, the rising edge time and the falling edge time are reduced, and the circuit power consumption can also be reduced.
  • GOA circuit module 100 of the embodiment of the present invention may be specifically referred to the GOA circuit module 100 in the connection diagram shown in FIG. 1 , and details are not described herein again.
  • FIG. 4A is a schematic diagram of a connection circuit of an amplifying circuit module 200 according to an embodiment of the present invention.
  • the amplifying circuit module 200 includes a third input port 16, a fourth input port 17, a fifth input port 18, and a second output. Port 19; wherein the third input port 16 is for inputting a current stage gate drive signal G(n).
  • the fourth input port 17 is used for inputting the first DC signal VSS, and may also be electrically connected to the first voltage source VSS, where the first voltage source may be a low voltage DC potential source of -5V.
  • the fifth input port 18 is used for inputting the second DC signal VGH, and may also be electrically connected to the second voltage source VGH, where the second voltage source may be a 28V high voltage DC potential source.
  • the amplifying circuit module 200 may include four thin film transistors, which are respectively illustrated as a first thin film transistor T112, a second thin film transistor T114, a third thin film transistor T116, and a fourth thin film transistor T118.
  • the gate and the drain of the first TFT (T112) are electrically connected to the fifth input port 18.
  • the source of T112 is electrically connected to the drain of the second TFT (T114) and the gate of the fourth TFT (T118).
  • the gate of the second TFT (T114) and the gate of the third TFT (T116) are electrically connected to the third input port 16.
  • the drain of the third TFT (T116) is electrically connected to the fifth input port 18.
  • the source of the third TFT (T116) and the drain of the fourth TFT (T118) are electrically connected to the second output port 19, respectively.
  • the source of the second TFT (T114) and the drain of the fourth TFT (T118) are electrically connected to the fourth input port 17, respectively.
  • the working principle of the amplifying circuit module 200 when G(N) is a low potential of -5V, the second TFT (T114) and the third TFT (T116) are in an off/off state, due to the gate connection of the first TFT (T112) VGH (28V), so the first TFT (T112) is turned on, the potential of S(N) is 28V, the fourth TFT (T118) is turned on, and G(n)_out outputs the low potential of VSS -5V.
  • FIG. 5 is a schematic diagram showing several waveforms in a gate driving circuit according to an embodiment of the present invention.
  • FIG. 4B is a schematic diagram of a connection circuit of another amplifying circuit module 200 according to an embodiment of the present invention.
  • the amplifying circuit module 200 may further include a capacitor, illustrated as a bootstrap capacitor Ca, across which a gate is connected between the gate and the source of the third TFT (T116).
  • the working principle of the amplifying circuit module 200 is that when G(N) is a low potential of -5V, T114 and T116 are in a closed state. Since the gate of T112 is connected to VGH (28V), the first TFT (T112) is turned on, the potential of S(N) is 28V, the fourth TFT (T118) is turned on, and G(n)_out outputs the low potential of VSS - 5V. When G(N) is 5V high, T114 and T116 are turned on. Since the gate of T112 is connected to VGH (28V), T112 and T116 are turned on.
  • FIG. 5 is a schematic diagram showing several waveforms in a gate driving circuit according to an embodiment of the present invention.
  • FIG. 6A and FIG. 6B are schematic diagrams of a gate driving circuit based on an IGZO process according to another embodiment of the present invention.
  • GOA circuit module 100 and the amplifying circuit module 200 are schematic diagrams of a gate driving circuit based on an IGZO process according to another embodiment of the present invention.
  • the embodiment of the present invention may also provide a liquid crystal display screen, which may include a schematic diagram of a gate driving circuit based on the IGZO process as shown in FIG. 6A or 6B.
  • a liquid crystal display screen which may include a schematic diagram of a gate driving circuit based on the IGZO process as shown in FIG. 6A or 6B.
  • FIG. 6A or 6B For details, refer to the related embodiments. Narration.
  • the disclosed apparatus may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or may be Integrate into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be electrical or otherwise.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the technical solution of the present invention which is essential or contributes to the prior art, or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk, and the like. .

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

提供了一种基于IGZO制程的栅极驱动电路及液晶显示屏，其中，栅极驱动电路包括：级联有N级的GOA栅极驱动电路模块，每级GOA栅极驱动电路模块均包括相互电性连接的GOA电路模块(100)和放大电路模块(200)；GOA电路模块(100)用于在第一时钟信号(CK/XCK)处于保持时间段时，维持输出电平不变，在第一时钟信号(CK/XCK)处于选通时间段时，将输入的上一级栅极驱动信号(G(n-1))作为当前级栅极驱动信号(G(n))输出；放大电路模块(200)用于对当前级栅极驱动信号(G(n))进行放大处理，以输出当前级栅极驱动放大信号(G(n)_out)，从而可改善GOA电路输出当前级栅极驱动信号(G(n))的输出波形，降低上升沿时间和下降沿时间，同时降低电路功耗。

Description

基于IGZO制程的栅极驱动电路及液晶显示屏 技术领域
本发明涉及终端技术领域，尤其涉及一种基于IGZO制程的栅极驱动电路及液晶显示屏。
背景技术
GOA(Gate Driver on Array)技术即是阵列基板行驱动技术，是利用薄膜晶体管(Thin Film Transistor，TFT)液晶显示器阵列制程将栅极扫描驱动电路制作在薄膜晶体管阵列基板上，以实现逐行扫描的驱动方式，具有降低生产成本和实现面板窄边框设计的优点，被多种显示器所使用。GOA电路具有两项基本功能分别为：输出栅极扫描驱动信号，以驱动面板内的栅极线，打开显示区内的TFT，对像素进行充电；移位寄存器功能，当一个栅极扫描驱动信号输出完成后，通过时钟控制进行下一个栅极扫描驱动信号的输出，并依次传递下去。
IGZO(indium gallium zinc oxide)是一种含有铟、镓和锌的非晶氧化物，具有较高的迁移率、和器件稳定性等优点，有利于提升像素的行扫描速率。因此，通常利用IGZO制程集成GOA电路。
现有技术中，针对IGZO的GOA电路研究较少，尤其针对大慈村的GOA电路需要克服IGZOO材料本身带来的问题。随着大尺寸液晶显示屏的发展趋势，面板尺寸和栅极驱动行数将增加，GOA的负载将变多，这样会增加GOA电路的功耗。
发明内容
本发明实施例所要解决的技术问题在于，提供一种基于IGZO制程的栅极驱动电路及液晶显示屏，可可改善GOA电路输出当前级栅极驱动信号的输出波形，降低上升沿时间和下降沿时间，还降低了电路功耗。
一方面，本发明实施例公开提供了一种基于IGZO制程的栅极驱动电路，包括：级联有N级的GOA栅极驱动电路模块，每级GOA栅极驱动电路模块均包括相互电性连接的GOA电路模块和放大电路模块；
所述GOA电路模块包括第一输入端口、第二输入端口和第一输出端口，所述第一输入端口和第二输入端口分别用于输入上一级栅极驱动信号和第一时钟信号；所述GOA电路模块用于在所述第一时钟信号处于保持时间段时，维持所述第一输出端口的输出电平不变，在所述第一时钟信号处于选通时间段时，将所述上一级栅极驱动信号作为当前级栅极驱动信号，并通过所述第一输出端口输出；
所述放大电路模块包括第三输入端口和第二输出端口，所述第三输入端口用于输入所述当前级栅极驱动信号，所述放大电路模块用于对所述当前级栅极驱动信号进行放大处理，并通过所述第二输出端口输出当前级栅极驱动放大信号。
其中可选地，所述放大电路模块包括第一薄膜晶体管TFT、第二TFT、第三TFT和第四TFT；所述第一TFT的源极分别与所述第二TFT的漏极和所述第四TFT的栅极电性连接，所述第二TFT的栅极分别与所述GOA电路模块的第一输出端口、和所述第三TFT的栅极电性连接，所述第三TFT的源极与所述第四TFT的漏极电性连接；所述第一TFT的栅极、所述第一TFT的漏极、及所述第三TFT的漏极分别与第一电压源(VGH)电性连接；所述第二TFT的源极和所述第四TFT的源极分别与第二电压源(VSS)电性连接。
其中可选地，所述放大电路模块还包括第一电容，所述第一电容跨接在所述第三TFT的栅极和源极之间。
其中可选地，所述GOA电路模块包括下拉维持电路单元、第二电容、第五TFT和第六TFT，所述下拉维持电路单元包括第一端口、第二端口、第三端口和第四端口；所述第五TFT的源极分别与所述第一端口和所述第六TFT的栅极电性连接，所述第六TFT的源极分别与所述第三端口、所述第一输出端口和第二电压源(VSS)电性连接，所述第五TFT的栅极和漏极分别与所述第一输入端口电性连接；所述第六TFT的漏极和所述第四端口分别与所述第二输入端口电性连接，所述第二端口与第二电压源(VSS)电性连接；所述第二电容跨接在所述第六TFT的栅极和源极之间。
其中可选地，所述GOA电路模块还包括：第七TFT和第八TFT；所述第七TFT的漏极分别与所述第五TFT的源极和所述第六TFT的栅极电性连接， 所述第七TFT的栅极与所述第八TFT的栅极电性连接，所述第八TFT的漏极与所述第六TFT的源极电性连接；所述第七TFT的源极和所述第八TFT的漏极分别与所述第二电压源(VSS)电性连接。
另一方面，本发明实施例还公开提供了一种液晶显示屏，所述液晶显示屏包括如上所述的基于IGZO制程的栅极驱动电路。
本发明实施例提供了一种基于IGZO制程的栅极驱动电路及液晶显示屏，其中，所述栅极驱动电路包括：级联有N级的GOA栅极驱动电路模块，每级GOA栅极驱动电路模块均包括相互电性连接的GOA电路模块和放大电路模块；所述GOA电路模块用于在第一时钟信号处于保持时间段时，维持输出电平不变，在所述第一时钟信号处于选通时间段时，将输入的上一级栅极驱动信号作为当前级栅极驱动信号输出，所述放大电路模块用于对所述当前级栅极驱动信号进行放大处理，以输出当前级栅极驱动放大信号；这样可改善GOA电路输出当前级栅极驱动信号的输出波形，降低上升沿时间和下降沿时间，还可降低电路功耗。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种GOA电路模块的连线示意图；
图2是本发明实施例提供的一种基于GOA电路模块的波形示意图；
图3是本发明实施例的一种基于IGZO制程的栅极驱动电路的示意图；
图4A和图4B是本发明实施例提供的两种放大电路模块的连线示意图；
图5是本发明实施例提供的一种栅极驱动电路中的波形示意图；
图6A和图6B是本发明另一实施例的一种基于IGZO制程的栅极驱动电路的示意图。
具体实施方式
为了使本技术领域的人员更好地理解本发明方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分的实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明保护的范围。
本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”和“第三”(如果存在)等是用于区别不同对象，而非用于描述特定顺序。此外，术语“包括”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
请参见图1，是本发明实施例提供的一种GOA电路模块的连线示意图，该GOA电路模块100包括：四个端口，图示分别为端口11至端口14，其中端口11和端口13分别为第一输出端口11、第二输入端口12和一输入端口13，端口14为第一输出端口14。其中第一输入端口11用于输入上一级栅极驱动信号G(n-1)。第二输入端口12输入第一时钟信号CK/XCK。输入端口13用于输入第一直流信号VSS，也可与第一电压源VSS电性连接。
GOA电路模块100可包括下拉维持单元102，两个薄膜晶体管(Thin Film Transistor，TFT)，图示分别为T104、T106，以及一个自举电容，图示为Cb。所述下拉维持单元102包括七个端口，图示分别为端口1至端口7。其中，T104的栅极和漏极与所述第一输入端口11电性连接，T104的源极分别与端口1、端口4、T106的栅极电性连接，T106的漏极和端口3分别与所述第二输入端口12电性连接。端口2与T106的源极电性连接，自举电容Cb跨接在T106的栅极和源极。T106的源极分别与第一输出端口14和输入端口13电性连接。
在本发明的一个实施例中，GOA电路模块100还可包括另外两个TFT，图示为T108及T110，T108的漏极与T106的源极电性连接，T108的源极与输入端口13电性连接。T110的栅极与T108的栅极电性连接，T110的漏极分别与T106的栅极和T104的源极电性连接，T110的源极与输入端口13电性连接。所述下拉维持单元的端口5、端口6及端口7分别与输入端口13电性连 接。
在本发明的又一个实施例中，GOA电路模块100还可另一输入端口15，所述输入端口15用于输入下一级栅极驱动信，所述输入端口15分别与T110的栅极和T108的栅极电性连接。
GOA电路模块100的工作原理为：当输入G(n)为高电平信号时，对自举电容Cb进行充电，下拉维持单元用于对输入的上一级栅极信号和第一时钟信号保持关闭状态，即保持输出低压直流信号(所述第一直流信号)。当输入G(n)为低电平信号时，自举电容Cb放电，从而通过第一输出端口14输出得到当前级栅极驱动信号G(n)。可选地，所述第一直流信号VSS可为-5V的低压直流电信号，即电位为-5V。如图2示出了本发明实施例提供的一种GOA电路模块工作涉及的几个波形示意图。其中STV为起始信号，即第一级栅极驱动信号。CK/XCK是信号完全相反的高频交流电信号，这些的高低电位分别是28V和-5V。
在一些实施例中，每相邻两级GOA电路模块中从第三输入端口13输入的第一时钟信号可为信号完全相反的高频交流电，如上一级GOA电路模块输入第一时钟信号为CK，则当前级GOA电路模块输入的第一时钟信号可为XCK。
请参见图3，是本发明实施例的一种基于IGZO制程的栅极驱动电路的示意图，该栅极驱动电路10包括：级联有N级的GOA栅极驱动电路模块，每级GOA栅极驱动电路模块均包括相互电性连接的GOA电路模块100和放大电路模块200；
所述GOA电路模块100包括第一输入端口11、第二输入端口12和第一输出端口14，所述第一输入端口11和第二输入端口12分别用于输入上一级栅极驱动信号G(n-1)和第一时钟信号CK/XCK；所述GOA电路模块1000用于在所述第一时钟信号CK/XCK处于保持时间段时，维持所述第一输出端口14的输出电平不变，在所述第一时钟信号CK/XCK处于选通时间段时，将所述上一级栅极驱动信号G(n-1)作为当前级栅极驱动信号G(n)，并通过所述第一输出端口14输出；
所述放大电路模块200包括第三输入端口16和第二输出端口19，所述第三输入端口4用于输入所述当前级栅极驱动信号G(n)，所述放大电路模块200用于对所述当前级栅极驱动信号G(n)进行放大处理，并通过所述第二输出端口19输出当前级栅极驱动放大信号G(n)_out。
通过实施本发明实施例，可改善GOA电路模块输出当前级栅极驱动信号的输出波形，降低上升沿时间和下降沿时间，还可降低电路功耗。
需要说明的是，本发明实施例所涉及的GOA电路模块100可具体参见图1所示连线示意图中的GOA电路模块100，这里不再赘述。
请参见图4A，是本发明实施例提供的一种放大电路模块200的连线示意图，该放大电路模块200包括第三输入端口16、第四输入端口17、第五输入端口18和第二输出端口19；其中，所述第三输入端口16用于输入当前级栅极驱动信号G(n)。所述第四输入端口17用于输入第一直流信号VSS，也可与第一电压源VSS电性连接，这里的第一电压源可为-5V的低压直流电位源。所述第五输入端口18用于输入第二直流信号VGH，也可与第二电压源VGH电性连接，这里的第二电压源可为28V的高压直流电位源。
放大电路模块200可包括四个薄膜晶体管，图示分别为第一薄膜晶体管T112、第二薄膜晶体管T114、第三薄膜晶体管T116和第四薄膜晶体管T118。其中，第一TFT(T112)的栅极和漏极与第五输入端口18电性连接。T112的源极与第二TFT(T114)的漏极和第四TFT(T118)的栅极电性连接。第二TFT(T114)的栅极和第三TFT(T116)的栅极与第三输入端口16电性连接。第三TFT(T116)的漏极与第五输入端口18电性连接。第三TFT(T116)的源极和第四TFT(T118)的漏极分别与第二输出端口19电性连接。第二TFT(T114)的源极和第四TFT(T118)的漏极分别与第四输入端口17电性连接。
放大电路模块200的工作原理：当G(N)为-5V低电位时，第二TFT(T114)和第三TFT(T116)处于截止/关闭状态，由于第一TFT(T112)的栅极接VGH(28V),所以第一TFT(T112)打开，S(N)的电位为28V，第四TFT(T118)导通，G(n)_out输出VSS的低电位-5V。当G(N)为5V高电位时，第二TFT(T114)和第三TFT(T116)导通，由于第一TFT(T112)的栅极接VGH(28V)， 所以第一TFT(T112)和第三TFT(T116)导通，由于T112和T114的分压作用，S(N)的电位为-5V，所以第四TFT(T118)处于关闭状态；G(n)_out输出VGH的高电位28V。具体可参见图5，示出了本发明实施例涉及的栅极驱动电路中的几种波形示意图。
在一些可能的实施例中，请参见图4B所示，是本发明实施例提供的又一种放大电路模块200的连线示意图。该放大电路模块200还可包括一个电容，图示为自举电容Ca，Ca跨接在所述第三TFT(T116)的栅极和源极之间。
该放大电路模块200的工作原理为：当G(N)为-5V低电位时，T114和T116处于关闭状态。由于T112的栅极接VGH(28V),所以第一TFT(T112)导通，S(N)的电位为28V，第四TFT(T118)导通，G(n)_out输出VSS的低电位-5V。当G(N)为5V高电位时，T114和T116导通，由于T112的栅极接VGH(28V),所以T112和T116导通，由于T112和T114的分压作用，S(N)的电位为-5V，所以T118处于关闭状态；G(N)_out输出VGH的高电位28V。此外，该过程G(n)_out的电位由原来的-5V变为28V，由于Ca电容效应，T(N)电位会由28V上升的更高，这样，第三TFT(T116)导通的更好，VGH的高电位更快更好的传递到G(n)_out，所以该电路有更好的gate输出波形和而且电路更加稳定。具体可参见图5，示出了本发明实施例涉及的栅极驱动电路中的几种波形示意图。
请参见图6A和图6B，分别是本发明另一实施例提供的一种基于IGZO制程的栅极驱动电路的示意图。其中GOA电路模块100和放大电路模块200具体可参见前述相关实施例中的描述，这里不再赘述。
本发明实施例还可提供一种液晶显示屏，该液晶显示屏可包括如图6A或6B所示提供的基于IGZO制程的栅极驱动电路的示意图，具体可参见前述相关实施例，这里不再赘述。
需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本发明并不受所描述的动作顺序的限制，因为依据本发明，某些步骤可以采用其他顺序或者 同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定是本发明所必须的。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置，可通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明的各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可为个人计算机、服务器或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，以上实施例仅用以说明本发明的技术方案，而非对其限制；尽 管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (10)

  1. 一种基于IGZO制程的栅极驱动电路，其特征在于，包括：级联有N级的GOA栅极驱动电路模块，每级GOA栅极驱动电路模块均包括相互电性连接的GOA电路模块和放大电路模块；
    所述GOA电路模块包括第一输入端口、第二输入端口和第一输出端口，所述第一输入端口和第二输入端口分别用于输入上一级栅极驱动信号和第一时钟信号；所述GOA电路模块用于在所述第一时钟信号处于保持时间段时，维持所述第一输出端口的输出电平不变，在所述第一时钟信号处于选通时间段时，将所述上一级栅极驱动信号作为当前级栅极驱动信号，并通过所述第一输出端口输出；
    所述放大电路模块包括第三输入端口和第二输出端口，所述第三输入端口用于输入所述当前级栅极驱动信号，所述放大电路模块用于对所述当前级栅极驱动信号进行放大处理，并通过所述第二输出端口输出当前级栅极驱动放大信号。
  2. 根据权利要求1所述的栅极驱动电路，其特征在于，所述放大电路模块包括第一薄膜晶体管TFT、第二TFT、第三TFT和第四TFT；
    所述第一TFT的源极分别与所述第二TFT的漏极和所述第四TFT的栅极电性连接，所述第二TFT的栅极分别与所述GOA电路模块的第一输出端口、和所述第三TFT的栅极电性连接，所述第三TFT的源极与所述第四TFT的漏极电性连接；
    所述第一TFT的栅极、所述第一TFT的漏极、及所述第三TFT的漏极分别与第一电压源(VGH)电性连接；所述第二TFT的源极和所述第四TFT的源极分别与第二电压源(VSS)电性连接。
  3. 根据权利要求2所述的栅极驱动电路，其特征在于，所述放大电路模块还包括第一电容，所述第一电容跨接在所述第三TFT的栅极和源极之间。
  4. 根据权利要求1所述的栅极驱动电路，其特征在于，所述GOA电路模块包括下拉维持电路单元、第二电容、第五TFT和第六TFT，所述下拉维持电路单元包括第一端口、第二端口、第三端口和第四端口；
    所述第五TFT的源极分别与所述第一端口和所述第六TFT的栅极电性连接，所述第六TFT的源极分别与所述第三端口、所述第一输出端口和第二电压源(VSS)电性连接，所述第五TFT的栅极和漏极分别与所述第一输入端口电性连接；所述第六TFT的漏极和所述第四端口分别与所述第二输入端口电性连接，所述第二端口与第二电压源(VSS)电性连接；所述第二电容跨接在所述第六TFT的栅极和源极之间。
  5. 根据权利要求4所述的栅极驱动电路，其特征在于，所述GOA电路模块还包括：第七TFT和第八TFT；
    所述第七TFT的漏极分别与所述第五TFT的源极和所述第六TFT的栅极电性连接，所述第七TFT的栅极与所述第八TFT的栅极电性连接，所述第八TFT的漏极与所述第六TFT的源极电性连接；所述第七TFT的源极和所述第八TFT的漏极分别与所述第二电压源(VSS)电性连接。
  6. 一种液晶显示屏，其特征在于，所述液晶显示屏包括基于IGZO制程的栅极驱动电路，其中，所述栅极驱动电路包括级联有N级的GOA栅极驱动电路模块，每级GOA栅极驱动电路模块均包括相互电性连接的GOA电路模块和放大电路模块；
    所述GOA电路模块包括第一输入端口、第二输入端口和第一输出端口，所述第一输入端口和第二输入端口分别用于输入上一级栅极驱动信号和第一时钟信号；所述GOA电路模块用于在所述第一时钟信号处于保持时间段时，维持所述第一输出端口的输出电平不变，在所述第一时钟信号处于选通时间段时，将所述上一级栅极驱动信号作为当前级栅极驱动信号，并通过所述第一输出端口输出；
    所述放大电路模块包括第三输入端口和第二输出端口，所述第三输入端口用于输入所述当前级栅极驱动信号，所述放大电路模块用于对所述当前级栅极 驱动信号进行放大处理，并通过所述第二输出端口输出当前级栅极驱动放大信号。
  7. 根据权利要求6所述的液晶显示屏，其特征在于，所述放大电路模块包括第一薄膜晶体管TFT、第二TFT、第三TFT和第四TFT；
    所述第一TFT的源极分别与所述第二TFT的漏极和所述第四TFT的栅极电性连接，所述第二TFT的栅极分别与所述GOA电路模块的第一输出端口、和所述第三TFT的栅极电性连接，所述第三TFT的源极与所述第四TFT的漏极电性连接；
    所述第一TFT的栅极、所述第一TFT的漏极、及所述第三TFT的漏极分别与第一电压源(VGH)电性连接；所述第二TFT的源极和所述第四TFT的源极分别与第二电压源(VSS)电性连接。
  8. 根据权利要求7所述的液晶显示屏，其特征在于，所述放大电路模块还包括第一电容，所述第一电容跨接在所述第三TFT的栅极和源极之间。
  9. 根据权利要求6所述的液晶显示屏，其特征在于，所述GOA电路模块包括下拉维持电路单元、第二电容、第五TFT和第六TFT，所述下拉维持电路单元包括第一端口、第二端口、第三端口和第四端口；
    所述第五TFT的源极分别与所述第一端口和所述第六TFT的栅极电性连接，所述第六TFT的源极分别与所述第三端口、所述第一输出端口和第二电压源(VSS)电性连接，所述第五TFT的栅极和漏极分别与所述第一输入端口电性连接；所述第六TFT的漏极和所述第四端口分别与所述第二输入端口电性连接，所述第二端口与第二电压源(VSS)电性连接；所述第二电容跨接在所述第六TFT的栅极和源极之间。
  10. 根据权利要求9所述的液晶显示屏，其特征在于，所述GOA电路模块还包括：第七TFT和第八TFT；
    所述第七TFT的漏极分别与所述第五TFT的源极和所述第六TFT的栅极 电性连接，所述第七TFT的栅极与所述第八TFT的栅极电性连接，所述第八TFT的漏极与所述第六TFT的源极电性连接；所述第七TFT的源极和所述第八TFT的漏极分别与所述第二电压源(VSS)电性连接。
PCT/CN2018/074101 2017-08-15 2018-01-25 基于igzo制程的栅极驱动电路及液晶显示屏 Ceased WO2019033713A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/060,521 US20200320947A1 (en) 2017-08-15 2018-01-25 Gate driver circuit based on igzo manufacturing process and liquid crystal display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710698881.2 2017-08-15
CN201710698881.2A CN107331361B (zh) 2017-08-15 2017-08-15 一种基于igzo制程的栅极驱动电路及液晶显示屏

Publications (1)

Publication Number Publication Date
WO2019033713A1 true WO2019033713A1 (zh) 2019-02-21

Family

ID=60201021

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/074101 Ceased WO2019033713A1 (zh) 2017-08-15 2018-01-25 基于igzo制程的栅极驱动电路及液晶显示屏

Country Status (3)

Country Link
US (1) US20200320947A1 (zh)
CN (1) CN107331361B (zh)
WO (1) WO2019033713A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107331361B (zh) * 2017-08-15 2020-05-05 深圳市华星光电半导体显示技术有限公司 一种基于igzo制程的栅极驱动电路及液晶显示屏
US10891902B2 (en) 2019-05-06 2021-01-12 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Driving circuit of display device
CN109961746B (zh) * 2019-05-06 2020-09-08 深圳市华星光电半导体显示技术有限公司 用于显示屏的驱动电路
KR102768805B1 (ko) * 2020-10-19 2025-02-19 삼성디스플레이 주식회사 표시 장치
WO2023216175A1 (zh) * 2022-05-12 2023-11-16 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置
US12380835B2 (en) * 2022-08-12 2025-08-05 Apple Inc. Electronic display pixel grouping to mitigate motion blur

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100066922A1 (en) * 2007-01-31 2010-03-18 Kouji Kumada Display device
CN104157259A (zh) * 2014-09-10 2014-11-19 深圳市华星光电技术有限公司 基于igzo制程的栅极驱动电路
CN107331361A (zh) * 2017-08-15 2017-11-07 深圳市华星光电半导体显示技术有限公司 一种基于igzo制程的栅极驱动电路及液晶显示屏

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100685842B1 (ko) * 2005-08-17 2007-02-22 삼성에스디아이 주식회사 발광제어 구동장치 및 이를 포함하는 유기전계발광표시장치
CN105185318B (zh) * 2015-10-19 2017-11-21 京东方科技集团股份有限公司 栅线驱动电路、输出发射控制信号的电路及触控显示装置
CN106952602B (zh) * 2017-04-14 2022-01-21 京东方科技集团股份有限公司 反相器模块、移位寄存器单元、阵列基板及显示装置
CN106940991B (zh) * 2017-04-25 2019-03-01 深圳市华星光电技术有限公司 扫描驱动电路及显示装置
CN107039016B (zh) * 2017-06-07 2019-08-13 深圳市华星光电技术有限公司 Goa驱动电路及液晶显示器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100066922A1 (en) * 2007-01-31 2010-03-18 Kouji Kumada Display device
CN104157259A (zh) * 2014-09-10 2014-11-19 深圳市华星光电技术有限公司 基于igzo制程的栅极驱动电路
CN107331361A (zh) * 2017-08-15 2017-11-07 深圳市华星光电半导体显示技术有限公司 一种基于igzo制程的栅极驱动电路及液晶显示屏

Also Published As

Publication number Publication date
CN107331361B (zh) 2020-05-05
US20200320947A1 (en) 2020-10-08
CN107331361A (zh) 2017-11-07

Similar Documents

Publication Publication Date Title
WO2019033713A1 (zh) 基于igzo制程的栅极驱动电路及液晶显示屏
CN103744206B (zh) 一种阵列基板驱动电路、阵列基板及相应的液晶显示器
CN103413532B (zh) 像素驱动电路和方法、阵列基板及液晶显示装置
CN104485079B (zh) 用于液晶显示装置的goa电路
CN104318888B (zh) 阵列基板栅极驱动单元、方法、电路和显示装置
CN104658466B (zh) 一种goa电路及其驱动方法、显示面板及显示装置
US10388241B2 (en) Pixel charging method and circuit, LCD panel, and LCD device
CN103928009B (zh) 用于窄边框液晶显示器的栅极驱动器
US9721522B2 (en) Array substrate including a charge sharing unit, driving method thereof, and display device
US9922589B2 (en) Emission electrode scanning circuit, array substrate and display apparatus
US9928922B2 (en) Shift register and method for driving the same, gate driving circuit and display device
CN108628049B (zh) 阵列基板、显示面板及显示装置
CN105336302A (zh) 基于ltps半导体薄膜晶体管的goa电路
CN108257578A (zh) 移位寄存器单元及其控制方法、栅极驱动装置、显示装置
US9972272B2 (en) Array substrate and driving method thereof, and display device
US20160210927A1 (en) Gate driving circuit and display apparatus including the same
US9390654B2 (en) Pixel driving circuit and array substrate of OLED display and the corresponding display
JP2017510829A (ja) ゲート駆動回路及び駆動方法
WO2016161694A1 (zh) 基于p型薄膜晶体管的goa电路
CN114078457A (zh) 栅极驱动电路以及显示装置
CN106448588A (zh) Goa驱动电路及液晶显示装置
CN107870489A (zh) 像素驱动电路及其驱动方法、阵列基板、显示面板、显示装置
US10386663B2 (en) GOA circuit and liquid crystal display device
CN105206234B (zh) 移位寄存器单元、栅极驱动方法、电路和栅极驱动装置
US10777161B2 (en) Array substrate, liquid crystal display panel and display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18846375

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18846375

Country of ref document: EP

Kind code of ref document: A1