WO2019028911A1 - 信号发送方法、接收方法及装置 - Google Patents

信号发送方法、接收方法及装置 Download PDF

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Publication number
WO2019028911A1
WO2019028911A1 PCT/CN2017/097266 CN2017097266W WO2019028911A1 WO 2019028911 A1 WO2019028911 A1 WO 2019028911A1 CN 2017097266 W CN2017097266 W CN 2017097266W WO 2019028911 A1 WO2019028911 A1 WO 2019028911A1
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Prior art keywords
sequence
sequences
signal
terminal device
another
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PCT/CN2017/097266
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English (en)
French (fr)
Inventor
汲桐
金哲
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP17921339.2A priority Critical patent/EP3664391A4/en
Priority to PCT/CN2017/097266 priority patent/WO2019028911A1/zh
Priority to CN201780093454.XA priority patent/CN110959279B/zh
Publication of WO2019028911A1 publication Critical patent/WO2019028911A1/zh
Priority to US16/787,749 priority patent/US11444816B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
    • H04L27/2662—Symbol synchronisation
    • H04L27/2663—Coarse synchronisation, e.g. by correlation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H04J13/10—Code generation
    • H04J13/102—Combining codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J11/00—Orthogonal multiplex systems, e.g. using WALSH codes
    • H04J11/0069—Cell search, i.e. determining cell identity [cell-ID]
    • H04J11/0073—Acquisition of primary synchronisation channel, e.g. detection of cell-ID within cell-ID group
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H04J13/0007—Code type
    • H04J13/0055—ZCZ [zero correlation zone]
    • H04J13/0059—CAZAC [constant-amplitude and zero auto-correlation]
    • H04J13/0062—Zadoff-Chu
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
    • H04L27/2668—Details of algorithms
    • H04L27/2673—Details of algorithms characterised by synchronisation parameters
    • H04L27/2675—Pilot or known symbols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0048—Allocation of pilot signals, i.e. of signals known to the receiver
    • H04L5/005—Allocation of pilot signals, i.e. of signals known to the receiver of common pilots, i.e. pilots destined for multiple users or terminals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/001—Synchronization between nodes
    • H04W56/0015—Synchronization between nodes one node acting as a reference for the others

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a signal transmitting method, a receiving method, and a device.
  • the terminal In communication systems with low cost and coverage enhancement requirements, such as the Narrow Band Internet of Things (NB-IoT), the terminal usually faces large crystal error when performing downlink synchronization processing (usually by cost). The problem caused by low).
  • a large crystal error means that there is a large carrier frequency offset of the received signal relative to the transmitted signal.
  • the carrier frequency offset in the frequency domain causes a continuous phase change of the sequence in the time domain.
  • a phase change in the time domain will cause the associated characteristics of the sequence to drop or even be corrupted.
  • the receiving end Once the relevant characteristics of the sequence are degraded or even destroyed, the receiving end will cause the correlation peak to disappear during the relevant processing, and the timing position cannot be determined.
  • the correlation process is that the receiving end convolves the received sequence with the local sequence, and the local sequence is a sequence without any channel or noise.
  • the primary synchronization signal in Long Term Evolution uses a ZC (Zadoff-Chu) sequence with a root index of 25, 29, or 34, and has a length of 63.
  • a ZC sequence is a sequence with good autocorrelation properties and is commonly used as a synchronization sequence. If the sequence design method in LTE (ie, a ZC sequence) is directly adopted in the NB-IoT system, the frequency offset performance is poor.
  • the sequence has no frequency offset (ie, the receiving sequence of the receiving end has no frequency offset with respect to the transmitting sequence), the correlation peak is more obvious when the receiving end performs correlation processing; as shown in FIG.
  • the sequence is There is a frequency offset (that is, the receiving sequence of the receiving end has a frequency offset with respect to the transmitting sequence), for example, the frequency offset is 18 kHz, and the correlation peak completely disappears when the receiving end performs correlation processing.
  • the embodiment of the invention provides a signal sending method, a receiving method and a device, which can resist frequency offset and accurately determine the timing position.
  • the embodiment of the present invention provides a signal sending method, where the signal sending method includes: the network device generates a first signal, where the first signal includes at least one sequence pair, and one sequence pair includes two sequences, optionally The sequences in the first signal are arranged according to the time domain symbol sequence of the sequence carried in the first signal.
  • the two sequences in a sequence pair may be adjacent sequences or non-adjacent sequences.
  • two sequences separated by S sequences form a sequence pair, and S is a natural number greater than or equal to 1.
  • one or more time domain symbols carry a sequence.
  • a sequence may exist in two sequence pairs at the same time, for example, any two adjacent sequences form a sequence pair, or a sequence exists only in one sequence pair.
  • the two sequences satisfy the condition that the element value of one sequence is the element value of the other of the two sequences using the first calculation rule.
  • the calculated value of the element value of the first sequence corresponding to the other sequence is calculated.
  • one sequence of one sequence pair is sequence C
  • the other sequence is sequence A
  • the first sequence corresponding to the other sequence is sequence B.
  • Sequence A, sequence B and sequence C have the same number of elements.
  • c i be the value of the element with index value i in sequence C
  • a i be the value of the element with index value i in sequence A
  • b i be the value of the element with index value i in sequence B
  • c i The value is a value calculated using the value of a i and the value of b i using the first calculation rule.
  • the first sequence corresponding to another sequence indicates that the first sequence is strongly correlated with another sequence in the sequence pair, for example, if the other sequence is A, the first sequence corresponding to the other sequence The sequence is A1, and if the other sequence is B, the first sequence corresponding to the other sequence is B1.
  • Each of the at least one sequence pair and the first sequence are complex sequences of length greater than one.
  • the network device sends the first signal to the terminal device, and the terminal device receives the first signal, where the first signal may be a signal that is affected by non-ideal factors such as channel, noise, carrier frequency offset (referred to as frequency offset), and the terminal device may Calculating two sequences in each sequence pair according to a target calculation rule, thereby obtaining a third sequence corresponding to another sequence in the sequence pair, the third sequence may be a first sequence passing channel, noise, carrier frequency offset
  • the sequence affected by non-ideal factors, such as frequency offset still retains the characteristics of the first sequence, and the terminal device can perform correlation processing using the first sequence and the third sequence.
  • the above scheme is used to design the sequence in the first signal, which can facilitate the terminal equipment to eliminate the influence of the frequency offset when receiving signals affected by non-ideal factors such as channel, noise, carrier frequency offset (referred to as frequency offset), thereby improving the anti-resistance.
  • the frequency offset performance while eliminating the frequency offset sequence, still retains the characteristics of the first sequence, such as retaining the good autocorrelation property of the first sequence, thereby facilitating the terminal device to accurately determine the timing position.
  • the first sequence corresponding to another sequence may be a complete sequence, such as a complete ZC sequence.
  • the first sequence corresponding to the another sequence may be a subsequence of the second sequence, for example, the second sequence is a complete ZC sequence, and the other sequence of the sequence pair corresponds to the first sequence.
  • a sequence can be a subsequence of the complete ZC sequence.
  • another sequence of each sequence pair corresponds to a first sequence
  • a first sequence corresponding to another sequence of all sequence pairs in the at least one sequence pair constitutes the second sequence.
  • the length of the first sequence corresponding to the other of the different sequence pairs may be the same.
  • the first signal includes M sequence pairs
  • the second sequence includes M sub-sequences
  • one sub-sequence corresponds to one sequence pair
  • the M sub-sequences are M sub-sequences formed by dividing the N elements of the second sequence.
  • Each subsequence includes P elements, where M and N are natural numbers greater than or equal to 2, and P is a natural number greater than or equal to 1.
  • the sequence obtained by the final terminal device is a relatively long sequence, so that the code division capacity can be increased, for example, indicating more cell identifiers.
  • the first calculation rule includes at least one of a multiplication rule, a conjugate multiplication rule, a division rule, and a conjugate division rule.
  • the complexity of the processing of the terminal device in the processing of the two sequences can be reduced by using the first calculation rule described above.
  • another sequence of one sequence pair may be a sequence calculated for N sequences using a second calculation rule, and N is a natural number greater than or equal to 2.
  • the second calculation rule may be the same as or different from the first calculation rule.
  • the other sequence may be a sequence obtained by multiplying all N sequences.
  • each of the N sequences may be a subsequence of the fifth sequence, wherein the fifth sequence may be the same sequence as the second sequence.
  • sequences in a sequence pair may be The sequence carried by the adjacent time domain symbols, for example, the sequence carried by any two adjacent time domain symbols constitutes a sequence pair, that is, one sequence can be in two different sequence pairs. In this way, more sequence pairs can be carried, thereby facilitating the terminal device to accurately determine the timing position.
  • sequence carried by the specific time domain symbol constitutes a sequence pair, for example, the sequence carried by the first time domain symbol and the sequence carried by the second time domain symbol form a sequence pair, the sequence carried by the third time domain symbol and the fourth
  • sequences carried by the time domain symbols constitute a sequence pair, that is, a sequence is only in one sequence pair. This embodiment of the present invention does not limit this.
  • the two sequences in a sequence pair may also be sequences carried by non-adjacent time domain symbols.
  • two sequences of S time-domain symbols in the middle form a sequence pair, and S is a natural number greater than or equal to 1.
  • a sequence can be in two different sequence pairs, the sequence carried by the first time domain symbol and the sequence carried by the third time domain symbol form a sequence pair, the sequence carried by the third time domain symbol and the fifth
  • the sequences carried by the time domain symbols constitute a sequence pair, the sequence carried by the second time domain symbol and the sequence carried by the fourth time domain symbol form a sequence pair, and so on.
  • a sequence is only in one sequence pair, and the sequence carried by the first time domain symbol and the sequence carried by the third time domain symbol form a sequence pair, the sequence carried by the fifth time domain symbol and the seventh
  • the sequences carried by the time domain symbols constitute a sequence pair, the sequence carried by the second time domain symbol and the sequence carried by the fourth time domain symbol form a sequence pair, and so on.
  • the first signal may be used to indicate whether the terminal device has paging scheduling information associated with the terminal device; and/or the first signal may be used to indicate that within a specific time, For example, in a discontinuous reception period (DRX cycle), whether there is downlink control information associated with the terminal device, such as PDCCH scheduling information; and/or, the first signal may be used to indicate whether the system message of the cell in which the terminal device is located is A change occurs; and/or the first signal can be used to indicate a cell identity of a cell in which the terminal device is located.
  • DRX cycle discontinuous reception period
  • PDCCH scheduling information whether there is downlink control information associated with the terminal device, such as PDCCH scheduling information
  • the first signal may be used to indicate whether the system message of the cell in which the terminal device is located is A change occurs; and/or the first signal can be used to indicate a cell identity of a cell in which the terminal device is located.
  • a sequence pair corresponds to a first sequence
  • the first signal may be performed on the terminal device by using a sequence of the first sequence corresponding to another sequence of each sequence pair of the at least one sequence pair in the first signal.
  • indication information please refer to the above description, such as indicating whether there is paging scheduling information associated with the terminal device, and/or indicating the cell identity of the cell in which the terminal device is located, and the like.
  • the order of the first sequence corresponding to another sequence of each sequence pair in the at least one sequence pair indicates the cell identifier of the cell in which the terminal device is located, it needs to be preset.
  • the different order of each first sequence corresponds to a different cell identity, and the terminal device can determine the cell identity of the cell in which it is located.
  • the first sequence corresponding to another sequence of one sequence pair is a subsequence of the second sequence
  • the first sequence corresponding to another sequence of each sequence pair of the at least one sequence pair constitutes the second sequence sequence.
  • the terminal device may be instructed by using a different second sequence that is composed. For specific information, refer to the foregoing description, such as indicating whether there is paging scheduling information associated with the terminal device, and/or indicating that the terminal device is located. The cell identity of the cell, and so on.
  • an embodiment of the present invention provides a signal receiving method, where the method includes: receiving, by a terminal device, a first signal, where the first signal includes at least one sequence pair, and each sequence pair of the at least one sequence pair includes Two sequences, the element values of one of the two sequences being subjected to a first calculation rule for the element values of the other of the two sequences and the element values of the first sequence corresponding to the other sequence Calculated value.
  • the first sequence corresponding to each of the at least one sequence pair and the other sequence of each sequence pair is a complex sequence having a length greater than one.
  • the terminal device calculates an element value of one sequence of two sequences in the sequence pair and an element value of another sequence of the two sequences according to a target calculation rule, and acquires another The third sequence corresponding to the sequence.
  • the third sequence is substantially the same as the first sequence, except that the third sequence is a sequence in which the first sequence is affected by non-ideal factors such as channel, noise, carrier frequency offset (referred to as frequency offset).
  • the terminal device performs the correlation processing by using the first sequence and the third sequence, where the first sequence is a sequence stored locally by the terminal device, and the first sequence is the same as the first sequence carried in the first signal sent by the network device side.
  • the network device performs the design mode described in the first aspect on the sequence in the first signal, which can facilitate the terminal device to eliminate the frequency after receiving the signal affected by non-ideal factors such as channel, noise, carrier frequency offset (referred to as frequency offset).
  • frequency offset carrier frequency offset
  • the partial influence, thereby improving the anti-frequency offset performance, while eliminating the third sequence after the frequency offset still retains the characteristics of the first sequence, such as retaining the good autocorrelation property of the first sequence, thereby facilitating the terminal device to accurately determine the timing position.
  • the target calculation rule corresponds to the first calculation rule, for example, the first calculation rule includes at least one of a multiplication rule, a conjugate multiplication rule, a division rule, and a conjugate division rule
  • the target calculation rule can be: a conjugate multiplication rule.
  • the terminal device multiplies the conjugate sequence of the other sequence in the two sequences by the one of the two sequences, thereby obtaining the third sequence corresponding to the other sequence.
  • the element value of the conjugate sequence of the other sequence is a conjugate complex number of the element values of the other sequence.
  • the terminal device multiplies the conjugate sequence of the one of the two sequences by the other sequence to obtain a third sequence.
  • the first sequence corresponding to another sequence may be a complete sequence, such as a complete ZC sequence, and the terminal device may perform processing when using the first sequence and the third sequence for correlation processing.
  • the first sequence and the third sequence are subjected to a convolution operation or a cyclic convolution operation, and a timing position is determined based on the operation result.
  • the terminal device can obtain multiple short complete sequences, and the terminal device can directly perform related processing, determine the timing position, and reduce the processing complexity of the terminal device.
  • the first sequence corresponding to another sequence may be a subsequence of the second sequence, such as the second sequence being a complete ZC sequence and the first sequence corresponding to another sequence of one sequence pair It may be a subsequence of the complete ZC sequence, the first sequence corresponding to the other sequence of the different sequence pairs, and the first sequence corresponding to the other sequence of all the sequence pairs of the at least one sequence pair constitutes the second sequence.
  • the terminal device When the terminal device performs correlation processing by using the first sequence and the third sequence, it is first necessary to acquire a fourth sequence, where the fourth sequence is a sequence consisting of a third sequence corresponding to another sequence of all sequence pairs, and each sequence is aligned.
  • the third sequence corresponding to the other sequence is strongly correlated with the other sequence.
  • the other sequence corresponding to another sequence of different sequence pairs is different. For example, if another sequence is A, the third sequence corresponding to the other sequence is A2, and if the other sequence is B, the third sequence corresponding to the other sequence is B2.
  • the terminal device performs a convolution operation or a cyclic convolution operation on the second sequence and the fourth sequence, and determines a timing position based on the operation result.
  • the terminal device can obtain a relatively long complete sequence, thereby improving the code division capacity, and having better correlation, and improving the accuracy of determining the timing position of the terminal device.
  • an embodiment of the present invention provides a signal sending apparatus, where the signal sending apparatus has a function of implementing network device behavior in the method of the first aspect.
  • the functions can be implemented by hardware or by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the signal sending apparatus includes: a processing module and a sending module, wherein the processing module is configured to generate a first signal, where the first signal includes at least one sequence pair, where the at least one Each sequence pair of a sequence pair includes two sequences, the element value of one of the two sequences being the first calculation rule for the element value of the other of the two sequences and the other The calculated value of the element value of the first sequence corresponding to the sequence, wherein each of the at least one sequence pair and the first sequence are complex sequences having a length greater than one.
  • the sending module is configured to send the first signal.
  • the signal sending apparatus includes: a transceiver, a memory, and a processor; wherein the transceiver is configured to receive a signal or send a signal. Storing a set of program code in a memory, and the processor is configured to call the program code stored in the memory, and perform the operations of: generating a first signal, wherein the first signal includes at least one sequence pair, each of the at least one sequence pair A sequence pair includes two sequences, and an element value of one of the two sequences is a first value corresponding to the other sequence by using a first calculation rule for an element value of another of the two sequences The calculated value of the element value of the sequence, wherein each of the at least one sequence pair and the first sequence is a complex sequence having a length greater than one; the first signal is transmitted to the terminal device.
  • the principle and the beneficial effects of the device can be referred to the method described in the first aspect and the beneficial effects thereof. Therefore, the implementation of the device can be referred to the implementation of the method, and the repeated description is not repeated.
  • an embodiment of the present invention provides a computer readable storage medium, wherein the computer readable storage medium stores instructions that, when run on a computer, cause the computer to perform the method described in the first aspect above.
  • an embodiment of the present invention provides a computer program product comprising instructions that, when run on a computer, cause the computer to perform the method described in the first aspect above.
  • an embodiment of the present invention provides a signal receiving apparatus, where the signal receiving apparatus has a function of implementing behavior of a terminal device in the method of the second aspect.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the signal receiving apparatus includes: a transceiver unit and a processing unit.
  • the transceiver unit is configured to receive a first signal, where the first signal includes at least one sequence pair, each of the at least one sequence pair includes two sequences, and one of the two sequences
  • An element value is a value calculated by using a first calculation rule for an element value of another one of the two sequences and an element value of a first sequence corresponding to the another sequence; wherein the at least one sequence
  • Each sequence in the pair and the first sequence are complex sequences of length greater than one.
  • the processing unit is configured to calculate an element value of one of the two sequences and an element value of another one of the two sequences according to a target calculation rule, to obtain the corresponding one of the other sequences a third sequence; the processing unit is further configured to acquire a timing position by using the first sequence and the third sequence.
  • the signal receiving apparatus includes: a transceiver, a memory, and a processor; wherein the transceiver is configured to receive a signal or send a signal.
  • a set of program code is stored in the memory, and the processor is configured to call the program code stored in the memory to: receive the first signal, the first signal includes at least one sequence pair, each of the at least one sequence pair A sequence pair includes two sequences, and an element value of one of the two sequences is a first value corresponding to the other sequence by using a first calculation rule for an element value of another of the two sequences a value obtained by calculating an element value of the sequence; wherein each of the at least one sequence pair and the The first sequence is a complex sequence having a length greater than one; calculating an element value of one of the two sequences and an element value of another of the two sequences according to a target calculation rule to obtain the other a third sequence corresponding to a sequence; obtaining the timing position using the first sequence and the third sequence.
  • the principle and the beneficial effects of the device can be referred to the method described in the second aspect and the beneficial effects thereof. Therefore, the implementation of the device can be referred to the implementation of the method, and the repeated description is not repeated.
  • an embodiment of the present invention provides a computer readable storage medium, where the computer readable storage medium stores instructions that, when run on a computer, cause the computer to perform the method described in the second aspect above.
  • an embodiment of the present invention provides a computer program product comprising instructions, which when executed on a computer, cause the computer to perform the method described in the second aspect above.
  • the first signal includes at least one sequence pair, and each sequence pair includes two sequences, and an element value of one of the two sequences is determined by using a first calculation rule in the two sequences.
  • the value of the sequence of another sequence is calculated from the first sequence corresponding to the other sequence. Since the two sequences in a sequence have the above relationship, the terminal device receives the channel, noise, and carrier frequency offset (referred to as frequency).
  • frequency carrier frequency offset
  • the frequency offset effect can be eliminated, thereby improving the frequency offset resistance, and a sequence can still be obtained after eliminating the frequency offset, and the sequence maintains the characteristics of the first sequence, thereby facilitating the terminal device. Accurately determine the timing position.
  • 1a is a schematic diagram of a sequence design of a PSS in LTE
  • Figure 1b is a simulation diagram of a PSS sequence design for LTE
  • Figure 1c is another simulation diagram for the PSS sequence design in LTE
  • FIG. 2 is a system architecture diagram provided by an embodiment of the present invention.
  • FIG. 3a is a schematic diagram of a sequence design of an NPSS in an NB-IoT according to an embodiment of the present invention
  • FIG. 3b is a simulation diagram of NPSS sequence design in the NB-IoT according to an embodiment of the present invention.
  • FIG. 6a is a schematic diagram of simulation provided by an embodiment of the present invention.
  • FIG. 6b is another schematic diagram of simulation provided by an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a signal sending apparatus according to an embodiment of the present invention.
  • FIG. 7b is a schematic structural diagram of another signal sending apparatus according to an embodiment of the present invention.
  • FIG. 7c is a schematic structural diagram of a terminal device according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a signal receiving apparatus according to an embodiment of the present invention.
  • FIG. 8b is a schematic structural diagram of a signal receiving apparatus according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a network device according to an embodiment of the present invention.
  • the sequence pair in the embodiment of the present invention refers to two sequences in the first signal that satisfy a specific condition, and the specific condition may be: in the two sequences, the element values of one sequence are in the two sequences by using the first calculation rule. The value of the element value of another sequence and the element value of the first sequence corresponding to the other sequence.
  • the two sequences may be sequences carried by adjacent time domain symbols, or may be sequences carried by non-adjacent time domain symbols.
  • the first sequence corresponding to the other sequence means that the first sequence is strongly correlated with the other sequence, for example, if another sequence is A, the other sequence is The first sequence corresponding to the sequence is A1, and if the other sequence is B, the first sequence corresponding to the other sequence is B1.
  • Another sequence of one sequence pair corresponds to a first sequence, and the first sequence corresponding to another sequence of different sequence pairs may be different.
  • the complete sequence referred to in the embodiments of the present invention may be: Zadoff-Chu (ZC) sequence, phase control sequence, m sequence, Gold sequence, M sequence, GMW sequence, kasami sequence, Bent sequence, Had code sequence, DFT sequence and many more.
  • ZC Zadoff-Chu
  • the present invention does not limit the sequence type as long as it is a complex sequence whose length is greater than one (the complex sequence means that the sequence elements are plural).
  • it may be a sequence with good autocorrelation or orthogonality.
  • the complete sequence mentioned in the embodiment of the present invention may also be various variant sequences of the above sequence, such as a sequence formed by cyclically shifting the above sequence, or a sequence in which a part of the sequence is truncated, Alternatively, the conjugate sequence of the above sequence, or the sequence in which the sequence is phase-rotated (that is, each element of the sequence is rotated by a given phase), or the sequence in which the plurality of sequences are multiplied, multiplied by a conjugate Subsequent sequence, added sequence, modulo 2 added sequence, and the like.
  • the complete sequence actually used in the present invention may be a sequence in which the above sequence is subjected to a plurality of the above-described modifications. For example, a sequence obtained by multiplying two sequences and performing cyclic shift expansion may be used. ,and many more.
  • the embodiments of the present invention can be applied to an LTE system, and can also be applied to other wireless communication systems, such as a Global System for Mobile Communication (GSM), a Universal Mobile Telecommunications System (UMTS), and code division multiple access. Code Division Multiple Access (CDMA) system, as well as new network systems.
  • GSM Global System for Mobile Communication
  • UMTS Universal Mobile Telecommunications System
  • CDMA Code Division Multiple Access
  • the embodiment of the present invention mainly uses the NB-IoT in the LTE system as an example for illustration.
  • the wireless communication system is usually composed of cells. As shown in FIG. 2, each cell includes a base station (BS), and the base station provides communication services to multiple terminal devices, and the base station is connected to the core network device.
  • the base station includes a baseband unit (BBU) and a remote radio unit (RRU).
  • BBU baseband unit
  • RRU remote radio unit
  • the BBU and the RRU can be placed in different places, for example, the RRU is pulled away, placed in an open area from high traffic, and the BBU is placed in the central computer room.
  • BBUs and RRUs can also be placed in the same room.
  • the BBU and RRU can also be different parts under one rack.
  • a base station is a device deployed in a radio access network to provide a wireless communication function for a terminal device.
  • the base station may include various forms of macro base stations, micro base stations (also referred to as small stations), relay stations, access points, transmission access point (TRP), and the like.
  • TRP transmission access point
  • the name of a device having a base station function may be different, for example, in an LTE system, an evolved Node B (evolved NodeB, eNB or eNodeB), in the third In a 3rd generation (3G) system, it is called a Node B (NB).
  • NB Node B
  • the foregoing provides the terminal device with no
  • the devices of the line communication function are collectively referred to as network devices.
  • the terminal device may be a device that provides voice and/or data connectivity to a user, a handheld device with a wireless connection function, or other processing device connected to a wireless modem.
  • the wireless terminal can communicate with one or more core networks via a Radio Access Network (RAN), which can be a mobile terminal, such as a mobile phone (or "cellular" phone) and a computer with a mobile terminal.
  • RAN Radio Access Network
  • RAN can be a mobile terminal, such as a mobile phone (or "cellular" phone) and a computer with a mobile terminal.
  • RAN Radio Access Network
  • it may be a portable, pocket, handheld, computer built-in or in-vehicle mobile device that exchanges language and/or data with a wireless access network.
  • a wireless terminal may also be called a system, a Subscriber Unit, a Subscriber Station, a Mobile Station, a Mobile, a Remote Station, an Access Point, and a remote terminal.
  • Remote Terminal Access Terminal, User Terminal, User Agent, User Device, or User Equipment.
  • terminal devices are collectively referred to as terminal devices.
  • the signal transmitted by the network device to the terminal device is affected by non-ideal factors such as channel, noise, carrier frequency offset (referred to as frequency offset), there will always be a certain carrier frequency offset, and the carrier frequency offset will cause the signal in the time domain. Continuous phase change.
  • the terminal device needs to perform downlink synchronization processing to determine the timing position.
  • the signal transmitted by the network device includes a sequence for performing synchronization, and the sequence may be a sequence having good autocorrelation characteristics, such as a ZC (Zadoff-Chu) sequence having very good autocorrelation and low Cross-correlation, this performance can be used to generate sequences for synchronization.
  • the sequence due to non-ideal factors such as channel, noise, carrier frequency offset (referred to as frequency offset), the sequence also has a certain carrier frequency offset, which causes the sequence to cause continuous phase changes in the time domain. Therefore, the related characteristics of the sequence may also be degraded or even destroyed.
  • the primary synchronization signal in LTE uses a ZC (Zadoff-Chu) sequence with a root index of 25, 29 or 34 and a length of 63.
  • the frequency offset of this sequence is relatively poor.
  • the sequence has no frequency offset (that is, the sequence received by the terminal device is not frequency offset with respect to the sequence sent by the network device), when the terminal device performs related processing, the correlation peak is relatively obvious, and the timing position is relatively easy to determine.
  • the frequency offset is 18 kHz
  • the related processing is that the terminal device performs a correlation operation on the received sequence and the locally stored sequence, and the sequence stored locally by the terminal device is a clean sequence corresponding to the received sequence, and the clean sequence is the channel, the noise, and the carrier frequency.
  • a sequence of non-ideal factors such as partial (referred to as frequency offset).
  • the current primary synchronization signal of the NB-IoT uses 11 identical ZC sequences with a root index of 5, each ZC sequence has a length of 11, and each ZC sequence is multiplied by 1. Or -1.
  • the sequence in the signal received by the terminal device has a continuous phase change in the time domain relative to the sequence in the signal transmitted by the network device, such as The phase change value is in the sequence of equal differences.
  • the terminal device performs an autocorrelation operation on the adjacent sequence (ie, the conjugate is multiplied by the previous sequence), so that the influence of the frequency offset can be eliminated.
  • an embodiment of the present invention discloses a sequence design method of a signal, where a network device generates a first signal, where the first signal includes at least one sequence pair, and each sequence pair includes two sequences, and the two sequences
  • the element value of one sequence in the sequence is a value calculated by using the first calculation rule to calculate the element value of the other of the two sequences and the element value of the first sequence corresponding to the other sequence.
  • a sequence pair includes two sequences, which may be any one of the sequence pairs carried in the first signal.
  • the embodiment of the present invention refers to one of the two sequences as sequence 2, the other sequence as sequence 3, and the first sequence corresponding to the other sequence is called sequence 1.
  • sequence 1 is strongly correlated with the sequence 3.
  • Another sequence of one sequence pair corresponds to a first sequence in which at least one sequence pair exists, and thus at least one first sequence also exists.
  • the first sequence corresponding to another of the different sequence pairs may be a different sequence.
  • the sequence 3 is a Z1 sequence
  • the sequence 1 corresponding to the sequence 3 is a Z2 sequence
  • the sequence 2 is a sequence calculated by the first calculation rule for the sequence 1 corresponding to the sequence 3, and the first calculation rule is used here.
  • the sequence 2 is Z1 ⁇ Z2
  • the two sequences in the pair are Z1 and Z1 ⁇ Z2. It should be noted that the two sequences are multiplied to obtain a product sequence of the same length as the two sequences, and each element in the obtained product sequence is the product of the corresponding elements in the two sequences.
  • the first sequence corresponding to another sequence in the one sequence pair may be a single complete sequence, such as a ZC sequence, or the first sequence corresponding to another sequence in the one sequence pair may be Is a subsequence of a complete sequence, such as a subsequence of a ZC sequence. It should be noted that, if the first sequence corresponding to another sequence in one sequence pair is a subsequence of one sequence, the other sequence of the at least one sequence pair included in the first signal corresponds to another sequence of each sequence pair.
  • the first sequence constitutes a complete sequence, for example, forming a ZC sequence. That is, the different subsequences of the complete sequence may be the first sequence corresponding to the other of the different sequence pairs.
  • the terminal device can calculate and process two sequences of one sequence pair according to the target calculation rule, thereby obtaining another sequence in the sequence pair.
  • the target calculation rule needs to be determined according to a first calculation rule adopted by the network device.
  • the first calculation rule is at least one of a multiplication rule, a conjugate multiplication rule, a division rule, and a conjugate division rule.
  • the target calculation rule may be two sequences for one sequence pair, and the conjugate sequence of the other sequence is multiplied by one sequence to obtain a third sequence corresponding to the other sequence.
  • the two sequences of the sequence pair are calculated and processed by the target calculation rule, which can improve the anti-frequency offset performance.
  • the third sequence is the same as the first sequence, due to channel, noise, carrier frequency offset (referred to as frequency offset), etc.
  • the fourth sequence may be the sequence of the first sequence affected by non-ideal factors such as channel, noise, carrier frequency offset (referred to as frequency offset).
  • the fourth sequence retains the relevant characteristics of the first sequence.
  • the first sequence is a ZC sequence, and the fourth sequence still retains the good autocorrelation properties of the ZC sequence. Therefore, when the first sequence and the third sequence are used for correlation processing, significant correlation peaks can still appear, which is convenient for the terminal device to accurately determine the timing position.
  • FIG. 4 is an interaction diagram of a signal processing method according to an embodiment of the present invention. As shown in the figure, the present invention is shown.
  • the signal processing method of the embodiment includes but is not limited to the following steps:
  • the network device generates a first signal, where the first signal includes at least one sequence pair, each of the at least one sequence pair includes two sequences, and an element value of one of the two sequences is Calculating, by a first calculation rule, a value obtained by calculating an element value of another one of the two sequences and an element value of the first sequence corresponding to the another sequence, wherein each of the at least one sequence pair
  • the sequences and the first sequence are complex sequences of length greater than one.
  • the network device generates a first signal.
  • the first signal includes at least one sequence pair, and two sequences of one sequence pair satisfy a condition: an element value of one sequence is an element value of another sequence of the two sequences using the first calculation rule and the other The calculated value of the element value of the first sequence corresponding to the sequence.
  • the first sequence corresponding to the another sequence is strongly correlated with the other sequence. For example, if another sequence is an A sequence, the first sequence corresponding to the other sequence is the A1 sequence, and the other The sequence is a B sequence, and the first sequence corresponding to the other sequence is a B1 sequence.
  • the other sequence of the different sequence pairs may be different, and the first sequence corresponding to the other sequence may also be different.
  • the embodiment of the present invention refers to one of the two sequences of one sequence pair as sequence 2, the other sequence as sequence 3, and the first sequence corresponding to the other sequence is called sequence 1.
  • sequence 3 is a Z1 sequence
  • the first sequence corresponding to the sequence 3 ie, the sequence 1
  • the sequence 2 is a sequence calculated by using the first calculation rule for the first sequence corresponding to the sequence 3 and the sequence 3.
  • the two sequences of each sequence pair in the at least one sequence pair included in the first signal satisfy the above conditions, except that the two sequences of different sequence pairs may not be identical.
  • the first sequence corresponding to another of the different sequence pairs may also be a different sequence.
  • the first calculation rule may include at least one of a multiplication rule, a conjugate multiplication rule, a division rule, and a conjugate division rule.
  • the sequence pair 2 and the sequence 3 are continued as an example.
  • the sequence 3 is a Z1 sequence
  • the first sequence corresponding to the sequence 3 ie, the sequence 1 is a Z2 sequence.
  • Sequence 2 is Z1 x Z2.
  • sequence 2 may be Z1 * ⁇ Z2 or sequence 2 may be Z1 ⁇ Z2 * .
  • the first calculation rule is a division rule, the sequence 2 may be Z1/Z2.
  • sequence 2 may be Z1 * /Z2, or sequence 2 may be Z1/Z2 * .
  • sequence Z * is a conjugate sequence of the sequence Z, that is, the value of each element in the sequence Z * is the conjugate complex number of the corresponding element in the sequence Z.
  • sequence 3 and the sequence 1 by using the first calculation rule may be performed by performing the registration calculation on the element value included in the sequence 3 and the element value included in the sequence 1.
  • sequence 3 is a 1 , a 2 ,..., a n
  • sequence 1 is b 1 , b 2 ,..., b n
  • the calculated sequence 2 is c 1 , c 2 ,...,c n
  • for each element value c i in sequence 2 is the value obtained by processing the a i and b i using the first calculation rule.
  • the first sequence corresponding to another sequence in one sequence pair may be a complete sequence, such as a ZC sequence, or the first sequence corresponding to another sequence in one sequence pair is a subsequence of the second sequence.
  • the second sequence is a complete ZC sequence
  • the first sequence corresponding to another sequence of one sequence pair is only one subsequence in the complete ZC sequence
  • the other sequence of the first sequence of the first signal is another sequence.
  • a corresponding first sequence constitutes the second sequence. It should be noted that the element included in the subsequence is a part of the complete sequence corresponding to the subsequence. Minute.
  • the second sequence includes N elements, and the N elements may be divided into M sub-sequences, each sub-sequence includes P elements, wherein the M is a natural number greater than or equal to 2, and the P is greater than or equal to 1 Natural number.
  • Each of the M subsequences is a first sequence corresponding to another sequence of one sequence pair.
  • the second sequence includes three sub-sequences, namely P1, P2, and P3.
  • the first signal includes three sequence pairs, which are sequence pair 1, sequence pair 2, and sequence pair 3, respectively, and then the first sequence corresponding to another sequence in sequence pair 1 is P1, and the other pair in sequence pair 2
  • the first sequence corresponding to the sequence is P2, and the first sequence corresponding to the other sequence of the sequence pair 3 is P3.
  • the N elements when dividing the sub-sequence, if the N elements are not equally divided, the N elements may be divided into M sub-sequences by cyclic shift. For example, if N is 5 and needs to be divided into 2 subsequences, the last two elements and the first element of the sequence can be divided into a subsequence. If the subsequence is divided in this way, M*P is Greater than N.
  • the second sequence formed is the deformed sequence of the ZC sequence, that is, the second sequence is a sequence formed by cyclic shift of the ZC sequence.
  • the truncation may be adopted to divide the N elements into M sub-sequences. For example, if N is 7, and two sub-sequences need to be divided, the last element of the sequence can be discarded, and the remaining elements are divided into two sub-sequences. If the sub-sequence is divided in this way, M*P is smaller than N. .
  • the second sequence formed is the deformed sequence of the ZC sequence, that is, the second sequence is a sequence formed by the ZC sequence truncating a part of the elements.
  • another sequence in a sequence pair may be a sequence, such as a ZC sequence or a subsequence of a ZC sequence, or a complex number, which may be 1 or otherwise.
  • the other sequence of one sequence pair may also be a sequence calculated by using the second calculation rule for N sequences, where N is a natural number greater than or equal to 2.
  • the second calculation rule may be the same as or different from the first calculation rule.
  • sequence pair including sequence 2 and sequence 3
  • sequence 2 is one of two sequences of one sequence pair
  • sequence 3 is another of the two sequences of the sequence pair.
  • the second calculation rule is, for example, a multiplication rule
  • the sequence 3 may be a sequence obtained by multiplying two sequences, for example, the sequence 3 is Z1 ⁇ Z2, the first sequence corresponding to the sequence 3 may be Z3, and the sequence 2 is Z1 ⁇ Z2. ⁇ Z3.
  • Z1, Z2 and Z3 may all be ZC sequences.
  • Z1, Z2 and Z3 may both be subsequences of the second sequence, for example, Z1, Z2 and Z3 may each be a subsequence of a ZC sequence.
  • the two sequences in one sequence pair may be a sequence carried by adjacent time domain symbols, or may be a sequence carried by non-adjacent time domain symbols.
  • the same sequence may be in two sequence pairs at the same time.
  • the sequence carried by any adjacent time domain symbols constitutes a sequence pair. It should be noted that the last sequence may exist only in one sequence pair. Alternatively, any one of the sequences may be in only one sequence pair, that is, the total number of sequences is an even number N, and the number of sequence pairs is N/2.
  • 5a-5d are several alternative sequence design manners provided by the embodiment of the present invention. It should be noted that the embodiment of the present invention carries a sequence with a time domain symbol as an example. It can be understood that The multiple time domain symbols carry one sequence, or one time domain symbol carries multiple sequences, which is not limited by the embodiment of the present invention. In addition, the embodiment of the present invention does not limit the existence form of the sequence carried in each time domain symbol in FIG. 5a-5d, and the sequence existing form in 5a-5d is only an example.
  • the sequences C, C1, C2, C3, and C4 in Figures 5a-5d may be arbitrarily complex sequences, and the elements in the sequence may be the same or different.
  • the two sequences of a sequence pair are sequences carried by adjacent time domain symbols.
  • the same sequence can be in two different sequence pairs, but the first sequence and the last A sequence is only in one sequence pair. That is, the sequences carried by any two adjacent time domain symbols in Figure 5a constitute a sequence pair.
  • the sequence Z1*Z2 carried by the third time domain symbol and the sequence Z1 carried by the adjacent time domain symbol form a sequence pair
  • the sequence Z1*Z2 carried by the third time domain symbol and the adjacent time domain symbol are carried.
  • the sequence Z1*Z2*Z3 also constitutes a sequence pair.
  • the sequence level difference is used in FIG. 5a, that is, the sequence carried by the latter time domain symbol is a sequence obtained by multiplying a sequence carried by the previous time domain symbol by a first sequence.
  • the different sequences correspond to the corresponding first sequence. That is, the first sequence in the sequence pair corresponds to the sequence carried in the previous time domain symbol in the sequence pair.
  • sequences Z1, Z2, Z3, Z4...Zn-1 in Figure 5a may all be a complete sequence, or the sequences Z1, Z2, Z3, Z4...Zn-1 may all be one complete.
  • a subsequence of the sequence i.e., the complete sequence includes n-1 subsequences, and the n-1 subsequences may constitute the complete sequence. That is, the sequences Z1, Z2, Z3, Z4...Zn-1 constitute a complete sequence, and it should be noted that the complete sequence herein may be a ZC sequence, or may be various deformation sequences of the ZC sequence, and no longer Narration. It is to be understood that the sequence in FIG. 5a may not be limited to the ZC sequence, which is not limited by the embodiment of the present invention.
  • the same sequence may be in only one sequence pair, but the two sequences of one sequence pair are carried by adjacent time domain symbols.
  • the sequence carried by the first time domain symbol and the second time domain symbol constitutes a sequence pair
  • the sequence carried by the third time domain symbol and the sequence carried by the fourth time domain symbol form a sequence pair, and so on.
  • the sequence carried by the latter time domain symbol is a sequence carried by the previous time domain symbol and multiplied by the first sequence corresponding to the sequence carried by the previous time domain symbol.
  • the resulting sequence It can be seen from the figure that the sequence carried by the previous time domain symbol is different, and the first sequence corresponding to the sequence carried by the previous time domain symbol may be different.
  • sequences Z1, Z2, Z3, Z4...Zn-1 in Figure 5b may all be a complete sequence, or the sequences Z1, Z2, Z3, Z4...Zn-1 may all be one complete.
  • a subsequence of the sequence i.e., the complete sequence includes n-1 subsequences, and the n-1 subsequences may constitute the complete sequence. That is, the sequences Z1, Z2, Z3, Z4...Zn-1 constitute a complete sequence, and it should be noted that the complete sequence herein may be a ZC sequence, or may be various deformation sequences of the ZC sequence, and no longer Narration. It is to be understood that the sequence in FIG. 5b is not limited to the ZC sequence, which is not limited by the embodiment of the present invention.
  • the two sequences of a sequence pair may be sequences carried by non-adjacent time domain symbols.
  • the number of the four sequences of the four time-domain symbols is taken as an example. It can be understood that the number of the sequences is not limited.
  • the same sequence can be in two different sequence pairs, one sequence of two sequences separated by one sequence.
  • the first sequence, the second sequence, the last sequence, and the penultimate sequence are in one sequence pair.
  • Any sequence carried by any time domain symbol in Figure 5c constitutes a sequence pair.
  • the different sequences correspond to the corresponding first sequence. That is, the first sequence in the sequence pair corresponds to the sequence carried in the preceding time domain symbol in the sequence pair.
  • sequences Z1, Z2, Z3, Z4...Z12 in Figure 5c may all be a complete sequence, or the sequences Z1, Z2, Z3, Z4...Z12 may all be subsequences of a complete sequence. That is, the complete sequence includes 12 subsequences, and the 12 subsequences can constitute the complete sequence. That is, the sequences Z1, Z2, Z3, Z4...Z12 constitute a complete sequence, and it should be noted that the complete sequence herein may be a ZC sequence, or may be various variants of the ZC sequence. The sequence will not be described here. It is to be understood that the sequence in FIG. 5c is not limited to the ZC sequence, which is not limited by the embodiment of the present invention.
  • the same sequence may be in only one sequence pair, or the same sequence may be in two different sequence pairs, and the two sequences of one sequence pair are separated by three time domain symbols.
  • the sequence carried by the first time domain symbol and the fifth time domain symbol constitutes a sequence pair
  • the sequence carried by the second time domain symbol and the sequence carried by the sixth time domain symbol form a sequence pair, and so on.
  • the sequence in which the subsequent time domain symbols are carried is the sequence carried by the time-order symbol in the preceding order and the sequence carried in the time-domain symbol in the previous order.
  • the first sequence is multiplied by the resulting sequence. It can be seen from the figure that the sequence of the preceding time domain symbols is different, and the corresponding first sequence is also different.
  • sequences Z1, Z2, Z3, Z4...Z10 in Figure 5d may all be a complete sequence, or the sequences Z1, Z2, Z3, Z4...Z10 may all be subsequences of a complete sequence. That is, the complete sequence includes 10 subsequences, and the 4 subsequences can constitute the complete sequence. That is, the sequence Z1, Z2, Z3, Z4, ..., Z10 constitute a complete sequence.
  • the complete sequence herein may be a ZC sequence, or may be a variety of variant sequences of the ZC sequence, and details are not described herein again. It is to be understood that the sequence in FIG. 5d is not limited to the ZC sequence, which is not limited by the embodiment of the present invention.
  • the network device sends the first signal.
  • the network device sends the first signal to the terminal device.
  • the first signal may be used to indicate whether there is paging scheduling information associated with the terminal device; and/or the first signal It can be used to indicate whether there is downlink control information associated with the terminal device, such as PDCCH scheduling information, within a specific time period, such as a discontinuous reception period (DRX cycle); and/or, the first signal can be used. And indicating whether the system message of the cell where the terminal device is located is changed; and/or the first signal may be used to indicate a cell identifier of a cell where the terminal device is located.
  • DRX cycle discontinuous reception period
  • the sequence of the first sequence corresponding to the other sequence of the plurality of sequence pairs may be in the first signal.
  • the sequence of the first sequence corresponding to the other sequence of the plurality of sequence pairs may be in the first signal.
  • the order of the first sequence corresponding to another sequence of each sequence pair in the at least one sequence pair indicates the cell identifier of the cell in which the terminal device is located, it needs to be preset.
  • the different order of each first sequence corresponds to a different cell identity, and the terminal device can determine the cell identity of the cell in which it is located.
  • the first sequence corresponding to another sequence of one sequence pair is a subsequence of the second sequence
  • the first sequence corresponding to another sequence of each sequence pair of the at least one sequence pair constitutes the second sequence sequence.
  • the terminal device may be instructed by using a different second sequence that is composed. For specific information, refer to the foregoing description, such as indicating whether there is paging scheduling information associated with the terminal device, and/or indicating that the terminal device is located. The cell identity of the cell, and so on.
  • the second sequence is a ZC sequence or various variant sequences of the ZC sequence, the root indices of the different ZC sequences are different.
  • the terminal device receives the first signal.
  • the first signal received by the terminal device may be the first signal sent by the network device.
  • Non-ideal factors such as channel, noise, carrier frequency offset (referred to as frequency offset) and other non-ideal factors, channel, noise, carrier frequency offset (referred to as frequency offset) and other non-ideal factors will cause the first signal to exist continuously in the time domain. Phase change.
  • the embodiments of the present invention are not limited in many ways.
  • the terminal device calculates, according to a target calculation rule, an element value of one of two sequences included in the first signal and an element value of another one of the two sequences, to obtain the The third sequence corresponding to another sequence.
  • the terminal device processes the two sequences of any one of the received first signals according to the target calculation rule: the element values of one of the two sequences and another sequence
  • the element value is calculated to obtain a third sequence corresponding to the other sequence.
  • the third sequence is the same as the first sequence, because there are channels, noise, carrier frequency offset (referred to as frequency offset), etc.
  • the ideal factor affects, so the third sequence is the sequence of the first sequence affected by non-ideal factors such as channel, noise, carrier frequency offset (referred to as frequency offset).
  • the target calculation rule needs to be determined according to the first calculation rule in step S10.
  • the first calculation rule includes at least one of a multiplication rule, a conjugate multiplication rule, a division rule, and a conjugate division rule.
  • the target calculation rule can be: a conjugate multiplication rule. For example, multiplying the conjugate sequence of the other of the two sequences by one of the two sequences to obtain a third sequence corresponding to the other sequence; it can be understood that One of the two sequences is divided by the other.
  • the terminal device may multiply the conjugate sequence of the one of the two sequences by the another sequence to obtain a third sequence. This third sequence preserves the characteristics of the first sequence.
  • one of the sequence pairs obtained by the first calculation rule in step S10 is Z1 ⁇ Z2, and the other sequence is Z1.
  • the target calculation rule may be Z1 * ⁇ (Z1 ⁇ Z2), finally obtain the sequence Z2, due to the non-ideal factors such as channel, noise, carrier frequency offset (referred to as frequency offset)
  • the third sequence is the sequence Z2 through the channel, noise, carrier frequency offset (referred to as frequency offset)
  • the sequence after the ideal factor For example, the third sequence has a fixed phase difference with the sequence Z2, and the third sequence still retains the characteristics of the Z2 sequence. For example, if the Z2 sequence is a ZC sequence, the third sequence still has good autocorrelation properties.
  • the terminal device acquires a timing position by using the first sequence and the third sequence.
  • the terminal device acquires the timing location using the first sequence and the third sequence stored locally.
  • the terminal device acquires the timing position by a convolution operation or a cyclic convolution operation by using the first sequence and the third sequence stored locally.
  • the first sequence may be a complete sequence
  • the third sequence obtained by the terminal device by using the target calculation rule is also a complete sequence
  • the first signal includes multiple sequence pairs, and multiple complete sequences may be obtained.
  • the terminal device can obtain multiple short ZC sequences.
  • the terminal device When performing the related processing, the terminal device performs correlation processing on the plurality of short ZC sequences obtained by the processing and the corresponding plurality of ZC sequences stored locally, thereby determining the timing position.
  • the sequences Z1, Z2, Z3, Z4...Zn-1 are all ZC sequences.
  • the simulation diagram of the correlation is shown in FIG. 6a.
  • the simulation curve corresponding to the sequence design mode of FIG. 5a corresponds to the sequence design mode of the NB-IoT of FIG. 3a.
  • the simulation curve, the correlation peak is more obvious, and it is convenient for the terminal device to determine the timing position.
  • the Z sequence in Fig. 6a is the above sequence Z1, Z2, Z3, Z4...Zn-1.
  • the first sequence may be a subsequence of a complete sequence (such as the second sequence), and the third sequence obtained by the terminal device by using the target calculation rule is also a subsequence of the fourth sequence.
  • the first signal includes a plurality of sequence pairs, and the two sequences of all sequence pairs are processed to obtain a plurality of third sequences, the plurality of third sequences are sub-sequences of the fourth sequence, and the plurality of third sequences are The fourth sequence is composed.
  • the terminal device When performing the related processing, the terminal device performs correlation processing on the obtained fourth sequence and the locally stored second sequence, thereby determining the timing position.
  • the sequences Z1, Z2, Z3, Z4...Zn-1 are all subsequences of a ZC sequence. That is, Z1, Z2, Z3, Z4...Zn-1 constitute the ZC sequence.
  • the simulation diagram of the correlation is shown in Figure 6b. It can be seen from Fig. 6b that the simulation curve corresponding to the sequence design mode of Fig. 5a is more obvious than the simulation curve corresponding to the sequence design mode of the NB-IoT of Fig. 3a, and the correlation peak is more obvious, which is convenient for the terminal device to determine the timing position.
  • the Z sequence in Fig. 6b is the above sequence Z1, Z2, Z3, Z4...Zn-1.
  • the first signal may be used to indicate whether there is paging scheduling information associated with the terminal device; and/or, and/or, within a specific time, such as a discontinuous reception cycle (DRX cycle) Whether there is downlink control information associated with the terminal device, such as PDCCH scheduling information; and/or whether a system message of a cell in which the terminal device is located is changed; and/or a cell identifier of a cell in which the terminal device is located.
  • DRX cycle discontinuous reception cycle
  • the terminal device may monitor the paging paging scheduling information on the PO; if the terminal device determines that the terminal device does not exist by using the first signal, The paging scheduling information, the terminal device may not listen to the information to save power consumption.
  • the terminal device may determine, by using the first information, a cell identifier of a cell where the terminal device is located, so that the signal may be further utilized for downlink measurement.
  • the first signal includes at least one sequence pair, and each sequence pair includes two sequences, and an element value of one of the two sequences is determined by using a first calculation rule in the two sequences.
  • the value of the sequence of another sequence is calculated from the first sequence corresponding to the other sequence. Since the two sequences in a sequence have the above relationship, the terminal device receives the channel, noise, and carrier frequency offset (referred to as frequency).
  • the target calculation rule can be used to calculate one sequence and the other sequence in the sequence pair, thereby eliminating the frequency offset effect, improving the anti-frequency offset performance, and eliminating the frequency offset.
  • a fourth sequence can still be obtained, which preserves the characteristics of the first sequence, thereby facilitating the terminal device to accurately determine the timing position.
  • FIG. 7a is a schematic diagram of a signal sending apparatus according to an embodiment of the present disclosure.
  • the signal sending apparatus may be a network device 10, or may be a chip or a circuit, such as a network device. Chip or circuit inside.
  • the network device 10 corresponds to a network device in the above method.
  • the signal transmitting apparatus may include a processing module 00 and a transmitting module 01; wherein:
  • the processing module 00 is configured to perform corresponding processing described in the foregoing method on the first signal to be sent by the sending module 01, and send the first signal by using the sending module 01.
  • the sending module 01 can be implemented by using the transceiver 140 in FIG. 7b, and the processing module 00 can be implemented by using the processor 110, or can be implemented by using the processor 110 and the memory 120.
  • the processing module 00 is configured to generate a first signal, where the first signal includes at least one sequence pair, each of the at least one sequence pair includes two sequences, and one of the two sequences
  • the element value is a value calculated by using a first calculation rule for an element value of another one of the two sequences and an element value of the first sequence corresponding to the another sequence, wherein the at least one Each sequence in the sequence pair and the first sequence are complex sequences of length greater than one.
  • the sending module 01 is configured to send the first signal generated by the processing module to the terminal device.
  • the first sequence corresponding to the another sequence is a subsequence of the second sequence.
  • the first calculation rule includes at least one of a multiplication rule, a conjugate multiplication rule, a division rule, and a conjugate division rule.
  • the other sequence is a sequence calculated for N sequences using a second calculation rule, and the N is a natural number greater than or equal to 2.
  • the one of the two sequences in the sequence pair and the other sequence are sequences carried by adjacent time domain symbols.
  • the first signal is used to indicate whether the terminal device has paging scheduling information associated with the terminal device, and/or the first signal is used to indicate a cell identifier of a cell where the terminal device is located.
  • FIG. 7b is a schematic structural diagram of another signal sending apparatus according to an embodiment of the present invention.
  • the signal sending apparatus may include: a processor 110 and a memory 120.
  • the memory 120 is configured to store instructions for executing the instructions stored by the memory 120 to cause the signal transmitting apparatus to implement the method corresponding to the network device side as shown in FIG.
  • the signal transmitting apparatus may further include a transceiver 140, wherein the processor 110 is configured to execute an instruction stored by the memory 110 to control the transceiver 140 to receive a signal, or control the transceiver 140 to send a signal to complete the network device in the foregoing method. Side steps.
  • the transceiver 140 can include a receiver and a transmitter, where the receiver and the transmitter can be the same or different physical entities. When the receiver and the transmitter are the same physical entity, they may be collectively referred to as the transceiver 140.
  • the memory 110 may be integrated in the processor 110 or may be provided separately from the processor 110.
  • the function of the transceiver 240 can be implemented by a dedicated chip through a transceiver circuit or a transceiver.
  • the processor 210 can be implemented by a dedicated processing chip, a processing circuit, a processor, or a general purpose chip.
  • a network device provided by an embodiment of the present application may be implemented by using a general-purpose computer.
  • the program code that is to implement the functions of the processor 210, the receiver 240 and the transmitter 250 is stored in a memory, and the general purpose processor implements the functions of the processor 210, the receiver 240, and the transmitter 250 by executing code in the memory.
  • FIG. 7 is a schematic structural diagram of a network device according to an embodiment of the present application, which may be a schematic structural diagram of a base station.
  • the base station 10 includes one or more radio frequency units, such as a remote radio unit (RRU) 101 and one or more baseband units (BBUs) (also referred to as digital units, DUs) 102.
  • RRU 101 may be referred to as a transceiver unit, a transceiver, a transceiver circuit, or a transceiver, etc., which may include at least one antenna 1011 and a radio frequency unit 1012.
  • the RRU101 part It is mainly used for transmitting and receiving radio frequency signals and converting radio frequency signals and baseband signals, for example, for transmitting the first signals described in the above embodiments to the terminal device.
  • the BBU 102 part is mainly used for performing baseband processing, controlling a base station, and the like.
  • the RRU 101 and the BBU 102 may be physically disposed together or physically separated, that is, distributed base stations.
  • the BBU 102 is a control center of a base station, and may also be referred to as a processing unit or a processing module, and is mainly used to perform baseband processing functions such as channel coding, multiplexing, modulation, spreading, and the like.
  • the BBU processing unit
  • the BBU can be used to control the base station to perform an operation procedure about the network device in the foregoing method embodiment.
  • the BBU 102 may be configured by one or more boards, and multiple boards may jointly support a single access standard radio access network (such as an LTE network), or may separately support different access technologies. Access Network.
  • the BBU 102 also includes a memory 1021 and a processor 1022.
  • the memory 1021 is used to store the necessary sequences.
  • the memory 1021 stores a sequence or the like for generating a first signal in the above embodiment.
  • the processor 1022 is configured to control a base station to perform necessary operations, for example, to control a base station to perform an operation procedure of the network device in the foregoing method embodiment.
  • the memory 1021 and the processor 1022 can serve one or more boards. That is, the memory and processor can be individually set on each board. It is also possible that multiple boards share the same memory and processor. In addition, the necessary circuits can be set on each board.
  • FIG. 8 is a schematic structural diagram of a signal receiving apparatus according to an embodiment of the present invention.
  • the signal receiving apparatus may be a terminal device, or may be a chip or a circuit, such as a chip or a circuit that can be disposed in a terminal device.
  • the terminal device may correspond to the terminal device in the above method.
  • the device may include a receiving module 02 and a processing module 03; wherein:
  • the receiving module 02 is configured to receive a first signal sent by the network device.
  • the processing module 03 can be configured to perform the corresponding processing described in the foregoing method on the first signal received by the receiving module 02.
  • the receiving module 02 can be implemented by using the transceiver 240 in FIG. 8b, and the processing module 03 can be implemented by using the processor 210, or can be implemented by using the processor 210 and the memory 220.
  • the receiving module 02 is configured to receive a first signal, where the first signal includes at least one sequence pair, each sequence pair of the at least one sequence pair includes two sequences, and one of the two sequences
  • the element value is a value calculated by using a first calculation rule for an element value of another one of the two sequences and an element value of the first sequence corresponding to the another sequence; wherein the at least one Each sequence in the sequence pair and the first sequence are complex sequences having a length greater than one;
  • the processing module 03 is configured to calculate, according to the target calculation rule, an element value of one of the two sequences received by the receiving module 02 and an element value of another one of the two sequences, to obtain the other A third sequence corresponding to a sequence, and obtaining a timing position using the first sequence and the third sequence.
  • FIG. 8b is a schematic structural diagram of another signal receiving apparatus according to an embodiment of the present invention.
  • the signal receiving apparatus may include a processor 210 and a memory 220.
  • the memory 220 is used to store instructions for executing the instructions stored in the memory 220 to implement the steps in the terminal device side corresponding method of FIG. 4 above.
  • the signal receiving device may further include a transceiver 240.
  • the processor 210 is configured to execute the memory 220
  • the stored instructions are used to control the transceiver 240 to receive signals, or to control the transceiver 240 to transmit signals to perform the steps on the terminal device side of the above method.
  • the transceiver 240 can include a receiver and a transmitter, and the receiver and the transmitter can be the same or different physical entities. When the receiver 240 and the transmitter 250 are the same physical entity, they may be collectively referred to as the transceiver 240.
  • the memory 220 may be integrated in the processor 210 or may be provided separately from the processor 210.
  • the function of the transceiver 240 can be implemented by a dedicated chip through a transceiver circuit or a transceiver.
  • the processor 210 can be implemented by a dedicated processing chip, a processing circuit, a processor, or a general purpose chip.
  • the terminal device provided by the embodiment of the present application may be implemented by using a general-purpose computer.
  • the program code of the transceiver function is stored in a memory, and the general purpose processor implements the functions of the processor 210, the transceiver 240 by executing code in the memory.
  • FIG. 8c is a schematic structural diagram of a terminal device provided by the present application.
  • the terminal device can be adapted for use in the system shown in FIG. 2.
  • Fig. 8c shows only the main components of the terminal device.
  • the terminal device 10 includes a processor, a memory, a control circuit, an antenna, and an input and output device.
  • the processor is mainly used for processing the received signal, and controlling the entire terminal device, executing a software program, and processing data of the software program, for example, for supporting the terminal device to perform the actions described in the foregoing signal receiving method embodiment.
  • the memory is primarily used to store software programs and data, such as to store the sequences described in the above embodiments.
  • the control circuit is mainly used for converting baseband signals and radio frequency signals and processing radio frequency signals.
  • the control circuit together with the antenna can also be called a transceiver, and is mainly used for transmitting and receiving RF signals in the form of electromagnetic waves.
  • Input and output devices such as touch screens, display screens, keyboards, etc., are primarily used to receive user input data and output data to the user.
  • the processor can read the software program in the storage unit, interpret and execute the instructions of the software program, and process the data of the software program.
  • the processor performs baseband processing on the data to be sent, and then outputs the baseband signal to the radio frequency circuit.
  • the radio frequency circuit performs radio frequency processing on the baseband signal, and then sends the radio frequency signal to the outside through the antenna in the form of electromagnetic waves.
  • the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor, which converts the baseband signal into data and processes the data.
  • Figure 8c shows only one memory and processor for ease of illustration. In an actual terminal device, there may be multiple processors and memories.
  • the memory may also be referred to as a storage medium or a storage device, and the like.
  • the processor may include a baseband processor and a central processing unit, and the baseband processor is mainly used to process the communication protocol and the communication data, and the central processing unit is mainly used to control and execute the entire terminal device.
  • the processor in Figure 8c integrates the functions of the baseband processor and the central processing unit.
  • the baseband processor and the central processing unit can also be separate processors.
  • the terminal device may include multiple baseband processors to accommodate different network standards, and the terminal device may include multiple central processors to enhance its processing capabilities.
  • the baseband processor can also be expressed as a baseband processing circuit or a baseband processing chip.
  • the central processing unit can also be expressed as a central processing circuit or a central processing chip.
  • the functions of processing the communication protocol and the communication data may be built in the processor, or may be stored in the storage unit in the form of a software program, and the processor executes the software program to implement the baseband processing function.
  • the antenna and control circuit having the transceiving function can be regarded as the receiving module 201 of the terminal device 20, and the processor having the processing function can be regarded as the processing module 202 of the terminal device 20.
  • the embodiment of the present application further provides a communication system, including the foregoing network device and at least one of the foregoing terminal devices.
  • the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSPs), and application specific integrated circuits (ASICs). , off-the-shelf programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the memory can include read only memory and random access memory and provides instructions and data to the processor.
  • a portion of the memory may also include a non-volatile random access memory.
  • each step of the above method may be completed by an integrated logic circuit of hardware in a processor or an instruction in a form of software.
  • the steps of the method disclosed in the embodiments of the present application may be directly implemented by the hardware processor, or may be performed by a combination of hardware and software modules in the processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory, and the processor reads the information in the memory and combines the hardware to complete the steps of the above method. To avoid repetition, it will not be described in detail here.
  • the size of the serial numbers of the above processes does not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not be taken to the embodiments of the present invention.
  • the implementation process constitutes any limitation.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above embodiments it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof.
  • software it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present invention are generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be from a website site, computer, server or data center Transfer to another website site, computer, server, or data center by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL), or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer readable storage medium can be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that includes one or more available media.
  • the usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (such as a solid state disk (SSD)).

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Abstract

本发明实施例公开一种信号发送方法、接收方法及装置，其中，信号发送方法包括：网络设备生成第一信号，所述第一信号中包括至少一个序列对，所述至少一个序列对中每个序列对包括两个序列，所述两个序列中的一个序列的元素值为采用第一计算规则对所述两个序列中的另一个序列的元素值与所述另一个序列所对应的第一序列的元素值进行计算得到的值，其中，所述至少一个序列对中每个序列以及所述第一序列为长度大于1的复数序列；所述网络设备向终端设备发送所述第一信号。采用本发明实施例，不仅可以抗频偏，并且还可以方便终端设备准确的确定定时位置。

Description

信号发送方法、接收方法及装置 技术领域
本发明涉及通信技术领域，尤其涉及一种信号发送方法、接收方法及装置。
背景技术
在有着低成本、覆盖增强等需求的通信系统中，比如窄带物联网(Narrow Band Internet of Things，NB-IoT)，终端在进行下行同步处理时，通常会面临着晶振误差大(通常是由成本低导致的)的问题。晶振误差大意味着接收信号相对于发送信号会存在较大的载波频偏，对于信号中的序列，频域上的载波频偏会导致该序列在时域上连续的相位变化。时域上的相位变化将会导致该序列的相关特性下降甚至被破坏。一旦该序列的相关特性下降甚至被破坏，接收端在相关处理过程中，将会导致相关峰消失，无法确定定时位置。相关处理即是接收端将接收序列与本地序列进行卷积运算，本地序列为无任何信道或者噪声影响的序列。
比如，如图1a所示，长期演进(Long Term Evolution，LTE)中的主同步信号用的是一个根指数为25、29或34的ZC(Zadoff-Chu)序列，长度为63。ZC序列是一个具有良好自相关特性的序列，通常被用来作为同步序列。若在NB-IoT系统中直接采用LTE中的序列设计方式(即一个ZC序列)，则抗频偏性能较差。如图1b所示，若该序列没有频偏(即接收端的接收序列相对于发送序列没有频偏)，接收端在进行相关处理时，相关峰比较明显；如图1c所示，但若该序列存在频偏(即接收端的接收序列相对于发送序列存在频偏)，比如频偏为18kHz，接收端在进行相关处理时，相关峰完全消失了。
发明内容
本发明实施例提供了一种信号发送方法、接收方法及装置，可以抗频偏，且准确的确定定时位置。
第一方面，本发明实施例提供一种信号发送方法，该信号发送方法包括：网络设备生成第一信号，该第一信号中包括至少一个序列对，一个序列对中包括两个序列，可选的，按照第一信号中携带序列的时域符号顺序，将第一信号中的序列进行排列。一个序列对中的两个序列可以是相邻序列，也可以是非相邻序列，比如，中间相隔S个序列的两个序列构成一个序列对，S为大于或者等于1的自然数。可选的，一个或者多个时域符号携带一个序列。
可选的，一个序列可以同时存在于两个序列对中，比如任意两个相邻序列构成一个序列对，或者，一个序列仅仅存在于一个序列对中。
对于上述至少一个序列对中任意一个序列对的两个序列，该两个序列满足的条件是：一个序列的元素值为采用第一计算规则对该两个序列中的另一个序列的元素值与所述另一个序列所对应的第一序列的元素值进行计算得到的值。比如，一个序列对的一个序列为序列C，另一个序列为序列A，该另一个序列所对应的第一序列为序列B。序列A、序列B与序列C中的元素个数相同。假设ci为序列C中索引值为i的元素的值，ai为序列A中索引值为i的元素的值，bi为序列B中索引值为i的元素的值，则ci的值为采用第一计算规则 对ai的值和bi的值计算得到的值。
其中，与另一个序列所对应的第一序列表示该第一序列与该序列对中的另一个序列强相关，比如，若该另一个序列是A时，则与该另一个序列对应的第一序列就是A1，若该另一个序列是B时，则与该另一个序列对应的第一序列就是B1。
上述至少一个序列对中的每个序列以及第一序列为长度大于1的复数序列。
网络设备向终端设备发送上述第一信号，终端设备接收该第一信号，该第一信号可以是经过信道、噪声、载波频偏(简称频偏)等非理想因素影响后的信号，终端设备可以根据目标计算规则对每个序列对中的两个序列进行计算，从而获得该序列对中另一个序列所对应的第三序列，该第三序列可以是第一序列经过信道、噪声、载波频偏(简称频偏)等非理想因素影响后的序列，仍然保留了第一序列的特性，终端设备可以采用第一序列和第三序列进行相关处理。
采用上述方案对第一信号中的序列进行设计，可以方便终端设备在接收到经过信道、噪声、载波频偏(简称频偏)等非理想因素影响后的信号时消除频偏影响，从而提高抗频偏性能，同时消除频偏后的序列仍然保留了第一序列的特性，比如保留了第一序列的良好自相关特性，从而方便终端设备准确的确定定时位置。
在一种可能的设计中，另一个序列所对应的第一序列可以是一个完整序列，比如一个完整的ZC序列。
在一种可能的设计中，所述另一个序列所对应的第一序列可以为第二序列的子序列，比如第二序列是一个完整的ZC序列，一个序列对的另一个序列所对应的第一序列可以是该完整ZC序列的子序列。其中，每个序列对的另一个序列对应一个第一序列，上述至少一个序列对中所有序列对的另一个序列对应的第一序列组成该第二序列。不同序列对中的另一个序列所对应的第一序列的长度可以相同。
比如，第一信号包括M个序列对，则第二序列包括M个子序列，一个子序列对应一个序列对，所述M个子序列为将该第二序列的N个元素划分形成的M个子序列，每个子序列包括P个元素，其中，M和N为大于或者等于2的自然数，P为大于或者等于1的自然数。
如果另一个序列所对应的第一序列为第二序列的子序列，最终终端设备得到的序列为比较长的序列，从而可以提高码分容量，比如指示更多的小区标识。
在一种可能的设计中，上述第一计算规则包括乘法规则、共轭乘法规则、除法规则和共轭除法规则中的至少一种规则。
采用上述第一计算规则可以减少终端设备在对该两个序列处理过程中的处理的复杂度。
在一种可能的设计中，一个序列对中的另一个序列可以是采用第二计算规则对N个序列计算得到的序列，N为大于或者等于2的自然数。
可选的，该第二计算规则可以与第一计算规则相同，也可以不同。比如，第二计算规则为乘法规则，则该另一个序列可以是将N个序列全部相乘得到的序列。
在一种可能的设计中，该N个序列中的每个序列可以是第五序列的子序列，其中，第五序列可以是与第二序列相同的序列。
在一种可能的设计中，若一个序列由一个时域符号携带，一个序列对中的两个序列可 以是相邻时域符号携带的序列，比如任意两个相邻时域符号携带的序列构成一个序列对，即是一个序列可以处于两个不同的序列对中。采用这种方式可以携带更多的序列对，从而方便终端设备精准确定定时位置。
或者特定时域符号携带的序列构成一个序列对，比如第一个时域符号携带的序列和第二个时域符号携带的序列构成一个序列对，第三个时域符号携带的序列和第四个时域符号携带的序列构成以序列对，即是一个序列仅仅处于一个序列对中。本发明实施例对此不作限定。
可选的，一个序列对中的两个序列也可以是非相邻时域符号携带的序列，比如中间间隔S个时域符号的两个序列构成一个序列对，S为大于或者等于1的自然数。例如，一个序列可以处于两个不同的序列对中，第一个时域符号携带的序列和第三个时域符号携带的序列构成一个序列对，第三个时域符号携带的序列和第五个时域符号携带的序列构成一个序列对，第二个时域符号携带的序列和第四个时域符号携带的序列构成一个序列对，以此类推。
还例如，一个序列仅仅处于一个序列对中，可以是第一个时域符号携带的序列和第三个时域符号携带的序列构成一个序列对，第五个时域符号携带的序列和第七个时域符号携带的序列构成一个序列对，第二个时域符号携带的序列和第四个时域符号携带的序列构成一个序列对，以此类推。
在一种可能的设计中，该第一信号可以用于指示终端设备是否存在与该终端设备关联的寻呼调度信息；和/或，该第一信号可以用于指示在一个特定的时间内，如一个非连续接收周期(DRX cycle)内，是否存在与该终端设备关联的下行控制信息，如PDCCH调度信息；和/或，该第一信号可以用于指示终端设备所处小区的系统消息是否发生变更；和/或，该第一信号可以用于指示终端设备所处小区的小区标识。
可选的，一个序列对对应一个第一序列，该第一信号可以通过该至少一个序列对中每个序列对的另一个序列所对应的第一序列在第一信号中的排序对终端设备进行指示，具体指示的信息请参照上述描述，比如指示是否存在与该终端设备关联的寻呼调度信息，和/或，指示该终端设备所处小区的小区标识等等。需要说明的是，在通过该至少一个序列对中每个序列对的另一个序列所对应的第一序列在第一信号中的排序指示该终端设备所处小区的小区标识时，需要预先设定各个第一序列的不同排序对应不同的小区标识，终端设备即可确定所处小区的小区标识。
可选的，若一个序列对的另一个序列所对应的第一序列为第二序列的子序列，该至少一个序列对中每个序列对的另一个序列所对应的第一序列组成该第二序列。可以通过所组成的不同的第二序列对终端设备进行指示，具体指示的信息请参照上述描述，比如指示是否存在与该终端设备关联的寻呼调度信息，和/或，指示该终端设备所处小区的小区标识等等。
第二方面，本发明实施例提供一种信号接收方法，该信号接收方法包括：终端设备接收第一信号，该第一信号中包括至少一个序列对，该至少一个序列对中每个序列对包括两个序列，该两个序列中的一个序列的元素值为采用第一计算规则对该两个序列中的另一个序列的元素值与所述另一个序列所对应的第一序列的元素值进行计算得到的值。其中，上 述至少一个序列对中每个序列以及每个序列对的另一个序列对应的第一序列为长度大于1的复数序列。
针对每个序列对，终端设备根据目标计算规则，对该序列对中两个序列的一个序列的元素值和该两个序列中的另一个序列的元素值进行计算，获取该序列对中另一个序列所对应的第三序列。其中，该第三序列与第一序列本质上相同，只是该第三序列是第一序列经过信道、噪声、载波频偏(简称频偏)等非理想因素影响后的序列。
所述终端设备采用第一序列和第三序列进行相关处理，第一序列为终端设备本地存储的序列，该第一序列与网络设备侧发送的第一信号中携带的第一序列相同。
网络设备对第一信号中的序列进行第一方面所阐述的设计方式，可以方便终端设备在接收到经过信道、噪声、载波频偏(简称频偏)等非理想因素影响后的信号时消除频偏影响，从而提高抗频偏性能，同时消除频偏后的第三序列仍然保留了第一序列的特性，比如保留了第一序列的良好自相关特性，从而方便终端设备准确的确定定时位置。
在一种可能的设计中，目标计算规则与第一计算规则对应，比如，所述第一计算规则包括乘法规则、共轭乘法规则、除法规则和共轭除法规则中的至少一种规则，则目标计算规则可以是：共轭相乘规则。比如，终端设备将两个序列中的所述另一个序列的共轭序列与所述两个序列中的所述一个序列相乘，从而获得所述另一个序列所对应的第三序列。其中，另一个序列的共轭序列的元素值是该另一个序列的元素值的共轭复数。或者，终端设备将两个序列中的所述一个序列的共轭序列与所述另一个序列相乘，从而得到第三序列。
在一种可能的设计中，另一个序列所对应的第一序列可以是一个完整序列，比如一个完整的ZC序列，终端设备在采用第一序列和所述第三序列进行相关处理时，可以是将该第一序列和所述第三序列进行卷积运算或循环卷积运算，并基于运算结果确定定时位置。
采用这种方式，终端设备可以得到多个短的完整序列，终端设备可以直接进行相关处理，确定定时位置，减少终端设备的处理复杂度。
在一种可能的设计中，另一个序列所对应的第一序列可以是第二序列的子序列，比如第二序列是一个完整的ZC序列，一个序列对的另一个序列所对应的第一序列可以是该完整ZC序列的子序列，不同序列对中的另一个序列所对应的第一序列不同，上述至少一个序列对中所有序列对的另一个序列对应的第一序列组成该第二序列。
终端设备在采用第一序列和第三序列进行相关处理时，首先需要获取第四序列，该第四序列为所有序列对中另一个序列所对应的第三序列组成的序列，每个序列对中另一个序列所对应的第三序列与该另一个序列强相关。不同序列对的另一个序列对应的第三序列不同。比如，若另一个序列为A，则该另一个序列对应的第三序列为A2，若另一个序列为B，则该另一个序列对应的第三序列为B2。
终端设备将第二序列和第四序列进行卷积运算或循环卷积运算，并基于运算结果确定定时位置。
采用这种方式，终端设备可以得到一个比较长的完整序列，从而提高码分容量，并且具有更好的相关性，提高终端设备确定定时位置的准确性。
第三方面，本发明实施例提供一种信号发送装置，该信号发送装置具有实现上述第一方面方法中网络设备行为的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应 的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
一种可能的实现方式中，所述信号发送装置包括：处理模块和发送模块，其中，所述处理模块，用于生成第一信号，所述第一信号中包括至少一个序列对，所述至少一个序列对中每个序列对包括两个序列，所述两个序列中的一个序列的元素值为采用第一计算规则对所述两个序列中的另一个序列的元素值与所述另一个序列所对应的第一序列的元素值进行计算得到的值，其中，所述至少一个序列对中每个序列以及所述第一序列为长度大于1的复数序列。所述发送模块，用于发送所述第一信号。
另一种可能的实现方式中，所述信号发送装置包括：收发器、存储器和处理器；其中，收发器用于接收信号或者发送信号。存储器中存储一组程序代码，且处理器用于调用存储器中存储的程序代码，执行以下操作：生成第一信号，所述第一信号中包括至少一个序列对，所述至少一个序列对中每个序列对包括两个序列，所述两个序列中的一个序列的元素值为采用第一计算规则对所述两个序列中的另一个序列的元素值与所述另一个序列所对应的第一序列的元素值进行计算得到的值，其中，所述至少一个序列对中每个序列以及所述第一序列为长度大于1的复数序列；向终端设备发送所述第一信号。
基于同一发明构思，由于该装置解决问题的原理以及有益效果可以参见第一方面所述的方法以及所带来的有益效果，因此该装置的实施可以参见方法的实施，重复之处不再赘述。
第四方面，本发明实施例提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述第一方面所述的方法。
第五方面，本发明实施例提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述第一方面所述的方法。
第六方面，本发明实施例提供一种信号接收装置，该信号接收装置具有实现上述第二方面方法中终端设备行为的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
一种可能的实现方式中，所述信号接收装置包括：收发单元和处理单元。所述收发单元，用于接收第一信号，所述第一信号中包括至少一个序列对，所述至少一个序列对中每个序列对包括两个序列，所述两个序列中的一个序列的元素值为采用第一计算规则对所述两个序列中的另一个序列的元素值与所述另一个序列所对应的第一序列的元素值进行计算得到的值；其中，所述至少一个序列对中每个序列以及所述第一序列为长度大于1的复数序列。所述处理单元，用于根据目标计算规则，对所述两个序列中的一个序列的元素值和所述两个序列中的另一个序列的元素值进行计算，获取所述另一个序列所对应的第三序列；所述处理单元，还用于采用所述第一序列和所述第三序列获取定时位置。
另一种可能的实现方式中，所述信号接收装置包括：收发器、存储器和处理器；其中，收发器用于接收信号或者发送信号。存储器中存储一组程序代码，且处理器用于调用存储器中存储的程序代码，执行以下操作：接收第一信号，所述第一信号中包括至少一个序列对，所述至少一个序列对中每个序列对包括两个序列，所述两个序列中的一个序列的元素值为采用第一计算规则对所述两个序列中的另一个序列的元素值与所述另一个序列所对应的第一序列的元素值进行计算得到的值；其中，所述至少一个序列对中每个序列以及所述 第一序列为长度大于1的复数序列；根据目标计算规则，对所述两个序列中的一个序列的元素值和所述两个序列中的另一个序列的元素值进行计算，获取所述另一个序列所对应的第三序列；采用所述第一序列和所述第三序列获取定时位置。
基于同一发明构思，由于该装置解决问题的原理以及有益效果可以参见第二方面所述的方法以及所带来的有益效果，因此该装置的实施可以参见方法的实施，重复之处不再赘述。
第七方面，本发明实施例提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述第二方面所述的方法。
第八方面，本发明实施例提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述第二方面所述的方法。
本发明实施例中，第一信号中包括至少一个序列对，每个序列对中包括两个序列，该两个序列中的一个序列的元素值为采用第一计算规则对该两个序列中的另一个序列的元素值与该另一个序列对应的第一序列计算得到的值，由于一个序列对中的两个序列存在上述关系，因此终端设备接收到经过信道、噪声、载波频偏(简称频偏)等非理想因素影响后的信号时，可以消除频偏影响，从而提高抗频偏性能，同时消除频偏后仍然可以得到一个序列，该序列保持了第一序列的特性，从而方便终端设备准确的确定定时位置。
附图说明
为了更清楚地说明本发明实施例或背景技术中的技术方案，下面将对本发明实施例或背景技术中所需要使用的附图进行说明。
图1a是LTE中PSS的序列设计示意图；
图1b是针对LTE的PSS序列设计的仿真图；
图1c是针对LTE中PSS序列设计的另一种仿真图；
图2是本发明实施例提供的一种系统架构图；
图3a是本发明实施例提供的NB-IoT中NPSS的序列设计示意图；
图3b是本发明实施例提供的NB-IoT中NPSS序列设计的仿真图；
图4是本发明实施例提供的一种信号处理方法的交互流程图；
图5a-5d是本发明实施例提供的序列设计示意图；
图6a是本发明实施例提供的一种仿真示意图；
图6b是本发明实施例提供的另一种仿真示意图；
图7a是本发明实施例提供的一种信号发送装置的结构示意图；
图7b是本发明实施例提供的另一种信号发送装置的结构示意图；
图7c是本发明实施例提供的一种终端设备的结构示意图；
图8a是本发明实施例提供的一种信号接收装置的结构示意图；
图8b是本发明实施例提供的一种信号接收装置的结构示意图；
图8c是本发明实施例提供的一种网络设备的结构示意图。
具体实施方式
下面结合本发明实施例中的附图对本发明实施例进行描述。
本发明实施例的序列对指第一信号中满足特定条件的两个序列，该特定条件可以是：该两个序列中，一个序列的元素值为采用第一计算规则对该两个序列中的另一个序列的元素值与该另一个序列所对应的第一序列的元素值计算得到的值。该两个序列可以是相邻时域符号携带的序列，也可以是非相邻时域符号携带的序列。
本发明实施例中，一个序列对的两个序列中，另一个序列对应的第一序列指：该第一序列与该另一个序列强相关，比如若另一个序列为A，则与该另一个序列对应的第一序列为A1，若另一个序列为B，则与该另一个序列对应的第一序列为B1。一个序列对的另一个序列对应一个第一序列，不同序列对的另一个序列对应的第一序列可能不同。
本发明实施例所提及的完整序列可以是：Zadoff-Chu(ZC)序列、相控序列、m序列、Gold序列、M序列、GMW序列、kasami序列、Bent序列、哈德码序列、DFT序列等等。需要说明的是，本发明对序列类型不做限制，只要是长度大于1的复数序列(复数序列意为序列元素为复数)即可。优选地，可以是具有良好自相关性或正交性的序列。
或者，本发明实施例所提及的完整序列也可以是上述序列的各种变形序列，比如将上述序列经过循环移位扩展后形成的序列，或者，将上述序列中截断一部分元素后的序列，或者，上述序列的共轭序列，或者，上述序列进行相位旋转后的序列(即将上述序列的每个元素旋转一个给定的相位)，或者多个上述序列相乘后的序列、共轭相乘后的序列、相加后的序列、模2相加后的序列等等。需要说明的是，本发明实际使用的完整序列，也可以是将上述序列经过多种上述变形后的序列，举个例子，可以使用两个上述序列相乘后并进行循环移位扩展后的序列，等等。
需要说明的是，为了便于说明，本发明实施例均采用ZC序列作为举例，可以理解的是，本发明实施例所提及的ZC序列也可以用上述所提及的任意一种完整序列进行替代。
本发明实施例可以适用于LTE系统，也可以适用于其他无线通信系统，例如全球移动通信系统(Global System for Mobile Communication，GSM)，移动通信系统(Universal Mobile Telecommunications System，UMTS)，码分多址接入(Code Division Multiple Access，CDMA)系统，以及新的网络系统等。本发明实施例主要以LTE系统中的NB-IoT为例进行举例说明。
其中，无线通信系统通常由小区组成，如图2所示，每个小区包含基站(Base Station，BS)，基站向多个终端设备提供通信服务，基站连接到核心网设备。其中，基站包含基带单元(Baseband Unit，BBU)和远端射频单元(Remote Radio Unit，RRU)。BBU和RRU可以放置在不同的地方，例如：RRU拉远，放置于离高话务量的开阔区域，BBU放置于中心机房。BBU和RRU也可以放置在同一机房。BBU和RRU也可以为一个机架下的不同部件。
本发明实施例所涉及的基站是一种部署在无线接入网中用以为终端设备提供无线通信功能的装置。所述基站可以包括各种形式的宏基站，微基站(也称为小站)，中继站，接入点，传输接入点(Transmission Receiver point，TRP)等。在采用不同的无线接入技术的系统中，具备基站功能的设备的名称可能会有所不同，例如，在LTE系统中，称为演进的节点B(evolved NodeB，eNB或者eNodeB)，在第三代(3rd Generation，3G)系统中，称为节点B(Node B，NB)等。为方便描述，本申请所有实施例中，上述为终端设备提供无 线通信功能的装置统称为网络设备。
本发明实施例涉及的终端设备，可以是指向用户提供语音和/或数据连通性的设备，具有无线连接功能的手持式设备、或连接到无线调制解调器的其他处理设备。无线终端可以经无线接入网(Radio Access Network，RAN)与一个或多个核心网进行通信，无线终端可以是移动终端，如移动电话(或称为“蜂窝”电话)和具有移动终端的计算机，例如，可以是便携式、袖珍式、手持式、计算机内置的或者车载的移动装置，它们与无线接入网交换语言和/或数据。例如，个人通信业务(PCS，Personal Communication Service)电话、无绳电话、会话发起协议(SIP)话机、无线本地环路(WLL，Wireless Local Loop)站、个人数字助理(PDA，Personal Digital Assistant)等设备。无线终端也可以称为系统、订户单元(SubscriberUnit)、订户站(Subscriber Station)，移动站(Mobile Station)、移动台(Mobile)、远程站(Remote Station)、接入点(Access Point)、远程终端(Remote Terminal)、接入终端(Access Terminal)、用户终端(User Terminal)、用户代理(User Agent)、用户设备(User Device)、或用户装备(User Equipment)。为方便描述，本申请所有实施例中，上面提到的设备统称为终端设备。
网络设备发送到终端设备的信号，经过信道、噪声、载波频偏(简称频偏)等非理想因素的影响后，往往会存在一定的载波频偏，载波频偏会在时域上引起信号的连续相位变化。终端设备接收到信号后，需要进行下行同步处理，以确定定时位置。通常为了方便同步，网络设备发送的信号中包括用于进行同步的序列，该序列可以是具有良好自相关特性的序列，比如ZC(Zadoff-Chu)序列具有非常好的自相关性和很低的互相关性，这种性能可以被用来产生用于进行同步的序列。
然而，由于信道、噪声、载波频偏(简称频偏)等非理想因素的影响，该序列也会存在一定的载波频偏，载波频偏会导致该序列在时域上引起连续的相位变化。因此也会导致该序列的相关特性下降甚至被破坏。比如，LTE中的主同步信号用的是一个根指数为25、29或34的ZC(Zadoff-Chu)序列，长度为63。该序列的抗频偏性就比较差。如图1b所示，若该序列没有频偏(即终端设备接收的序列相对于网络设备发送的序列没有频偏)，终端设备在进行相关处理时，相关峰比较明显，比较容易确定定时位置。但若该序列存在频偏(即终端设备接收的序列相对于网络设备发送的序列存在频偏)，比如频偏为18kHz，终端设备在进行相关处理时，相关峰完全消失了，无法确定定时位置。其中，相关处理即是，终端设备将接收的序列与本地存储的序列进行相关运算，终端设备本地存储的序列是与接收的序列对应的干净序列，干净序列即是未经过信道、噪声、载波频偏(简称频偏)等非理想因素影响的序列。
可选的，如图3a所示，目前NB-IoT的主同步信号用的是11个相同的根指数为5的ZC序列，每个ZC序列的长度为11，每个ZC序列会乘以1或-1。由于信道、噪声、载波频偏(简称频偏)等非理想因素的影响，终端设备接收的信号中的序列相对于网络设备发送的信号中的序列，在时域上存在连续的相位变化，比如相位变化值成等差序列。终端设备在进行同步处理之前，将相邻的序列进行自相关运算(即前一个序列的共轭乘后一个序列)，这样可以消除频偏的影响。但是在经过自相关运算(即频偏消除处理)后的序列中不存在ZC序列的良好自相关特性。因此也会导致定时位置不准确。如图3b所示，即是采用 NB-IoT的主同步信号中序列设计方式得到的仿真图，该仿真图为终端设备在相关处理过程中的相关性仿真图。如图所示，相关峰比较平缓，不陡峭，在后续同步处理过程之后引入模糊度，导致同步精度不高。
为了解决上述问题，本发明实施例公开了一种信号的序列设计方式，网络设备生成第一信号，该第一信号中包括至少一序列对，每个序列对中包括两个序列，该两个序列中的一个序列的元素值为，采用第一计算规则对该两个序列中的另一个序列的元素值与该另一个序列所对应的第一序列的元素值进行计算得到的值。比如，一个序列对中包括两个序列，该序列对可以是第一信号中所携带的任意一个序列对。为了方便描述，本发明实施例将该两个序列中的一个序列称为序列2，另一个序列称为序列3，该另一个序列对应的第一序列称为序列1。需要说明的是，该序列1与该序列3强相关。一个序列对的另一个序列对应一个第一序列，该第一信号中存在至少一个序列对，因此也存在至少一个第一序列。不同序列对中的另一个序列对应的第一序列可以是不同序列。
比如，序列3为Z1序列，序列3所对应的序列1为Z2序列，则序列2为采用第一计算规则对序列3与该序列3对应的序列1计算得到的序列，这里以第一计算规则为乘法规则作为举例说明，则序列2为Z1×Z2，该序列对中的两个序列为Z1和Z1×Z2。需要说明的是，两个序列相乘，得到一个与该两个序列长度一样的乘积序列，且得到的乘积序列中的每个元素为该两个序列中对应元素的乘积。
可选的，上述一个序列对中的另一个序列所对应的第一序列可以是一个单独的完整序列，比如一个ZC序列，或者，上述一个序列对中的另一个序列所对应的第一序列可以是一个完整序列的子序列，比如一个ZC序列的子序列。需要说明的是，若一个序列对中的另一个序列所对应的第一序列是一个序列的子序列，则第一信号所包括的至少一序列对中每个序列对的另一个序列所对应的第一序列组成一个完整序列，比如，组成一个ZC序列。即是该完整序列的不同子序列可以是不同序列对中另一个序列所对应的第一序列。
由于一个序列对中的两个序列存在上述关系，终端设备接收到第一信号后，可以根据目标计算规则，对一个序列对的两个序列进行计算处理，从而获得该序列对中另一个序列所对应的第三序列。其中，目标计算规则需要根据网络设备所采用的第一计算规则确定，比如第一计算规则为乘法规则、共轭乘法规则、除法规则和共轭除法规则中的至少一种规则。则目标计算规则可以是针对一个序列对的两个序列，将另一个序列的共轭序列与一个序列相乘，从而得到另一个序列所对应的第三序列。通过目标计算规则对序列对的两个序列进行计算处理，可以提高抗频偏性能。
需要说明的是，若无信道、噪声、载波频偏(简称频偏)等非理想因素影响，该第三序列与第一序列相同，由于存在信道、噪声、载波频偏(简称频偏)等非理想因素的影响，因此，第四序列可以是第一序列经过信道、噪声、载波频偏(简称频偏)等非理想因素影响后的序列。但是第四序列保留了第一序列的相关特性，比如，第一序列为ZC序列，第四序列仍然保留了ZC序列的良好自相关特性。因此采用第一序列和第三序列进行相关处理时，仍然可以出现明显的相关峰，便于终端设备准确的确定定时位置。
请参照图4，为本发明实施例提供的一种信号处理方法的交互图，如图所示，本发明 实施例的信号处理方法包括但不限于以下步骤：
S10，网络设备生成第一信号，所述第一信号中包括至少一个序列对，所述至少一个序列对中每个序列对包括两个序列，所述两个序列中的一个序列的元素值为采用第一计算规则对所述两个序列中的另一个序列的元素值与所述另一个序列所对应的第一序列的元素值进行计算得到的值，其中，所述至少一个序列对中每个序列以及所述第一序列为长度大于1的复数序列。
在一个实施例中，网络设备生成第一信号。该第一信号中包括至少一个序列对，一个序列对中的两个序列满足条件：一个序列的元素值为采用第一计算规则对该两个序列中的另一个序列的元素值与该另一个序列所对应的第一序列的元素值计算得到的值。需要说明的是，该另一个序列所对应的第一序列与该另一个序列强相关，比如若另一个序列为A序列，则与该另一个序列对应的第一序列为A1序列，若另一个序列为B序列，则与该另一个序列对应的第一序列为B1序列。不同序列对中的另一个序列不同，则另一个序列所对应的第一序列也可以是不同的。
为了方便描述，本发明实施例将一个序列对的两个序列中的一个序列称为序列2，另一个序列称为序列3，该另一个序列对应的第一序列称为序列1。比如，序列3为Z1序列，序列3所对应的第一序列(即序列1)为Z2序列，则序列2为采用第一计算规则对序列3与该序列3对应的第一序列计算得到的序列。需要说明的是，上述第一信号包括的至少一个序列对中每个序列对的两个序列均满足上述条件，区别在于不同序列对的两个序列可以不完全相同。不同序列对中的另一个序列所对应的第一序列也可以是不同序列。
可选的，第一计算规则可以包括乘法规则、共轭乘法规则、除法规则和共轭除法规则中的至少一种规则。这里继续以一个序列对中包括序列2和序列3作为举例说明，序列3为Z1序列，序列3所对应的第一序列(即序列1)为Z2序列，若第一计算规则为乘法规则，则序列2为Z1×Z2。若第一计算规则为共轭乘法规则，则序列2可以是Z1*×Z2或者，序列2可以是Z1×Z2*。若第一计算规则为除法规则，则序列2可以是Z1/Z2。若第一计算规则为共轭除法规则，则序列2可以是Z1*/Z2，或者序列2可以是Z1/Z2*。需要说明的是，上述序列Z*为序列Z的共轭序列，即是序列Z*中的每个元素的值均为序列Z中对应元素的共轭复数。
进一步可选的，采用第一计算规则对序列3和序列1进行计算的方式可以是，将序列3所包含的元素值与序列1所包含的元素值进行对位计算。比如序列3为a1，a2，...，an，序列1为b1，b2，...，bn，计算得到的序列2为c1，c2，...，cn，则对于序列2中的每个元素值ci为采用第一计算规则对ai和bi处理得到的值。这里以第一计算规则为乘法规则作为举例说明，则ci＝ai×bi，i＝1，2，...，n。若第一计算规则为共轭乘法规则，则ci＝ai×bi *，i＝1，2，...，n，或者，ci＝ai *×bi，i＝1，2，...，n，其中，bi表示bi的共轭复数。
可选的，一个序列对中的另一个序列对应的第一序列可以是一个完整序列，比如一个ZC序列，或者，一个序列对中的另一个序列对应的第一序列为第二序列的子序列，比如该第二序列为一个完整的ZC序列，一个序列对中的另一个序列对应的第一序列仅仅为该完整ZC序列中的一个子序列，该第一信号的所有序列对中另一个序列对应的第一序列组成该第二序列。需要说明的是，子序列中所包含的元素是该子序列所对应的完整序列的一部 分。
比如第二序列包括N个元素，可以将该N个元素划分为M个子序列，每个子序列包括P个元素，其中，所述M为大于或者等于2的自然数，所述P为大于或者等于1的自然数。该M个子序列中的每个子序列是一个序列对的另一个序列对应的一个第一序列。比如，第二序列包括3个子序列，分别为P1、P2和P3。第一信号中包括三个序列对，分别为序列对1、序列对2和序列对3，则可以是序列对1中的另一个序列对应的第一序列为P1，序列对2中的另一个序列对应的第一序列为P2，序列对3中的另一个序列对应的第一序列为P3。
需要说明的是，在划分子序列时，若N个元素不够平均划分，则可以采取循环移位的方式，将N个元素划分形成M个子序列。比如，N为5，需要划分为2个子序列，则可以将最后两个元素和该序列的第一个元素划分形成一个子序列，如果采用这种方式进行子序列的划分，则M*P就大于N。采用这种子序列的划分方式，所组成的第二序列即为ZC序列的变形序列，即第二序列是ZC序列循环移位后形成的序列。
或者，若N个元素不够平均划分，也可以采取截断的方式，将N个元素划分形成M个子序列。比如N为7，需要划分形成两个子序列，则可以将该序列的最后一个元素舍弃，将剩余元素划分形成两个子序列，如果采用这种方式进行子序列的划分，则M*P就小于N。采用这种子序列的划分方式，所组成的第二序列即为ZC序列的变形序列，即第二序列是ZC序列截断一部分元素后形成的序列。
可选的，一个序列对中的另一个序列可以是一个序列，比如一个ZC序列或者一个ZC序列的子序列，或者一个复数，复数可以是1或者其他。
可选的，一个序列对中的另一个序列也可以是采用第二计算规则对N个序列计算得到的序列，N为大于或者等于2的自然数。其中，第二计算规则可以与第一计算规则相同或者不同。为方便描述，这里继续以一个序列对中包括序列2和序列3为例进行说明，序列2为一个序列对的两个序列中的一个序列，序列3为该序列对的两个序列中的另一序列。第二计算规则比如为乘法规则，序列3可以是将两个序列相乘得到的序列，比如序列3为Z1×Z2，该序列3对应的第一序列可以是Z3，则序列2为Z1×Z2×Z3。其中Z1、Z2以及Z3可以均为ZC序列。或者，Z1、Z2和Z3可以均为第二序列的子序列，比如，Z1、Z2和Z3可以均为一个ZC序列的子序列。
可选的，一个序列对中的两个序列可以是相邻时域符号携带的序列，也可以是非相邻时域符号携带的序列。可选的，同一个序列可以是同时处于两个序列对中，比如任意相邻时域符号携带的序列构成一个序列对，需要说明的是，最后一个序列可以仅仅存在于一个序列对中。或者，任意一个序列可以是仅仅处于一个序列对中，即序列总数为偶数N，则序列对的个数为N/2。
请参照图5a-5d为本发明实施例提供的几种可选的序列设计方式，需要说明的是，本发明实施例以一个时域符号携带一个序列作为举例说明，可以理解的是，也可以是多个时域符号携带一个序列，或者，一个时域符号携带多个序列，本发明实施例对此不作限定。并且本发明实施例对图5a-5d中各个时域符号中所携带序列的存在形式也不作限定，5a-5d中序列存在形式仅为举例。在图5a-5d中的序列C、C1、C2、C3以及C4可以任意复数序列，该序列中的元素可以相同，也可以不同。
请参照图5a和5b所示，一个序列对的两个序列为相邻时域符号携带的序列。
请参照图5a所示，同一个序列可以处于两个不同的序列对中，但是第一个序列和最后 一个序列仅仅处于一个序列对中。即图5a中任意两个相邻时域符号携带的序列均构成一个序列对。比如第三个时域符号携带的序列Z1*Z2与相邻的时域符号携带的序列Z1构成一个序列对，同时第三个时域符号携带的序列Z1*Z2与相邻的时域符号携带的序列Z1*Z2*Z3也构成一个序列对。
可选的，图5a中采用序列级差分的形式，即后一个时域符号携带的序列是前一个时域符号携带的序列与一个第一序列相乘得到的序列。从图中可以看出，不同序列对所对应的第一序列不同。即序列对中的第一序列与该序列对中的前一个时域符号携带的序列对应。
可选的，图5a中的序列Z1、Z2、Z3、Z4...Zn-1可以均为一个完整序列，或者，序列Z1、Z2、Z3、Z4...Zn-1可以均为一个完整序列的子序列，即该完整序列包括n-1个子序列，并且该n-1个子序列可以组成该完整序列。即序列Z1、Z2、Z3、Z4...Zn-1组成一个完整序列，需要说明的是，这里的完整序列可以一个ZC序列，或者也可以是ZC序列的各种变形序列，在此不再赘述。可以理解的是，图5a中的序列可以不仅限于ZC序列，本发明实施例对此不作限定。
请参照图5b所示，同一个序列可以仅仅处于一个序列对中，但是一个序列对的两个序列由相邻时域符号携带。比如第一个时域符号和第二个时域符号携带的序列构成一个序列对，第三个时域符号携带的序列和第四个时域符号携带的序列构成一个序列对，以此类推。
如图5b所示，对于一个序列对中的两个序列，后一个时域符号携带的序列是前一个时域符号携带的序列与前一个时域符号携带的序列所对应的第一序列相乘得到的序列。从图中可以看出，前一个时域符号所携带的序列不同，则该前一个时域符号携带的序列所对应的第一序列可以不同。
可选的，图5b中的序列Z1、Z2、Z3、Z4...Zn-1可以均为一个完整序列，或者，序列Z1、Z2、Z3、Z4...Zn-1可以均为一个完整序列的子序列，即该完整序列包括n-1个子序列，并且该n-1个子序列可以组成该完整序列。即序列Z1、Z2、Z3、Z4...Zn-1组成一个完整序列，需要说明的是，这里的完整序列可以一个ZC序列，或者也可以是ZC序列的各种变形序列，在此不再赘述。可以理解的是，图5b中的序列不仅限于ZC序列，本发明实施例对此不作限定。
请参照图5c和5d所示，一个序列对的两个序列可以为非相邻时域符号携带的序列。在图5c和图5d中仅以14个时域符号携带的14个序列作为举例，可以理解的是，也可以是其他数量的序列，本发明实施例对此不作限定。
请参照图5c所示，同一个序列可以处于两个不同的序列对中，一个序列对的两个序列之间相隔一个序列。第一个序列、第二个序列、最后一个序列以及倒数第二个序列处于一个序列对中。图5c中任意相隔一个时域符号携带的序列均构成一个序列对。
从图中可以看出，不同序列对所对应的第一序列不同。即序列对中的第一序列与该序列对中排列在前的时域符号携带的序列对应。
可选的，图5c中的序列Z1、Z2、Z3、Z4...Z12可以均为一个完整序列，或者，序列Z1、Z2、Z3、Z4...Z12可以均为一个完整序列的子序列，即该完整序列包括12个子序列，并且该12个子序列可以组成该完整序列。即序列Z1、Z2、Z3、Z4...Z12组成一个完整序列，需要说明的是，这里的完整序列可以一个ZC序列，或者也可以是ZC序列的各种变形 序列，在此不再赘述。可以理解的是，图5c中的序列不仅限于ZC序列，本发明实施例对此不作限定。
请参照图5d所示，同一个序列可以仅仅处于一个序列对中，或者同一个序列可以处于两个不同序列对中，一个序列对的两个序列之间相隔3个时域符号。比如第一个时域符号和第五个时域符号携带的序列构成一个序列对，第二个时域符号携带的序列和第六个时域符号携带的序列构成一个序列对，以此类推。
如图5d所示，对于一个序列对中的两个序列，排序在后的时域符号携带的序列是排序在前的时域符号携带的序列与排序在前的时域符号携带的序列所对应的第一序列相乘得到的序列。从图中可以看出，排序在前的时域符号所携带的序列不同，则所对应的第一序列也不同。
可选的，图5d中的序列Z1、Z2、Z3、Z4...Z10可以均为一个完整序列，或者，序列Z1、Z2、Z3、Z4...Z10可以均为一个完整序列的子序列，即该完整序列包括10个子序列，并且该4个子序列可以组成该完整序列。即序列Z1、Z2、Z3、Z4...Z10组成一个完整序列，需要说明的是，这里的完整序列可以一个ZC序列，或者也可以是ZC序列的各种变形序列，在此不再赘述。可以理解的是，图5d中的序列不仅限于ZC序列，本发明实施例对此不作限定。
S11，所述网络设备发送所述第一信号。
在一个实施例中，网络设备向终端设备发送该第一信号，可选的，该第一信号可以用于指示是否存在与该终端设备关联的寻呼调度信息；和/或，该第一信号可以用于指示在一个特定的时间内，如一个非连续接收周期(DRX cycle)内，是否存在与该终端设备关联的下行控制信息，如PDCCH调度信息；和/或，该第一信号可以用于指示终端设备所处小区的系统消息是否发生变更；和/或，该第一信号可以用于指示该终端设备所处小区的小区标识。
可选的，若一个序列对的另一个序列所对应的第一序列为一个完整序列，则可以通过多个序列对的另一个序列所对应第一序列在该第一信号中的排序对终端设备进行指示，具体指示的信息请参照上述描述，比如指示是否存在与该终端设备关联的寻呼调度信息，和/或，指示该终端设备所处小区的小区标识等等。需要说明的是，在通过该至少一个序列对中每个序列对的另一个序列所对应的第一序列在第一信号中的排序指示该终端设备所处小区的小区标识时，需要预先设定各个第一序列的不同排序对应不同的小区标识，终端设备即可确定所处小区的小区标识。
可选的，若一个序列对的另一个序列所对应的第一序列为第二序列的子序列，该至少一个序列对中每个序列对的另一个序列所对应的第一序列组成该第二序列。可以通过所组成的不同的第二序列对终端设备进行指示，具体指示的信息请参照上述描述，比如指示是否存在与该终端设备关联的寻呼调度信息，和/或，指示该终端设备所处小区的小区标识等等。可选的，若该第二序列为一个ZC序列或者ZC序列的各种变形序列，则不同ZC序列的根指数不同。
S12，终端设备接收所述第一信号。
需要特别强调的是，终端设备所接收的第一信号可以是网络设备发送的第一信号经过 信道、噪声、载波频偏(简称频偏)等非理想因素影响后的信号，信道、噪声、载波频偏(简称频偏)等非理想因素会导致该第一信号在时域上存在连续的相位变化。对此，本发明实施例不做过多限制。
S13，所述终端设备根据目标计算规则，对所述第一信号中包括的两个序列中的一个序列的元素值和所述两个序列中的另一个序列的元素值进行计算，获取所述另一个序列所对应的第三序列。
在一个实施例中，终端设备根据目标计算规则，对所接收的第一信号中的任意一个序列对的两个序列作如下处理：将该两个序列中的一个序列的元素值与另一个序列的元素值进行计算，获得该另一个序列所对应的第三序列。需要说明的是，若无信道、噪声、载波频偏(简称频偏)等非理想因素影响，第三序列与第一序列相同，由于存在信道、噪声、载波频偏(简称频偏)等非理想因素影响，因此第三序列是第一序列经过信道、噪声、载波频偏(简称频偏)等非理想因素影响后的序列。
可选的，目标计算规则需要根据步骤S10中的第一计算规则确定，比如，第一计算规则包括乘法规则、共轭乘法规则、除法规则和共轭除法规则中的至少一种规则。则目标计算规则可以是：共轭相乘规则。比如，将该两个序列中的另一个序列的共轭序列与该两个序列中的一个序列相乘，从而获得该另一个序列所对应的第三序列；可以理解的是，也可以是将两序列中的一个序列除以另一个序列。或者，还可以是终端设备将两个序列中的所述一个序列的共轭序列与所述另一个序列相乘，从而得到第三序列。该第三序列保留了第一序列的特性。
比如，在步骤S10中采用第一计算规则进行处理得到的一个序列对中的一个序列是Z1×Z2，另一个序列是Z1，则采用目标计算规则进行处理时，可以是Z1*×(Z1×Z2)，最后得到序列Z2，由于存在信道、噪声、载波频偏(简称频偏)等非理想因素的影响，第三序列是序列Z2经过信道、噪声、载波频偏(简称频偏)等非理想因素后的序列。比如第三序列与序列Z2存在固定相位差，第三序列仍然保留了Z2序列的特性，比如Z2序列为ZC序列，则第三序列仍然具有良好的自相关特性。
S14，所述终端设备采用所述第一序列和所述第三序列获取定时位置。
在一个实施例中，终端设备采用本地存储的第一序列和第三序获取定时位置。可选的，终端设备采用本地存储的第一序列和第三序通过卷积运算或者循环卷积运算获取定时位置。
可选的，第一序列可以为一个完整序列，则终端设备采用目标计算规则处理后得到的第三序列也是一个完整序列，第一信号包括多个序列对，则可以得到多个完整序列。比如第一序列为ZC序列，则终端设备可以得到多个短的ZC序列。
终端设备在进行相关处理时，是将处理得到的多个短的ZC序列与本地存储的对应的多个ZC序列进行相关处理，从而确定定时位置。
示例性的，若采用如图5a所示的序列设计方式，序列Z1、Z2、Z3、Z4...Zn-1均为ZC序列。则终端设备在进行相关处理时，相关性的仿真图如图6a所示，从图6a中可以看出，图5a的序列设计方式对应的仿真曲线比图3a的NB-IoT的序列设计方式对应的仿真曲线，相关峰更加明显，方便终端设备确定定时位置。需要说明的是，图6a中的Z序列即为上述序列Z1、Z2、Z3、Z4...Zn-1。
可选的，第一序列可以是一个完整序列(比如第二序列)的子序列，则终端设备采用目标计算规则处理后得到的第三序列也是第四序列的子序列。第一信号包括多个序列对，对所有序列对的两个序列进行处理，可以得到多个第三序列，该多个第三序列均为第四序列的子序列，且该多个第三序列组成该第四序列。
终端设备在进行相关处理时，是将获得的第四序列与本地存储的第二序列进行相关处理，从而确定定时位置。
示例性的，若采用如图5a所示的序列设计方式，序列Z1、Z2、Z3、Z4...Zn-1均为一个ZC序列的子序列。即Z1、Z2、Z3、Z4...Zn-1组成该ZC序列。终端设备在进行相关处理时，相关性的仿真图如图6b所示。从图6b中可以看出，图5a的序列设计方式对应的仿真曲线比图3a的NB-IoT的序列设计方式对应的仿真曲线，相关峰更加明显，方便终端设备确定定时位置。并且由于最后得到的ZC序列比较长，因此相关性仿真图中仿真曲线的相关峰比图6a的更加明显。需要说明的是，图6b中的Z序列即为上述序列Z1、Z2、Z3、Z4...Zn-1。
可选的，第一信号可以用于指示：是否存在与该终端设备关联的寻呼调度信息；和/或，和/或，在一个特定的时间内，如一个非连续接收周期(DRX cycle)内，是否存在与该终端设备关联的下行控制信息，如PDCCH调度信息；和/或，终端设备所处小区的系统消息是否发生变更；和/或，该终端设备所处小区的小区标识。
若终端设备通过第一信号确定存在与该终端设备关联的寻呼调度信息，则终端设备可以在PO上监听寻呼paging的调度信息；若终端设备通过第一信号确定不存在与该终端设备关联的寻呼调度信息，则终端设备可以不监听信息以节省功耗。
可选的，终端设备可以通过第一信息确定该终端设备所处小区的小区标识，从而可以进一步利用该信号做下行测量。
本发明实施例中，第一信号中包括至少一个序列对，每个序列对中包括两个序列，该两个序列中的一个序列的元素值为采用第一计算规则对该两个序列中的另一个序列的元素值与该另一个序列对应的第一序列计算得到的值，由于一个序列对中的两个序列存在上述关系，因此终端设备接收到经过信道、噪声、载波频偏(简称频偏)等非理想因素影响后的信号时，可以采用目标计算规则对该序列对中的一个序列和另一个序列进行计算处理，从而消除频偏影响，提高抗频偏性能，同时消除频偏后仍然可以得到一个第四序列，该第四序列保留了第一序列的特性，从而方便终端设备准确的确定定时位置。
根据前述方法，图7a为本申请实施例提供的一种信号发送装置的示意图，如图7a所示，该信号发送装置可以为网络设备10，也可以为芯片或电路，如可设置于网络设备内的芯片或电路。该网络设备10对应上述方法中的网络设备。如图7a所示，该信号发送装置可以包括处理模块00和发送模块01；其中：
处理模块00，可用于对发送模块01所要发送的第一信号进行以上方法所描述的相应的处理并通过所述发送模块01发送所述第一信号。
其中，发送模块01可以采用图7b中的收发器140实现，处理模块00可以采用处理器110实现，或者可以采用处理器110和存储器120实现。
具体细节，可以参考以上方法中的描述，在此不予赘述。
比如，处理模块00，用于生成第一信号，所述第一信号中包括至少一个序列对，所述至少一个序列对中每个序列对包括两个序列，所述两个序列中的一个序列的元素值为采用第一计算规则对所述两个序列中的另一个序列的元素值与所述另一个序列所对应的第一序列的元素值进行计算得到的值，其中，所述至少一个序列对中每个序列以及所述第一序列为长度大于1的复数序列。
发送模块01，用于向终端设备发送所述处理模块生成的第一信号。
示例性的，所述另一个序列所对应的第一序列为第二序列的子序列。
示例性的，所述第一计算规则包括乘法规则、共轭乘法规则、除法规则和共轭除法规则中的至少一种规则。
示例性的，所述另一个序列为采用第二计算规则对N个序列计算得到的序列，所述N为大于或者等于2的自然数。
示例性的，所述序列对中的所述两个序列中的所述一个序列和所述另一个序列为相邻时域符号携带的序列。
示例性的，所述第一信号用于指示终端设备是否存在与所述终端设备关联的寻呼调度信息，和/或，所述第一信号用于指示终端设备所处小区的小区标识。
请参照图7b所示，为本发明实施例提供的另一种信号发送装置的结构示意图，如图所示，该信号发送装置可以包括：处理器110和存储器120。该存储器120用于存储指令，该处理器110用于执行该存储器120存储的指令，以使所述信号发送装置实现前述如图4网络设备侧所对应的方法。
进一步的，该信号发送装置还可以包括收发器140其中，处理器110用于执行该存储器110存储的指令，以控制收发器140接收信号，或者控制收发器140发送信号，完成上述方法中网络设备侧的步骤。其中，收发器140可以包括接收器和发送器，其中，接收器和发送器可以为相同或者不同的物理实体。当接收器和发送器为相同的物理实体时，可以统称为收发器140。所述存储器110可以集成在所述处理器110中，也可以与所述处理器110分开设置。
作为一种实现方式，收发器240的功能可以考虑通过收发电路或者收发的专用芯片实现。处理器210可以考虑通过专用处理芯片、处理电路、处理器或者通用芯片实现。
作为另一种实现方式，可以考虑使用通用计算机的方式来实现本申请实施例提供的网络设备。即将实现处理器210，接收器240和发送器250功能的程序代码存储在存储器中，通用处理器通过执行存储器中的代码来实现处理器210，接收器240和发送器250的功能。
所述信号发送装置所涉及的与本申请实施例提供的技术方案相关的概念，解释和详细说明及其他步骤请参见前述方法或其他实施例中关于这些内容的描述，此处不做赘述。
图7c为本申请实施例提供的一种网络设备的结构示意图，如可以为基站的结构示意图。如图7c所示，该基站可应用于如图2所示的系统中。基站10包括一个或多个射频单元，如远端射频单元(remote radio unit，RRU)101和一个或多个基带单元(basebandunit，BBU)(也可称为数字单元，digital unit，DU)102。所述RRU101可以称为收发单元、收发机、收发电路、或者收发器等等，其可以包括至少一个天线1011和射频单元1012。所述RRU101部分 主要用于射频信号的收发以及射频信号与基带信号的转换，例如用于向终端设备发送上述实施例中所述的第一信号。所述BBU102部分主要用于进行基带处理，对基站进行控制等。所述RRU101与BBU102可以是物理上设置在一起，也可以物理上分离设置的，即分布式基站。
所述BBU102为基站的控制中心，也可以称为处理单元或者处理模块，主要用于完成基带处理功能，如信道编码，复用，调制，扩频等等。例如所述BBU(处理单元)可以用于控制基站执行上述方法实施例中关于网络设备的操作流程。
在一个示例中，所述BBU102可以由一个或多个单板构成，多个单板可以共同支持单一接入制式的无线接入网(如LTE网)，也可以分别支持不同接入制式的无线接入网。所述BBU102还包括存储器1021和处理器1022。所述存储器1021用以存储必要的序列。例如存储器1021存储上述实施例中的用于生成第一信号的序列等。所述处理器1022用于控制基站进行必要的动作，例如用于控制基站执行上述方法实施例中关于网络设备的操作流程。所述存储器1021和处理器1022可以服务于一个或多个单板。也就是说，可以每个单板上单独设置存储器和处理器。也可以是多个单板共用相同的存储器和处理器。此外每个单板上还可以设置有必要的电路。
如图8a所示，为本发明实施例提供的一种信号接收装置的结构示意图，该信号接收装置可以为终端设备，也可以为芯片或电路，比如可设置于终端设备的芯片或电路。该终端设备可以对应上述方法中的终端设备。如图8a所示，该设备可以包括接收模块02和处理模块03；其中：
接收模块02，可用于接收网络设备发送的第一信号。所述处理模块03可用于对接收模块02所接收的第一信号进行以上方法所描述的相应的处理。
其中，接收模块02可以采用图8b中的收发器240实现，处理模块03可以采用处理器210实现，或者，可以采用处理器210和存储器220实现。
具体细节，可以参考以上方法中的描述，在此不予赘述。
比如，接收模块02，用于接收第一信号，所述第一信号中包括至少一个序列对，所述至少一个序列对中每个序列对包括两个序列，所述两个序列中的一个序列的元素值为采用第一计算规则对所述两个序列中的另一个序列的元素值与所述另一个序列所对应的第一序列的元素值进行计算得到的值；其中，所述至少一个序列对中每个序列以及所述第一序列为长度大于1的复数序列；
处理模块03，用于根据目标计算规则，对所述接收模块02接收的两个序列中的一个序列的元素值和所述两个序列中的另一个序列的元素值进行计算，获取所述另一个序列所对应的第三序列，以及采用所述第一序列和所述第三序列获取定时位置。
请参照图8b所示，为本发明实施例提供的另一种信号接收装置的结构示意图，如图所示，该信号接收装置可以包括：包括处理器210和存储器220。该存储器220用于存储指令，该处理器210用于执行该存储器220存储的指令，以实现如上图4终端设备侧对应方法中的步骤。
进一步的，该信号接收装置还可以包括收发器240。处理器210用于执行该存储器220 存储的指令，以控制收发器240接收信号，或者控制收发器240发送信号，完成上述方法中终端设备侧的步骤。其中，收发器240可以包括接收器和发送器，接收器和发送器可以为相同或者不同的物理实体。当接收器240和发送器250为相同的物理实体时，可以统称为收发器240。所述存储器220可以集成在所述处理器210中，也可以与所述处理器210分开设置。
作为一种实现方式，收发器240的功能可以考虑通过收发电路或者收发的专用芯片实现。处理器210可以考虑通过专用处理芯片、处理电路、处理器或者通用芯片实现。
作为另一种实现方式，可以考虑使用通用计算机的方式来实现本申请实施例提供的终端设备。即将实现处理器210，收发器功能的程序代码存储在存储器中，通用处理器通过执行存储器中的代码来实现处理器210，收发器240的功能。
该信号接收装置所涉及的与本申请实施例提供的技术方案相关的概念，解释和详细说明及其他步骤请参见前述方法或其他实施例中关于这些内容的描述，此处不做赘述。
图8c为本申请提供的一种终端设备的结构示意图。该终端设备可适用于图2所示出的系统中。为了便于说明，图8c仅示出了终端设备的主要部件。如图8c所示，终端设备10包括处理器、存储器、控制电路、天线以及输入输出装置。处理器主要用于对所接收的信号进行处理，以及对整个终端设备进行控制，执行软件程序，处理软件程序的数据，例如用于支持终端设备执行上述信号接收方法实施例中所描述的动作。存储器主要用于存储软件程序和数据，例如存储上述实施例中所描述的序列。控制电路主要用于基带信号与射频信号的转换以及对射频信号的处理。控制电路和天线一起也可以叫做收发器，主要用于收发电磁波形式的射频信号。输入输出装置，例如触摸屏、显示屏，键盘等主要用于接收用户输入的数据以及对用户输出数据。
当终端设备开机后，处理器可以读取存储单元中的软件程序，解释并执行软件程序的指令，处理软件程序的数据。当需要通过无线发送数据时，处理器对待发送的数据进行基带处理后，输出基带信号至射频电路，射频电路将基带信号进行射频处理后将射频信号通过天线以电磁波的形式向外发送。当有数据发送到终端设备时，射频电路通过天线接收到射频信号，将射频信号转换为基带信号，并将基带信号输出至处理器，处理器将基带信号转换为数据并对该数据进行处理。
本领域技术人员可以理解，为了便于说明，图8c仅示出了一个存储器和处理器。在实际的终端设备中，可以存在多个处理器和存储器。存储器也可以称为存储介质或者存储设备等，本发明实施例对此不做限制。
作为一种可选的实现方式，处理器可以包括基带处理器和中央处理器，基带处理器主要用于对通信协议以及通信数据进行处理，中央处理器主要用于对整个终端设备进行控制，执行软件程序，处理软件程序的数据。图8c中的处理器集成了基带处理器和中央处理器的功能，本领域技术人员可以理解，基带处理器和中央处理器也可以是各自独立的处理器。本领域技术人员可以理解，终端设备可以包括多个基带处理器以适应不同的网络制式，终端设备可以包括多个中央处理器以增强其处理能力。所述基带处理器也可以表述为基带处理电路或者基带处理芯片。所述中央处理器也可以表述为中央处理电路或者中央处理芯片。对通信协议以及通信数据进行处理的功能可以内置在处理器中，也可以以软件程序的形式存储在存储单元中，由处理器执行软件程序以实现基带处理功能。
示例性的，在发明实施例中，可以将具有收发功能的天线和控制电路视为终端设备20的接收模块201，将具有处理功能的处理器视为终端设备20的处理模块202。
根据本申请实施例提供的方法，本申请实施例还提供一种通信系统，其包括前述的网络设备和至少一个前述的终端设备。
应理解，在本申请实施例中，处理器可以是中央处理单元(Central Processing Unit，CPU)，该处理器还可以是其他通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现成可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
该存储器可以包括只读存储器和随机存取存储器，并向处理器提供指令和数据。存储器的一部分还可以包括非易失性随机存取存储器。
在实现过程中，上述方法的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。为避免重复，这里不再详细描述。
还应理解，本文中涉及的第一、第二、第三、第四以及各种数字编号仅为描述方便进行的区分，并不用来限制本发明实施例的范围。
应理解，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。 当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (24)

  1. 一种信号发送方法，其特征在于，包括：
    网络设备生成第一信号，所述第一信号中包括至少一个序列对，所述至少一个序列对中每个序列对包括两个序列，所述两个序列中的一个序列的元素值为采用第一计算规则对所述两个序列中的另一个序列的元素值与所述另一个序列所对应的第一序列的元素值进行计算得到的值，其中，所述至少一个序列对中每个序列以及所述第一序列为长度大于1的复数序列；
    所述网络设备向终端设备发送所述第一信号。
  2. 如权利要求1所述的方法，其特征在于，所述另一个序列所对应的第一序列为第二序列的子序列。
  3. 如权利要求1或2所述的方法，其特征在于，所述第一计算规则包括乘法规则、共轭乘法规则、除法规则和共轭除法规则中的至少一种规则。
  4. 如权利要求1或2所述的方法，其特征在于，所述另一个序列为采用第二计算规则对N个序列计算得到的序列，所述N为大于或者等于2的自然数。
  5. 如权利要求1所述的方法，其特征在于，所述序列对中的所述两个序列中的所述一个序列和所述另一个序列为相邻时域符号携带的序列。
  6. 如权利要求1-5任意一项所述的方法，其特征在于，所述第一信号用于指示终端设备是否存在与所述终端设备关联的寻呼调度信息，和/或，所述第一信号用于指示终端设备所处小区的小区标识。
  7. 一种信号接收方法，其特征在于，包括：
    终端设备接收第一信号，所述第一信号中包括至少一个序列对，所述至少一个序列对中每个序列对包括两个序列，所述两个序列中的一个序列的元素值为采用第一计算规则对所述两个序列中的另一个序列的元素值与所述另一个序列所对应的第一序列的元素值进行计算得到的值；其中，所述至少一个序列对中每个序列以及所述第一序列为长度大于1的复数序列；
    所述终端设备根据目标计算规则，对所述两个序列中的一个序列的元素值和所述两个序列中的另一个序列的元素值进行计算，获取所述另一个序列所对应的第三序列；
    所述终端设备采用所述第一序列和所述第三序列获取定时位置。
  8. 如权利要求7所述的方法，其特征在于，所述第一计算规则包括乘法规则、共轭乘法规则、除法规则和共轭除法规则中的至少一种规则；
    所述终端设备根据目标计算规则，对所述两个序列中的一个序列的元素值和所述两个序列中的另一个序列的元素值进行计算，获取所述另一个序列所对应的第三序列，包括：
    所述终端设备将所述两个序列中的所述另一个序列的共轭序列与所述两个序列中的所述一个序列相乘，获得所述另一个序列所对应的第三序列，所述另一个序列的共轭序列的元素值是所述另一个序列的元素值的共轭复数。
  9. 如权利要求7或8所述的方法，其特征在于，所述终端设备采用所述第一序列和所述第三序列获取定时位置，包括：
    所述终端设备将所述第一序列和所述第三序列进行卷积运算或循环卷积运算，并基于运算结果确定定时位置。
  10. 如权利要求7或8所述的方法，其特征在于，所述另一个序列所对应的第一序列为第二序列的子序列；
    所述终端设备采用所述第一序列和所述第三序列获取定时位置，包括：
    所述终端设备获取第四序列，所述第四序列为所述至少一序列对中每个序列对中所述另一个序列所对应的第三序列组成的序列；
    所述终端设备将所述第二序列和所述第四序列进行卷积运算或循环卷积运算，并基于运算结果确定定时位置。
  11. 一种信号发送装置，其特征在于，包括：
    处理模块，用于生成第一信号，所述第一信号中包括至少一个序列对，所述至少一个序列对中每个序列对包括两个序列，所述两个序列中的一个序列的元素值为采用第一计算规则对所述两个序列中的另一个序列的元素值与所述另一个序列所对应的第一序列的元素值进行计算得到的值，其中，所述至少一个序列对中每个序列以及所述第一序列为长度大于1的复数序列；
    发送模块，用于向终端设备发送所述处理模块生成的第一信号。
  12. 如权利要求11所述的装置，其特征在于，所述另一个序列所对应的第一序列为第二序列的子序列。
  13. 如权利要求11或12所述的装置，其特征在于，所述第一计算规则包括乘法规则、共轭乘法规则、除法规则和共轭除法规则中的至少一种规则。
  14. 如权利要求11或12所述的装置，其特征在于，所述另一个序列为采用第二计算规则对N个序列计算得到的序列，所述N为大于或者等于2的自然数。
  15. 如权利要求11所述的装置，其特征在于，所述序列对中的所述两个序列中的所述一个序列和所述另一个序列为相邻时域符号携带的序列。
  16. 如权利要求11-15任意一项所述的装置，其特征在于，所述第一信号用于指示终端设备是否存在与所述终端设备关联的寻呼调度信息，和/或，所述第一信号用于指示终端设备所处小区的小区标识。
  17. 一种信号接收装置，其特征在于，包括：
    接收模块，用于接收第一信号，所述第一信号中包括至少一个序列对，所述至少一个序列对中每个序列对包括两个序列，所述两个序列中的一个序列的元素值为采用第一计算规则对所述两个序列中的另一个序列的元素值与所述另一个序列所对应的第一序列的元素值进行计算得到的值；其中，所述至少一个序列对中每个序列以及所述第一序列为长度大于1的复数序列；
    处理模块，用于根据目标计算规则，对所述接收模块接收的两个序列中的一个序列的元素值和所述两个序列中的另一个序列的元素值进行计算，获取所述另一个序列所对应的第三序列，以及采用所述第一序列和所述第三序列获取定时位置。
  18. 如权利要求17所述的装置，其特征在于，所述处理模块具体用于，在所述目标计算规则包括乘法规则、共轭乘法规则、除法规则和共轭除法规则中的至少一种规则时，将所述两个序列中的所述另一个序列的共轭序列与所述两个序列中的所述一个序列相乘，获得所述另一个序列所对应的第三序列，所述另一个序列的共轭序列的元素值是所述另一个序列的元素值的共轭复数。
  19. 如权利要求17或18所述的装置，其特征在于，所述处理模块具体用于：
    将所述第一序列和所述第三序列进行卷积运算或循环卷积运算，并基于运算结果确定定时位置。
  20. 如权利要求17或18所述的装置，其特征在于，所述处理模块具体用于，在所述另一个序列所对应的第一序列为第二序列的子序列时，获取第四序列，所述第四序列为所述至少一序列对中每个序列对中所述另一个序列所对应的第三序列组成的序列，将所述第二序列和所述第四序列进行卷积运算或循环卷积运算，并基于运算结果确定定时位置。
  21. 一种计算机可读存储介质，包括计算机程序，当其在计算机上运行时，使得如权利要求1至6项任意一项所述的方法被执行。
  22. 一种计算机可读存储介质，包括计算机程序，当其在计算机上运行时，使得如权利要求7至10项任意一项所述的方法被执行。
  23. 一种信号通信装置，包括处理器，其特征在于，所述处理器用于执行如权利要求1至6项任意一项所述的方法。
  24. 一种信号通信装置，包括处理器，其特征在于，所述处理器用于执行如权利要求7至10项任意一项所述的方法。
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