WO2019025117A1

WO2019025117A1 - Method for producing an optoelectronic component, and optoelectronic component

Info

Publication number: WO2019025117A1
Application number: PCT/EP2018/068270
Authority: WO
Inventors: Thomas Oszinda; Attila Molnar; Fabian Kopp
Original assignee: Osram Opto Semiconductors Gmbh
Priority date: 2017-08-01
Filing date: 2018-07-05
Publication date: 2019-02-07
Also published as: US20210091269A1; DE112018003935A5; US11322655B2; DE102017117414A1; DE112018003935B4

Abstract

The invention relates to a method for producing an optoelectronic component (100), comprising the following steps: A) providing a semiconductor layer sequence (1) on an auxiliary carrier (7), B) applying a first insulation layer (2) to the n-doped semiconductor layer (11) over the full surface, C) structuring the first insulation layer (11), D) applying a first metallization (4) for contacting the p-doped semiconductor layer (12) and a second metallization (5) for contacting the n-doped semiconductor layer (11) to the n-doped semiconductor layer (11) over the full surface such that the first and second metallizations (4, 5) are connected to each other, E) performing chemical-mechanical polishing of the first and second metallizations (4, 5) such that a planar surface (261) is produced and the two metallizations (4, 5) are spatially separated from each other, and F) applying a second insulation layer (3) for electrically insulating the first and second metallizations (4, 5), and subsequently structuring the second insulation layer (3).

Description

description

METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT AND OPTOELECTRONIC COMPONENT

The invention relates to a method for producing an optoelectronic component. Furthermore, the invention relates to an optoelectronic component, which is preferably produced by the method described here.

An object of the invention is to provide a method for

To provide an optoelectronic component and to provide an optoelectronic device that can be easily produced inexpensively.

This object is achieved by a method for producing an optoelectronic component according to claim 1 and an optoelectronic component according to independent claim 15. Advantageous embodiments and modifications of the invention are the subject of the dependent claims.

In at least one embodiment, the method for producing an optoelectronic component comprises steps A) to F), in particular in the order given here:

A) Providing a semiconductor layer sequence. The

Semiconductor layer sequence is on a subcarrier

provided. The semiconductor layer sequence has at least one n-doped semiconductor layer, at least one p-doped semiconductor layer and an active layer arranged between the p- and n-doped semiconductor layers. B) applying a first insulating layer. The first

Insulation layer is applied over the whole area to the n-doped

Semiconductor layer applied. C) structuring the first insulation layer.

D) Applying a first metallization. The first

Metallization serves to contact the p-doped

Semiconductor layer. At the same time or subsequently or before the application of the first metallization takes place

Applying a second metallization. The second

Metallization serves to contact the n-doped

Semiconductor layer. The first and / or second metallization is wholly on the n-doped semiconductor layer

applied, so that the first and second metallization are interconnected. In particular, the

Metallizations electrically and / or mechanically interconnected. E) Chemical-mechanical polishing of the first and second metallizations to form a planar surface and spatially separate the two metallizations

be separated. In particular, the two are

Metallizations electrically and / or mechanically separated from each other.

F) applying a second insulating layer to

electrical isolation of the first and second metallization. Subsequently, the second insulation layer can be patterned.

According to at least one embodiment, the method comprises a step A), providing a Semiconductor layer sequence. The semiconductor layer sequence comprises at least one n-doped semiconductor layer, at least one p-doped semiconductor layer and active elements arranged between the n- and p-doped semiconductor layer

Layers. The semiconductor layers are preferably based on a III-V compound semiconductor material. "To a

Nitride compound semiconductor material "in the present context means that the semiconductor layer sequence or at least one layer thereof comprises a III-nitride compound semiconductor material, preferably In _x AlyGa _] _- _x -yN, where 0 <x <1, 0 <y <1 and x + y <1. This material does not necessarily have to be mathematically exact

Having composition according to the above formula. Rather, it may contain one or more dopants as well as additional

Have components that are the characteristic

physical properties of In _x AlyGa _] __ _x _yN material in

Essentially not change. For the sake of simplicity, however, the above formula contains only the essential constituents of the crystal lattice (In, Al, Ga, N), even if these may be partially replaced by small amounts of other substances.

The semiconductor layer sequence includes an active layer with at least one pn junction and / or with one or more quantum well structures. During operation of the component, electromagnetic radiation is generated in the active layer. A wavelength of the radiation is preferably in the ultraviolet and / or visible range, in particular at wavelengths between 420 nm inclusive and

including 680 nm, for example between 440 nm inclusive and 480 nm inclusive.

In accordance with at least one embodiment, the optoelectronic component is a light-emitting diode, or LED for short. The component is then preferably configured to emit blue, yellow, green, red, orange and / or white light. In accordance with at least one embodiment, the

Semiconductor layer sequence applied to a subcarrier. As a subcarrier, for example, serve sapphire. Alternatively, the auxiliary carrier may comprise, for example, silicon, silicon carbide or gallium nitride.

The subcarrier can be removed again in subsequent process steps. Preferably, the subcarrier is removed, and a carrier made of, for example, silicon or containing silicon is integrated into the optoelectronic device.

According to at least one embodiment, the method comprises a step B), applying a first

Insulation layer over the entire surface of the n-doped

Semiconductor layer. Preferably, the first

Insulation layer in step C) structured.

In accordance with at least one embodiment, after step A) and before step B), step AI), application of a,

in particular dielectric, layer on the p-doped

Semiconductor layer. In particular, the, in particular dielectric, layer is applied in direct mechanical and / or electrical contact to the p-doped semiconductor layer. Preferably, the, in particular

dielectric, layer formed from ITO or contains ITO. The, in particular dielectric, layer may also be formed from other oxides or contain other oxides. The, in particular dielectric, layer preferably contains a transparent, conductive oxide (TCO). The, in particular dielectric layer may be formed in this case also electrically conductive. Transparent, electrically conductive oxides (TCO) are

transparent, electrically conductive materials, usually metal oxides, such as zinc oxide, tin oxide,

Cadmium oxide, titanium oxide, indium oxide, indium tin oxide (ITO) or aluminum zinc oxide (AZO). In addition to binary

Metal oxygen compounds such as ZnO, SnO 2 or Ιη 2θ 3 also include ternary metal oxygen compounds such as Zn 2 SnO 2, Cd Sn 3, Zn SnO 3, Mgln 2Ozi, GalnO 3, 2ηηηθ 5 or In 4 Sn 3 O 2 or mixtures of different transparent, conductive oxides into the group of TCOs.

Furthermore, the TCOs do not necessarily correspond to one

stoichiometric composition and may also be p- or n-doped.

The, in particular dielectric, layer protects the p-doped semiconductor layer, which is in particular p-GaN, before subsequent photo and plasma etching processes. In particular, the dielectric layer is formed as a thin film layer. This means here that the layer thickness is between 10 and 100 nm.

In addition, the, in particular dielectric, layer can serve as a starting layer for the first mirror element (p-mirror layer stack) in a later method step. According to at least one embodiment takes place after step

AI) and before step B) step A2), structuring the p-doped semiconductor layer, so that the n-doped

Semiconductor layer is exposed, the exposure of the n- doped semiconductor layer optionally by means of a first mask, in particular a photomask, and plasma etching takes place. The plasma etching takes place after application of the first mask. Alternatively or additionally, the first mask can subsequently be removed by means of a lift-off method. When

For example, lift-off can be performed by the so-called "pull-off process" or lift-off by means of a wet-lift process. In accordance with at least one embodiment, the first

Insulation layer on the structured p-doped

Semiconductor layer applied.

In accordance with at least one embodiment, the component has a second insulation layer. The first and / or second insulation layer are formed as a distributive Bragg reflector (DBR, distributed bragg reflector) with an alternative layer sequence. As a layer sequence can

For example, an alternate arrangement of a layer of silicon dioxide and a layer of titanium dioxide or an alternating layer sequence of silicon dioxide and niobium oxide serve. In particular, the final distributive Bragg reflector depends on the final wavelength of the semiconductor layer sequence. The first and / or second insulating layer can serve to protect the so-called Combometall - for example, a subsequent layer containing silver or silver - for the n-contact or to realize a construction without Combometall. The first and / or second insulating layers may be formed by conventional manufacturing methods, such as sputtering, chemical vapor deposition (CVD), PE-CVD, atomic layer deposition techniques deposition, ALD) or spin on. These methods are sufficiently known to the person skilled in the art and are therefore not explained in detail here. For example, the alternating layer sequence of at least two layer pairs of titanium dioxide and

Silica or niobium oxide and silicon dioxide exist or have. In accordance with at least one embodiment, the method comprises a step C), structuring the first one

Insulation layer. The structuring of the first

Insulation layer takes place in step C) between adjacent structured regions of the p-doped semiconductor layer.

Alternatively or additionally, the first insulation layer is structured in a ring.

Alternatively, the first insulating layer can be structured in a double ring, so that a core of the first

Insulation layer is generated by the second

Metallization is surrounded annularly.

According to at least one embodiment, this is done

Structuring the first insulation layer by means

Plasma process.

According to at least one embodiment, after step C), a first mirror element for the p-doped

Semiconductor layer and / or a second mirror element for the n-doped semiconductor layer applied. It can first the first mirror element and then the second

Mirror element or vice versa, so first the second Mirror element and then the first mirror element are applied to the structured regions of the p-doped semiconductor layer. In particular, the first mirror element is directly on the, in particular dielectric, layer

arranged. The second dielectric mirror element is preferably arranged directly on the first mirror element. In addition, the second dielectric mirror element may overlay the regions of the first isolation layer that are between adjacent p-type semiconductor layer regions

are arranged extend.

In accordance with at least one embodiment, the method comprises a step D), applying a first metallization. The first metallization is used for electrical contacting of the p-doped semiconductor layer. Additionally or alternatively, a second metallization can be applied. The second metallization serves for contacting the n-doped semiconductor layer. The first and / or the second

Metallization can be applied over the entire area to the n-doped

Semiconductor layer can be applied, so that the first and second metallization with each other mechanically and / or

are electrically connected.

In accordance with at least one embodiment, the first and the second metallization are generated simultaneously. In other words, here the contacts of both the p-doped

Semiconductor layer and the n-doped semiconductor layer can be produced in one process step. This saves time

Material and costs.

According to at least one embodiment, the first one

Mirror element made of or molded with silver. In addition, the first mirror element may comprise zinc oxide. The share of Silver in the first mirror element is in particular larger than the proportion of the zinc oxide. Alternatively or additionally, the second mirror element comprises silver. In addition, the second mirror element may comprise zinc oxide. The proportion of silver in the second mirror element may be smaller than the proportion of zinc oxide.

In accordance with at least one embodiment, the second

Mirror element over the entire surface of the n-doped

Semiconductor layer applied.

According to at least one embodiment, the first and / or second metallization by means of sputtering, PVD, PE-CVD,

Electroplating (plating) applied. Alternatively or

In addition, the first and / or second metallization comprises platinum, gold and titanium or the individual metals separately.

In accordance with at least one embodiment, the method comprises a step E), chemical-mechanical polishing of the first and the second metallization, so that a planar surface is produced. In addition, by the

chemical-mechanical polishing spatially separated the two metallizations. The chemical-mechanical polishing, also chemical-mechanical planarization (CMP, English chemical mechanical polishing or chemical mechanical planarization), is a

Polishing process in wafer processing to remove thin layers evenly. The method is known per se to those skilled in the art, but not in a process flow as described herein. There is therefore no further explanation of the actual process. According to at least one embodiment, the method comprises a step F), applying a second

Insulation layer. The second insulation layer is used for electrical insulation of the first and / or second

Metallization. The second insulation layer can be patterned in a subsequent process.

According to at least one embodiment, after step F), a step G), applying a third metallization.

In accordance with at least one embodiment, alternatively or additionally after step G), a step H), application of a contact metallization takes place. According to at least one embodiment, after step H), a step I), bonding of the generated in step H)

Arrangement on a support, wherein the support is silicon

optional. The subcarrier will in particular

away .

According to at least one embodiment, a step J) is carried out after step I), introducing a trench, in particular a mesa trench, at least into one doped one

Semiconductor layer. Preferably, the trench extends into the n-doped semiconductor layer. In addition, the trench may also extend from the n-doped semiconductor layer into the active layer. Additionally or alternatively, the trench may extend from the n-doped semiconductor layer via the active layer into the p-doped semiconductor layer.

In accordance with at least one embodiment, the method after step J) comprises a step K), roughening the Semiconductor layer sequence on the carrier

opposite side. The roughening can be through

different method, whereby the wet-chemical process by means of KOH is the most common. Alternatively, however, a combination of lithography and plasma etching is conceivable.

Subsequently, a passivation layer can be applied to the n-doped semiconductor layer. When

Passivation layer may serve, for example, silica or alumina or a combination of both.

In accordance with at least one embodiment, the method after step K) comprises a step L), structuring or opening the passivation layer such that the p-doped one

Semiconductor layer is open at least in a small area for applying a contact pad. Subsequently, a metal can be introduced as a contact pad. As a metal, for example, a platinum-gold bilayer can be used in particular with thin platinum.

The invention further relates to an optoelectronic

Component. Preferably, the method described here can produce the optoelectronic component described here. All explanations and definitions for the optoelectronic apply to the process

Component and vice versa.

According to at least one embodiment, the

Optoelectronic component on a semiconductor layer sequence. The semiconductor layer sequence comprises at least one n-doped semiconductor layer, at least one p-doped one

Semiconductor layer and one between the p- and n-doped Semiconductor layers arranged active layer. The

Component has a plurality of openings, so at least two openings on. The openings extend through the p-doped semiconductor layer to the n-doped semiconductor layer. The openings are seen in plan view annular or double ring shaped. in the

Seen lateral cross-section, the openings are at least partially arranged laterally to the p-doped semiconductor layer. The p-doped semiconductor layer is preferably structured in this case, that is, has

Areas of p-doped semiconductor layers. The

Breakthroughs have sidewalls. The side walls are covered by a first insulation layer. Within the

Breakthroughs, a core of the first insulating layer is arranged in the case of the double-ring-shaped configuration. in the

Side cross-section seen between the core of the first insulating layer and the side walls of the openings covering the first insulating layer is a second

Metallization for contacting the n-doping

Semiconductor layer arranged. Seen in plan view so the second metallization surrounds the core of the first

Insulation layer annular.

In accordance with at least one embodiment, this is

optoelectronic component obtainable by a method described here.

The inventors have recognized that by the step E) described here, ie the chemical-mechanical polishing of the first and second metallization, the different heights of the individual previously applied layers or elements can be removed and thus the surface can be planarized. The method described here differs from conventional methods in some process steps and in particular in the arrangement of the order of

Process steps. First, a p-doped

Semiconductor layer, in particular of p-GaN, are patterned and then a first insulating layer are applied vertically. This can be generated by so-called photo processes. Thus, an insulation between the p- and n-doped semiconductor layer, in particular the p- and n-GaN can be generated. The first insulation layer can

be formed annular or double annular. Alternatively, it is also possible to use non-annularly shaped insulation layers that are in the region of adjacent p-doped layers

Semiconductor layer sequence are arranged to be used. The annular or double annular shaped first

Insulation layers increase the brightness by increasing the reflective surface. In addition, the first and second

Metallization, so the contacts for the n- and p-doped semiconductor layer, are applied at the same time, which in turn takes place several process steps in comparison to the insertion of a single step E).

The step E), ie the chemical mechanical polishing, is required in order to planarize the component and to electrically isolate or separate the first and second metallization from one another, so that a short circuit during operation is avoided. With the method described here, compared to conventionally described processes, at least two photo-structuring steps and various

Lifting procedure can be saved.

The first insulation layer may be made, for example

Be formed silica. Alternatively, the first Isolation layer also be formed from a distributive Bragg reflector. The first insulating layer is arranged vertically in the lateral cross section. In addition, a so-called combo mirror can be used on the top of the n-contacting. In particular, however, a so-called combo mirror is completely dispensed with here. The second insulating layer can be applied planar to the device and thus the adhesion to the n-metal can be controlled. This can be done, for example

Plasma treatment, such as with oxygen flow, whereby the underlying layers are not affected.

Overall, the inventors have realized that this

described method increases the so-called performance, saves costs and leads to an easy process flow. In addition, fewer defects during the production of bonding as well as other process steps are saved. The inventors have realized that by using the chemical mechanical polishing to planarize the first and second

Metallization a planar surface can be generated, which remains until the application of the bonding structures. In addition, the first insulation layer is vertical in

Side cross-section seen shaped so that it serves to isolate the p- and n-doped semiconductor layer.

The first and second metallizations are also applied simultaneously. The first and second mirror elements may consist of or comprise silver. Alternatively or additionally, zinc oxide or, alternatively, other materials may be added, which the p-doped semiconductor layer during further process steps, such as photographic or

Structuring steps, protect. The mirror elements can have a layer structure of ITO / silicon dioxide / ITO / silver respectively. The, in particular dielectric, layer can serve as a protective layer for the p-doped semiconductor layer during the process flow. The ITO serves as a p-contact area. The overlying S1O2 serves as

Dielectric mirror, that is, a part of the light is already reflected here. The second ITO layer is necessary because silver does not adhere to S1O2, that is, it serves first

Line as a bonding agent. Alternatively to ITO as a material for, in particular

Dielectric layer, other so-called TCOs can be used. The first and second insulation layer can also consist of a single layer or alternatively of a so-called DBR. The DBR as vertical pn isolation preferably comprises a combination of silica with other materials such as titanium dioxide, tantalum oxide,

Magnesium fluoride or a combination thereof. The annular or double annular configuration of the first insulating layer also reduces the absorption losses of the light. In particular, no DBR remains in the middle and the metallization corresponds to a cylinder and no ring.

The metallizations can be applied for example by means of PVD or PE-CVD or electroplating. Alternatively, a nucleation layer may be used for electroplating. Due to the new process flow, the

Combo mirrors are omitted if the first or second isolation layer is a DBR. In this case hardly any light comes up and thus can not be absorbed on or in the second metallization. If a small part may get through, the combo mirror can also be present. The inventors have realized that by the method described herein, the photopatterning steps can be reduced from seven to five. In addition, the

Lifting procedure can be reduced from seven to three or five. It is also possible that the so-called

Combo mirror is not used. For the lift-off method, in particular for the wet-chemical lift Off, a plasma-based lift can alternatively also be carried out. This one

described method produces fewer breaks and holes during bonding, less peeling during bonding due to the planarization of the first and second

Metallization. It creates a better surface and adhesion control. The method described here shows the following further

Advantages on:

The process flow including chemical mechanical polishing ^¬ described here produces flat structures for Nachmetallisierung. In addition, in particular, the first and second metallizations are generated at the same time. The p-doped semiconductor layer is etched as a first process step. A novel type of first mirror element made of ITO / silicon oxide / ITO / silver is used. The, in particular dielectric, layer can be used as a protective layer for the p-doped semiconductor layer during the production. In addition, a DBR can be used as pn isolation in the horizontal direction. In addition to the standard cylindrical VIA shape in which a round contact is formed, in the corresponding photostructuring step, a

annular VIA are generated. This can reduce the effective contact area. This is possible because of the Current flow within the standard cylindrical VIA's occurs mostly at the edge.

The so-called p-n metallization is applied simultaneously in addition to sputtering and PVD processes. In addition, chemical plating can be easily incorporated into these process flows

to get integrated. Instead of chemical plating, electroplating or electroless plating may also be used. The use of a combo mirror does not have to

mandatory, because the DBR of the first

Insulation layer and / or second insulation layer

shows enough reflection. The planarization allows a homogeneous metallization and

Bonding metal film deposition. This will produce fewer breaks and holes during the process. Furthermore, a flat surface allows for better adhesion within the layers, resulting in a reduction of delamination

or withdrawals guaranteed. This increases the yield of the optoelectronic components.

Further advantages, advantageous embodiments and

Further developments emerge from the following in

Compound described with the figures

Exemplary embodiments.

Show it:

Figures 1A to 26B each show a method for producing an optoelectronic device according to a

Embodiment and FIGS. 27A to 52 show a method for producing an optoelectronic component according to FIG

Comparative Example. In the exemplary embodiments and in the figures, identical, identical or identically acting elements can each be provided with the same reference numerals. The illustrated elements and their proportions with each other are not to be regarded as true to scale. Rather, individual elements, such as layers, components, components and areas for exaggerated representability and / or better understanding can be displayed exaggerated.

FIGS. 1A to 26B show a method for producing an optoelectronic component according to FIG

Embodiment.

1A shows the arrangement of the respective layers or elements, in particular the arrangement of a subcarrier 7, on which an n-doped semiconductor layer 11,

For example, from n-GaN, and arranged thereon, a p-doped semiconductor layer 12, for example of p-GaN, is applied. The subcarrier 7 may be formed of sapphire, for example.

FIG. 1B shows the associated side cross section.

In the subsequent method step, as shown in FIGS. 2A and 2B, a layer 14, in particular dielectric, can be applied over the whole area to the p-doped semiconductor layer 12

be applied. The, in particular dielectric, layer 14 is preferably formed of ITO. The, in particular dielectric, layer 14 serves to protect the p-doped Semiconductor layer 12 for further process steps, in particular photo and plasma etching, the later

respectively. Preferably, the, in particular dielectric, layer 14 is formed as a thin film. The, in particular dielectric, layer 14 may in a subsequent

Process step as start layer for the first

Mirror element (p-mirror layer sequence) serve. FIG. 2B shows the associated side cross-section. As shown in FIGS. 3A and 3B, a first mask, photomask, 19 can then be applied to the, in particular

dielectric, layer 14 are applied. The first mask

19 is applied structured. Everyone can do it

commercially available positive or negative coatings are used. These materials are well known to those skilled in the art and therefore will not be described in detail here

explained.

Subsequently, as shown in Figures 4A and 4B, the, in particular dielectric, layer 14 and the p-doped

Semiconductor layer 12 are structured. The structuring

20 can be done for example by means of plasma etching. Thus, the n-type semiconductor layer 11 can be exposed. As shown in FIG. 4B, the p-doped semiconductor layer 12 is no longer over the whole area on the n-doped

Semiconductor layer 11 is arranged, but forms areas which are laterally spaced apart. In a subsequent process step, the

Photoresist mask or the first mask 19 by means of a

Lifting process, such as resist strip or wet-chemical lift-off removed (Figures 5A and 5B). Subsequently, as shown in FIGS. 6A and 6B, the first insulating layer 2 can be applied over the whole area to the n-doped semiconductor layer 11. The first

Insulation layer 2 surrounds the p-doped semiconductor layer 12 and the, in particular dielectric, layer 14

frame-like and is thus in direct mechanical and / or electrical contact with the n-doped semiconductor layer 11, the p-doped semiconductor layer 12 and / or the, in particular dielectric, layer 14th

The first insulating layer 2 can be made up as a distributive Bragg reflector with an alternating layer sequence, as shown in FIG. 6C. As an alternating

Layers of layers of silicon dioxide and titanium dioxide or silicon dioxide and niobium dioxide or silicon dioxide and tantalum dioxide can be applied.

The first insulation layer 2 can be applied, for example, by means of common methods, such as sputtering, CVD, PE-CVD, ALD or spin-on. Due to the design of the first insulating layer 2 as a DBR can on a so-called

Combo mirror or a combo metal for n-contacting

be waived. Subsequently, a second photomask 23 on the first

Insulation layer 2 are applied. The photomask 23 or the second mask 23 can be applied in such a way that subsequently the first insulating layer 2 is structured in an annular manner 35 (see top view in FIG. 7C).

Alternatively or additionally, the first insulation layer 2 may be double-ring-shaped 34 (see top view in FIG. 7D). be structured and additionally have a core of the first insulating layer 102 (Figure 7D).

FIGS. 7C and 7D each show a plan view of an optoelectronic component, FIG. 7A shows a schematic arrangement of the layer sequence and FIG. 7B shows a schematic side view of an optoelectronic component during manufacture. Subsequently, as shown in FIGS. 8A and 8B, the first insulation layer 2 may be patterned 24 in the region between adjacent p-doped semiconductor layer regions 12 and thus openings 36 may be produced. Thus, the first insulating layer 2 has side walls 101 and a core 102.

FIGS. 9A and 9B show the removal of the second mask 23. The removal can be effected by means of a lift-off method, such as resist strip or wet-chemical lift Off. The use of the, in particular dielectric, layer 14, in particular of ITO, can protect the p-doped semiconductor layer 12 during the plasma processes and can also be the first layer for the first mirror element 9. If the insulating layer is a DBR layer, the

Dry etching process are controlled very accurately on the end point determination in the etching process. The sequence of layers makes it possible to determine exactly when the last layer will be etched before reaching the ITO. This allows for a special application which is gentle on the ITO.

In the next process step, as shown in Figures 10A and 10B, a third mask 25 in the region of

structured first insulating layer 2 are applied. This process step is optional and may be missing.

In addition, this application of the third mask 25 serves as protection of the first insulating layer 2, so that the first and / or second mirror element 9, 10 can be applied without hindrance.

The application of the first mirror element 9 may be optional. The first mirror element 9 can be applied first and then the second mirror element 10.

Alternatively, only the second mirror element 10 and then the first mirror element 9 can be applied.

Alternatively, only the second mirror element 10 can be arranged on the, in particular dielectric, layer 14.

FIGS. IIA and IIB show the application of the first mirror element 9. The first mirror element 9 serves for the p-doped semiconductor layer 12. The first mirror element 9 may comprise silver. In addition, the first

Mirror element 9 have zinc oxide. The proportion of silver in the first mirror element is preferably greater than the proportion of zinc oxide. The first mirror element 9 is the so-called mirror for the p-doped semiconductor layer 12 and may also comprise ITO / silicon dioxide / ITO / silver / zinc oxide by a so-called curing step. The

Layer structure is subject to the following function. The first ITO layer is used for power distribution. The silica serves as the first reflector and is intended to reflect most of the incoming light. The second ITO layer is needed for the silver to adhere. Silver adheres very poorly to pure silica and therefore requires a so-called

Adhesion promoter. Subsequently, as shown in FIGS. 12A and 12B, the third mask 25 may be removed again.

Subsequently, as shown in FIGS. 13A and 13B, the second mirror element 10 may be applied. The second mirror element 10 may have the entire area on the n-doped

Semiconductor layer 11 are arranged. The second

Mirror element 10 covers both the structured first insulation layer 2 and the first mirror element 9. The second mirror element 10 preferably comprises zinc oxide and silver. The proportion of zinc oxide in the second

Mirror element 10 is preferably larger than the proportion of silver. The second mirror element 10 can also be used on the

Top of the so-called p-contact pads are applied without negatively affecting this, so can a

Photo structuring step can be saved.

In the subsequent method step, as shown in FIGS. 14A and 14B, the first and second metallizations 4, 5 can be applied. The first and / or second metallization 4, 5 are applied over the whole area to the n-doped semiconductor layer 11. For this purpose, all possible techniques, such as sputtering, PVD, PE-CVD or electroplating can be used. In the subsequent process step, as shown in FIGS. 15A and 15B, the first and second metallization 4, 5 or the metals, which later on can be the first and the second

Metallization 4, 5 form, chemically-mechanically polished 26 (CMP), so that a planar surface 261 is generated and the two metallizations 4, 5 are spatially separated from each other. As material for the first and second

Metallization 4, 5 can be used platinum, gold, copper, aluminum and titanium. The first and second Metallization 4, 5 can be removed by means of CMP at a removal rate of a few nanometers per minute up to 100 nm per minute and more. In the case of using non-inert metals such as copper, it is important to precede the subsequent process, deposition of a second insulating layer, an in situ reduction step. In this case, before the isolation of the insulation is a reducing gas such as

Hydrogen or ammonia introduced into the deposition chambers.

In the further method step F) according to claim 1 and as shown in FIGS. 16A and 16B, a second insulation layer 3 for the electrical insulation of the first and second metallization 4, 5 can be applied over the whole area. The second insulation layer 3 is applied horizontally when viewed in the lateral cross-section.

The second insulation layer 3 may have the same configurations as the first insulation layer 2. In particular, the second insulation layer 3 may be formed as a DBR with an alternating layer sequence of silicon dioxide, titanium dioxide or silicon dioxide and niobium oxide.

If the vertical isolation 2 is sufficient for the

Light reflection and light absorption, this is not critical. In addition, a new insulation material may be used, such as silicon dioxide, silicon nitride,

Silicon oxycarbide, silicon carbonitride,

Organosilicon compounds. The second insulation layer 3 can be applied, for example, by means of sputtering, CVD, PE-CVD, ALD or spin-on. Subsequently, as shown in Figs. 17A and 17B, a new mask 27 (fourth mask) may be applied. The fourth mask 27 is structured on the second

Insulation layer 3 is arranged.

As shown in FIGS. 18A and 18B, subsequently the second insulation layer 3 can be patterned. In particular, the second insulation layer 3 is patterned 28 in regions above adjacent p-doped semiconductor layer regions 12.

In the subsequent method step, as shown in FIGS. 19A and 19B, the fourth mask 27 can be removed again.

Subsequently, a third metallization 6 can be applied over the whole area to the arrangement. The third

Metallization 6 may include, for example, titanium, platinum, gold, nickel, or a combination thereof. The third metallization 6 serves for contacting the n-doped semiconductor layer 11.

In a subsequent method step, as shown in FIGS. 21A and 21B, a contact metallization 16 may be applied. The contact metallization 16 serves for bonding pad metallization.

The contact metallization 16 has a layer sequence. The layer sequence may comprise a layer, such as titanium, nickel, tin, titanium-gold or a combination thereof. Subsequently, a layer of titanium tungsten nitride, followed by a layer of gold and then a layer of platinum can be arranged. The contact metallization 16 may be a carrier 8, in particular made of silicon, downstream.

In the subsequent method step, as shown in FIGS. 22A and 22B, the component can be rotated and the auxiliary carrier 7 removed and the carrier 8 arranged. The carrier 8 may be made of silicon, the subcarrier 7 of sapphire. In a subsequent method step, a trench 15 can be introduced within the n-doped semiconductor layer 11, as shown in FIGS. 23A and 23B. In particular, the trench 15 extends through the entire n-doped semiconductor layer 11 as far as the p-doped semiconductor layer 12.

In the subsequent method step, as shown in FIGS. 24A and 24B, the n-doped semiconductor layer 11 can be roughened. As a final layer can be a

Passivation layer 18 are applied. The

Passivation layer may be formed of, for example, silicon dioxide, alumina, another optically transparent material, or a combination of different materials.

Subsequently, as shown in FIGS. 25A and 25B, an opening 29 can be introduced into the passivation layer 18 as far as the p-doped semiconductor layer 12. This opening serves for contacting the p-doped semiconductor layer 12.

In a subsequent method step, as shown in FIGS. 26A and 26B, a metallization 30 can be introduced into the opening as a contact pad. Subsequently, the remaining lacquer of the lithographic step with the help of a plasma-based or a wet-chemical based process in a so-called lift-off process (LOP) removed. In particular, the process steps indicated in FIGS. 1A to 26B are in the order given here

perform. Alternatively, individual process steps can also be omitted or the order can be reversed.

The inventors have realized that the one described here

Method has various new process steps. The method comprises a process step of chemical mechanical polishing ^¬. Thus, a vertical first insulating layer 2 can be generated, which serves to separate the first and second metallization 4, 5. In addition, the CMP can be terminated when the two metallizations 4, 5 are separated from each other. In an earlier process step, a mesa trench can also be generated. To damage the p-doped

To prevent semiconductor layer, a, in particular dielectric, layer is arranged as a protective layer on the p-doped semiconductor layer, which can be removed later. In the method described here, the, in particular dielectric, layer is still in the component, but can alternatively be removed again.

The mirror elements can be completely or partially applied. The mirror elements may be silver and / or zinc oxide or ITO and / or silicon dioxide or other post-mesa dielectric materials

respectively. The, in particular dielectric, layer or Insulating layer may include materials that have sufficient insulation and also the

Reduce light absorption. Preferably, a DBR comprising a combination of repeating units of layers of silica with titania, niobium oxide,

Tantalum oxide or magnesium fluoride. In addition, the insulation layers can also be made of single layers, such as

Silicon dioxide, be shaped. After applying the,

especially dielectric, layer can be a

Plasma structuring done in a later

Process step the first and second metallization

to be able to raise at the same time. In this step, the horizontal isolation layer is patterned to produce a vertical separation between the p-spreader and the n-VIA. The structuring can be done differently. It can be done a subsequent structuring of the first and second mirror element. The deposition of the mirror (for p-GaN and n-GaN) can take place in different forms. Depending on the respective material are the following

Scenarios conceivable. The p-GaN level becomes first and

completely isolated. The p-GaN level is initially but incompletely deposited. That is possible if that

Last layer material is the same as what is used in the first layer of the n-mirror. Alternatively, however, the n-GaN mirror can also be deposited first. The same applies here as stated for the p-GaN level. If the last layer is identical to the material with the first layer of the subsequent step (p-GaN mirror), the mirror can be incompletely deposited. Depending on

Mirror material, the sequence and the material combination are very flexible. The metallization can be applied by sputtering or PVD or PE-CVD or other methods such as electroplating. As metallization, gold, silver or copper or

Alloys thereof are used. The metallizations become particularly after the CMP step, which leads to an electrical separation of the first and second

Metallization and planarization of the wafer leads produced. The CMP should be stopped at the latest at the step where the vertical insulation is located.

After successful CMP, the second insulating layer can be applied horizontally. The application can

for example, by CVD, sputtering, PE-CVD or spin on, ALD done. The second insulating layer may comprise a material of silicon dioxide, silicon nitride and may also be formed as a DBR. After the second insulation layer is applied, an opening in the region of the "n"

respectively. For a photo process can be used for structuring, with this photomask in subsequent

Process steps are removed again. It can any metals, such as gold and silver, as

Metallization be used. Usually one will

Combometall used, but which can be omitted here by using a DBR. This saves more

Process steps and costs. The semiconductor device may then be treated with further process steps known to those skilled in the art. For example, flipping, laser lift-off (LLO), surface roughening, insertion of mesa trenches, passivation, contact structuring and

Metallization. FIGS. 27A to 52 show a method for producing an optoelectronic component according to FIG

Comparative Example. Figures 27A and 27B show the provision of a

Semiconductor layer sequence comprising a p-doped

Semiconductor layer 12, an n-type semiconductor layer 11, an active layer (not shown here) on a

Subcarrier 7, which is formed for example of sapphire.

Subsequently, a photo-patterning with a first mask 19, as shown in Figures 28A and 28B, take place. In this case, as shown in FIGS. 29A and 29B, a first mirror element 9 can then be applied in regions which are not covered by the first mask 19 on the p-doped semiconductor layer 12.

In the subsequent method step, as shown in Figures 30A and 30B, the first mask 19 by means of

Lift-off procedures, such as resist strip or wet-chemical lift off, are removed.

Subsequently, as shown in Figs. 31A and 31B, a second photomask 23 may be applied. The second

Photomask 23 is to serve to produce the first metallization 4 (p-metallization).

FIGS. 32A and 32B show the application of the first metallization 4, which may in particular comprise platinum, gold and titanium. The first metallization 4 is applied between the second mask 23 on the first mirror element 9. In a subsequent method step, as shown in FIGS. 33A and 33B, the second mask 23 can by means of

Lifting procedures, such as resist strip and wet-chemical lift off, are removed.

Subsequently, as shown in FIGS. 34A and 34B, a first insulation layer 2 can be applied over the whole area to the p-doped semiconductor layer 12. The first

Insulation layer 2 here typically corresponds to a double layer consisting of two insulating materials, such as silicon oxide and silicon nitride.

Subsequently, a next photo-structuring step can take place. For this purpose, as shown in FIGS. 35A and 35B, a further third mask 25 can be applied.

Subsequently, the areas not covered by the third photomask 25 and shown in Figs. 36A and 36B can be removed. It will therefore be the p-doped

Semiconductor layer 12 and the n-doped semiconductor layer 11 exposed by plasma etching. Subsequently, the third mask 25 can be removed by lift-off methods such as resist strip or wet-chemical lift off (see FIGS. 37A and 37B).

FIG. 37C is a plan view of FIG

Optoelectronic component according to a

Comparative example. In this case, the openings, which are produced by the structuring, formed annular.

In contrast to the method according to the embodiment, the openings described here have no core of

Insulation layer 101 on. Subsequently, a second insulating layer 3 over the entire surface, as shown in Figures 38A and 38B,

be applied. The second insulation layer 3 may be multi-layered of three layer pairs of SiN and S1O2.

FIGS. 39A and 39B show that a further photo-structuring step subsequently takes place. For this purpose, a fourth photomask 27 can be applied. This serves for

Generation of the second mirror element 10 for the n-doped semiconductor layer 11.

FIGS. 40A and 40B show the structuring step by means of etching, and FIGS. 41A and 41B show the application of the second mirror element 10 into the previously structured one

Areas.

The second mirror element 10 may be formed of, for example, zinc oxide and silver. Subsequently, as shown in Figs. 42A and 42B, the fourth mask 27 may be removed again.

Subsequently, as shown in FIGS. 43A and 43B, another photostructuring step may be performed by means of a fifth mask 31. This structuring step serves for

Applying a so-called combo mirror 32 (see Figures 44A and 44B).

The combo mirror 32 may be, for example, titanium, silver, platinum and / or titanium. The combo mirror 32 is applied to the previously patterned areas on the second mirror element 10. Subsequently, as shown in Figs. 45A and 45B, the fifth mask can be removed by lift-off method such as resist strip or wet-chemical lift Off. In a subsequent method step, as shown in FIGS. 46A and 46B, the third metallization 6 can be used for contacting the n-doped semiconductor layer 11

be applied over the entire surface. The third metallization 6 may comprise titanium, platinum, gold and nickel.

Subsequently, the contact metallization 16, as already described in relation to the method according to the exemplary embodiment and to which reference is made here, can be applied.

Also, the carrier 8 can then be applied and the subcarrier 7 are removed. The carrier 8 may be made of silicon (see FIGS. 47A to 48B). Figures 49A and 49B show the introduction or etching of a mesa trench 15 within the n-doped one

Semiconductor layer 11 analogous to the method as described according to the embodiment. Subsequently, as shown in FIGS. 50A and 50B, the n-type semiconductor layer 11 may be roughened 17 and a passivation layer 18 may be deposited. The

Passivation layer 18 can be opened again (FIG. 51) to introduce a contact pad 30 (FIG. 52).

The result is a device that is also known as a so-called UX3 chip. In comparison with the method according to one embodiment described here, no one takes place here chemical-mechanical polishing. In addition, the first

Metallization and second metallization also not in one step, especially at the same time, applied. According to at least one embodiment, the first

Metallization and the second metallization 4, 5 the same material or the same material composition. In addition, the component described here can have a double-ring-shaped structured insulation layer which has a core of the first insulation layer, wherein the second metallization 5 surrounds the core of the first insulation layer 102 in an annular manner.

The ones described in connection with the figures

Embodiments and their features can also be combined with each other according to further embodiments, even if such combinations are not explicitly shown in the figures. Furthermore, the embodiments described in connection with the figures may have additional or alternative features as described in the general part.

The invention is not limited by the description based on the embodiments of these. Rather, the invention includes every new feature as well as any combination of

Features, which includes in particular any combination of features in the claims, even if this feature or this combination itself is not explicitly in the

Claims or embodiments is given.

This patent application claims the priority of German Patent Application 10 2017 117 414.1, the disclosure of which is hereby incorporated by reference. Reference sign list

100 optoelectronic component

1 semiconductor layer sequence

11 n-doped semiconductor layer

12 p-doped semiconductor layer

13 active layer

2 first insulation layer

21 first layer of the first insulating layer 22 second layer of the second insulating layer

101 side walls of the first insulation layer

102 core of the first insulation layer

3 second insulation layer

4 first metallization (p-metallization) 5 second metallization (n-metallization)

6 third metallization

7 subcarriers

8 carriers

9 first mirror element

10 second mirror element

14 in particular dielectric layer

15 ditch

16 contact metallization

17 roughening

18 passivation layer

19 first mask

20 first structuring

23 second mask

24 second structuring

25 third mask

26 CMP (chemical-mechanical polishing)

261 planar surface

27 fourth mask 28 fourth structuring

29 structuring

31 fifth mask

32 combo mirror

33 breakthroughs

330 side walls

30 pad metallization

34 double-ringed

35 annular

36 breakthroughs

Claims

claims

1. A method for producing an optoelectronic

Device (100) with the steps:

A) providing a semiconductor layer sequence (1) on an auxiliary carrier (7), wherein the semiconductor layer sequence (1) at least one n-doped semiconductor layer (11), at least one p-doped semiconductor layer (12) and one between the p- and n-doped Having semiconductor layers (11, 12) arranged active layer (13),

B) application of a first insulation layer (2) over the whole area to the n-doped semiconductor layer (11),

C) structuring the first insulation layer (11),

D) applying a first metallization (4) to

Contacting the p-doped semiconductor layer (12) and a second metallization (5) for contacting the n-doped semiconductor layer (11) over the entire surface of the n-doped semiconductor layer (11), so that the first and second metallization (4, 5) with each other are connected,

E) chemical-mechanical polishing of the first and the second metallization (4, 5), so that a planar surface (261) is generated and the two metallizations (4, 5) are spatially separated from each other, and

F) applying a second insulating layer (3) to

electrical insulation of the first and second metallization (4, 5) and then structuring the second

Insulation layer (3).

2. The method according to claim 1,

wherein the first metallization (4) and the second

Metallization (5) are generated simultaneously.

3. The method according to any one of the preceding claims, wherein step A) takes place after step A) and before step B):

AI) applying a, in particular dielectric, layer (14) on the p-doped semiconductor layer (12).

4. The method according to claim 3,

wherein after step AI) and before step B) step A2) takes place:

A2) structuring of the p-doped semiconductor layer (12), so that the n-doped semiconductor layer (11) is exposed, wherein the exposure of the n-doped semiconductor layer (11) by means of a first mask (19) and plasma etching takes place, optionally the first mask (19) is subsequently removed by means of a lift-off method.

5. The method according to any one of the preceding claims, wherein the first and / or second insulating layer (2, 3) as a distributive Bragg reflector with an alternating

Layer sequence (21, 22) of silicon dioxide and titanium dioxide or silicon dioxide and niobium oxide is applied.

6. The method according to any one of the preceding claims, wherein the structuring of the first insulating layer (2) in step C) takes place between adjacent structured regions of the p-doped semiconductor layer (12), wherein the first

Insulating layer (2) is structured annularly or wherein the first insulating layer (2) is structured double-ring-shaped, so that a core of the first insulating layer (102) is generated by the second metallization (5)

is surrounded annularly.

7. The method according to any one of the preceding claims, wherein after step C) a first mirror element (9) for the p-doped semiconductor layer (12) and / or a second

Mirror element (10) for the n-doped semiconductor layer (11) is applied, wherein first the first mirror element (9) and then the second mirror element (10) or

vice versa applied to the structured regions of the p-doped semiconductor layer (12).

8. The method according to claim 7,

wherein the first mirror element (9) comprises silver and zinc oxide, the proportion of silver in the first

Mirror element (9) is greater than the proportion of zinc oxide or wherein the second mirror element (10) comprises silver and zinc oxide, wherein the proportion of silver in the second

Mirror element (10) is smaller than the proportion of zinc oxide.

9. The method according to any one of the preceding claims,

wherein the second mirror element (10) is applied over the whole area to the n-doped semiconductor layer (11).

10. The method according to any one of the preceding claims, wherein the first and / or second metallization (4, 5) by means of sputtering, PVD, PE-CVD, electroplating is applied

and / or wherein the first and / or second metallization (4, 5) comprises platinum, gold and titanium.

11. The method according to any one of the preceding claims, wherein after step F) a step G) is carried out:

G) application of a third metallization (6) and / or after step G) a step H) takes place:

H) applying a contact metallization (16).

12. The method according to any one of the preceding claims, wherein after step H) a step I) takes place:

I) transposing the arrangement generated in step H) to a

Carrier (8), wherein the carrier (8) comprises silicon.

13. The method according to any one of the preceding claims, wherein after step I), a step J) is carried out:

J) introducing a trench (15) at least into the one n-doped semiconductor layer (11).

14. The method according to any one of the preceding claims, wherein after step J) a step K) is carried out:

K) roughening the semiconductor layer sequence (1) on the opposite side of the carrier (8) and applying a passivation layer (18) on the n-doped

Semiconductor layer (11).

15. Optoelectronic component having

a semiconductor layer sequence (1), wherein the

Semiconductor layer sequence (1) at least one n-doped

Semiconductor layer (11), at least one p-doped

Semiconductor layer (12) and between the p- and n-doped semiconductor layers (11, 12) arranged active layer (13),

- A plurality of openings (33) extending through the p-doped semiconductor layer (12) to the n-doped

Semiconductor layer (11) extend, wherein the openings (33) seen in plan view are formed doppelringförmig and seen in lateral cross-section at least partially laterally to the p-doped semiconductor layer (12) are arranged, wherein the openings (33) side walls (330), which of a first insulating layer (2) are covered, wherein within the openings (33) a core of the first insulating layer (102) is arranged, wherein seen in the lateral cross-section a second metallization (5) for contacting the n-doped semiconductor layer (11) between the core of the first insulation layer (102) and the first insulation layer (2) covering the sidewalls of the openings (330)

is arranged, which, seen in plan view, the core of the first insulating layer (102) annularly surrounds.