WO2019021095A1 - Système de commande de charge d'une cellule auxiliaire et procédé de détection d'anomalie dans une cellule auxiliaire - Google Patents

Système de commande de charge d'une cellule auxiliaire et procédé de détection d'anomalie dans une cellule auxiliaire Download PDF

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WO2019021095A1
WO2019021095A1 PCT/IB2018/055129 IB2018055129W WO2019021095A1 WO 2019021095 A1 WO2019021095 A1 WO 2019021095A1 IB 2018055129 W IB2018055129 W IB 2018055129W WO 2019021095 A1 WO2019021095 A1 WO 2019021095A1
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Prior art keywords
secondary battery
data
transistor
image data
memory cell
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PCT/IB2018/055129
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English (en)
Japanese (ja)
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智 大下
耕平 豊高
真里奈 檜山
敏行 伊佐
亮太 田島
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株式会社半導体エネルギー研究所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H01M10/48—Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

Definitions

  • One aspect of the present invention relates to an object, a method, or a method of manufacturing.
  • the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
  • One embodiment of the present invention relates to a method for manufacturing a semiconductor device, a display device, a light-emitting device, a power storage device, a lighting device, or an electronic device.
  • the present invention relates to a charge control system, a charge control method, and an electronic device having a secondary battery.
  • One embodiment of the present invention relates to a vehicle or a vehicle electronic device provided in the vehicle.
  • a power storage device refers to all elements and devices having a power storage function.
  • a storage battery also referred to as a secondary battery
  • a lithium ion secondary battery such as a lithium ion secondary battery, a lithium ion capacitor, an all solid battery, an electric double layer capacitor, and the like are included.
  • one aspect of the present invention relates to a neural network and a charge control system using the same. Further, one aspect of the present invention relates to a vehicle using a neural network. Further, one embodiment of the present invention is not limited to a vehicle, and can also be applied to a power storage device for storing power obtained from a power generation facility such as a solar power generation panel installed in a structure or the like. Further, one embodiment of the present invention relates to an electronic device using a neural network. Further, one aspect of the present invention relates to an abnormality detection system using a neural network.
  • lithium ion secondary batteries having high output and high energy density can be used in portable information terminals such as mobile phones, smartphones, tablets, or notebook computers, portable music players, digital cameras, medical devices, or hybrid vehicles (HEVs).
  • portable information terminals such as mobile phones, smartphones, tablets, or notebook computers, portable music players, digital cameras, medical devices, or hybrid vehicles (HEVs).
  • HEVs hybrid vehicles
  • demand is rapidly expanding with the development of the semiconductor industry, such as next-generation clean energy vehicles such as electric vehicles (EVs) and plug-in hybrid vehicles (PHEVs), and modern information as a source of rechargeable energy Has become an integral part of the
  • a plurality of secondary batteries are connected in series or in parallel to form a protective circuit, which is used as a battery pack (also referred to as a battery pack).
  • the battery pack refers to a battery pack in which a plurality of secondary batteries are accommodated together with a predetermined circuit in a container (metal can, film outer package) in order to facilitate handling of the secondary battery.
  • the battery pack is provided with an ECU (Electronic Control Unit) to manage the operation state.
  • ECU Electronic Control Unit
  • neural networks In recent years, machine learning techniques such as artificial neural networks (hereinafter referred to as neural networks) have been actively developed.
  • Patent Document 1 shows an example of using a neural network to calculate the remaining capacity of a secondary battery.
  • Safety of the secondary battery is secured by detecting the abnormality of the secondary battery and changing the operating conditions of the secondary battery, for example, when a phenomenon that reduces the safety of the secondary battery is detected or foreseen. Do.
  • Another problem is to install a system for detecting an abnormality in a secondary battery by using artificial intelligence (AI) such as a neural network in a portable information terminal or an electric vehicle.
  • AI artificial intelligence
  • a secondary battery abnormality detection system for detecting an abnormality of a secondary battery with a low cost IC chip in a portable information terminal or an electric vehicle.
  • the actual and accurate remaining amount of the secondary battery can be obtained by discharging and detecting the secondary battery, but it is possible to actually discharge it to make the remaining amount zero and use the device Since it can not be done, the remaining amount is estimated from the parameter (battery voltage or integrated current) having a correlation with the remaining amount. Further, since the secondary battery uses a chemical reaction, it may be erroneous to estimate the remaining amount instantaneously based on a small amount of data.
  • An object of one embodiment of the present invention is to provide a novel battery management circuit, a power storage device, an electronic device, and the like.
  • the charge characteristics of the secondary battery are converted into image data, and a normal characteristic and an abnormal characteristic of the secondary battery are determined based on the learning data using a convolutional neural network (CNN) model. After determining that the state of the secondary battery is abnormal, a warning for the secondary battery exhibiting abnormal characteristics, or a stop of use, or a proposal for replacement of the secondary battery, or a charge control system for the secondary battery that changes the charging condition I assume.
  • CNN convolutional neural network
  • the graph with the charge voltage value on the vertical axis and the time on the horizontal axis is converted to 8-bit gray gradation image data, and then normal Turn
  • the image data is array data as shown in FIG. 2 (B) and FIG. 2 (D).
  • it is 8-bit gray tone, one pixel is represented by 8 bits, it indicates data including only brightness without color information, and gray scale is represented by 256 tones.
  • normalization is transforming data etc. based on a fixed rule, organizing in order to handle it efficiently, and making it easy to use.
  • the data is labeled as normal or abnormal.
  • the features of the image are extracted by CNN processing and pooling processing.
  • the filter parameters of the CNN for extracting features are "weights”.
  • it is determined whether the secondary battery is normal or abnormal by using a fully coupled neural network.
  • the image data is used for calculation, and the image data is not displayed. Since image data is used, determination can be made using CNN.
  • the detection accuracy can be improved, and it can be determined whether the secondary battery is a normal secondary battery or an abnormal secondary battery.
  • the charge operation may be performed on a load such as a circuit under certain conditions to acquire data. It is preferable that the power used for acquisition be supplied not from the secondary battery to be monitored, but from another secondary battery or an external power source. In addition, it is preferable that the arithmetic processing and the like be performed by supplying power from an external power supply.
  • the external power source refers to a power source such as an AC power source or a DC power source, such as a battery mounted on an electric vehicle or a stationary battery installed in a house.
  • the charge control system for a secondary battery disclosed herein comprises: a secondary battery; measurement means for measuring the voltage value of the secondary battery; and means for converting the measured voltage value of the secondary battery into image data And determination means for classifying the image data.
  • the determination means is a product-sum operation, and the determination means includes a transistor using an oxide semiconductor material as the semiconductor layer.
  • a transistor including an oxide semiconductor material typically, an oxide semiconductor containing In, Ga, and Zn in a channel for the memory can store data with relatively little power, power can be saved.
  • operating systems for software various operating systems such as Windows (registered trademark), UNIX (registered trademark), and macOS (registered trademark) can be used.
  • Software programs include Python, Go, Perl, Ruby, Prelog, Visual Basic, C, C ++, Swift, Java (registered trademark),. It can be written in various programming languages such as NET.
  • Applications may also be created using frameworks such as Chainer (available in Python), Caffe (available in Python and C ++), TensorFlow (available in C, C ++, and Python).
  • the CNN model requires a large amount of convolution processing. Since convolution processing uses product-sum operation, an LSI chip capable of forming a power-saving product-sum operation circuit, in particular, an IC chip using a transistor using an oxide semiconductor material can be used. Alternatively, an IC (also referred to as an inference chip) incorporating an artificial intelligence (AI) system may be used. An IC incorporating an AI system may be called a circuit (microcomputer) that performs neural network operations.
  • a circuit microcomputer
  • creation of an algorithm is not limited to CNN, You may use SVR, RVM (Relevance Vector Machine), a random forest etc. Although the circuit configuration is increased, CNN and Long Short-Term Memory (LSTM) may be combined as appropriate.
  • RVM Relevance Vector Machine
  • LSTM Long Short-Term Memory
  • a method of detecting an abnormality of the secondary battery is also disclosed herein.
  • the voltage value of the secondary battery is measured in a first period, and the measured voltage value of the secondary battery is converted into first image data, The first image data is classified, the voltage value of the secondary battery is measured in a second period after the first period, and the measured voltage value of the secondary battery is converted into second image data. Then, the second image data is classified, and from the classification results of the first and second image data, determination of normality or abnormality is performed.
  • the length of the second period is equal to or less than the first period. Since a certain amount of information for feature extraction is required during the first period from the start of charging, it is preferable to make the first period longer.
  • the length of the first period is preferably determined based on the abnormal data among the learning data of the secondary battery. By setting the length of the second period to be equal to or less than the first period, it is possible to give real time characteristics.
  • the determination processing period may be extended in the vicinity of the middle of the charging period where the change is small in constant current charging, in order to reduce the power consumption.
  • the measurement of the voltage value of the secondary battery may be performed at regular intervals, and the number of measurements of the abnormality detection test by the AI system may be smaller than the number of measurements of the voltage value of the secondary battery.
  • one charging period of the secondary battery is characterized by switching to constant voltage charging after performing constant current charging, and including a first period and a second period. Both the first period and the second period may be set in the constant current charging period.
  • the charge voltage value in the first period is the vertical axis
  • the time is the horizontal axis
  • the converted graph is converted into 8-bit gradation image data and then normalized. It is determined whether the secondary battery is normal or abnormal by classifying the image data.
  • data from the charging start to the second period are used as image data Convert, normalize, perform CNN processing, and pooling processing, and determine whether the secondary battery is normal or abnormal by the fully coupled neural network.
  • the image data which is array data
  • the image data is used for calculation, and the image data is not displayed. Since image data that is array data is used, determination can be made using CNN. Further, the detection accuracy can be improved by learning fine tuning or subdivision of an abnormality, and it can be determined whether it is a normal secondary battery or an abnormal secondary battery.
  • the present invention can also be applied to a solid battery using a solid electrolyte and a fuel cell, and abnormality detection can be performed.
  • the solid electrolyte is not particularly limited as long as it can conduct lithium ions and contains a solid component.
  • ceramics, polymer electrolytes and the like can be mentioned.
  • the polymer electrolyte can be roughly divided into a polymer gel electrolyte containing an electrolyte solution and a polymer solid electrolyte not containing an electrolyte solution.
  • the change of the secondary battery can be accurately grasped, and can be reflected in the management of the degree of deterioration of the secondary battery.
  • the size and cost of the entire system can be reduced without degrading the accuracy of detecting an abnormality of the secondary battery.
  • the present invention it is possible to detect a micro short circuit of a secondary battery which has conventionally been difficult to detect accurately.
  • by accurately grasping the change of the secondary battery during charging and increasing the number of times of abnormality detection it is possible to immediately execute the charging stop, and it is possible to provide a safe charging method of the secondary battery. .
  • FIG. 7 is an example of a flowchart illustrating an embodiment of the present invention. They are an example of the charge characteristic which shows one mode of the present invention, and an example of image data. It is a flowchart at the time of learning. The figure which shows the structure of a neural network. 7 is an example of a flowchart illustrating an embodiment of the present invention. 7 is an example of a flowchart illustrating an embodiment of the present invention.
  • FIG. 18 is a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of
  • FIG. 18 is a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • 7A and 7B are a block diagram and a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • BRIEF DESCRIPTION OF THE DRAWINGS The block diagram which shows the structural example of AI system which concerns on 1 aspect of this invention.
  • 7 is an example of a flowchart illustrating an embodiment of the present invention.
  • FIG. 7 is a diagram showing, in chronological order, image data showing one embodiment of the present invention.
  • 5 is image data representing one embodiment of the present invention.
  • It is a figure which shows the neural network of a present Example.
  • FIG. 6 illustrates an example of an electronic device.
  • FIG. 6 illustrates an example of an electronic device.
  • FIG. 6 illustrates an example
  • Embodiment 1 In this embodiment, an example will be described in which a neural network is used to detect the occurrence of an abnormality (specifically, the occurrence of a microshort) of a secondary battery.
  • an abnormality specifically, the occurrence of a microshort
  • micro short refers to a minute short inside the secondary battery, not to the extent that the positive electrode and the negative pole of the secondary battery are shorted to cause a state in which charging and discharging are not possible. This refers to a phenomenon in which a short circuit current flows for a period of 10 nanoseconds or more and less than 1 microsecond.
  • the cause of the micro short is that the charge and discharge are performed multiple times, and the uneven distribution of the positive electrode active material causes local concentration of current at a part of the positive electrode and a part of the negative electrode, and a part of the separator The occurrence of a nonfunctional part or the generation of a side reaction product.
  • the neural network is first used to form the secondary battery. Try to detect an abnormality occurrence.
  • the state of the secondary battery to be judged is analyzed to create data.
  • the capacity of the secondary battery can be determined, for example, by the product of the current and time of the secondary battery.
  • the coulomb counter CC may be used to determine the capacity of the secondary battery.
  • the SOC (state of charge) of the secondary battery may be used.
  • the SOC of the secondary battery may be determined by estimation from the voltage of the secondary battery.
  • the fully charged state can also be said to be SOC 100%.
  • the fully charged state means a state in which the battery is charged to the range of the charge termination voltage.
  • the state of charge is indicated by an SOC that represents the amount of charge being charged relative to the capacity of the secondary battery.
  • the SOC is defined as the ratio of the remaining capacity to the maximum capacity of the secondary battery.
  • step S2 If the SOC is less than 50%, the process proceeds to the next step, charging start (step S2). If the SOC is 50% or more, the secondary battery is discharged by the discharge circuit to make the SOC less than 50%, preferably 20% or less.
  • step S3 Data on charge characteristics of the secondary battery is measured until charging is started to detect an abnormality and the battery is fully charged, and the measured data is stored in the memory unit (step S3).
  • the charge curve is obtained by imaging a graph obtained by accumulating the charge data, and an example of the charge curve is FIG. 2 (A) or FIG. 2 (C).
  • FIG. 2A and FIG. 2C show charge curves with the horizontal axis representing time and the vertical axis representing voltage. Also, by taking log data, it is possible to leave a record or history even if charging is interrupted between charging start and full charging, so that data on charging characteristics can be measured even if charging is started again. .
  • the obtained charge curve is converted into image data to obtain a plurality of input data (step S4).
  • a normal charge curve is obtained, the charge curve shown in FIG. 2A is obtained, which is converted into image data and visualized as shown in FIG. 2B.
  • a charge curve in which a micro short occurs is obtained in the second half of the charge, for example, the charge curve shown in FIG. 2C is obtained, and is converted into image data and visualized in FIG.
  • the charge curve is converted into image data of 8-bit gradation from 0 to 255.
  • the discharged state (low voltage) is black and the fully charged state is white.
  • the left of FIG. 2 (B) and FIG. 2 (D) has shown charge start, and the right has shown charge completion.
  • the input data is determined (step 5).
  • this determination or classification
  • processing of a neural network is performed and product-sum operation is used.
  • the features of the input data are classified as normal or abnormal using the weight parameters created at the time of training.
  • weight parameters also referred to as filters
  • feature data are extracted in advance using data for images with correct labels as input data
  • weight parameters for feature extraction are stored in an array, and weights are set for each minibatch size.
  • Update to learn The mini-batch size is the number of data samples of the mini-batch.
  • the learning sequence that is, the flow at the time of learning is illustrated in FIG. Error back propagation is used to update learning.
  • the feature of the image is extracted, it is judged whether it is normal or abnormal, the judgment result is compared with the correct answer label, and the rate of error is calculated. Update the weight values to reduce the error. The error is gradually reduced by repetitive learning, and the weight at the minimum is used for inference.
  • FIG. 2C and FIG. 2D are examples of data corresponding to data that can be regarded as an abnormality, which is classified as an abnormality of the secondary battery due to the occurrence of a microshort.
  • FIGS. 2C and 2D it is preferable to discontinue or replace the secondary battery.
  • start timing of the series of procedures may be determined by the user or may be automatically performed periodically.
  • FIG. 2 (B) and FIG. 2 (D) image data is visualized (image display when displayed on a display device).
  • the system configuration Can be simplified. If the system is simplified, the power used for computation can be reduced, and power saving can be achieved for the entire system.
  • Second Embodiment an example of the configuration of the neural network NN used in the neural network processing at step S5 shown in FIG. 1 in Embodiment 1, that is, when classifying the state of the secondary battery is shown.
  • FIG. 4 shows an example of a neural network of one embodiment of the present invention.
  • the neural network shown in FIG. 4 has an input layer IL, an output layer OL, and a hidden layer (intermediate layer) HL.
  • the neural network can be configured by a neural network having a plurality of hidden layers HL, that is, a deep neural network. Learning in a deep neural network may be called deep learning.
  • the output layer OL, the input layer IL, and the hidden layer HL each have a plurality of neuron circuits, and neuron circuits provided in different layers are connected via a synapse circuit.
  • the function to analyze the state of the secondary battery at a certain point is added to the neural network by learning. Then, when the measured secondary battery parameters are input to the neural network, calculation processing is performed in each layer. Arithmetic processing in each layer is performed by a product-sum operation of the output of the neuron circuit of the front layer and the weighting factor.
  • the layer-to-layer connection may be a full connection in which all neuron circuits are connected to each other, or a partial connection in which some neuron circuits are connected to each other.
  • a convolutional neural network may be used, in which only certain units are coupled between adjacent layers and have convolutional and pooling layers.
  • the CNN is used, for example, for classification of image data converted from data of charging characteristics.
  • an operation using image data and weight parameters is performed.
  • the pooling layer is preferably placed immediately after the convolutional layer.
  • the convolution layer has a function of performing convolution on image data.
  • the convolution is performed by repeating an operation using a part of the image data and the filter value of the weight parameter.
  • By convolution in the convolution layer features of the image data are extracted.
  • a weight parameter (also called a weight filter) can be used for the convolution.
  • the image data input to the convolutional layer is subjected to filter processing using weight parameters.
  • the data subjected to convolution is converted by the activation function and then output to the pooling layer.
  • the activation function ReLU (Rectified Linear Unit) or the like can be used.
  • ReLU is a normalized linear function that outputs "0" when the input value is negative and outputs the input value as it is when the input value is "0" or more.
  • a sigmoid function, a tanh function or the like can be used as the activation function.
  • the pooling layer has a function of performing pooling on image data input from the convolution layer. Pooling is a process of dividing image data into a plurality of regions, extracting predetermined data for each of the regions, and arranging the data in a matrix. Pooling reduces the image data while leaving the features extracted by the convolutional layer. As pooling, maximum pooling, average pooling, Lp pooling and the like can be used.
  • CNN convolutional neural network
  • the entire bonding layer be arranged.
  • the entire bonding layer may be arranged in multiple layers.
  • the entire combined layer has a function of determining whether the secondary battery is normal or abnormal using image data subjected to convolution and pooling.
  • this embodiment mode can be freely combined with Embodiment Mode 1.
  • FIG. 1 An example which is partially different from the first embodiment is shown in FIG. This is the same as FIG. 1 except that a plurality of abnormality determination outputs are prepared, so the detailed description will be omitted.
  • the first embodiment shows an example of classifying two types, normal and abnormal.
  • the accuracy of abnormality detection can be raised by finely classifying.
  • data of the occurrence of three types of micro shorts are stored at the time of learning, and using these data, it is classified as normal or abnormal.
  • this embodiment mode can be freely combined with Embodiment Mode 1.
  • Embodiment 4 In the present embodiment, an example which is partially different from the first embodiment is shown in FIG. The process is the same as that of FIG. 1 except that the value of the measured charge data and the like are stored in the memory unit in step S3, and thus the detailed description will be omitted.
  • Power saving can be achieved by using a transistor including an oxide semiconductor for the memory portion.
  • the configuration is useful because many arithmetic processes are performed with data held in the memory unit.
  • NOSRAM nonvolatile oxide semiconductor RAM
  • 2T type, 3T type a memory device using an OS transistor
  • OS memory a memory device using an OS transistor such as a NOSRAM
  • the OS memory is a memory that has at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor is a transistor with extremely small off current, the OS memory has excellent retention characteristics and can function as a non-volatile memory.
  • FIG. 7 shows an example of the configuration of the NOSRAM.
  • the NOSRAM 1600 shown in FIG. 7 includes a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660, and an output driver 1670.
  • the NOSRAM 1600 is a multivalued NOSRAM that stores multivalued data in one memory cell.
  • the memory cell array 1610 has a plurality of memory cells 1611, a plurality of word lines WWL and RWL, a bit line BL, and a source line SL.
  • the word line WWL is a write word line
  • the word line RWL is a read word line.
  • 3-bit (eight-valued) data is stored in one memory cell 1611.
  • the controller 1640 controls the entire NOSRAM 1600 in a centralized manner, writes the data WDA [31: 0], and reads the data RDA [31: 0].
  • the controller 1640 processes external command signals (for example, a chip enable signal, a write enable signal, etc.) to generate control signals for the row driver 1650, the column driver 1660 and the output driver 1670.
  • the row driver 1650 has a function of selecting a row to access.
  • the row driver 1650 includes a row decoder 1651 and a word line driver 1652.
  • Column driver 1660 drives source line SL and bit line BL.
  • the column driver 1660 includes a column decoder 1661, a write driver 1662, and a DAC (digital-to-analog conversion circuit) 1663.
  • the DAC 1663 converts 3-bit digital data into an analog voltage.
  • the DAC 1663 converts 32-bit data WDA [31: 0] into analog voltages every three bits.
  • the write driver 1662 has a function of precharging the source line SL, a function of electrically floating the source line SL, a function of selecting the source line SL, and an input of the write voltage generated by the DAC 1663 to the selected source line SL.
  • the output driver 1670 includes a selector 1671, an ADC (analog-digital conversion circuit) 1672, and an output buffer 1673.
  • the selector 1671 selects the source line SL to be accessed, and transmits the voltage of the selected source line SL to the ADC 1672.
  • the ADC 1672 has a function of converting an analog voltage into 3-bit digital data. The voltage of the source line SL is converted into 3-bit data in the ADC 1672, and the output buffer 1673 holds the data output from the ADC 1672.
  • the configurations of the row driver 1650, the column driver 1660, and the output driver 1670 described in this embodiment are not limited to the above. Arrangements of these drivers and wirings connected to the drivers may be changed according to the configuration or driving method of the memory cell array 1610 or the like, or functions of the drivers and wirings connected to the drivers are changed Or you may add. For example, part of the functions of the source line SL may be provided to the bit line BL.
  • each memory cell 1611 is 3 bits in the above description, the configuration of the storage device described in this embodiment is not limited to this.
  • the amount of information held by each memory cell 1611 may be 2 bits or less, or 4 bits or more.
  • the DAC 1663 and the ADC 1672 may not be provided.
  • FIG. 8A is a circuit diagram showing a configuration example of the memory cell 1611.
  • the memory cell 1611 is a 2T-type gain cell, and the memory cell 1611 is electrically connected to the word lines WWL and RWL, the bit line BL, the source line SL, and the wiring BGL.
  • the memory cell 1611 includes a node SN, an OS transistor MO61, a transistor MP61, and a capacitive element C61.
  • the OS transistor MO61 is a write transistor.
  • the transistor MP61 is a read transistor, and is formed of, for example, a p-channel Si transistor.
  • the capacitive element C61 is a holding capacitance for holding the voltage of the node SN.
  • the node SN is a data holding node and corresponds to the gate of the transistor MP61 here.
  • the NOSRAM 1600 can hold data for a long time.
  • bit line is a common bit line for writing and reading, but as shown in FIG. 8B, the bit line WBL functioning as a writing bit line and the reading bit line And the bit line RBL may be provided.
  • FIGS. 8C to 8E show other configuration examples of the memory cell.
  • FIGS. 8C to 8E show an example in which the write bit line WBL and the read bit line RBL are provided, but as shown in FIG. 8A, they are shared by writing and reading. Bit lines may be provided.
  • a memory cell 1612 shown in FIG. 8C is a modified example of the memory cell 1611, in which the read transistor is changed to an n-channel transistor (MN 61).
  • the transistor MN61 may be an OS transistor or a Si transistor.
  • the OS transistor MO61 may be an OS transistor without a back gate.
  • the memory cell 1613 illustrated in FIG. 8D is a 3T-type gain cell, and is electrically connected to the word lines WWL and RWL, the bit lines WBL and RBL, the source line SL, and the wirings BGL and PCL.
  • the memory cell 1613 includes a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62.
  • the OS transistor MO62 is a write transistor.
  • the transistor MP62 is a read transistor, and the transistor MP63 is a selection transistor.
  • a memory cell 1614 shown in FIG. 8E is a modification of the memory cell 1613, in which the read transistor and the select transistor are changed to n-channel transistors (MN62 and MN63).
  • the transistors MN62 and MN63 may be OS transistors or Si transistors.
  • the OS transistors provided in the memory cells 1611-1614 may be transistors without back gates or may be transistors with back gates.
  • FIG. 9 is a circuit diagram showing a configuration example of a NAND type memory cell array 1610.
  • the memory cell array 1610 illustrated in FIG. 9 includes a source line SL, a bit line RBL, a bit line WBL, a word line WWL, a word line RWL, a wiring BGL, and a memory cell 1615.
  • the memory cell 1615 includes a node SN, an OS transistor MO63, a transistor MN64, and a capacitive element C63.
  • the transistor MN64 is formed of, for example, an n-channel Si transistor.
  • the transistor MN 64 may be a p-channel Si transistor or an OS transistor.
  • the memory cell 1615 a and the memory cell 1615 b illustrated in FIG. 9 will be described as an example.
  • reference numerals of a wiring or a circuit element connected to either the memory cell 1615 a or the memory cell 1615 b are denoted by a or b.
  • the gate of the transistor MN64a, one of the source and the drain of the OS transistor MO63a, and one of the electrodes of the capacitive element C63a are electrically connected. Further, the bit line WBL and the other of the source and the drain of the OS transistor MO63a are electrically connected. In addition, the word line WWLa and the gate of the OS transistor MO63a are electrically connected. Further, the wiring BGLa and the back gate of the OS transistor MO63a are electrically connected. The word line RWLa and the other of the electrodes of the capacitive element C 63 a are electrically connected.
  • the memory cell 1615 b can be provided symmetrically with the memory cell 1615 a with the contact portion with the bit line WBL as an axis of symmetry. Accordingly, the circuit element included in the memory cell 1615 b is also connected to the wiring in the same manner as the memory cell 1615 a.
  • the source of the transistor MN64a included in the memory cell 1615a is electrically connected to the drain of the transistor MN64b in the memory cell 1615b.
  • the drain of the transistor MN64a included in the memory cell 1615a is electrically connected to the bit line RBL.
  • the source of the transistor MN64b included in the memory cell 1615b is electrically connected to the source line SL through the transistor MN64 included in the plurality of memory cells 1615.
  • the plurality of transistors MN64 are connected in series between the bit line RBL and the source line SL.
  • write operation and read operation are performed for each of a plurality of memory cells (hereinafter referred to as a memory cell column) connected to the same word line WWL (or word line RWL).
  • the write operation can be performed as follows. A potential at which the OS transistor MO63 is turned on is applied to the word line WWL connected to the memory cell column to be written, and the OS transistor MO63 of the memory cell column to be written is turned on. Thereby, the potential of the bit line WBL is applied to one of the gate of the transistor MN64 of the designated memory cell column and the electrode of the capacitive element C63, and a predetermined charge is applied to the gate. Then, when the OS transistor MO63 of the memory cell column is turned off, the predetermined charge given to the gate can be held. Thus, data can be written to the memory cell 1615 of the specified memory cell column.
  • the read operation can be performed as follows. First, to a word line RWL not connected to a memory cell column to be read, a potential that turns on the transistor MN64 regardless of the charge applied to the gate of the transistor MN64 is applied to read a memory cell column The other transistors MN64 are turned on. Then, a potential (read potential) is applied to the word line RWL connected to the memory cell column to be read by the charge of the gate of the transistor MN64 so that the on state or the off state of the transistor MN64 is selected. Then, a constant potential is applied to the source line SL, and the reading circuit connected to the bit line RBL is brought into an operating state.
  • the conductance between the source line SL and the bit line RBL is for reading It is determined by the state (on state or off state) of the transistor MN64 of the memory cell column.
  • the conductance of the transistor differs depending on the charge of the gate of the transistor MN64 in the memory cell column to be read, and accordingly, the potential of the bit line RBL takes a different value.
  • Information can be read out from the memory cell 1615 of the specified memory cell column by reading out the potential of the bit line RBL by the reading circuit.
  • the number of times of rewriting is in principle not limited, and data can be written and read with low energy.
  • the refresh frequency can be reduced.
  • the OS transistors MO61, MO62, and MO63, capacitive elements C61, C62, and C63, and transistors MP61, MP62, MP63, MN61, and MN62. , MN 63 and MN 64 can be used.
  • the area occupied by the transistor and the pair of capacitor elements in top view can be reduced, so that the memory device can be further highly integrated.
  • the storage capacity per unit area of the storage device can be increased.
  • DOSRAM registered trademark
  • 1T transistor
  • 1C capacitor
  • FIG. 10 shows a configuration example of DOSRAM.
  • the DOSRAM 1400 has a controller 1405, a row circuit 1410, a column circuit 1415, a memory cell and a sense amplifier array 1420 (hereinafter also referred to as "MC-SA array 1420").
  • the row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier driver circuit 1414.
  • the column circuit 1415 has a global sense amplifier array 1416 and an input / output circuit 1417.
  • the global sense amplifier array 1416 has a plurality of global sense amplifiers 1447.
  • the MC-SA array 1420 has a memory cell array 1422, a sense amplifier array 1423, and global bit lines GBLL and GBLR.
  • the MC-SA array 1420 has a stacked structure in which the memory cell array 1422 is stacked on the sense amplifier array 1423.
  • Global bit lines GBLL and GBLR are stacked on memory cell array 1422.
  • a hierarchical bit line structure hierarchized by local bit lines and global bit lines is adopted as the structure of bit lines.
  • Memory cell array 1422 includes N (N is an integer of 2 or more) local memory cell arrays 1425 ⁇ 0> to 1425 ⁇ N-1>.
  • N is an integer of 2 or more
  • the local memory cell array 1425 has a plurality of memory cells 1445, a plurality of word lines WL, and a plurality of bit lines BLL and BLR.
  • the structure of the local memory cell array 1425 is an open bit line type, but may be a folded bit line type.
  • FIG. 11B shows a circuit configuration example of a pair of memory cells 1445a and 1445b connected in pair to the common bit line BLL (BLR).
  • the memory cell 1445a includes a transistor MW1a, a capacitive element CS1a, and terminals B1a and B2a, and is connected to the word line WLa and the bit line BLL (BLR).
  • the memory cell 1445 b has a transistor MW 1 b, a capacitive element CS 1 b, terminals B 1 b and B 2 b, and is connected to the word line WLb and the bit line BLL (BLR). Note that, in the following, when one of the memory cell 1445a and the memory cell 1445b is not particularly limited, the memory cell 1445 and the configuration attached to the memory cell 1445 may not be denoted by the symbol a or b.
  • the transistor MW1a has a function of controlling charging and discharging of the capacitive element CS1a
  • the transistor MW1b has a function of controlling charging and discharging of the capacitive element CS1b.
  • the gate of transistor MW1a is electrically connected to word line WLa, the first terminal is electrically connected to bit line BLL (BLR), and the second terminal is electrically connected to the first terminal of capacitive element CS1a.
  • the gate of transistor MW1b is electrically connected to word line WLb, the first terminal is electrically connected to bit line BLL (BLR), and the second terminal is electrically connected to the first terminal of capacitive element CS1b. It is done.
  • the bit line BLL (BLR) is commonly used for the first terminal of the transistor MW1a and the first terminal of the transistor MW1b.
  • the transistor MW1 has a function of controlling charging and discharging of the capacitive element CS1.
  • the second terminal of the capacitive element CS1 is electrically connected to the terminal B2.
  • a constant voltage (for example, low power supply voltage) is input to the terminal B2.
  • the transistor MW1a, the transistor MW1b, the capacitor CS1a, and the capacitor CS1b can be used.
  • the area occupied by the transistor and the pair of capacitor elements in top view can be reduced, so that the memory device can be highly integrated.
  • the storage capacity per unit area of the storage device can be increased.
  • the transistor MW1 has a back gate, and the back gate is electrically connected to the terminal B1. Therefore, the threshold voltage of the transistor MW1 can be changed by the voltage of the terminal B1.
  • the voltage of the terminal B1 may be a fixed voltage (for example, a negative constant voltage), or the voltage of the terminal B1 may be changed according to the operation of the DOS RAM 1400.
  • the back gate of the transistor MW1 may be electrically connected to the gate, the source, or the drain of the transistor MW1. Alternatively, the transistor MW1 may not be provided with a back gate.
  • Sense amplifier array 1423 includes N local sense amplifier arrays 1426 ⁇ 0> to 1426 ⁇ N-1>.
  • the local sense amplifier array 1426 includes one switch array 1444 and a plurality of sense amplifiers 1446.
  • a bit line pair is electrically connected to sense amplifier 1446.
  • the sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying a voltage difference between the bit line pair, and a function of holding the voltage difference.
  • the switch array 1444 has a function of selecting a bit line pair and conducting between the selected bit line pair and the global bit line pair.
  • bit line pair means two bit lines which are simultaneously compared by the sense amplifier.
  • the global bit line pair refers to two global bit lines which are simultaneously compared by the global sense amplifier.
  • a bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines.
  • bit line BLL and the bit line BLR form a pair of bit lines.
  • Global bit line GBLL and global bit line GBLR form a pair of global bit lines.
  • bit line pair (BLL, BLR) and the global bit line pair (GBLL, GBLR) are also referred to.
  • the controller 1405 has a function of controlling the overall operation of the DOS RAM 1400.
  • the controller 1405 performs a logical operation on an externally input command signal to determine an operation mode, and generates a control signal for the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. And a function of holding an address signal input from the outside, and a function of generating an internal address signal.
  • the row circuit 1410 has a function of driving the MC-SA array 1420.
  • the decoder 1411 has a function of decoding an address signal.
  • the word line driver circuit 1412 generates a selection signal for selecting the word line WL in the access target row.
  • the column selector 1413 and the sense amplifier driver circuit 1414 are circuits for driving the sense amplifier array 1423.
  • the column selector 1413 has a function of generating a selection signal for selecting a bit line of the access target column.
  • the selection signal of column selector 1413 controls switch array 1444 of each local sense amplifier array 1426.
  • the control signals of the sense amplifier driver circuit 1414 drive the plurality of local sense amplifier arrays 1426 independently.
  • Column circuit 1415 has a function of controlling an input of data signal WDA [31: 0] and a function of controlling an output of data signal RDA [31: 0].
  • the data signal WDA [31: 0] is a write data signal
  • the data signal RDA [31: 0] is a read data signal.
  • Global sense amplifier 1447 is electrically connected to global bit line pair (GBLL, GBLR).
  • the global sense amplifier 1447 has a function of amplifying a voltage difference between the global bit line pair (GBLL, GBLR) and a function of holding this voltage difference. Writing and reading of data to the global bit line pair (GBLL, GBLR) are performed by the input / output circuit 1417.
  • Data is written to the global bit line pair by input / output circuit 1417.
  • Data of the global bit line pair is held by the global sense amplifier array 1416.
  • the data of the global bit line pair is written to the bit line pair of the target column by the switch array 1444 of the local sense amplifier array 1426 designated by the address.
  • the local sense amplifier array 1426 amplifies and holds the written data.
  • the row circuit 1410 selects the word line WL of the target row, and the data held by the local sense amplifier array 1426 is written to the memory cell 1445 of the selected row.
  • One row of the local memory cell array 1425 is designated by the address signal.
  • the word line WL in the target row is selected, and the data of the memory cell 1445 is written to the bit line.
  • the local sense amplifier array 1426 detects and holds the voltage difference of the bit line pair of each column as data.
  • data in the column designated by the address signal is written to the global bit line pair by switch array 1444.
  • the global sense amplifier array 1416 detects and holds data of the global bit line pair.
  • the held data of the global sense amplifier array 1416 is output to the input / output circuit 1417. Thus, the read operation is completed.
  • the number of times of rewriting is not limited in principle in the DOSRAM 1400, and data can be written and read with low energy.
  • the circuit configuration of the memory cell 1445 is simple, the capacity can be easily increased.
  • the transistor MW1 is an OS transistor. Since the off-state current of the OS transistor is extremely small, charge leakage from the capacitive element CS1 can be suppressed. Therefore, the retention time of the DOS RAM 1400 is very long compared to the DRAM. Therefore, since the frequency of refresh can be reduced, the power required for the refresh operation can be reduced. Therefore, the DOSRAM 1400 is suitable for a memory device that rewrites a large amount of data with high frequency, for example, a frame memory used for image processing.
  • bit lines can be shortened to a length approximately equal to the length of local sense amplifier array 1426.
  • the bit line capacitance can be reduced and the storage capacitance of the memory cell 1445 can be reduced.
  • the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. From the above reasons, the load driven at the time of access to the DOS RAM 1400 is reduced, and power consumption can be reduced. Therefore, memory power consumption can be reduced also in neural network processing.
  • this embodiment mode can be freely combined with Embodiment Mode 1.
  • FIG. 13 shows an example of an IC in which an AI system is incorporated.
  • FIG. 12 is a block diagram showing a configuration example of the AI system 4041.
  • the AI system 4041 includes an operation unit 4010, a control unit 4020, and an input / output unit 4030.
  • the operation unit 4010 includes an analog operation circuit 4011, a DOSRAM 4012, a NOSRAM 4013, and an FPGA 4014.
  • the DOSRAM 1400 and the NOSRAM 1600 described in Embodiment 4 can be used as the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014.
  • the control unit 4020 includes a central processing unit (CPU) 4021, a graphics processing unit (GPU) 4022, a phase locked loop (PLL) 4023, a static random access memory (SRAM) 4024, and a programmable read only memory (PROM) 4025. , A memory controller 4026, a power supply circuit 4027, and a PMU (Power Management Unit) 4028.
  • CPU central processing unit
  • GPU graphics processing unit
  • PLL phase locked loop
  • SRAM static random access memory
  • PROM programmable read only memory
  • the input / output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, a video codec 4033, a general purpose input / output module 4034, and a communication module 4035.
  • the operation unit 4010 can execute learning or inference by a neural network.
  • the analog operation circuit 4011 includes an A / D (analog / digital) conversion circuit, a D / A (digital / analog) conversion circuit, and a product-sum operation circuit.
  • the analog arithmetic circuit 4011 is preferably formed using an OS transistor.
  • the analog operation circuit 4011 using the OS transistor has an analog memory, and can perform the product-sum operation necessary for learning or inference with low power consumption.
  • the DOSRAM 4012 is a DRAM formed using an OS transistor, and the DOSRAM 4012 is a memory for temporarily storing digital data sent from the CPU 4021.
  • the DOSRAM 4012 has a memory cell including an OS transistor and a read out circuit unit including an Si transistor. Since the memory cell and the read out circuit portion can be provided in different stacked layers, the DOSRAM 4012 can reduce the entire circuit area.
  • Calculations using neural networks may have more than 1000 input data.
  • the SRAM has a limited circuit area and a small storage capacity, so the input data can not but be divided and stored.
  • the DOSRAM 4012 can arrange memory cells in a highly integrated manner even with a limited circuit area, and has a larger storage capacity than an SRAM. Therefore, the DOS RAM 4012 can store the input data efficiently.
  • the NOSRAM 4013 is a non-volatile memory using an OS transistor.
  • the NOSRAM 4013 consumes less power when writing data as compared to other non-volatile memories such as flash memory, ReRAM (Resistive Random Access Memory) and MRAM (Magnetoresistive Random Access Memory).
  • flash memory ReRAM (Resistive Random Access Memory)
  • MRAM Magneticoresistive Random Access Memory
  • the NOSRAM 4013 can store multi-value data of 2 bits or more in addition to 1-bit binary data.
  • the NOSRAM 4013 can reduce the memory cell area per bit by storing multi-value data.
  • the NOSRAM 4013 can store analog data. Therefore, the analog operation circuit 4011 can also use the NOSRAM 4013 as an analog memory. Since the NOSRAM 4013 can store analog data as it is, no D / A conversion circuit or A / D conversion circuit is required. Therefore, the NOSRAM 4013 can reduce the area of peripheral circuits.
  • analog data refers to data having a resolution of 3 bits (eight values) or more. The above-mentioned multi-value data may be included in the analog data.
  • Data and parameters used for neural network calculations can be temporarily stored in the NOSRAM 4013.
  • the above data and parameters may be stored in a memory provided outside the AI system 4041 via the CPU 4021.
  • the NOSRAM 4013 provided inside has higher speed and lower power consumption than the data and parameters. Can be stored. Further, since the NOSRAM 4013 can make the bit line longer than the DOS RAM 4012, the storage capacity can be increased.
  • the FPGA 4014 is an FPGA using an OS transistor.
  • the AI system 4041 uses the FPGA 4014 to perform deep neural networks (DNN), convolutional neural networks (CNN), recursive neural networks (RNN), self-coder, deep Boltzmann machine (DBM), which will be described later in hardware. It is possible to configure connections of neural networks, such as Deep Belief Networks (DBNs).
  • DNNs Deep Belief Networks
  • the FPGA 4014 is an FPGA having an OS transistor.
  • the OS-FPGA can have a smaller memory area than an FPGA configured with SRAM. Therefore, even if the context switching function is added, the area increase is small.
  • the OS-FPGA can also transmit data and parameters at high speed by boosting.
  • the AI system 4041 can provide the analog operation circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 on one die (chip). Therefore, the AI system 4041 can perform neural network calculations at high speed and low power consumption. Further, the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be manufactured by the same manufacturing process. Therefore, the AI system 4041 can be manufactured at low cost.
  • the arithmetic unit 4010 need not have all the DOS RAM 4012, the NOSRAM 4013, and the FPGA 4014.
  • One or more of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 may be selected and provided in accordance with the problem that the AI system 4041 wants to solve.
  • the AI system 4041 can perform deep neural network (DNN), convolutional neural network (CNN), recursive neural network (RNN), self-coder, deep Boltzmann machine (DBM), deep belief network ( Methods such as DBN) can be implemented.
  • the PROM 4025 can store programs for performing at least one of these techniques. In addition, part or all of the program may be stored in the NOSRAM 4013.
  • the AI system 4041 preferably includes a GPU 4022.
  • the AI system 4041 can execute the product-sum operation that is rate-limiting in the operation unit 4010 and can execute the other product-sum operations in the GPU 4022. By doing so, learning and inference can be performed at high speed.
  • the power supply circuit 4027 not only generates a low power supply potential for a logic circuit, but also performs potential generation for analog operation.
  • the power supply circuit 4027 may use an OS memory.
  • the power supply circuit 4027 can reduce power consumption by storing the reference potential in the OS memory.
  • the PMU 4028 has a function of temporarily stopping the power supply of the AI system 4041.
  • the CPU 4021 and the GPU 4022 preferably have OS memory as a register.
  • OS memory By having the OS memory, the CPU 4021 and the GPU 4022 can keep data (logical value) in the OS memory even when the power supply is stopped. As a result, the AI system 4041 can save power.
  • the PLL 4023 has a function of generating a clock.
  • the AI system 4041 operates based on the clock generated by the PLL 4023.
  • the PLL 4023 preferably has an OS memory.
  • the PLL 4023 having an OS memory can hold an analog potential for controlling the oscillation cycle of the clock.
  • the AI system 4041 may store data in an external memory such as DRAM. Therefore, the AI system 4041 preferably has a memory controller 4026 that functions as an interface with an external DRAM. In addition, the memory controller 4026 is preferably disposed near the CPU 4021 or the GPU 4022. By doing so, it is possible to exchange data at high speed.
  • Part or all of the circuits illustrated in the control unit 4020 can be formed over the same die as the computing unit 4010. By doing so, the AI system 4041 can perform neural network calculations at high speed and low power consumption.
  • the AI system 4041 preferably includes an external storage control circuit 4031 that functions as an interface with an external storage device.
  • the AI system 4041 includes a voice codec 4032 and a video codec 4033.
  • the audio codec 4032 encodes (decodes) and decodes (decodes) audio data
  • the video codec 4033 encodes and decodes video data.
  • the AI system 4041 can perform learning or inference using data obtained from an external sensor. Therefore, the AI system 4041 has a general purpose input / output module 4034.
  • the general-purpose input / output module 4034 includes, for example, Universal Serial Bus (USB), Inter-Integrated Circuit (I2C), and the like.
  • the AI system 4041 can perform learning or inference using data obtained via the Internet. Therefore, the AI system 4041 preferably has a communication module 4035.
  • the analog operation circuit 4011 may use a multi-level flash memory as an analog memory.
  • the flash memory is limited in the number of rewrites.
  • the analog arithmetic circuit 4011 may use ReRAM as an analog memory.
  • ReRAM is limited in the number of times of rewriting, and there is a problem in storage accuracy.
  • the element since the element has two terminals, the circuit design that separates writing and reading of data becomes complicated.
  • the analog operation circuit 4011 may use an MRAM as an analog memory.
  • the MRAM has a low rate of change in resistance, and has problems in storage accuracy.
  • the analog arithmetic circuit 4011 use the OS memory as an analog memory.
  • the AI system can integrate a digital processing circuit made of a Si transistor such as a CPU, an analog operation circuit using an OS transistor, and an OS memory such as an OS-FPGA and DOSRAM or NOSRAM in one die.
  • a digital processing circuit made of a Si transistor such as a CPU, an analog operation circuit using an OS transistor, and an OS memory such as an OS-FPGA and DOSRAM or NOSRAM in one die.
  • FIG. 13 shows an example of an IC incorporating an AI system.
  • An AI system IC 7000 shown in FIG. 13 has a lead 7001 and a circuit portion 7003.
  • AI system IC 7000 is mounted on, for example, printed circuit board 7002.
  • a plurality of such IC chips are combined and electrically connected on the printed circuit board 7002 to complete a board (mounting board 7004) on which electronic components are mounted.
  • the various circuits described in the above embodiment are provided in one die.
  • the circuit portion 7003 has a stacked structure and is roughly classified into a Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033. Since the OS transistor layer 7033 can be stacked on the Si transistor layer 7031, the AI system IC 7000 can be easily miniaturized.
  • QFP Quad Flat Package
  • a digital processing circuit such as a CPU, an analog operation circuit using an OS transistor, an OS-FPGA and an OS memory such as DOSRAM or NOSRAM may be formed in the Si transistor layer 7031, the wiring layer 7032 and the OS transistor layer 7033 it can. That is, the elements constituting the above AI system can be formed by the same manufacturing process. Therefore, the IC shown in this embodiment does not need to increase the manufacturing process even if the number of elements is increased, and the above-mentioned AI system can be incorporated at low cost.
  • the state of the secondary battery to be judged is analyzed to create data. Specifically, the remaining amount information of the secondary battery is acquired (step S1).
  • the capacity of the secondary battery can be determined, for example, by the product of the current and time of the secondary battery.
  • the coulomb counter CC may be used to determine the capacity of the secondary battery.
  • the SOC (state of charge) of the secondary battery may be used.
  • the SOC of the secondary battery may be estimated from the voltage of the secondary battery.
  • step S2 If the SOC is less than 50%, the process proceeds to the next step, charging start (step S2). If the SOC is 50% or more, the secondary battery is discharged by the discharge circuit to make the SOC less than 50%, preferably 20% or less.
  • Step S3 Data on the charge characteristics of the secondary battery is measured from the start of charging for detection of abnormality to time t, and the measured data is stored in the memory unit (step S3).
  • the charging curve is an image obtained by imaging a graph obtained by accumulating the charging data.
  • the obtained charge curve is converted into image data to obtain a plurality of input data (step S4).
  • the charge curve is converted into image data (210 ⁇ 210) of 8-bit gray gradation from 0 to 255.
  • the discharged state (low voltage) is black and the fully charged state is white.
  • the left of FIG. 15 (A) has shown the charge start position.
  • the input data is determined (step 5).
  • this determination or classification
  • processing of a neural network is performed and product-sum operation is used.
  • the features of the input data are classified as normal or abnormal using the weight parameters created at the time of training.
  • the mode is divided into two types: a mode in which the voltage sharply drops as a tendency of the occurrence of a micro short and a mode in which the voltage falls slowly.
  • FIG. 16A is an example of image data when fully charged, and the right shows completion of charging.
  • the detection timing is set every 2100 seconds, but after the first detection timing is set to 2100 seconds, it may be set every 60 seconds, or it may be set closer to real time to make an abnormality. It is preferable to set it as the abnormality detection system which can respond promptly, when it detects.
  • the reason for setting the first detection timing to 2100 seconds was found from the data of the secondary battery for learning, and was obtained by trial and error. Therefore, if the type of secondary battery to be targeted changes, It may change depending on the data of the next battery. However, it can be said empirically that it is preferable to maintain the principle of lengthening the interval from the charge start to the first detection timing and making the subsequent detection intervals the same or shorter.
  • FIG. 16B shows an example of image data at the time of full charge of data in which a micro short has occurred for comparison.
  • FIG. 16 (B) although the occurrence of the micro short circuit is observed near the middle of the charge, the occurrence of the micro short is observed near the middle of the charge, so when the abnormality detection method of this embodiment is used, the abnormality is detected during the charge. It is possible to stop charging or warn immediately.
  • image data is visualized (image display when displayed on a display device).
  • a television set also referred to as a television or a television receiver
  • a monitor for a computer a digital camera, a digital video camera, a digital photo frame
  • a mobile phone A large-sized game machine such as a telephone, a mobile phone device), a portable game machine, a portable information terminal, a sound reproduction device, a pachinko machine and the like can be mentioned.
  • FIGS. 18A and 18B illustrate an example of a foldable tablet terminal.
  • the tablet terminal 9600 illustrated in FIGS. 18A and 18B includes a housing 9630a, a housing 9630b, a movable portion 9640 connecting the housing 9630a and the housing 9630b, a display portion 9631, a display mode switching switch 9626 , A power switch 9627, a power saving mode switching switch 9625, a fastener 9629, and an operation switch 9628.
  • FIG. 18A shows a state in which the tablet terminal 9600 is opened
  • FIG. 18B shows a state in which the tablet terminal 9600 is closed.
  • the tablet terminal 9600 includes a power storage body 9635 inside the housings 9630 a and 9630 b.
  • the power storage unit 9635 is provided over the housing 9630 a and the housing 9630 b through the movable portion 9640.
  • a portion of the display portion 9631 can be a touch panel region, and data can be input by touching a displayed operation key.
  • the keyboard button can be displayed on the display portion 9631 by touching the position where the keyboard display switching button of the touch panel is displayed with a finger, a stylus, or the like.
  • the display mode switching switch 9626 can switch the display orientation such as vertical display or horizontal display, and can select switching between black and white display and color display.
  • the power saving mode switching switch 9625 can optimize display luminance in accordance with the amount of outside light at the time of use detected by the light sensor incorporated in the tablet terminal 9600.
  • the tablet type terminal may incorporate not only an optical sensor but also other detection devices such as a sensor for detecting inclination of a gyro, an acceleration sensor or the like.
  • FIG. 18B shows a state where the tablet terminal 9600 is closed, and the tablet terminal includes a charge and discharge control circuit 9634 including a housing 9630, a solar cell 9633, and a DCDC converter 9636.
  • the secondary battery abnormality detection system according to one embodiment of the present invention is used with the storage battery 9635 as a monitoring target.
  • the tablet terminal can perform neural network processing for detecting an abnormality of the secondary battery by electrically connecting an IC incorporating the AI system to the storage battery 9635.
  • the tablet terminal 9600 can be folded in two, the housing 9630a and the housing 9630b can be folded so as to overlap when not in use. Since the display portion 9631 can be protected by folding, durability of the tablet terminal 9600 can be improved.
  • the power storage unit 9635 including the abnormality detection system of one embodiment of the present invention can provide a tablet terminal 9600 that can be used for a long time.
  • the tablet type terminal shown in FIGS. 18A and 18B has a function of displaying various information (still image, moving image, text image, etc.), a calendar, a date or time, etc.
  • a function of displaying on the display portion, a touch input function of performing touch input operation or editing of information displayed on the display portion, a function of controlling processing by various software (programs), and the like can be provided.
  • Electric power can be supplied to the touch panel, the display portion, the video signal processing portion, or the like by the solar battery 9633 mounted on the surface of the tablet terminal.
  • the solar battery 9633 can be provided on one side or both sides of the housing 9630, and can be efficiently charged with the power storage unit 9635.
  • FIG. 18C illustrates a solar cell 9633, a storage battery 9635, a DCDC converter 9636, a converter 9637, switches SW1 to SW3, and a display portion 9631.
  • the storage battery 9635, the DCDC converter 9636, the converter 9637, the switch SW1 to The portion SW3 corresponds to the charge / discharge control circuit 9634 shown in FIG.
  • the electric power generated by the solar cell is stepped up or down by the DCDC converter 9636 so as to be a voltage for charging the power storage unit 9635. Then, when the power from the solar cell 9633 is used for the operation of the display portion 9631, the switch SW1 is turned on, and the converter 9637 boosts or steps down the voltage necessary for the display portion 9631. In addition, when display on the display portion 9631 is not performed, the switch SW1 may be turned off and the switch SW2 may be turned on to charge the power storage unit 9635.
  • the solar cell 9633 is illustrated as an example of the power generation means, it is not particularly limited, and a configuration in which the power storage body 9635 is charged by another power generation means such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element) It may be For example, a non-contact power transmission module that transmits and receives power wirelessly (without contact) to charge the battery, or another charging unit may be combined.
  • FIG. 19 shows an example of another electronic device.
  • a display device 8000 is an example of an electronic device on which the abnormality detection system for the secondary battery 8004 is mounted.
  • the display device 8000 corresponds to a display device for receiving a TV broadcast, and includes a housing 8001, a display portion 8002, a speaker portion 8003, a secondary battery 8004, and the like.
  • the abnormality detection system according to one embodiment of the present invention is provided inside the housing 8001.
  • the display device 8000 can receive power supply from a commercial power supply, or can use power stored in the secondary battery 8004.
  • the display device 8000 can perform neural network processing for detecting an abnormality of a secondary battery by electrically connecting an IC in which an AI system is incorporated to the secondary battery 8004.
  • the display portion 8002 includes a liquid crystal display device, a light emitting device including a light emitting element such as an organic EL element in each pixel, an electrophoretic display device, a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel), and an FED (Field Emission Display). Etc.) can be used.
  • a light emitting device including a light emitting element such as an organic EL element in each pixel
  • an electrophoretic display device a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel), and an FED (Field Emission Display). Etc.) can be used.
  • the voice input device 8005 also uses a secondary battery.
  • the voice input device 8005 can perform neural network processing for detecting an abnormality of the secondary battery by electrically connecting an IC incorporating the AI system to the secondary battery.
  • the voice input device 8005 includes a microphone and a plurality of sensors (optical sensor, temperature sensor, humidity sensor, barometric pressure sensor, illuminance sensor, motion sensor, etc.) in addition to a wireless communication element, and the user's instructional words Power supply operation of a device such as the display device 8000, light amount adjustment of the lighting device 8100, and the like can be performed.
  • the voice input device 8005 can operate peripheral devices by voice and can replace the manual remote control.
  • the voice input device 8005 has wheels and mechanical moving means, moves in the direction in which the user can hear the voice, hears the command accurately with the built-in microphone, and displays the contents on the display portion 8008. Or a touch input operation of the display portion 8008 can be performed.
  • the voice input device 8005 can also function as a charging dock of a portable information terminal 8009 such as a smartphone.
  • the portable information terminal 8009 and the voice input device 8005 can transmit and receive power by wire or wirelessly. There is no need to carry the portable information terminal indoors, and it is necessary to maintain and maintain the necessary capacity, and to avoid load and deterioration of the secondary battery, so the voice input device 8005 manages and maintains the secondary battery. It is desirable to be able to In addition, since the speaker 8007 and the microphone are included, hands-free conversation can be performed even during charging.
  • the capacity of the secondary battery of the voice input device 8005 is lowered, it moves in the direction of the arrow, and charging may be performed by wireless charging from the charging module 8010 connected to the external power supply. If an IC incorporating an AI system is mounted on the charging module 8010, it is possible to perform neural network processing indirectly for detecting an abnormality in the secondary battery of the portable information terminal 8009.
  • the voice input device 8005 is installed on the floor is shown in FIG. 19, it is not particularly limited, and wheels or mechanical moving means may be provided to move to a desired position. You may fix without providing.
  • the display device includes all display devices for displaying information, such as for personal computers, for displaying advertisements, as well as for receiving TV broadcasts.
  • a stationary lighting device 8100 is an example of an electronic device using a secondary battery 8103 controlled by a microprocessor (including APS) which controls charging.
  • the lighting device 8100 includes a housing 8101, a light source 8102, a secondary battery 8103, and the like.
  • FIG. 19 illustrates the case where the secondary battery 8103 is provided inside the ceiling 8104 on which the housing 8101 and the light source 8102 are installed, the secondary battery 8103 is provided inside the housing 8101. It may be done.
  • the lighting device 8100 can receive power from a commercial power supply. Alternatively, the lighting device 8100 can use power stored in the secondary battery 8103.
  • the secondary battery is a stationary type provided on, for example, the side wall 8105, the floor 8106, the window 8107, and the like other than the ceiling 8104. It can also be used for a lighting device, and can also be used for a desk-type lighting device or the like.
  • an artificial light source which artificially obtains light using electric power can be used.
  • a discharge lamp such as an incandescent lamp and a fluorescent lamp
  • a light emitting element such as an LED or an organic EL element are mentioned as an example of the artificial light source.
  • an air conditioner having an indoor unit 8200 and an outdoor unit 8204 is an example of an electronic device using a secondary battery 8203.
  • the indoor unit 8200 includes a housing 8201, an air outlet 8202, a secondary battery 8203, and the like.
  • FIG. 19 illustrates the case where the secondary battery 8203 is provided in the indoor unit 8200, the secondary battery 8203 may be provided in the outdoor unit 8204. Alternatively, the secondary battery 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204.
  • the air conditioner can receive power from a commercial power supply, or can use power stored in the secondary battery 8203.
  • an electric refrigerator-freezer 8300 is an example of an electronic device using a secondary battery 8304.
  • the electric refrigerator-freezer 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, a secondary battery 8304, and the like.
  • the secondary battery 8304 is provided inside the housing 8301.
  • the electric refrigerator-freezer 8300 can receive power supply from a commercial power supply, or can use power stored in the secondary battery 8304.
  • the power usage rate when the electronic equipment is not used, especially in a time zone where the ratio of the amount of power actually used (referred to as the power usage rate) to the total amount of power that can be supplied by the commercial power supply source is low.
  • the power usage rate By storing power in the secondary battery, it is possible to suppress an increase in the power usage rate outside the above time zone.
  • the electric refrigerator-freezer 8300 electric power is stored in the secondary battery 8304 at night when the cold room door 8302 and the freezer room door 8303 are not opened / closed because the air temperature is low. Then, in the daytime when the temperature of the room rises and the refrigerator door 8302 and the freezer door 8303 are opened and closed, by using the secondary battery 8304 as an auxiliary power source, it is possible to suppress the daytime power usage rate low.
  • the secondary battery can be mounted on any electronic device other than the above-described electronic device. According to one aspect of the present invention, the cycle characteristics of the secondary battery are improved. Therefore, by mounting a microprocessor (including an APS) which controls charging, which is one embodiment of the present invention, in the electronic device described in this embodiment, the electronic device can have a longer lifetime. This embodiment can be implemented in appropriate combination with the other embodiments.
  • FIG. 20A an example of a cylindrical secondary battery 600 is illustrated in FIG. 20A as an example of a secondary battery mounted in an electric device.
  • the cylindrical secondary battery 600 has a positive electrode cap (battery lid) 601 on the top and a battery can (outer can) 602 on the side and bottom.
  • the positive electrode cap 601 and the battery can (outer can) 602 are insulated by a gasket (insulation packing) 610.
  • FIG. 20 (B) is a view schematically showing a cross section of a cylindrical secondary battery.
  • a battery element in which a strip-shaped positive electrode 604 and a negative electrode 606 are wound with a separator 605 interposed therebetween.
  • the battery element is wound around the center pin.
  • One end of the battery can 602 is closed and the other end is open.
  • a metal such as nickel, aluminum, titanium or the like having corrosion resistance to an electrolytic solution, or an alloy of these or an alloy of these with another metal (for example, stainless steel or the like) can be used. .
  • the battery element in which the positive electrode, the negative electrode, and the separator are wound is sandwiched between a pair of opposing insulating plates 608 and 609.
  • a non-aqueous electrolyte (not shown) is injected into the inside of the battery can 602 provided with the battery element.
  • the secondary battery includes a positive electrode containing an active material such as lithium cobaltate (LiCoO 2 ) and lithium iron phosphate (LiFePO 4 ), a negative electrode made of a carbon material such as graphite capable of absorbing and releasing lithium ions, and ethylene It comprises a non-aqueous electrolytic solution in which an electrolyte composed of a lithium salt such as LiBF 4 or LiPF 6 is dissolved in an organic solvent such as carbonate or diethyl carbonate.
  • an active material such as lithium cobaltate (LiCoO 2 ) and lithium iron phosphate (LiFePO 4 )
  • a negative electrode made of a carbon material such as graphite capable of absorbing and releasing lithium ions
  • ethylene ethylene
  • It comprises a non-aqueous electrolytic solution in which an electrolyte composed of a lithium salt such as LiBF 4 or LiPF 6 is dissolved in an organic solvent such as carbonate or diethyl carbonate.
  • a positive electrode terminal (positive electrode current collection lead) 603 is connected to the positive electrode 604, and a negative electrode terminal (negative electrode current collection lead) 607 is connected to the negative electrode 606. Both the positive electrode terminal 603 and the negative electrode terminal 607 can be made of a metal material such as aluminum.
  • the positive electrode terminal 603 is resistance welded to the safety valve mechanism 612, and the negative electrode terminal 607 is resistance welded to the bottom of the battery can 602.
  • the safety valve mechanism 612 is electrically connected to the positive electrode cap 601 via a PTC element (Positive Temperature Coefficient) 611.
  • the safety valve mechanism 612 disconnects the electrical connection between the positive electrode cap 601 and the positive electrode 604 when the increase in internal pressure of the battery exceeds a predetermined threshold.
  • the PTC element 611 is a heat sensitive resistance element whose resistance increases when the temperature rises, and the amount of current is limited by the increase of the resistance to prevent abnormal heat generation.
  • a barium titanate (BaTiO 3 ) -based semiconductor ceramic or the like can be used for the PTC element.
  • a plurality of secondary batteries 600 may be interposed between the conductive plate 613 and the conductive plate 614 to form a module 615.
  • the plurality of secondary batteries 600 may be connected in parallel, may be connected in series, or may be connected in series and then connected in series. By configuring the module 615 including the plurality of secondary batteries 600, large power can be extracted.
  • FIG. 20D is a top view of the module 615.
  • the conductive plate 613 is shown by a dotted line to clarify the figure.
  • the module 615 may have a conductor 616 electrically connecting the plurality of secondary batteries 600.
  • the conductive plate 613 can be provided over the conductive wire 616 in an overlapping manner.
  • the temperature control device 617 may be provided between the plurality of secondary batteries 600. When the secondary battery 600 is overheated, it can be cooled by the temperature control device 617, and when the secondary battery 600 is too cold, it can be heated by the temperature control device 617. Therefore, the performance of the module 615 is less susceptible to the outside air temperature.
  • an IC incorporating an AI system is mounted as a protection circuit for the plurality of secondary batteries 600, neural network processing for detecting an abnormality in the plurality of secondary batteries 600 can be performed.
  • a next-generation clean energy vehicle such as a hybrid vehicle (HEV), an electric vehicle (EV), or a plug-in hybrid vehicle (PHEV).
  • HEV hybrid vehicle
  • EV electric vehicle
  • PHEV plug-in hybrid vehicle
  • FIG. 21 illustrates a vehicle using a secondary battery abnormality detection system according to an aspect of the present invention.
  • An automobile 8400 shown in FIG. 21A is an electric automobile using an electric motor as a motive power source for traveling.
  • it is a hybrid car that can be used by appropriately selecting and using an electric motor and an engine as a power source for traveling.
  • the automobile 8400 has a battery module 8402 having a plurality of secondary batteries. If an IC incorporating an AI system is mounted as a protection circuit for a secondary battery, neural network processing for detecting an abnormality in the secondary battery can be performed. Even in an automobile 8400 using 1000 or more secondary batteries, neural network processing for detecting an abnormality of the secondary battery can be efficiently performed.
  • the secondary battery many small cylindrical secondary batteries shown in FIG. 20C may be used side by side with respect to the floor portion in the car. Further, as shown in FIG. 21 (A), the secondary battery shown in FIG. 20 (C) may be provided with a plurality of combined battery packs with respect to the floor portion in the vehicle.
  • the secondary battery can not only drive the electric motor 8406 but can also supply power to light emitting devices such as the headlight 8401 and the room light (not shown).
  • the secondary battery can supply power to a display device such as a speedometer or a tachometer which the automobile 8400 has.
  • the secondary battery can supply power to a semiconductor device such as a navigation system of the automobile 8400.
  • a solar cell 8405 is provided on the exterior of the vehicle.
  • An automobile 8400 shown in FIG. 21A includes an electric motor 8406 in a wheel, and a camera 8403 instead of a side mirror.
  • Reference numeral 8404 in FIG. 21A denotes a windshield.
  • FIG. 21B An automobile 8500 illustrated in FIG. 21B can be charged by receiving power supply from an external charging facility to a secondary battery included in the automobile 8500 by a plug-in system, a non-contact power feeding system, or the like.
  • FIG. 21B shows a state in which the secondary battery 8024 mounted on the vehicle 8500 from the ground-mounted charging device 8021 is charged through the cable 8022.
  • the charging method, the standard of the connector, etc. may be appropriately performed by a predetermined method such as CHAdeMO (registered trademark) or combo.
  • the charging device 8021 may be a charging station provided in a commercial facility, or may be a home power source.
  • the plug-in technology can charge the secondary battery 8024 mounted on the automobile 8500 by external power supply.
  • Charging can be performed by converting AC power into DC power through a converter such as an ACDC converter included in the charging device 8021.
  • a converter such as an ACDC converter included in the charging device 8021.
  • charging can be performed even if AC power is connected.
  • an IC incorporating an AI system is mounted on the charging device 8021, neural network processing for detecting an abnormality in a secondary battery of the automobile 8500 can be performed.
  • the power receiving device may be mounted on a vehicle, and power may be supplied contactlessly from a ground power transmitting device for charging.
  • charging can be performed not only while the vehicle is stopped but also while it is traveling by incorporating the power transmission device on the road or the outer wall.
  • power may be transmitted and received between vehicles using this method of non-contact power feeding.
  • a solar cell may be provided on the exterior of the vehicle to charge the secondary battery when the vehicle is stopped or traveling.
  • an electromagnetic induction method or a magnetic resonance method can be used for such non-contact power supply.
  • FIG. 21 (C) is an example of a two-wheeled vehicle mounted with an IC incorporating an AI system.
  • a scooter 8600 shown in FIG. 21C includes a secondary battery 8602, a side mirror 8601, and a direction indicator light 8603.
  • the secondary battery 8602 can supply electricity to the direction indicator 8603.
  • An IC incorporating an AI system can detect an abnormality in the secondary battery 8602.
  • a scooter 8600 shown in FIG. 21C can store the secondary battery 8602 in the under-seat storage 8604.
  • the secondary battery 8602 can be stored in the under-seat storage 8604 even if the under-seat storage 8604 is small.
  • the secondary battery 8602 can be removed, and at the time of charging, the secondary battery 8602 may be carried indoors, carried, charged, and stored before traveling.
  • the secondary battery mounted in the vehicle can also be used as an electric power supply source other than a vehicle.
  • a commercial power supply for example, at the peak of the power demand. If it is possible to avoid using a commercial power source at the peak of power demand, it can contribute to energy saving and reduction of carbon dioxide emissions.
  • image data are used, 70% of the whole are allocated for learning and 30% for testing, and the abnormality detection accuracy is confirmed.
  • the algorithm for inference was created in Python (Chainer).
  • the image data is converted into two-dimensional data representing the charging characteristics of the secondary battery measured in advance in gray tones, that is, array data of n rows ⁇ n (n> 2) columns.
  • array data represented in gray tones an algorithm used in pattern recognition for categorizing image data can be used. Since a program or IC used in image pattern recognition can be used, the cost for development can be reduced.
  • weight parameters also referred to as filters
  • features are extracted beforehand using normal data as correct labels and image data with correct labels as input data, and weighting parameters for feature extraction are stored in an array. Update and learn weights for each mini-batch size.
  • the mini-batch size is the number of data samples of the mini-batch.
  • the learning data if it is detected as abnormal at a certain time during charging, it is determined that a micro short has occurred in the secondary battery even if there is no abnormality in data after a certain time, and labeled as abnormal data and learned.
  • the mini-batch 40 is used, and the size of the array data is set to 210 ⁇ 210 so as to form a square matrix, and the gray scale is 8 bits.
  • the neural network processing in the neural network processing, three sets of convolution processing, max pooling processing, and dropout processing are performed to be inferred.
  • the normal characteristics and the abnormal characteristics of the secondary battery are determined based on the learning data.
  • the process is performed in the order of convolution (convolution and integration, product-sum) processing, max pooling processing, and dropout processing.
  • the extracted feature quantities are pooled, and the feature quantities are used as the output of the intermediate layer.
  • the dropout process is a process of removing certain data. After three sets of the above convolution processing, max pooling processing, and dropout processing, all combination processing is performed and then output.
  • the number of samples tested was 2500, and the number of incorrect answers was 2.
  • the correct answer rate was 99.92%. From these results, it can be said that abnormality (micro short) of the secondary battery could be detected with high probability using CNN.
  • the present invention was not limited to 8 bits, and similar results could be obtained even if the image data is 6 bits.

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Abstract

Selon la présente invention, lorsqu'une anomalie est détectée dans une cellule auxiliaire, par exemple, lorsqu'un phénomène qui réduit la sécurité de la cellule auxiliaire est détecté ou prévu, les conditions de fonctionnement de la cellule auxiliaire sont modifiées, ce qui permet de maintenir la sécurité de la cellule auxiliaire. Les caractéristiques de charge d'une cellule auxiliaire sont converties en données pour une image, et un modèle de réseau neuronal à convolution (CNN) est utilisé pour faire la distinction entre des caractéristiques normales et des caractéristiques anormales de la cellule auxiliaire sur la base de données d'apprentissage. Il est ainsi possible d'obtenir un système pour commander la charge de la cellule auxiliaire de telle sorte que, après que l'état de la cellule auxiliaire est évalué comme étant anormal, le système émet une alarme vers la cellule auxiliaire indiquant des caractéristiques anormales, ou arrête l'utilisation de la cellule auxiliaire, ou propose un remplacement de la cellule auxiliaire, ou change les conditions de charge.
PCT/IB2018/055129 2017-07-26 2018-07-12 Système de commande de charge d'une cellule auxiliaire et procédé de détection d'anomalie dans une cellule auxiliaire WO2019021095A1 (fr)

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