WO2019019294A1 - 一种适用于多任务调度环境下的双缓冲协议数据分析系统 - Google Patents

一种适用于多任务调度环境下的双缓冲协议数据分析系统 Download PDF

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WO2019019294A1
WO2019019294A1 PCT/CN2017/101334 CN2017101334W WO2019019294A1 WO 2019019294 A1 WO2019019294 A1 WO 2019019294A1 CN 2017101334 W CN2017101334 W CN 2017101334W WO 2019019294 A1 WO2019019294 A1 WO 2019019294A1
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data
ring buffer
decoding
task
module
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French (fr)
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赖志威
曾宪玮
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广州路派电子科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0736—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function
    • G06F11/0739—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function in a data processing system embedded in automotive or aircraft systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/10—Protocols in which an application is distributed across nodes in the network
    • H04L67/1001—Protocols in which an application is distributed across nodes in the network for accessing one among a plurality of replicated servers

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  • the invention belongs to the technical field of data analysis systems, and particularly relates to a double buffering protocol data analysis system suitable for a multi-task scheduling environment.
  • Communication between two different hardware systems usually encodes the data to be transmitted and sends it to the other party through the hardware channel; the receiver of the data decodes the received data before starting further work.
  • the way and purpose of data encoding and decoding in different systems are not necessarily the same: some are used to compress data and reduce the pressure of data transmission and storage; some encrypt data to improve the security of data transmission; some add original data. Additional data is formed to form so-called protocol data and the like.
  • the decoding of data is relatively time consuming. In the environment where the hardware or the underlying software is insufficiently cached, the upper layer software that requires decoding is quickly decoded. Otherwise, it is very likely that the data is not analyzed and the new data has already updated the underlying cache.
  • FIG. 1 is a schematic diagram of a communication structure with protocol data between different embedded systems commonly used in the prior art or between a PC and an embedded system.
  • the right system is a data sender, and the data sender is composed of two parts.
  • the upper part of the data sender is its encoding part, its encoding format is “AA+BB+data1+data2+data3+CRC”, this string of data is called data frame, “AA” and “data frame” BB” is collectively referred to as the frame header, where the frame header is the only criterion for judging the arrival/emission of a frame of data, the frame header is followed by the three-byte raw data to be transmitted, and the last of the data frame is the checksum "CRC”.
  • the left system in Figure 1 is the data receiver, and the data receiver consists of two parts: 1) the underlying hardware data acquisition and buffer, as shown in the upper part of the left side of Figure 1, this part of the structure is mainly to make a data collected. Simple cache, its performance is determined by the specific hardware and operating system, usually The cache size of this part is not too large, and the upper layer software is required to quickly fetch the cached data. Otherwise, the data in the cache that has not been taken out is likely to be replaced by the newly acquired data; 2) software decoding The area, as shown in the lower left part of Figure 1, the part continuously acquires data from the underlying buffer, and decodes and reorganizes the data, first determining whether the consecutive two data collected are two frames of "AA" and "BB".
  • the three data collected from the underlying buffer are saved, and finally another data is collected from the underlying buffer as the collected "CRC"; in order to ensure that the detected data is valid Sex, the necessary test of the data, the three data just saved are added to get a value compared with the "CRC” just collected, if the data is consistently proved to be valid, then the three confirmed The valid data is passed to the higher level module for related logic operations or other operations.
  • the above-mentioned prior art data analysis system has several problems: 1.
  • the cache is significantly insufficient, and one frame of data is collected, and the speed of the decoding part is affected by the CPU of the operation. If the CPU frequency is not high, the underlying buffer data is easily In this case, the above-mentioned "frame header" and "CRC" are likely to be destroyed, so that the efficiency of collecting valid data becomes very low; 2. After collecting valid data, it is directly handed over to the rest to use decoded data.
  • the module performs operations in which the operation time is affected by its modules, and the efficiency of collecting valid data is also greatly affected.
  • an object of the present invention is to provide a double buffering protocol data analysis system suitable for use in a multitasking scheduling environment that avoids the above technical drawbacks.
  • a double buffering protocol data analysis system suitable for multi-task scheduling environment comprising a first-level ring buffer, a decoding task module, a second-level ring buffer, an underlying data detection task module and an underlying hardware cache module, and an underlying data detection task module
  • the data of the underlying hardware cache module is sent to the first-level ring buffer; the decoding task module reads data from the first-level ring buffer, and after decoding, sends the obtained data group to the secondary ring buffer.
  • the primary ring buffer is a ring buffer, and the size of the data of the primary ring buffer is one byte per write and read, which is consistent with the data size of the underlying hardware cache module.
  • the secondary ring buffer is a ring buffer, and the data size of the secondary ring buffer is written and read each time to the size of the decoded data group.
  • the data for writing and reading the secondary ring buffer each time is 3 bytes.
  • the secondary ring buffer is also connected with other task modules that use decoded data, and other task modules that use the decoded data actively read data from the secondary ring buffer.
  • a data analysis method for double buffering protocol suitable for multi-task scheduling environment comprising the following steps:
  • the underlying data detection task module continuously detects whether there is data in the underlying hardware cache module after the system is started, and if the data is detected, the data of the underlying hardware cache module is continuously sent to the first-level ring buffer;
  • the decoding task module continuously detects whether there is data in the primary ring buffer after the system is started, directly decodes if data is detected, and then transmits the decoded data to the secondary ring buffer for related logical operations or other operating.
  • the decoding step of the decoding task module is: the decoding task module reads data from the first-level ring buffer area, decodes and reorganizes the data, and first determines whether the collected two consecutive data are frame headers, if it is detected The frame header is saved for the three data collected from the underlying buffer, and finally another data is collected from the underlying buffer as the collected CRC; the necessary checks are performed on the data, and the three stored will be saved. The data is added to obtain a value that is compared with the collected CRC, if it is consistently proved that the collected data is valid.
  • the double buffering protocol data analysis system suitable for multi-task scheduling environment improves the correct rate and decoding speed of protocol data parsing by introducing three independent task modules and two-level variable size ring buffer.
  • the dependence on the hardware performance; the total size of the two ring buffers in the present invention and the size of each read and write can be changed according to the design requirements, and the system resources are well utilized, especially in the embedded
  • the environment can exert its advantages more effectively; the invention can also be applied to the decoding of other various forms of protocol data, and can have higher decoding accuracy and speed, and can well meet the needs of practical applications.
  • FIG. 1 is a block diagram of a communication structure with protocol data between different embedded systems or between a PC and an embedded system commonly used in the prior art;
  • FIG. 2 is a structural block diagram of a double buffering protocol data analysis system suitable for use in a multitasking scheduling environment according to the present invention.
  • a double buffering data analysis system suitable for a multi-task scheduling environment includes a first-level ring buffer RingBuffer1, a decoding task module, a secondary ring buffer RingBuffer2, an underlying data detection task module Task, and a bottom layer.
  • Hardware cache module As shown in FIG. 2, a double buffering data analysis system suitable for a multi-task scheduling environment includes a first-level ring buffer RingBuffer1, a decoding task module, a secondary ring buffer RingBuffer2, an underlying data detection task module Task, and a bottom layer.
  • Hardware cache module is a double buffering data analysis system suitable for a multi-task scheduling environment.
  • the underlying data detection task module Task will always be in the working state after the system is started. It continuously detects whether there is data in the underlying hardware cache module. If data is detected, the data of the underlying hardware cache module is continuously buffered to the first level. The area is sent to RingBuffer1.
  • the first-level ring buffer RingBuffer1 is a ring buffer. Each time the RingBuffer1 data is written and read, the size of the data is one byte, which is consistent with the data size of the underlying hardware cache module.
  • the decoding task module is also in working state after the system is started, and continuously detects whether there is data in the RingBuffer1 of the first-level ring buffer. If data is detected, the decoding is directly performed.
  • the decoding step is: decoding the task module from the first-level ring buffer RingBuffer1 Read data, decode and reorganize the data, first determine whether the two consecutive data collected are "AA" and "BB". If the frame header is detected, it is collected from the underlying buffer. The three data are saved, and finally another data is collected from the underlying buffer as the collected "CRC” (CRC is the cyclic redundancy check code); in order to ensure the validity of the collected data, the data is necessary.
  • CRC is the cyclic redundancy check code
  • the decoding task module no longer directly reads data from the underlying hardware cache module, but reads data from the first-level ring buffer RingBuffer1, and finally obtains the data group after decoding. Actively send to the secondary ring buffer RingBuffer2 immediately after the next round of decoding, no longer passively waiting for other modules that need to use the decoded data to take the data to start the next round of data decoding work.
  • the secondary ring buffer RingBuffer2 is a ring buffer, each time writing and reading RingBuffer2
  • the data size is the size of the decoded data group, and the size is 3 bytes as shown in FIG. 2, and the size can be appropriately changed in other applications.
  • the secondary ring buffer RingBuffer2 is also connected to other task modules that use decoded data. Other task modules that use decoded data actively read data from the secondary ring buffer RingBuffer2.
  • a data analysis method for double buffering protocol suitable for multi-task scheduling environment comprising the following steps:
  • the underlying data detection task module continuously detects whether there is data in the underlying hardware cache module after the system is started, and if the data is detected, the data of the underlying hardware cache module is continuously sent to the first-level ring buffer;
  • the decoding task module continuously detects whether there is data in the primary ring buffer after the system is started, directly decodes if data is detected, and then transmits the decoded data to the secondary ring buffer for related logical operations or other operating.
  • the decoding step of the decoding task module is: the decoding task module reads data from the first-level ring buffer area, decodes and reorganizes the data, and first determines whether the collected two consecutive data are “AA” and “BB”. Frame headers, if the frame header is detected, the three data collected from the underlying buffer are saved, and finally another data is collected from the underlying buffer as the collected CRC; the necessary check is performed on the data. The saved three data are added to obtain a value to be compared with the collected CRC, if the data collected is consistently proved to be valid.

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Abstract

一种适用于多任务调度环境下的双缓冲协议数据分析系统，包括一级环形缓冲区、解码任务模块、二级环形缓冲区、底层数据检测任务模块和底层硬件缓存模块，底层数据检测任务模块用于将底层硬件缓存模块的数据往一级环形缓冲区中送去；解码任务模块从一级环形缓存区中读取数据，进行解码后将得到的数据组往二级环形缓冲区中送去。所述系统通过引入三个独立的任务模块和两级可变大小环形缓冲，提高了协议数据解析的正确率和解码速度，降低了对硬件性能的依赖，所述系统中的两个环形缓冲区的总大小和每次读写的大小是可以随设计需要而改变的，很好地利用了系统资源，特别是应用在嵌入式的环境中更能发挥其优势，可以很好地满足实际应用的需要。

Description

一种适用于多任务调度环境下的双缓冲协议数据分析系统 技术领域
本发明属于数据分析系统技术领域，具体涉及一种适用于多任务调度环境下的双缓冲协议数据分析系统。
背景技术
在两个不同的硬件体系之间通讯通常会对要传输的数据进行适当编码再通过硬件渠道发送到对方；而数据的接收方对接收的数据先进行解码，再开始作进一步的工作。在不同系统中数据的编解码的方式和目的不一定相同：有的是为了将数据压缩，减轻数据的传输和储存的压力；有的是对数据进行加密，提高数据传输的安全性；有的是对原始的数据加上额外的数据，形成所谓的协议数据等。
数据的解码工作相对来说是一份比较耗时的工作。硬件或底层软件缓存不足的环境下，则要求进行解码的上层软件快速解码，否则很有可能造成数据没分析完成，新的数据就已经把底层缓存更新了的现象。
如图1所示为现有技术中常用的不同嵌入式系统之间或PC与嵌入式系统之间带有协议数据的通讯结构示意图，图1中右边系统为数据发送方，数据发送方由两部分组成：数据生成部分，如图1中的Dx Dx Dx为最新产生的三个字节的原始数据即由该部分生成的；编码部分，所有原始数据都要经过一定格式的编码后再被发送出去，如数据发送方的上部分为其编码部分，其编码格式为“AA+BB+数据1+数据2+数据3+CRC”，这一串数据称为数据帧，数据帧中“AA”和“BB”共同称为帧头，在这里帧头是判断一帧数据到来/发出的唯一标准，帧头接着的是要发送的三字节原始数据，数据帧的最后的是校验和“CRC”，这里的校验和算法为“CRC＝数据1+数据2+数据3”，发送方将数据按上述格式编码好后，向数据接收方一字节一字节地发送过去。
图1中左边系统为数据接收方，数据接收方由两部分组成：1)底层硬件数据采集及缓冲区，如图1左边的上部分所示，这部分结构主要是对采集的的数据做一个简单的缓存，其性能是由具体的硬件和操作系统来决定的，通常情况 下这部分的缓存大小不会太大，要求上层软件要快速取出这些缓存的数据，否则那些还没被取出的在缓存中的数据很有可能被新采集到的数据所更替；2)软件解码区，如图1左边下部分所示，该部分不断从底层缓冲中获取数据，并且对数据进行解码重组，先判断采集的连续的两个数据是否为“AA”和“BB”这两个帧头，如果检测到帧头，就对接着从底层缓冲区采集到的三个数据保存起来，最后再从底层缓冲区中采集另外一个数据作为采集到的“CRC”；为了保证检测采集到数据有效性，对数据进行了必要的检验，将刚才保存的三个数据进行相加得到一个数值与刚才采集到的“CRC”进行比较，如果一致证明采集的数据有效，接着就将这三个已确认的有效数据传给更上一层的模块进行相关的逻辑运算或其他操作。
上述的现有技术的数据分析系统存在几个问题：1.缓存显著不足，采集一帧数据，解码部分的速度受运算的CPU所影响，假如CPU的主频不高，底层缓冲数据很容易被更替，这样的话，上述的“帧头”和“CRC”很有可能被破坏，这样采集到有效数据的效率变得很低下；2.采集到有效数据后直接交由其余需要用到解码数据的模块执行操作，其中的操作时间受其这些模块的影响，采集到有效数据的效率也受到相当大的影响。
发明内容
针对上述现有技术中存在的问题，本发明的目的在于提供一种可避免出现上述技术缺陷的适用于多任务调度环境下的双缓冲协议数据分析系统。
为了实现上述发明目的，本发明提供的技术方案如下：
一种适用于多任务调度环境下的双缓冲协议数据分析系统，包括一级环形缓冲区、解码任务模块、二级环形缓冲区、底层数据检测任务模块和底层硬件缓存模块，底层数据检测任务模块用于将底层硬件缓存模块的数据往一级环形缓冲区中送去；解码任务模块从一级环形缓存区中读取数据，进行解码后将得到的数据组往二级环形缓冲区中送去。
进一步地，一级环形缓冲区为环形缓存，每次写入和读出一级环形缓冲区数据的大小都为一个字节，与底层硬件缓存模块的数据大小保持一致。
进一步地，二级环形缓冲区为环形缓存，每次写入和读出二级环形缓冲区的数据大小为解码后的数据组的大小。
进一步地，每次写入和读出二级环形缓冲区的数据为3个字节。
进一步地，二级环形缓冲区还连接有其他要用到解码数据的任务模块，其他要用到解码数据的任务模块主动从二级环形缓冲区中读取数据。
一种适用于多任务调度环境下的双缓冲协议数据分析方法，包括以下步骤：
底层数据检测任务模块在系统启动时后不断地检测底层硬件缓存模块中是否有数据，如果检测到有数据就不断把底层硬件缓存模块的数据往一级环形缓冲区中送去；
解码任务模块在系统启动后不断检测一级环形缓冲区中是否有数据，如果检测到有数据就直接进行解码，然后将解码后的数据传给二级环形缓冲区中进行相关的逻辑运算或其他操作。
进一步地，所述解码任务模块的解码步骤为：解码任务模块从一级环形缓存区中读取数据，对数据进行解码重组，先判断采集的连续的两个数据是否为帧头，如果检测到帧头，就对接着从底层缓冲区采集到的三个数据保存起来，最后再从底层缓冲区中采集另外一个数据作为采集到的CRC；对数据进行必要的检验，将保存的所述三个数据进行相加得到一个数值与采集到的CRC进行比较，如果一致证明采集的数据有效。
本发明提供的适用于多任务调度环境下的双缓冲协议数据分析系统，通过引入三个独立的任务模块和两级可变大小环形缓冲，提高了协议数据解析的正确率和解码速度，同时降低了对硬件性能的依赖；本发明中的两个环形缓冲区的总大小和每次读写的大小是可以随设计需要而改变的，很好地利用了系统资源，特别是应用在嵌入式的环境中更能发挥其优势；本发明还可以应用于其他多种形式的协议数据的解码中，而且能有较高的解码的正确率和速度，可以很好地满足实际应用的需要。
附图说明
图1为为现有技术中常用的不同嵌入式系统之间或PC与嵌入式系统之间带有协议数据的通讯结构框图；
图2为本发明的适用于多任务调度环境下的双缓冲协议数据分析系统的结构框图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，下面结合附图和具体实施例对本发明做进一步说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图2所示，一种适用于多任务调度环境下的双缓冲协议数据分析系统，包括一级环形缓冲区RingBuffer1、解码任务模块、二级环形缓冲区RingBuffer2、底层数据检测任务模块Task和底层硬件缓存模块。
底层数据检测任务模块Task在系统启动时后会一直处于工作状态，其不断地检测底层硬件缓存模块中是否有数据，如果检测到有数据的话就不断把底层硬件缓存模块的数据往一级环形缓冲区RingBuffer1中送去。
一级环形缓冲区RingBuffer1为环形缓存，每次写入和读出RingBuffer1数据的大小都为一个字节，与底层硬件缓存模块的数据大小保持一致。
解码任务模块在系统启动后也处于工作状态，不断检测一级环形缓冲区RingBuffer1中是否有数据，如果检测到有数据就直接进行解码，解码步骤为：解码任务模块从一级环形缓存区RingBuffer1中读取数据，对数据进行解码重组，先判断采集的连续的两个数据是否为“AA”和“BB”这两个帧头，如果检测到帧头，就对接着从底层缓冲区采集到的三个数据保存起来，最后再从底层缓冲区中采集另外一个数据作为采集到的“CRC”(CRC即循环冗余校验码)；为了保证检测采集到数据有效性，对数据进行了必要的检验，将刚才保存的三个数据进行相加得到一个数值与刚才采集到的“CRC”进行比较，如果一致证明采集的数据有效，接着就将这三个已确认的有效数据传给二级环形缓冲区RingBuffer2中进行相关的逻辑运算或其他操作。与图1中所示解码过程不同的是，解码任务模块不再直接从底层硬件缓存模块中读取数据，而是从一级环形缓存区RingBuffer1中读取数据，而且最后解码后得到的数据组主动地往二级环形缓冲区RingBuffer2中送去后马上进行下一轮的解码，不再被动地等待其他需要用到解码数据的模块来把数据采走才开始下一轮的数据解码工作。
二级环形缓冲区RingBuffer2为环形缓存，每次写入和读出RingBuffer2的 数据大小为解码后的数据组的大小，大小为如图2中所示的3个字节，在其他应用上该大小可以适当地发生改变。
二级环形缓冲区RingBuffer2还连接有其他要用到解码数据的任务模块。其他要用到解码数据的任务模块主动从二级环形缓冲区RingBuffer2中读取数据。
一种适用于多任务调度环境下的双缓冲协议数据分析方法，包括以下步骤：
底层数据检测任务模块在系统启动时后不断地检测底层硬件缓存模块中是否有数据，如果检测到有数据就不断把底层硬件缓存模块的数据往一级环形缓冲区中送去；
解码任务模块在系统启动后不断检测一级环形缓冲区中是否有数据，如果检测到有数据就直接进行解码，然后将解码后的数据传给二级环形缓冲区中进行相关的逻辑运算或其他操作。
所述解码任务模块的解码步骤为：解码任务模块从一级环形缓存区中读取数据，对数据进行解码重组，先判断采集的连续的两个数据是否为“AA”和“BB”这两个帧头，如果检测到帧头，就对接着从底层缓冲区采集到的三个数据保存起来，最后再从底层缓冲区中采集另外一个数据作为采集到的CRC；对数据进行必要的检验，将保存的所述三个数据进行相加得到一个数值与采集到的CRC进行比较，如果一致证明采集的数据有效。
以上所述实施例仅表达了本发明的实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (7)

  1. 一种适用于多任务调度环境下的双缓冲协议数据分析系统，其特征在于，包括一级环形缓冲区、解码任务模块、二级环形缓冲区、底层数据检测任务模块和底层硬件缓存模块，底层数据检测任务模块用于将底层硬件缓存模块的数据往一级环形缓冲区中送去；解码任务模块从一级环形缓存区中读取数据，进行解码后将得到的数据组往二级环形缓冲区中送去。
  2. 根据权利要求1所述的适用于多任务调度环境下的数据分析系统，其特征在于，一级环形缓冲区为环形缓存，每次写入和读出一级环形缓冲区数据的大小都为一个字节，与底层硬件缓存模块的数据大小保持一致。
  3. 根据权利要求1-2所述的适用于多任务调度环境下的双缓冲协议数据分析系统，其特征在于，二级环形缓冲区为环形缓存，每次写入和读出二级环形缓冲区的数据大小为解码后的数据组的大小。
  4. 根据权利要求1-3所述的适用于多任务调度环境下的双缓冲协议数据分析系统，其特征在于，每次写入和读出二级环形缓冲区的数据为3个字节。
  5. 根据权利要求1-4所述的适用于多任务调度环境下的双缓冲协议数据分析系统，其特征在于，二级环形缓冲区还连接有其他要用到解码数据的任务模块，其他要用到解码数据的任务模块主动从二级环形缓冲区中读取数据。
  6. 一种适用于多任务调度环境下的双缓冲协议数据分析方法，其特征在于，包括以下步骤：
    底层数据检测任务模块在系统启动时后不断地检测底层硬件缓存模块中是否有数据，如果检测到有数据就不断把底层硬件缓存模块的数据往一级环形缓冲区中送去。
    解码任务模块在系统启动后不断检测一级环形缓冲区中是否有数据，如果检测到有数据就直接进行解码，然后将解码后的数据传给二级环形缓冲区中进行相关的逻辑运算或其他操作。
  7. 根据权利要求1所述的适用于多任务调度环境下的双缓冲协议数据分析方法，其特征在于，所述解码任务模块的解码步骤为：解码任务模块从一级环 形缓存区中读取数据，对数据进行解码重组，先判断采集的连续的两个数据是否为帧头，如果检测到帧头，就对接着从底层缓冲区采集到的三个数据保存起来，最后再从底层缓冲区中采集另外一个数据作为采集到的CRC；对数据进行必要的检验，将保存的所述三个数据进行相加得到一个数值与采集到的CRC进行比较，如果一致证明采集的数据有效。
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