WO2019016940A1

WO2019016940A1 - Display device and driving method thereof

Info

Publication number: WO2019016940A1
Application number: PCT/JP2017/026455
Authority: WO
Inventors: 史幸小林
Original assignee: シャープ株式会社
Priority date: 2017-07-21
Filing date: 2017-07-21
Publication date: 2019-01-24

Abstract

The present application discloses an organic EL display device capable of performing a sufficient threshold value compensation in a pixel circuit regardless of a gradation value of each pixel of an image to be displayed without adding a configuration to the pixel circuit or changing the configuration of the pixel circuit. An initialization signal line VINIj is arranged along each data signal line Dj in a display unit. Before writing a data signal D(j, i) as pixel data through the data signal line Dj corresponding to each pixel circuit Pix(j, i), a data signal line driving circuit initializes a gate voltage Vg of a driving transistor M1 by supplying, to the pixel circuit Pix(j, i) through the corresponding initialization signal line VINIj, an initialization signal Vini(j, i) for a value which has been obtained by subtracting a predetermined value ΔV (fixed value) from the value of the data signal D(j, i). Thus, a gate-source voltage Vgs0 of a driving transistor at the start of a threshold value compensation operation in each pixel circuit Pix(j, i) becomes constant regardless of a gradation value indicated by the pixel data.

Description

Display device and driving method thereof

The present invention relates to a display device, and more particularly to a display device including a display element driven by current such as an organic EL (Electro Luminescence) display device and a method of driving the same.

BACKGROUND In recent years, organic EL display devices provided with pixel circuits including organic electro luminescence (Electro Luminescence) elements (hereinafter referred to as “organic EL elements”) have been put to practical use. The pixel circuit of the organic EL display device includes, in addition to the organic EL element, a drive transistor, a write control transistor, a holding capacitor, and the like. A thin film transistor (hereinafter referred to as "TFT") is used for the drive transistor and the write control transistor, and a holding capacitor is connected to a gate terminal as a control terminal of the drive transistor. From the data signal line to the voltage corresponding to the video signal representing the image to be displayed (more specifically, it is a voltage indicating the gradation value of the pixel to be formed by the pixel circuit, hereinafter referred to as "data voltage") Given. The organic EL element is a self-luminous display element that emits light with luminance according to the amount of current flowing therethrough. The driving transistor is provided in series with the organic EL element, and controls the amount of current flowing to the organic EL element in accordance with the voltage held by the holding capacitor.

Variations and fluctuations occur in the characteristics of the organic EL element and the drive transistor. For this reason, in order to perform high-quality display in the organic EL display device, it is necessary to compensate for variations and fluctuations in the characteristics of these elements. With respect to the organic EL display device, a method of compensating the characteristics of the element inside the pixel circuit and a method of performing compensation outside the pixel circuit are known. In the former method, after the voltage at the gate terminal of the drive transistor, ie, the voltage held by the storage capacitor, is initialized to a predetermined level (hereinafter, the voltage at the gate terminal at the time of initialization is referred to as “initial voltage Vini”) And charging the holding capacitor with the data voltage through the drive transistor in a diode connection state. This compensates for variations and fluctuations in the threshold voltage of the drive transistor (hereinafter, compensation for variations and fluctuations in the threshold voltage is referred to as “threshold compensation”).

The matters relating to the organic EL display as described above are described in Patent Documents 1 to 3. For example, in Patent Document 1, in a pixel circuit of a display device having an organic light emitting element, an initialization voltage is determined in accordance with a threshold voltage fluctuation of the drive transistor M1 or a change in gradation data. It is described that the voltage difference is made constant (paragraphs [0041] to [0046], [0067]). Further, Patent Document 3 mentions a configuration in which a reset voltage Vrst applied to bring the drive transistor 11a constituting the pixel 16 in the EL display device into a reset state is changed according to the video signal voltage Vdata (paragraph [ 0036].

Japanese Patent Application Laid-Open No. 2014-115543 Japanese Patent Application Laid-Open No. 2015-011267 Japan JP 2009-258227

As described above, in the organic EL display device in which the threshold compensation is performed by charging the holding capacitor through the drive transistor in the diode connection state, the time required for the threshold compensation (hereinafter referred to as “time required for threshold compensation”) is The initial gate-source voltage Vgs0 corresponds to the difference between the initial voltage Vini and the data voltage, depending on the gate-source voltage Vgs (hereinafter referred to as "initial gate-source voltage Vgs0") of the drive transistor at the start of charging. Do. Usually, since a fixed voltage is given as the initial voltage Vini, the threshold compensation required time depends on the data voltage, and the threshold compensation required time differs depending on the gradation value of the pixel to be formed by the pixel circuit.

For example, in a pixel circuit using a P-channel TFT as a drive transistor (see FIG. 2 described later), when forming a high gradation pixel (when the data voltage is low), the initial gate-source voltage Vgs0 is small, so data The charging speed of the holding capacitor by the voltage is low, and the time required for threshold compensation becomes long. It is conceivable to use a sufficiently low voltage as the initial voltage Vini to increase the charge rate. However, when the initial voltage Vini is lowered, when forming a low gradation pixel (when the data voltage is high), since the difference between the data voltage and the initial voltage Vini is large, the time required for threshold compensation becomes long. On the other hand, when the horizontal period is shortened along with the recent high definition of display images, the time which can be secured for charging the storage capacitor by the data voltage is also shortened. For this reason, depending on the gradation value of the pixel, the time required for threshold compensation may be insufficient, and the display quality may be degraded.

On the other hand, in the display device of Patent Document 1, good compensation performance can be ensured by making the voltage difference between the initialization voltage and the gradation data constant. However, in the display device of Patent Document 1, each pixel circuit needs a pre-data write operation for making the voltage difference between the initialization voltage and the gradation data constant. Further, Patent Document 3 does not disclose a specific configuration for making the voltage difference between the initialization voltage and the gradation data constant.

Therefore, an organic EL display device or the like capable of sufficiently performing threshold compensation in the pixel circuit regardless of the gradation value of each pixel of the image to be displayed without requiring addition / change of the configuration or the predata write operation for the pixel circuit. It is desirable to provide a current driven display device.

A display device according to some embodiments of the present invention includes a plurality of data signal lines, a plurality of scanning signal lines intersecting the plurality of data lines, the plurality of data signal lines, and the plurality of scanning signal lines. And a plurality of pixel circuits arranged in a matrix along the
A plurality of initialization signal lines disposed to correspond to the plurality of data signal lines,
A data signal line drive circuit for driving the plurality of data signal lines;
And a scanning signal line drive circuit for selectively driving the plurality of scanning signal lines,
Each of the plurality of pixel circuits corresponds to any one of the plurality of data signal lines and corresponds to any one of the plurality of scanning signal lines,
Each pixel circuit includes a display element driven by a current, a drive transistor connected in series with the display element to control a drive current of the display element, and a control terminal of the drive transistor connected to a control terminal of the drive transistor. And the voltage of the corresponding initialization signal line is applied to the holding capacitor before the corresponding scanning signal line is in the selected state, and the corresponding scanning signal line is When in the selected state, the drive transistor is diode-connected, and the voltage of the corresponding data signal line is applied to the holding capacitor via the drive transistor.
The data signal line drive circuit is
A plurality of drive data signals in the form of an analog voltage signal generated by delaying a plurality of data signals representing an image to be displayed by a predetermined time are generated, and the plurality of drive data signals are applied to the plurality of data signal lines, respectively. Driving signal generation circuit,
A plurality of initialization signals each having a plurality of values obtained by subtracting or adding the same predetermined value to each value of the plurality of data signals according to the configuration of the pixel circuit in the form of an analog voltage signal And an initialization signal generation circuit that generates and applies the plurality of initialization signals to the plurality of initialization signal lines.

A driving method according to another embodiment of the present invention includes a plurality of data signal lines, a plurality of scanning signal lines crossing the plurality of data lines, the plurality of data signal lines, and the plurality of scanning signals. A method of driving a display device, comprising: a plurality of pixel circuits arranged in a matrix along a line,
The display device further includes a plurality of initialization signal lines arranged to correspond to the plurality of data signal lines,
Each of the plurality of pixel circuits corresponds to any one of the plurality of data signal lines and corresponds to any one of the plurality of scanning signal lines,
Each pixel circuit includes a display element driven by a current, a drive transistor connected in series with the display element to control a drive current of the display element, and a control terminal of the drive transistor connected to a control terminal of the drive transistor. And the voltage of the corresponding initialization signal line is applied to the holding capacitor before the corresponding scanning signal line is in the selected state, and the corresponding scanning signal line is When in the selected state, the drive transistor is diode-connected, and the voltage of the corresponding data signal line is applied to the holding capacitor via the drive transistor.
The driving method is
A data signal line driving step for driving the plurality of data signal lines;
And a scan signal line drive step of sequentially selecting the plurality of scan signal lines,
The data signal line driving step
Generating, in the form of an analog voltage signal, a plurality of driving data signals in which a plurality of data signals representing an image to be displayed are delayed by a predetermined time;
Applying the plurality of driving data signals to the plurality of data signal lines, respectively;
A plurality of initialization signals each having a plurality of values obtained by subtracting or adding the same predetermined value to each value of the plurality of data signals according to the configuration of the pixel circuit in the form of an analog voltage signal Generating steps,
Applying the plurality of generated initialization signals to the plurality of initialization signal lines.

In the above embodiments of the present invention, in each pixel circuit, the voltage of the corresponding initialization signal line is applied to the holding capacitor before the corresponding scanning signal line is selected, and the corresponding scanning signal line is selected. When in the state, the drive transistor is diode-connected, and the voltage of the corresponding data signal line is applied to the holding capacitor through the drive transistor. Further, a plurality of drive data signals obtained by delaying a plurality of data signals representing an image to be displayed by a predetermined time are applied in the form of analog voltage signals to the plurality of data signal lines, and the plurality of initialization signals A plurality of initialization signals each having a plurality of values obtained by subtracting or adding the same predetermined value to each value of the plurality of data signals according to the configuration of the pixel circuit are analog voltage signals Applied in the form of As a result, in each pixel circuit, a voltage obtained by subtracting or adding the same predetermined voltage (predetermined value) to the voltage of the data signal line to be applied to the holding capacitor in the selection period before the selection period of the corresponding scan signal line. Is given to the holding capacitor as an initialization voltage, and the voltage at the control terminal of the drive transistor is equal to the initialization voltage. Therefore, at the start of the selection period, the voltage between the control terminal of the drive transistor and the conduction terminal on the data signal line side is related to the voltage of the corresponding data signal line (voltage indicating pixel data to be written). The same predetermined value is obtained. As this predetermined value increases, the amount of charge in the holding capacitor increases, but the display is made by determining the predetermined value in advance from the viewpoint of shortening the time required for threshold compensation taking into account the amount of charge and the compensation speed. The variation and fluctuation of the threshold voltage of the drive transistor in each pixel circuit can be sufficiently compensated regardless of the gradation value of each pixel of the image to be processed.

FIG. 1 is a block diagram showing an entire configuration of a display device according to a first embodiment. It is a circuit diagram showing composition of a pixel circuit in a 1st embodiment of the above. It is a signal waveform diagram for demonstrating the drive of the display apparatus which concerns on the said 1st Embodiment. It is a block diagram for demonstrating initialization operation | movement of the control terminal of the drive transistor in the pixel circuit in the said 1st Embodiment. It is a block diagram which shows the whole structure of the display apparatus which concerns on 2nd Embodiment. It is a block diagram which shows the whole structure of the display apparatus which concerns on 3rd Embodiment. FIG. 16 is a circuit diagram for describing a configuration of a demultiplexer included in a data signal line drive circuit in the third embodiment. It is a signal waveform diagram for demonstrating the drive of the display apparatus which concerns on the said 3rd Embodiment. FIG. 21 is a circuit diagram for describing an initialization operation of a control terminal of a drive transistor in a pixel circuit in the third embodiment.

Hereinafter, each embodiment will be described with reference to the attached drawings. In each transistor mentioned below, a gate terminal corresponds to a control terminal, one of a drain terminal and a source terminal corresponds to a first conduction terminal, and the other corresponds to a second conduction terminal. Further, although the transistors in each embodiment are described as being all P-channel transistors, the present invention is not limited thereto. Furthermore, although the transistor in each embodiment is, for example, a thin film transistor, the present invention is not limited thereto. Furthermore, “connection” in the present specification means “electrical connection” unless specifically stated otherwise, and in the range not departing from the gist of the present invention, not only when it means direct connection but also other connections. It also includes the case of implying an indirect connection through an element.

<1. First embodiment>
<1.1 Overall Configuration>
FIG. 1 is a block diagram showing the overall configuration of a display device 10 according to the first embodiment. The display device 10 is an organic EL display device that performs internal compensation. That is, in the display device 10, when writing pixel data to each pixel circuit, the storage capacitor is charged with the voltage (data voltage) of the data signal through the drive transistor in the diode connection state in the pixel circuit. Variations and fluctuations in the threshold voltage of the drive transistor are compensated (details will be described later).

As shown in FIG. 1, the display device 10 includes a display unit 11, a display control circuit 20, a data side drive circuit (also referred to as “data driver”) 30, and a scanning signal line drive / emission control circuit 40. There is. The scanning signal line drive / light emission control circuit 40 is a dual circuit of a scanning signal line drive circuit (also referred to as “gate driver”) and a light emission control circuit (also referred to as emission driver). The circuit and the light emission control circuit may be separated. Further, the scanning signal line drive / light emission control circuit 40 may be formed integrally with the display unit 11. These points are the same in other embodiments and modifications described later.

The display unit 11 includes m (m is an integer of 2 or more) data signal lines D1 to Dm and n + 1 (n is an integer of 2 or more) scan signal lines G0 to Gn crossing these. N emission control lines (also referred to as "emission lines") E1 to En are arranged along n scanning signal lines G1 to Gn, respectively, and m emission data lines D1 to Dm are respectively provided. Along the lines, m initialization signal lines VINI1 to VINIm are arranged. Further, as shown in FIG. 1, the display unit 11 is provided with m × n pixel circuits 15. The m × n pixel circuits 15 include m data signal lines D1 to Dm and n data circuits. Are arranged in a matrix along each of the scanning signal lines G1 to Gn, and each pixel circuit 15 corresponds to any one of m data signal lines D1 to Dm, and n scanning signal lines G1 to In the case where each pixel circuit 15 is to be distinguished, the pixel circuit corresponding to the i-th scanning signal line Gi and the j-th data signal line Dj is referred to as “i-th row j-th column And the symbol “Pix (j, i)”. The m initialization signal lines VINI1 to VINIm correspond to the m data signal lines D1 to Dm, respectively, and the n emission control lines E1 to En correspond to the n scanning signal lines G1 to Gn, respectively. Therefore, each pixel circuit 15 corresponds to any one of m initialization signal lines VINI 1 to VINIm, and also corresponds to any one of n emission control lines E 1 to En. The m data signal lines D1 to Dm and the m initialization signal lines VINI1 to VINIm are connected to the data side drive circuit 30, and the data side drive circuit 30 functions as a data signal line drive circuit. The n + 1 scanning signal lines G 0 to Gn and the n light emission control lines E 1 to En are connected to the scanning side drive / light emission control circuit 40.

Further, the display unit 11 is provided with a power supply line (not shown) common to the pixel circuits 15. More specifically, a power supply line for supplying a high level power supply voltage ELVDD for driving an organic EL element to be described later (hereinafter referred to as "high level power supply line" and denoted by the same reference symbol ELVDD as the high level power supply voltage) And a power supply line for supplying a low level power supply voltage ELVSS for driving the organic EL element (hereinafter referred to as a "low level power supply line" and denoted by the same reference symbol ELVSS as the low level power supply voltage). . These voltages ELVDD and ELVSS are supplied from a power supply circuit (not shown).

The display control circuit 20 receives an input signal Sin including image information representing an image to be displayed and timing control information for image display from the outside of the display device 10, and based on the input signal Sin, the data side control signal Scd and scanning The side control signal Scs is generated, and the data side control signal Scd is output to the data side drive circuit (data signal line drive circuit) 30, and the scan side control signal Scs is output to the scan signal line drive / emission control circuit 40.

As shown in FIG. 1, the data side drive circuit 30 includes a serial / parallel conversion / latch circuit 32, a data signal delay circuit 34, a look-up table (hereinafter abbreviated as "LUT") 36, and an initial / data voltage generation circuit 38. Contains. The data side drive circuit 30 functions as a drive signal generation circuit that generates data signals D (1, i) to D (m, i) for driving the data signal lines D1 to Dm, and an initialization signal. It also functions as an initialization signal generation circuit that generates initialization signals Vini (1, i + 1) to Vini (m, i + 1) to be supplied to lines VINI1 to VINIm (this point is the data side in the second embodiment described later). The same applies to the drive circuit 30b). The data side control signal Scd supplied from the display control circuit 20 to the data side drive circuit 30 includes a digital image signal DA representing an image to be displayed, a data side start pulse signal DSP, a data side clock signal DCK, and a latch pulse. Based on these signals, serial / parallel conversion / latch circuit 32 converts digital image signal DA representing an image to be displayed from serial form to parallel form, and based on latch pulse signal LS. The data for one line of the image to be displayed is output in parallel for each horizontal period. Assuming that the horizontal period in which the i-th scanning signal line in the display unit 11 is active (low level in this embodiment) is referred to as “i-th horizontal period” (i = 1 to n), a serial-parallel conversion / latch circuit 32 are m internal digital signals d (1, i) to d (m,) corresponding to one row of image data to be written to the display section 11 in the i-th horizontal period immediately before the i-1 horizontal period. i) is output in parallel, and the outputs of the internal digital signals d (1, i) to d (m, i) are maintained during the (i-1) th horizontal period (see FIGS. 3 and 4 described later). The data signal delay circuit 34 delays the internal digital signals d (1, i) to d (m, i) for one row output from the serial / parallel conversion / latch circuit 32 by one horizontal period. Thus, these internal digital signals d (1, i) to d (m, i) are output from the data signal delay circuit 34 in the ith horizontal period. In this i-th horizontal period, as shown in FIG. 1, the m-piece internal digital signals corresponding to one row of image data to be written to the display unit 11 from the serial / parallel conversion / latch circuit 32 in the i + 1 horizontal period. d (1, i + 1) to d (m, i + 1) are output in parallel.

The LUT 36 is configured to convert each internal digital signal d (j, i + 1) output from the serial / parallel conversion / latch circuit 32 into a signal having a value obtained by subtracting a predetermined value ΔV (> 0) described later from the value. (J = 1 to m). That is, the LUT 36 functions as a digital operation circuit that subtracts the predetermined value ΔV from the value of each internal digital signal d (j, i + 1), and outputs m signals corresponding to the subtraction result as an initialization digital signal. Here, the predetermined value ΔV is a fixed value, and an appropriate value is determined in advance in consideration of a compensation speed described later and a charge amount at the time of data writing.

The initial / data voltage generation circuit 38 functions as a DA converter, and outputs m internal digital signals d (1, i) to d (m, i) output from the data signal delay circuit 34 to m analog voltage signals. Of the first DA conversion circuit for converting data signals D (1, i) to D (m, i), and initialization of m initialization digital signals output from the LUT 36 into m analog voltage signals And a second DA conversion circuit for converting signals Vini (1, i + 1) to Vini (m, i + 1), respectively. Further, the initial / data voltage generation circuit 38 has an output buffer circuit realized by using a voltage follower or the like, and in the i-th horizontal scanning period, the data signals D (1, i) to D (m, i) Is output through the output buffer circuit and applied to the data signal lines D1 to Dm in the display unit 11, and the initialization signals Vini (1, i + 1) to Vini (m, i + 1) are output through the output buffer circuit. Then, the signal is outputted and applied to initialization signal lines VINI1 to VINIm in the display unit 11, respectively. The data signal D (j, i) indicates pixel data to be written to the pixel circuit Pix (j, i) in the i-th row and the j-th column.

The scan signal line drive / light emission control circuit 40 drives the scan signal lines G0 to Gn and the light emission control lines E1 to En based on the scan side control signal Scs from the display control circuit 20. More specifically, the scanning signal line drive / light emission control circuit 40 sequentially selects one scanning signal line from the scanning signal lines G0 to Gm based on the scanning side control signal Scs, and selects the selected scanning signal line Gk. Apply an active signal (low level voltage) to it. As a result, the m pixel circuits Pix (1, k) to Pix (m, k) corresponding to the selected scanning signal line Gk (1 ≦ k ≦ n) are collectively selected. As described above, in the k-th horizontal period, the data-side drive circuit 30 generates m data signals D (1, k) to D (m, k) corresponding to the digital image signal DA based on the data-side control signal Scd. The data signal lines D1 to Dm are respectively applied. Thus, voltages of m data signals D (1, k) to D (m, k) are selected as pixel data in the selected m pixel circuits Pix (1, k) to Pix (m, k). Will be written. Further, the scanning signal line drive / light emission control circuit 40 applies a light emission control signal (high level voltage) indicating no light emission in the (i-1) -th horizontal period and the ith horizontal period to the ith light emission control line Ei. In the other periods, a light emission control signal (low level voltage) indicating light emission is applied. The organic EL elements in the pixel circuit (hereinafter also referred to as "pixel circuit in the i-th row") Pix (1, i) to Pix (m, i) corresponding to the i-th scanning signal line Gi are the light emission control lines Ei. While the voltage is low, that is, while the light emission control line Ei is in the selected state, light is emitted with luminance according to the data voltage written to the pixel circuits Pix (1, i) to Pix (m, i).

<1.2 Configuration of Pixel Circuit>
FIG. 2 is a circuit diagram showing a configuration of the pixel circuit 15, and more specifically, a circuit diagram showing a configuration of a pixel circuit Pix (j, i) corresponding to the i-th scanning signal line Gi and the j-th data signal line Dj. (1 ≦ i ≦ n, 1 ≦ j ≦ m). As shown in FIG. 2, the pixel circuit 15 includes an organic EL element OLED, a drive transistor M1, a write transistor M2, a compensation transistor M3, an initialization transistor M4, a power supply transistor M5, a light emission control transistor M6, and , And includes a data holding capacitor C1 for holding a data voltage.

In the pixel circuit 15, corresponding scanning signal lines (referred to as “corresponding scanning signal lines” for convenience in the description focusing on the pixel circuits) Gi, and scanning signal lines (scanning signal lines G1 to Gn) immediately before the corresponding scanning signal lines Gi. The scanning signal line immediately before in the scanning order, which is referred to as “preceding scanning signal line” Gi-1 for convenience in the description focusing on the pixel circuit, and the corresponding emission control line (for convenience in the description focusing on the pixel circuit Line “) Ei, the corresponding data signal line (referred to as“ corresponding data signal line ”for convenience in the description focusing on the pixel circuit) Dj, and the corresponding initialization signal line (corresponding corresponding to the description focusing on the pixel circuit Are connected, the high level power supply line ELVDD, and the low level power supply line ELVSS.

In the pixel circuit 15, the write transistor M2 has a gate terminal connected to the corresponding scanning signal line Gi and a source terminal connected to the corresponding data signal line Dj, and functions as a switching element. The write transistor M2 supplies the voltage of the corresponding data signal line Dj, that is, the voltage of the data signal D (j, i) as the data voltage to the drive transistor M1 in response to the selection of the corresponding scan signal line Gi. The source terminal as the first conduction terminal of the drive transistor M1 is connected to the drain terminal of the write transistor M2. The drive transistor M1 supplies a drive current I corresponding to the gate-source voltage Vgs to the organic EL element OLED. The compensation transistor M3 is provided between the gate terminal as the control terminal of the drive transistor M1 and the drain terminal as the second conduction terminal, and functions as a switching element. The gate terminal of the compensation transistor M3 is connected to the corresponding scanning signal line Gi. The compensation transistor M3 makes the drive transistor M1 in a diode connection state according to the selection of the corresponding scanning signal line Gi.

The gate terminal of the initialization transistor M4 is connected to the preceding scan signal line Gi-1, and is provided between the gate terminal of the drive transistor M1 and the corresponding initialization signal line VINIj, and functions as a switching element. The initializing transistor M4 applies the voltage of the corresponding initializing signal line VINIj, that is, the voltage of the initializing signal Vini (j, i) to the data holding capacitor C1 in response to the selection of the preceding scanning signal line Gi-1. The voltage (hereinafter referred to as "gate voltage") Vg of the gate terminal of the drive transistor M1 is initialized.

The power supply transistor M5 has a gate terminal connected to the light emission control line Ei, is provided between the high level power supply line ELVDD and the first conductive terminal of the drive transistor M1, and functions as a switching element. The power supply transistor M5 supplies the high level power supply voltage ELVDD to the source terminal as the first conduction terminal of the drive transistor M1 according to the selection of the light emission control line Ei. The light emission control transistor M6 has a gate terminal connected to the light emission control line Ei, is provided between the drain terminal as the second conduction terminal of the drive transistor M1 and the anode of the organic EL element OLED, and functions as a switching element Do. The light emission control transistor M6 transmits the drive current I to the organic EL element OLED in accordance with the selection of the light emission control line Ei.

The data holding capacitor C1 has a first terminal connected to the high level power supply line ELVDD, and a second terminal connected to the gate terminal of the driving transistor M1. The data holding capacitor C1 is charged with the voltage (data voltage) of the corresponding data signal line Dj when the corresponding scanning signal line Gi is in the selected state, and holds the data voltage written by this charging, thereby the corresponding scanning. When the signal line Gi is in the non-selected state, the gate voltage Vg of the drive transistor M1 is maintained. As described above, the voltage of the corresponding initialization signal line VINIj is applied to (the second terminal of) the data holding capacitor C1 in accordance with the selection of the preceding scanning signal line Gi-1, so that the gate voltage of the drive transistor M1 Vg is initialized.

The organic EL element OLED has an anode connected to the second conduction terminal of the drive transistor M1 via the light emission control transistor M6, and a cathode connected to the low level power supply line ELVSS. The organic EL element OLED emits light at a luminance corresponding to the drive current I.

<1.3 Drive method>
Next, a method of driving the display device 10 according to the present embodiment will be described with reference to FIGS. 1 to 4 focusing on the pixel circuit Pix (j, i) in the i-th row and j-th column shown in FIG. FIG. 3 is a signal waveform diagram for explaining the driving of the display device 10 according to the present embodiment, and FIG. 4 is an initial stage of the gate terminal of the drive transistor M1 of the pixel circuit Pix (j, i) in the present embodiment. It is a block diagram for demonstrating the conversion operation.

FIG. 3 shows changes in respective signals in initialization and pixel data writing in the pixel circuit Pix (j, i) in the i-th row and the j-th column. In FIG. 3, a period from time t1 to t6 is a non-light emission period of the pixel circuits Pix (1, i) to Pix (m, i) in the i-th row. The period from time t2 to t4 is the (i-1) -th horizontal period, and the period from time t2 to t3 is the selection period of the (i-1) -th scanning signal line Gi-1 ("i-1st scanning selection period" or It is called "scanning selection period". The scan selection period (t2 to t3) corresponds to the discharge period of the pixel circuits Pix (1, i) to Pix (m, i) in the i-th row, and the pixel circuits Pix (1, i) on the i-1th row. It also corresponds to the write / threshold compensation period of −1) to Pix (m, i−1). The period from time t4 to t7 is the ith horizontal period, and the period from time t4 to t5 is the selection period of the ith scanning signal line Gi (referred to as "the ith scanning selection period" or simply "scanning selection period") . The scan selection period (t4 to t5) corresponds to the write / threshold compensation period of the pixel circuits Pix (1, i) to Pix (m, i) in the i-th row, and the pixel circuit Pix (i + 1) -th row is selected. , I + 1) to Pix (m, i + 1).

In the pixel circuit Pix (j, i) in the i-th row and j-th column, when the voltage of the light emission control line Ei changes from low level to high level at time t1 as shown in FIG. It changes to the off state, and the organic EL element OLED is in the non-emission state. Data signal D (j, i-1) is applied to data signal line Dj by data side drive circuit 30 from time t1 to the start time t2 of the (i-1) th scan selection period, and the initialization signal line An initialization signal Vini (j, i) is applied to VINIj. The operation of the data side drive circuit 30 at this time will be described with reference to FIG.

From time t1 to the start time t2 of the (i-1) -th horizontal period, the serial-to-parallel conversion / latch circuit 32 generates the pixel circuits Pix (1, i) to Pix in the i-th row of the display unit 11 in the i-th horizontal period. Outputting m internal digital signals d (1, i) to d (m, i) corresponding to one line of image data to be written to (m, i) in parallel (see FIG. 4); The output of the internal digital signals d (1, i) to d (m, i) is maintained during the -1 scanning selection period (t2 to t3). Data signal delay circuit 34 delays internal digital signals d (1, i) to d (m, i) for one row by one horizontal period. Therefore, these internal digital signals d (1, i) to d (m, i) are output from data signal delay circuit 34 in the ith horizontal period (see FIG. 1).

Also, from the time t1 to the start time t2 of the (i-1) -th horizontal period, the internal digital signals d (1, i-1) to d (m,) for one row stored in the data signal delay circuit 34. i-1) is output from the data signal delay circuit 34 and input to the initial / data voltage generation circuit 38. On the other hand, the internal digital signals d (1, i) to d (m, i) output from the serial / parallel conversion / latch circuit 32 are also input to the LUT 36, thereby subtracting their respective values by a predetermined value ΔV. It is converted into m digital signals having values. These m digital signals are also input to the initial / data voltage generation circuit 38 as m digital initialization signals.

As shown in FIG. 4, the initial / data voltage generation circuit 38 generates m internal digital signals d (1, i-1) to d (m, i-1) output from the data signal delay circuit 34. Data signals D (1, i-1) to D (m, i-1) which are analog voltage signals are respectively converted. These data signals D (1, i-1) to D (m, i-1) are applied to the data signal lines D1 to Dm in the display unit 11 at least during the (i-1) th scan selection period (t2 to t3). Each is applied (see FIG. 3). Further, the initial / data voltage generation circuit 38 converts the m initialization digital signals output from the LUT 36 into initialization signals Vini (1, i) to Vini (m, i) which are m analog voltage signals. Do. These initialization signals Vini (1, i) to Vini (m, i) are respectively applied to initialization signal lines VINI1 to VINIm in the display unit 11 at least during the (i-1) th scan selection period (t2 to t3). (See Figure 3).

In the (i-1) th selective scanning period (t2 to t3), the voltage of the data signals D (1, i-1) to D (m, i-1) becomes a data signal by the operation of the data side drive circuit 30 as described above. The pixel circuits Pix (1, i-1) to Pix (m, i-1) in the (i-1) -th row are written via the lines D1 to Dm. Further, by the operation of the data side drive circuit 30, the voltage of the initialization signals Vin (1, i) to Vini (m, i) is set to the pixel circuit Pix in the i-th row through the initialization signal lines VINI1 to VINIm. The voltages are respectively given as (1, i) to Pix (m, i) as initialization voltages. At this time, in each pixel circuit Pix (j, i) in the i-th row, the voltage of the corresponding initialization signal line VINIj is applied to the data holding capacitor C1 through the initialization transistor M4, whereby the charge of the data holding capacitor C1 is generated. Is discharged to initialize the gate voltage Vg of the drive transistor M1.

The serial-to-parallel conversion / latch circuit 32 generates the pixel circuit Pix in the (i + 1) th row of the display unit 11 in the (i + 1) -th horizontal period from the end time t3 of the i-1th scan selection period to the start time t4 of the i-th horizontal period. M internal digital signals d (1, i + 1) to d (m, i + 1) corresponding to one row of image data to be written to (1, i + 1) to Pix (m, i + 1) are output in parallel (see FIG. 1), maintaining the output of the internal digital signals d (1, i + 1) to d (m, i + 1) for at least the ith scan selection period (t4 to t5). The data signal delay circuit 34 delays the internal digital signals d (1, i + 1) to d (m, i + 1) for one row output from the serial / parallel conversion / latch circuit 32 by one horizontal period.

In addition, the internal digital signal d (1, i) for one row stored in data signal delay circuit 34 from the end time t3 of the (i-1) th scan selection period to the start time t4 of the ith horizontal period. ... D (m, i) are output from the data signal delay circuit 34 and input to the initial / data voltage generation circuit 38. On the other hand, the internal digital signals d (1, i + 1) to d (m, i + 1) output from the serial / parallel conversion / latch circuit 32 are also input to the LUT 36, thereby subtracting their respective values by a predetermined value ΔV. It is converted into m digital signals having values. These m digital signals are also input to the initial / data voltage generation circuit 38 as m digital initialization signals.

As shown in FIG. 1, the initial / data voltage generation circuit 38 outputs m internal digital signals d (1, i) to d (m, i) output from the data signal delay circuit 34 to m analog voltage signals. Each data signal D (1, i) to D (m, i) is converted. These data signals D (1, i) to D (m, i) are respectively applied to data signal lines D1 to Dm in the display unit 11 at least during the i-th scan selection period (t4 to t5) (see FIG. 3). Further, the initial / data voltage generation circuit 38 converts the m initialization digital signals output from the LUT 36 into initialization signals Vini (1, i + 1) to Vini (m, i + 1) which are m analog voltage signals. Do. These initialization signals Vini (1, i + 1) to Vini (m, i + 1) are respectively applied to initialization signal lines VINI1 to VINIm in display unit 11 at least during the i-th scan selection period (t4 to t5). (See Figure 3).

In the i-th selection scanning period (t4 to t5), the voltage of the data signals D (1, i) to D (m, i) is transmitted through the data signal lines D1 to Dm by the operation of the data side drive circuit 30 as described above. The data is written to the pixel circuits Pix (1, i) to Pix (m, i) in the i-th row. At this time, in each pixel circuit Pix (j, i) (j = 1 to m) in the i-th row, the voltage of the corresponding data signal line Dj is applied to the data holding capacitor C1 through the drive transistor M1 in the diode connection state. Thus, variations and fluctuations in the threshold voltage of the drive transistor M1 are compensated. The operation of the pixel circuit at this time will be described with reference to FIG. 2 focusing on the pixel circuit Pix (j, i) in the i-th row and the j-th column.

In the pixel circuit Pix (j, i) in the i-th row and the j-th column, the initialization transistor M4 is in the on state in the (i-1) th scan selection period (t2 to t3), and the voltage of the corresponding initialization signal line VINIj is The gate voltage Vg of the drive transistor M1 is initialized to the voltage of the initialization signal Vini (j, i) by being supplied to the data holding capacitor C1 through the initialization transistor M4. The initialization signal Vini (j, i) is an analog voltage signal generated by the above-described operation in the data side drive circuit 30 (see FIG. 4), and from the value of the internal digital signal d (j, i) It has a value obtained by subtracting a predetermined value ΔV. Therefore, this initialization signal Vini (j, i) can be expressed as the following equation.
Vini (j, i) = D (j, i) -ΔV (1)

Therefore, at the start time t4 of the i-th scan selection period, the gate voltage Vg of the drive transistor M1 has the value of the initialization signal Vini (j, i) represented by the above equation (1). During the ith scan selection period (t4 to t5), the write transistor M2 and the compensation transistor M3 are in the on state, and the voltage of the corresponding data signal line Dj, that is, the voltage of the data signal D (j, i) Data holding capacitor C1 is applied through transistor M2 and drive transistor M1 in a diode connection state. Thereby, the gate voltage Vg of the drive transistor M1 changes toward a value corresponding to the data signal D (j, i). That is, assuming that the threshold voltage of the drive transistor M1 is Vth (<0), the gate voltage Vg is D (j, i) from the value of the initialization signal Vini (j, i) in the ith selection scan period (t4 to t5). It changes toward)-| Vth |. Here, for convenience of explanation, it is assumed that the gate voltage Vg has reached D (j, i)-| Vth | at the end time t5 of the i-th scanning selection period.

At time t5, the write transistor M2 and the compensation transistor M3 change to the off state, and after time t5, the data holding capacitor C1 holds the voltage indicated by ELVDD-D (j, i) + | Vth |.

Thereafter, at time t6, the voltage of the light emission control line Ei changes to the low level. Along with this, the power supply transistor M5 and the light emission control transistor M6 are turned on. After time t6, current flows from the high level power supply line ELVDD to the low level power supply line ELVSS via the power supply transistor M5, the drive transistor M1, the light emission control transistor M6, and the organic EL element OLED. This current I1 is expressed by the following equation using a constant K relating to the characteristics of the drive transistor M1, assuming that the gate-source voltage of the drive transistor M1 is Vgs (> 0).
I1 = K (Vgs- | Vth |) ² (2)
When the power supply transistor M5 is on, the gate-source voltage Vgs of the drive transistor M1 corresponds to the voltage held by the data holding capacitor C1,
Vgs = ELVDD-D (j, i) + | Vth | (3)
It is. Therefore, the current I1 is given by the following equation.
I1 = K (ELVDD-D (j, i) + | Vth |-| Vth |)
= K (ELVDD-D (j, i)) ² ... (4)

Thus, after time t6, the organic EL element OLED sets the voltage of the data signal D (j, i) written as the data voltage to the pixel circuit Pix (j, i) regardless of the threshold voltage Vth of the drive transistor M1. It emits light with the corresponding brightness.

<1.4 Actions and effects>
As described above, in the pixel circuit Pix (j, i) in the i-th row and the j-th column, the voltage of the data signal D (j, i) is the data voltage (pixel data) in the i-th scan selection period (t4 to t5) This is a period during which data is written to the data holding capacitor C1. At this time, the data voltage is written via the drive transistor M1 in the diode connection state to compensate for variations and fluctuations in the threshold voltage. Therefore, the ith scan selection period (t4 to t5) corresponds to the threshold compensation period. The compensation speed of the threshold voltage of the drive transistor M1 depends on the gate-source voltage of the drive transistor M1, that is, the initial gate-source voltage Vgs0 at the start time t4 of the threshold compensation period, and the initial gate-source voltage Vgs0 (> 0 The larger the compensation speed, the larger the compensation speed.

In the present embodiment, the gate voltage Vg of the drive transistor M1 at the start time t4 of the i-th scan selection period is Vini (j, i) = D (j, i)-ΔV, so the initial gate-source voltage Vgs0 is It is expressed by the following equation.
Vgs0 = D (j, i) -Vini (j, i)
= ΔV (5)
As described above, since the predetermined value ΔV (> 0) is a fixed value, the compensation speed does not depend on the data voltage (data signal D (j, i)) to be written to the pixel circuit Pix (j, i).

From the above, as the predetermined value ΔV (= D (j, i)-Vini (j, i)) is increased, the compensation speed is increased. However, data is held in the selected scanning period (t4 to t5) as the threshold compensation period. The charge amount (charge amount to be stored) in the capacitor C1 becomes large. Therefore, in the present embodiment, an appropriate predetermined value ΔV is determined in advance based on computer simulation, experiments, or the like from the viewpoint of shortening the time required for threshold value compensation in consideration of the charge amount and the compensation speed.

Thus, in the present embodiment, the initialization signal Vini (j, i) to be supplied to each pixel circuit Pix (j, i) is a value obtained by subtracting the predetermined value ΔV from the value of the data signal D (j, i). Therefore, the gate-source voltage Vgs at the start of the threshold compensation period, that is, the initial gate-source voltage Vgs0 becomes equal to the predetermined value ΔV. Therefore, according to the present embodiment, even if the horizontal period is shortened due to the increase in resolution of the display device, the variation in threshold voltage of the drive transistor in each pixel circuit or the threshold value of each pixel of the image to be displayed. Fluctuation compensation (internal compensation) can be sufficiently performed.

<2. Second embodiment>
In the data-side drive circuit 30b according to the first embodiment, m internal digital signals d (1) corresponding to one row of image data to be written to the pixel circuits Pix (1, i) to Pix (m, i). , I) to d (m, i) by performing digital processing by data signal delay circuit 34 and LUT 36, m internal digital signals and m initialization digital signals delayed by one horizontal period are generated. Data signals D (1, i) to D (m, i) as analog voltage signals to be applied to the data signal lines D1 to Dm in the i-th selection scanning period are generated by DA conversion of these signals. And the initialization signals Vini (1, i) to Vini (m, i) to be applied to the initialization signal lines VINI 1 to VINIm in the (i−1) th scan selection period (see FIG. , Figure 3, Figure 4). However, the configuration of the data side drive circuit 30 is not limited to such a configuration. For example, the data driver circuit may output m internal digital signals d (1, i) to d (m) corresponding to one row of image data to be written to the pixel circuits Pix (1, i) to Pix (m, i). , I) by first performing DA conversion to generate data signals D (1, i) to D (m, i) as analog voltage signals, and thereafter, these data signals D (1, i) to D Analog processing is applied to (m, i) to output data signals D (1, i) to D (m, i) to be applied to data signal lines D1 to Dm in the i-th selection scanning period, The initialization signals Vini (1, i) to Vini (m, i) to be applied to the initialization signal lines VINI1 to VINIm in the (i−1) th scan selection period may be output. Hereinafter, a display apparatus provided with such a data side drive circuit will be described as a second embodiment.

FIG. 5 is a block diagram showing the overall configuration of a display device 10b according to the second embodiment. The display device 10b is also an organic EL display device that performs internal compensation.

In this display device 10b, the configuration of the data side drive circuit 30b is different from the configuration of the data side drive circuit 30 in the first embodiment, but the other configuration and the operation of the other configuration are the first embodiment. (See FIGS. 1 to 3 and 5). Therefore, in the following, the same reference numerals are given to the same parts as those of the first embodiment in the configuration of the present embodiment, and the detailed description will be omitted. Hereinafter, the present embodiment will be described focusing on the data side drive circuit 30b.

As shown in FIG. 5, the data side drive circuit 30b in this embodiment includes a serial-parallel conversion / latch circuit 32, a DA conversion circuit 33, a data signal delay circuit 34a as an analog delay circuit, an analog subtraction circuit 36a, and an output. A buffer circuit 39 is included.

As in the first embodiment, the serial-to-parallel conversion / latch circuit 32 converts the digital image signal DA representing the image to be displayed, the data side start pulse signal DSP, the data side clock signal DCK, and the latch pulse signal LS. Are received from the display control circuit 20, and based on these signals, the digital image signal DA representing the image to be displayed is converted from serial form to parallel form and displayed based on the latch pulse signal LS. Data for one line of the image are output in parallel for each horizontal period. More specifically, the serial-parallel conversion / latch circuit 32 should write to the pixel circuits Pix (1, i) to Pix (m, i) in the i-th row during the i-th horizontal period immediately before the i-1 horizontal period. The m internal digital signals d (1, i) to d (m, i) corresponding to one row of image data are output in parallel, and the internal digital signal d (1, 1) is output during the (i-1) -th horizontal period. i) Maintain the output of d (m, i). Further, the serial / parallel conversion / latch circuit 32 is for one row to be written to the pixel circuits Pix (1, i + 1) to Pix (m, i + 1) in the (i + 1) th row immediately before the ith horizontal period. The m internal digital signals d (1, i + 1) to d (m, i + 1) corresponding to the image data are output in parallel, and during the i-th horizontal period, the internal digital signals d (1, i + 1) to d (m) , I + 1) are maintained.

The DA conversion circuit 33 converts these internal digital signals d (1, i + 1) to d (m, i + 1) into data signals D (1, i + 1) to D (m, i + 1) which are analog voltage signals. These data signals D (1, i + 1) to D (m, i + 1) are input to data signal delay circuit 34a and analog subtraction circuit 26a.

Unlike the data signal delay circuit 34 in the first embodiment, the data signal delay circuit 34a delays each of the data signals D (1, i + 1) to D (m, i + 1) by one horizontal period as an analog voltage signal. Let The data signal delay circuit 34a as such an analog delay circuit can be realized, for example, using a capacitor for holding an analog voltage signal and a transistor as a switching element. The data signals D (1, i + 1) to D (m, i + 1) delayed by one horizontal period are output from the data side drive circuit 30 b through the output buffer circuit 39 and at least during the (i + 1) th scan selection period. Data signal lines D1 to Dm are respectively applied. On the other hand, in the i-th horizontal period, which is the immediately preceding horizontal period, m internals corresponding to one row of image data to be written to the pixel circuits Pix (1, i) to Pix (m, i) in the i-th row. Data signals D (1, i) to D (m, i) obtained by DA converting digital signals d (1, i) to d (m, i) are output from a data signal delay circuit 34a. These data signals D (1, i) to D (m, i) are output from the data side drive circuit 30b through the output buffer circuit 39, and are applied to the data signal lines D1 to Dm for at least the i th scan selection period. Each is applied.

The analog subtraction circuit 36a is an analog operation that subtracts the predetermined value ΔV from each value of the data signals D (1, i + 1) to D (m, i + 1) by analog processing instead of the LUT 26 in the first embodiment. It is a circuit. For example, such an analog subtraction circuit 36a can be realized using a capacitor that holds an analog voltage signal and a transistor as a switching element, or an operational amplifier, a resistance element, and the like. The m analog voltage signals as subtraction results obtained by the analog subtraction circuit 36a are output from the data side drive circuit 30b through the output buffer circuit 39 as initialization signals Vini (1, i + 1) to Vini (m, i + 1). , And is applied to the initialization signal lines VINI1 to VINIm, respectively, for at least the i-th scan selection period.

The output buffer circuit 39 has the same configuration as the output buffer circuit included in the initial / data voltage generation circuit 38 in the first embodiment, and is realized using a voltage follower or the like.

According to the data side drive circuit 30b as described above, the initialization signals Vini (1, i) to Vini (m, i) are at least during the (i-1) th scan selection period, as in the first embodiment. Data signals D (1, i) to D (m, i) are applied to data signal lines D1 to Dm, respectively, for at least the i-th scan selection period. 3). Therefore, the driving method of the display device 10b according to the present embodiment is substantially the same as that of the first embodiment, and each pixel circuit Pix (j, i) operates in the same manner (FIG. 2, FIG. 3). reference). Therefore, the present embodiment exhibits the same effects as those of the first embodiment. In addition to this, according to the present embodiment, since the circuit amount of the DA conversion circuit is greatly reduced (1/2) as compared with the first embodiment (see FIGS. 4 and 5), as an analog delay circuit By appropriately configuring the data signal delay circuit 34a and the analog subtraction circuit 36a, it is possible to reduce the entire circuit amount of the data side drive circuit 30b.

<3. Third embodiment>
In the first and second embodiments, the data signal lines D1 to Dm in the display unit 11 are directly connected to the data side drive circuits 30 and 30b, but instead, the data side drive circuit and the data signal are used. A demultiplexing circuit is provided between lines D1 to Dm, and each data signal D (j, i) generated by the data side drive circuit is demultiplexed to form two or more data signal lines (source line Drive method (hereinafter referred to as “SSD (Source Shared Driving) method)” may be adopted. Hereinafter, an organic EL display device adopting the SSD method will be described as a third embodiment.

<3.1 Configuration>
FIG. 6 is a block diagram showing the overall configuration of a display device 10c according to the third embodiment. The display device 10c is an organic EL display device which performs internal compensation as in the first and second embodiments, but the first and second display devices 10c are different in that the SSD system having a multiplicity of 3 is employed. This is different from the embodiment of FIG. In addition, this display device 10c performs color display with three primary colors of red, green and blue, and sets three data signal lines corresponding to the three primary colors as one set to three data signal lines in each set. An SSD system that drives in a divided manner is adopted. With the adoption of this SSD method, three initialization signal lines respectively corresponding to the three data signal lines corresponding to the three primary colors are regarded as one set, and the initialization signals are provided to three initialization signal lines in each set. It is given time-divisionally. The configuration of this embodiment is the same as that of the first or second embodiment except for the configuration relating to these points, so the same or corresponding portions are denoted with the same reference numerals and detailed description thereof will be omitted.

As shown in FIG. 6, the display device 10c according to the present embodiment includes a display unit 11c, a display control circuit 20, a data signal line drive circuit 35, and a scanning signal line drive / emission control circuit 40.

In the display section 11c, three data signal lines consisting of R data signal lines Drj, G data signal lines Dgj, and B data signal lines Dbj respectively corresponding to red, green and blue constituting the three primary colors are considered as one set. m sets (3 m) of data signal lines Dr1, Dg1, Db1 to Drm, Dgm, Dbm and n + 1 scanning signal lines G0 to Gn intersecting these are arranged, and the 3 m data signals The 3 m initializing signal lines VINIx1 to VINIxm (x = r, g, b) are disposed along the lines Dx1 to Dxm (x = r, g, b), respectively. These 3 m initializing signal lines VINIx1 to VINIxm (x = r, g, b) are also associated with initializing signal lines VINIrj, VINIgj respectively corresponding to R data signal line Drj, G data signal line Dgj, and B data signal line Dbj. , And VIN Ibj are grouped as one set. Hereinafter, the initialization signal line corresponding to the “X data signal line” is also referred to as “X initialization signal line” (X = R, G, B). Further, as in the first embodiment, n emission control lines E1 to En are disposed along n scanning signal lines G1 to Gn, respectively.

Further, as shown in FIG. 6, in the display section 11c, 3m × n pixel circuits 15 include 3m data signal lines Dx1 to Dxm (x = r, g, b) and n scanning signal lines G1 to Gn. The pixel circuits 15 correspond to any one of 3m data signal lines Dx1 to Dxm (x = r, g, b), and n scan signals It corresponds to any one of the lines G1 to Gn. In the following, in order to distinguish each pixel circuit 15, the pixel circuit corresponding to the i-th scanning signal line Gi and the j-th R data signal line Drj is referred to as "the i-th row j-th R pixel circuit" A pixel circuit indicated by a code "Pr (j, i)" and corresponding to the ith scanning signal line Gi and the j-th G data signal line Dgj is referred to as "i-th row j-th G pixel circuit". A pixel circuit indicated by "Pg (j, i)" and corresponding to the i-th scanning signal line Gi and the j-th B data signal line Dbj is referred to as "the i-th row j-th B pixel circuit" It is indicated by Pb (j, i) ". Each pixel circuit Px (j, i) also corresponds to any one of 3m initialization signal lines VINIx1 to VINIxm, and to any one of n emission control lines E1 to En. Also correspond (x = r, g, b). The configuration of each pixel circuit 15 (Px (j, i)) in the present embodiment is the same as the configuration of the pixel circuit 15 in the first embodiment, so the same reference numerals are given to the same portions. Is omitted (see FIG. 2).

The 3m data signal lines Dx1 to Dxm (x = r, g, b) and the 3m initialization signal lines VINIx1 to VINIxm (x = r, g, b) are described later in the data signal line drive circuit 35. The n + 1 scanning signal lines G0 to Gn and the n emission control lines E1 to En, which are connected to the demultiplexing circuit 50, are connected to the scanning signal line drive / emission control circuit 40 as in the first embodiment. It is done.

Further, as in the first embodiment, a high level power supply line (high level power supply voltage) for supplying the high level power supply voltage ELVDD is used as a power supply line (not shown) common to the pixel circuits 15 in the display section 11c. And a power supply line (denoted by the same reference symbol ELVSS as the low level power supply voltage) for supplying the low level power supply voltage ELVSS.

Similar to the first embodiment, the display control circuit 20 receives an input signal Sin from the outside of the display device 10c, and generates a data side control signal Scd and a scan side control signal Scs based on the input signal Sin. The control signal Scd is output to a data-side drive circuit 30 c described later in the data signal line drive circuit 35, and the scan-side control signal Scs is output to the scan signal line drive / emission control circuit 40. In addition to this, the display control circuit 20 outputs an R selection control signal SSDr, a G selection control signal SSDg, and a B selection control signal SSDb to a demultiplexer circuit 50 described later in the data signal line drive circuit 35.

As shown in FIG. 6, the data signal line drive circuit 35 includes a data side drive circuit 30c and a demultiplexer circuit 50. The data signal line drive circuit 35 functions as a drive signal generation circuit that generates data signals Dx (1, i) to Dx (m, i) for driving the data signal lines Dx1 to Dxm, and is initialized. It also functions as an initialization signal generation circuit that generates initialization signals Vinix (1, i + 1) to Vinix (m, i + 1) to be given to the signal lines VINIx1 to VINIxm (x = r, g, b).

The data side drive circuit 30c has the same configuration as any of the data side drive circuits 30 and 30b in the first and second embodiments. However, in the present embodiment, since the SSD method having a multiplicity of 3 as described above is adopted, the data-side drive circuit 30c functions as a time-division data signal generation circuit and a time-division initialization signal It also functions as a generation circuit. That is, based on the data side control signal Scd from the display control circuit 20, the data side drive circuit 30c controls the R data signal Dr (j, i) and G data to be applied to the R data signal line Drj in each horizontal period. Output G data signal Dg (j, i) to be applied to signal line Dgj and B data signal Db (j, i) to be applied to B data signal line Dbj as data signal D (j, i) in a time division manner (J = 1 to m). In addition, the data side drive circuit 30c controls the R initialization signal Vinir (j, i + 1), G to be applied to the R initialization signal line VINIrj in each horizontal period based on the data control signal Scd from the display control circuit 20. The G initialization signal Vinig (j, i + 1) to be applied to the initialization signal line VINIgj and the B initialization signal Vinib (j, i + 1) to be applied to the B initialization signal line VINIbj are time-divisionally initialized to the initialization signal Vini Output as (j, i + 1) (j = 1 to m). That is, each horizontal period includes three periods consisting of the first to third periods, and in the i-th horizontal period, R data signal Dr (j, i) and R initialization signal Vinir (j, i + 1) are generated in the first period. Is output, and the G data signal Dg (j, i) and the G initialization signal Vinig (j, i + 1) are output in the second period, and the B data signal Db (j, i) and the B initialization signal in the third period. Vinib (j, i + 1) is output. The data signals Dr (j, i), Dg (j, i), Db (j, i) are the pixel circuits Pr (j, i), Pg (j, i) of the i-th row and the j-th group, respectively. It shows pixel data to be written to Pb (j, i).

The demultiplexing circuit 50 has m demultiplexers consisting of first to m-th demultiplexers 51 to 5m. Each demultiplexer 5j (j = 1 to m) has the same configuration, and functions as a data demultiplexer that demultiplexes data signal D (j, i) output from data drive circuit 30c. At the same time, it also functions as an initialization demultiplexer that demultiplexes the initialization signal Vini (j, i) output from the data side drive circuit 30c. The R selection control signal SSDr, the G selection control signal SSDg, and the B selection control signal SSDb output from the display control circuit 20 are applied to all the demultiplexers 51 to 5m. The data driver circuit 30c has m data output terminals Ta1 to Tam and m initialization output terminals Tb1 to Tbm, and the input side of the j-th demultiplexer 5j is the j-th data output The output side is connected to the three data signal lines Drj, Dgj, Dbj of the j-th set, which are connected to the terminal Taj and the initialization output terminal Tbj.

FIG. 7 is a circuit diagram for explaining the configuration of the j-th demultiplexer 5j (j = 1 to m). As shown in FIG. 7, each demultiplexer 5j includes, as switching elements, three data selection transistors including an R data selection transistor Mdr, a G data selection transistor Mdg, and a B data selection transistor Mdb. It includes three initialization selection transistors including an R initialization selection transistor Mir, a G initialization selection transistor Mig, and a B initialization selection transistor Mib. R, G, and B selection control signals SSDr, SSDg, and SSDb are applied to gate terminals as control terminals of R, G, and B data selection transistors Mdr, Mdg, and Mdb, respectively. The R, G, and B selection control signals SSDr, SSDg, and SSDb are also applied to gate terminals as control terminals of the initialization select transistors Mir, Mig, and Mib, respectively. Each data selection transistor Mdx is in the on state when the selection control signal SSDx applied to its gate terminal is at the low level (active), and is in the off state when the selection control signal SSDx is at the high level (inactive) (x = r, g, b). Each initialization selection transistor Mix is also on when the selection control signal SSDx applied to its gate terminal is low (active) and off when it is high (inactive) (x = r). , G, b).

Among the select transistors in the j-th demultiplexer 5j, drain terminals as first conduction terminals of R, G, and B data select transistors Mdr, Mdg, Mdb are j-th set of R, G, and B data signal lines The source terminals of Drj, Dgj, and Dbj, which are respectively connected to the second conduction terminals of R, G, and B data selection transistors Mdr, Mdg, and Mdb, are all connected to the j-th data in data side drive circuit 30c. It is connected to the output terminal Taj. Drain terminals as first conduction terminals of R, G, and B initialization selection transistors Mir, Mig, and Mib are connected to j-th R, G, and B initialization signal lines VINIrj, VINIgj, and VINIbj, respectively. The source terminals of the R, G, and B initialization selection transistors Mir, Mig, Mib as the second conduction terminals are all connected to the j-th initialization output terminal Tbj in the data side drive circuit 30c. There is.

<3.2 Drive method>
Next, the driving method of the display device 10c according to the present embodiment focuses on the three pixel circuits Pr (j, i), Pg (j, i) and Pb (j, i) in the i-th row and j-th group. Description will be made with reference to FIGS. 2 and 6 to 9. FIG. 8 is a signal waveform diagram for explaining the driving of the display device 10c according to the present embodiment, and FIG. 9 is an initialization of the gate terminal (control terminal) of the drive transistor M1 of the pixel circuit 15 in the present embodiment. It is a block diagram for demonstrating operation | movement.

FIG. 8 shows changes in respective signals in initialization and pixel data writing in three pixel circuits Pr (j, i), Pg (i, j), Pb (i, j) in the i-th row and j-th set. ing. In FIG. 8, the period from time t1 to t13 is a non-light emission period of the pixel circuits Px (1, i) to Px (m, i) (x = r, g, b) in the i-th row. The period from time t1 to t7 is the (i-1) -th horizontal period, and the period from time t5 to t6 is the selection period of the (i-1) -th scanning signal line Gi-1, ie, the scanning selection period within the (i-1) -th horizontal period. is there. The scan selection period (t5 to t6) corresponds to the discharge period of the pixel circuits Px (1, i) to Px (m, i) (x = r, g, b) in the i-th row, and i-1 row It also corresponds to the write / threshold compensation period of the pixel circuits Px (1, i-1) to Px (m, i-1) (x = r, g, b) of the eye. The period from time t7 to t13 is the ith horizontal period, and the period from time t11 to t12 is the selection period of the ith scanning signal line Gi, that is, the scanning selection period within the ith horizontal period. The scan selection period (t11 to t12) corresponds to the write / threshold compensation period of the pixel circuits Px (1, i) to Px (m, i) (x = r, g, b) in the i-th row, It also corresponds to the discharge period of the pixel circuits Px (1, i + 1) to Px (m, i + 1) (x = r, g, b) in the (i + 1) th row.

In this embodiment, in each horizontal period as shown in FIG. 8, the R selection control signal SSDr and the G selection control signal SSDg are provided in a period (hereinafter referred to as a “pre-selection period”) before the start time of the scan selection period. , And B selection control signals SSDb sequentially go low (active) for a predetermined period, so that in each demultiplexer 5j, the R data selection transistor Mdr, the G data selection transistor Mdg, and the B data selection transistor Mdb The predetermined period is sequentially turned on, and the selection transistor for R initialization Mir, the selection transistor for G initialization Mig, and the selection transistor B for B initialization are sequentially turned on for the predetermined period (see FIG. 7). .

On the other hand, as shown in FIG. 8, the R selection control signal SSDr and the G selection control are generated from the data output terminal Taj of the data driver circuit 30c in the pre-selection period (t1 to t5) in the (i-1) th horizontal period. R data signal Dr (j, i-1), G data signal Dg (j, i-1), and B data signal Db (j, i-1) are interlocked with signals SSDg and B selection control signal SSDb. It is output sequentially. The voltage of the R data signal Dr (j, i-1), the G data signal Dg (j, i-1), and the B data signal Db (j, i-1), which are sequentially output, is the above-mentioned demultiplexer 5j. Are supplied to the data signal lines Drj, Dgj, Dbj, respectively, and held in the wiring capacitances of the data signal lines Drj, Dgj, Dbj (hereinafter, each data signal line Dxj (x = r, g, b) The wiring capacitance to be formed is called "data line capacitance Cdxj". That is, during the period before the selection (t1 to t5), when R selection control signal SSDr is at a low level (hereinafter referred to as "R line charging period"), the R data signal is generated with the voltage of R data signal Dr (j, i-1). The data line capacitance Cdrj, which is the line capacitance of the line Drj, is charged, and the voltage of the G data signal Dg (j, i-1) is maintained while the G selection control signal SSDg is low (hereinafter referred to as the "G line charging period"). The data line capacitance Cdgj, which is the wiring capacitance of the G data signal line Dgj, is charged, and the B data signal Db (j, i-1) is in a period in which the B selection control signal SSDb is low (hereinafter referred to as "B line charging period"). The data line capacitance Cdbj, which is the wiring capacitance of the B data signal line Dbj, is charged with the voltage of As shown in FIG. 8, the voltage of R data signal line Drj at the end of R line charging period, the voltage of G data signal line Dgj at the end of G line charging period, and B at the end of B line charging period. The voltage of the data signal line Dbj is held at least during a scan selection period (t5 to t6) in the horizontal period.

Further, from the initialization output terminal Tbj of the data side drive circuit 30c, as shown in FIG. 8, the R selection control signal SSDr or G is selected in the pre-selection period (t1 to t5) in the (i-1) th horizontal period. The R initialization signal Vinir (j, i), the G initialization signal Vinig (j, i), and the B initialization signal Vinib (j, i) are sequentially interlocked with the control signal SSDg and the B selection control signal SSDb. It is output. The voltages of the R initialization signal Vinir (j, i), the G initialization signal Vinig (j, i), and the B initialization signal Vinib (j, i) that are sequentially output are initialized by the demultiplexer 5 j. Signal lines VINIrj, VINIgj, and VINIbj are supplied to the wiring capacitances of their respective initialization signal lines VINIrj, VINIgj, and VINIbj (hereinafter referred to as “initialization signal lines VINIxj (x = r, g, b) The wiring capacitance formed is called “initialization line capacitance Cixj”). That is, in the R-line charging period in the pre-selection period (t1 to t5), the voltage of the R initialization signal Vinir (j, i) charges the initialization line capacitance Cirj which is the wiring capacitance of the R initialization signal line VINIri, In the G-line charging period, the initialization line capacitance Cigj, which is the wiring capacitance of the G initialization signal line VINIgj, is charged with the voltage of the G initialization signal Vinig (j, i), and in the B-line charging period, the B initialization signal Vinib (j , And i) charge the initialization line capacitance Cibj, which is the wiring capacitance of the B initialization signal line VINIbj. As shown in FIG. 8, the voltage of the R initialization signal line VINIrj at the end of the R line charging period, the voltage of the G initialization signal line VINIgj at the end of the G line charging period, and the end of the B line charging period. The voltage of the B initialization signal line VINIbj is held at least during a scan selection period (t5 to t6) within the horizontal period.

After that, the voltage of the scanning signal line Gi-1 changes to low level (active) at the start of the scanning selection period (t5 to t6), and during the scanning selection period (t5 to t6), the voltage becomes low level. Maintained. Therefore, during this scan selection period (t5 to t6), writing transistor M2 in each pixel circuit Px (j, i-1) (x = r, g, b) in the i-1th row j group and The compensation transistor M3 is in the on state, and the initialization transistor M4 in each pixel circuit Px (j, i) (x = r, g, b) in the i-th row and the j-th group is also in the on state (see FIG. 2) .

Therefore, in this scan selection period (t5 to t6), the voltage of R data signal line Drj, that is, the voltage of R data signal Dr (j, i-1) held in data line capacitance Cdrj is i-1 row j The voltage of the G data signal line Dgj, that is, the voltage of the G data signal Dg (j, i-1) held in the data line capacitance Cdgj is written in the R pixel circuit Pr (j, i-1) of the set as the pixel data. Are written as pixel data into the G pixel circuit Pg (j, i-1) in the i-1th row j set, and the voltage of the B data signal line Dbj, that is, the B data signal Db held in the data line capacitance Cdbj , I-1) are written as pixel data in the i-th row and j-th set of B pixel circuits Pb (j, i-1).

Further, during this scan selection period (t5 to t6), the voltage of R initialization signal line VINIrj, that is, the voltage of R initialization signal Vinir (j, i) held in initialization line capacitance Cirj The gate voltage Vg of the drive transistor M1 is initialized by being supplied to the data holding capacitor C1 in the R pixel circuit Pr (j, i) of the eye. Further, the voltage of the G initialization signal line VINIgj, that is, the voltage of the G initialization signal Vinig (j, i) held in the initialization line capacitance Cigj is in the i th row j th G pixel circuit Pg (j, i) The gate voltage Vg of the drive transistor M1 is initialized by being applied to the data holding capacitor C1, and the B initialization signal Vinib (j, j) held by the voltage of the B initialization signal line VINIbj, that is, the initialization line capacitance Cibj. The voltage of i) is applied to the data holding capacitor C1 in the i-th row and j-th set of B pixel circuits Pb (j, i) to initialize the gate voltage Vg of the drive transistor M1.

Also in the pre-selection period (t7 to t11) in the i-th horizontal period (t7 to t13) which is the next horizontal period, in each demultiplexer 5j, the R data select transistor Mdr, the G data select transistor Mdg, and B are selected. The data selection transistor Mdb is sequentially turned on for each predetermined period, and the R initialization selection transistor Mir, the G initialization selection transistor Mig, and the B initialization selection transistor Mib are also sequentially turned on for the predetermined period. (See Figure 7).

In the pre-selection period (t7 to t11) in the ith horizontal period, the R selection control signal SSDr, the G selection control signals SSDg, and B as shown in FIG. 8 from the data output terminal Taj of the data driver circuit 30c. The R data signal Dr (j, i), the G data signal Dg (j, i), and the B data signal Db (j, i) are sequentially output in conjunction with the selection control signal SSDb. The voltage of the R data signal Dr (j, i), the G data signal Dg (j, i), and the B data signal Db (j, i), which are sequentially output, is output from the data signal line Drj, The data are supplied to Dgj and Dbj, and are held in the wiring capacitances of the data signal lines Drj, Dgj and Dbj, respectively. That is, in the R-line charging period in the pre-selection period (t7 to t11), the data line capacitance Cdrj, which is the wiring capacitance of the R data signal line Drj, is charged with the voltage of the R data signal Dr (j, i). Data line capacitance Cdgj, which is the wiring capacitance of G data signal line Dgj, is charged with the voltage of G data signal Dg (j, i) in the line charging period, and the voltage of B data signal Db (j, i) is charged in the B line charging period. Thus, the data line capacitance Cdbj, which is the wiring capacitance of the B data signal line Dbj, is charged. The voltage of R data signal line Drj at the end of R line charging period, the voltage of G data signal line Dgj at the end of G line charging period, and the voltage of B data signal line Dbj at the end of B line charging period are And at least for a scanning selection period (t11 to t12) in the horizontal period.

In addition, in the pre-selection period (t7 to t11) in the ith horizontal period, the R selection control signal SSDr and the G selection control signal SSDg as shown in FIG. 8 from the initialization output terminal Tbj of the data driver circuit 30c. The R initialization signal Vinir (j, i + 1), the G initialization signal Vinig (j, i + 1), and the B initialization signal Vinib (j, i + 1) are sequentially output in synchronization with the, and B selection control signals SSDb. . The voltages of the R initialization signal Vinir (j, i + 1), the G initialization signal Vinig (j, i + 1), and the B initialization signal Vinib (j, i + 1) that are sequentially output are initialized by the demultiplexer 5 j. The signal lines VINIrj, VINIgj, and VINIbj are respectively supplied, and held in the wiring capacitances of the initialization signal lines VINIrj, VINIgj, and VINIbj, ie, initialization line capacitances Cirj, Cigj, and Cibj.

After that, the voltage of the scanning signal line Gi changes to the low level (active) at the start of the scanning selection period (t11 to t12), and the voltage is kept at the low level during the scanning selection period (t11 to t12) Be done. Therefore, the writing transistor M2 and the compensating transistor M3 in each pixel circuit Px (j, i) (x = r, g, b) in the i-th row and the j-th group during the scanning selection period (t11 to t12). Is on (see FIG. 2).

Therefore, in this scan selection period (t11 to t12), the voltage of R data signal line Drj, that is, the voltage of R data signal Dr (j, i) held in data line capacitance Cdrj The voltage of the G data signal line Dgj written to the pixel circuit Pr (j, i) as pixel data, that is, the voltage of the G data signal Dg (j, i) held in the data line capacitance Cdgj is the i-th row j-th group The voltage of the B data signal line Dbj written to the G pixel circuit Pg (j, i) as pixel data, that is, the voltage of the B data signal Db (j, i) held in the data line capacitance Cdbj is the i-th row j set Are written as pixel data in the B pixel circuit Pb (j, i) of Writing of pixel data to the pixel circuit Px (i, j) (x = r, g, b) in the i-th row and j-th group is performed on the pixel to the R pixel circuit Pr (i, j) in the i-th row and j-th group Data writing will be described in more detail by way of example. In the following, it is assumed that the threshold voltage (<0) of the drive transistor in each pixel circuit Px (i, j) in the i-th row and the j-th set is represented by “Vthx” (x = r, g, b).

As described above, in the i-th row and j-th R pixel circuit Pr (j, i), the voltage of the R initialization signal line VINIrj, that is, the scan selection period (t5 to t6) in the i-1 horizontal period. R initialization signal Vinir (j, i) is applied to data holding capacitor C1 through initialization transistor M4, whereby the gate voltage Vg of drive transistor M1 becomes the voltage of R initialization signal Vinir (j, i). It is initialized (see FIGS. 8 and 9). The R initialization signal Vinir (j, i) is an analog voltage signal generated in the data side drive circuit 30c having the same configuration as that of the data side drive circuit 30 or 30b in the first or second embodiment. Yes (see FIG. 4 and FIG. 5) and can be expressed as the following equation.
Vinir (j, i) = Dr (j, i) -ΔV (6)

Therefore, immediately before the scan selection period (t11 to t12) in the i-th horizontal period, the gate voltage Vg of the drive transistor M1 is equal to the value of the R initialization signal Vinir (j, i) shown by the above equation (6). It has become. In the scan selection period (t11 to t12), the writing transistor M2 and the compensating transistor M3 are in the on state, and the voltage of the R data signal line Drj, that is, the R data signal Dr (j, i) is the writing transistor M2. And the data holding capacitor C1 via the drive transistor M1 in the diode connection state (see FIG. 2). Thereby, the gate voltage Vg of the drive transistor M1 changes toward a value corresponding to the R data signal Dr (j, i). That is, in this selective scanning period (t11 to t12), the gate voltage Vg changes from the value of the R initialization signal Vinir (j, i) toward Dr (j, i)-| Vthr |. Here, for convenience of explanation, it is assumed that the gate voltage Vg has reached Dr (j, i) − | Vthr | at the end time t12 of this scanning selection period.

Also for the G pixel circuit Pg (i, j) and the B pixel circuit Pb (i, j) in the i-th row j, writing similar to the above writing operation of pixel data to the R pixel circuit Pr (i, j) The action is taken. That is, in the G pixel circuit Pg (i, j), immediately before the scan selection period (t11 to t12) in the i-th horizontal period, the gate voltage Vg of the drive transistor M1 is G represented by the following equation (7). In the B pixel circuit Pb (i, j), immediately before the scanning selection period (t11 to t12) in the i-th horizontal period, the B pixel circuit Pb (i, j) has a value of the initialization signal Vinig (j, i). The gate voltage Vg is a value of the B initialization signal Vinib (j, i) represented by the following equation (8).
Vinig (j, i) = Dg (j, i) -ΔV (7)
Vinib (j, i) = Db (j, i) -ΔV (8)
In the G pixel circuit Pg (i, j), in the scanning selection period (t11 to t12), the G data signal Dg (j, i) holds data via the writing transistor M2 and the driving transistor M1 in a diode connection state. By being applied to capacitor C1 (see FIG. 2), gate voltage Vg of drive transistor M1 changes toward a value corresponding to G data signal Dg (j, i), that is, Dg (j, i)-| Vthg | Do. Further, in the B pixel circuit Pb (i, j), the B data signal Db (j, i) passes through the writing transistor M 2 and the driving transistor M 1 in the diode connection state in the scanning selection period (t 11 to t 12). By being applied to data holding capacitor C1 (see FIG. 2), gate voltage Vg of drive transistor M1 is driven to a value corresponding to B data signal Db (j, i), that is, Db (j, i)-| Vthb | Change. Here, for convenience of explanation, at the end time t12 of this scan selection period, the gate voltage Vg of the drive transistor M1 in the G pixel circuit Pg (i, j) has reached Dg (j, i)-| Vthg | Here, it is assumed that the gate voltage Vg of the driving transistor M1 in the B pixel circuit Pb (i, j) has reached Db (j, i)-| Vthb |.

At the end time t12 of this scanning selection period, the writing transistor M2 and the compensating transistor M3 are turned off in each pixel circuit Px (i, j) (x = r, g, b) in the i-th row j set. Change. After time t12, the data holding capacitor C1 in the R pixel circuit Pr (i, j), the G pixel circuit Pg (i, j), and the B pixel circuit Pb (i, j) is ELVDD-Dr (j, i). And the voltage indicated by ELVDD-Dg (j, i) + | Vthg |, and the voltage indicated by ELVDD-Db (j, i) + | Vthb |).

Thereafter, at time t13, the voltage of the light emission control line Ei changes to the low level. Along with this, in each pixel circuit Px (j, i) (x = r, g, b) in the ith row j, the power supply transistor M5 and the light emission control transistor M6 are turned on. After time t13, current flows from the high level power supply line ELVDD to the low level power supply line ELVSS via the power supply transistor M5, the drive transistor M1, the light emission control transistor M6, and the organic EL element OLED. This current I1 is expressed by the following equation using a constant K relating to the characteristics of the drive transistor M1, assuming that the gate-source voltage of the drive transistor M1 in each pixel circuit Px (i, j) is Vgsx (> 0) x = r, g, b).
I1 = K (Vgsx− | Vthx |) ² (9)
When the power supply transistor M5 is on, the gate-source voltage Vgsx of the drive transistor M1 corresponds to the voltage held by the data holding capacitor C1,
Vgsx = ELVDD-Dx (j, i) + | Vthx | (10)
It is. Therefore, the current I1 is given by the following equation.
I1 = K (ELVDD-Dx (j, i) + | Vthx |-| Vthx |) ²
= K (ELVDD-Dx (j, i)) ² ... (11)

Thus, after time t13, in each pixel circuit Px (i, j) in the i-th row and the j-th row, the organic EL element OLED receives the pixel circuit Px (j, i) regardless of the threshold voltage Vthx of the drive transistor M1. Light is emitted at a luminance according to the voltage of the data signal Dx (j, i) written as pixel data (x = r, g, b). However, the emission color in the R pixel circuit Pr (i, j) is red, the emission color in the G pixel circuit Pg (i, j) is green, and the emission color in the B pixel circuit Pb (i, j) is blue It is.

<3.3 Action and effect>
As described above, in each pixel circuit Px (j, i) (x = r, g, b) in the i-th row and j-th group, the scan selection period (t11 to t12) in the i-th horizontal period is the data signal Dx ( j, i) is a period during which data is stored in the data holding capacitor C1 as a data voltage indicating pixel data. At this time, the variation or fluctuation of the threshold voltage is compensated by writing the data voltage via the drive transistor M1 in the diode connection state. Ru. Therefore, the scan selection period (t11 to t12) corresponds to a threshold compensation period. The compensation speed of the threshold voltage of the drive transistor M1 depends on the initial gate-source voltage Vgs0 which is the gate-source voltage of the drive transistor M1 at the start time t11 of the threshold compensation period, and the initial gate-source voltage Vgs0 (> The compensation speed increases as 0) increases.

In the present embodiment, the gate voltage Vg of the drive transistor M1 of each pixel circuit Px (i, j) at the start time t11 of the scan selection period in the i-th horizontal period is Vinix (j, i) = Dx (j, i) Since it is −ΔV (x = r, g, b), the initial gate-source voltage Vgs0 is expressed by the following equation.
Vgs0 = Dx (j, i) -Vini (j, i)
= ΔV
As described above, since the predetermined value ΔV (> 0) is a fixed value, the compensation speed depends on the data voltage (data signal Dx (j, i)) to be written to each pixel circuit Px (j, i). The same is true for any pixel circuit Px (i, j). As for the predetermined value ΔV, an appropriate value is determined in advance based on computer simulation, experiments, and the like from the viewpoint of shortening the time required for threshold compensation, as in the first embodiment.

Thus, in the present embodiment, the initial gate-source voltage Vgs0 in each pixel circuit Px (j, i) becomes the same fixed value (the predetermined value ΔV). Therefore, according to the present embodiment, as in the first and second embodiments, even if the horizontal period is shortened due to the increase in resolution of the display device, the pixels regardless of the tone value of each pixel of the image to be displayed Compensation (internal compensation) of variation and fluctuation of the threshold voltage of the drive transistor in the circuit can be sufficiently performed.

Further, in the present embodiment, since the SSD method is adopted, the data signal line drive circuit 35 demultiplexes each data signal D (j, i) output from the data side drive circuit 30 c and The initialization signals Vini (j, i) supplied to the data signal lines Drj, Dgj, Dbj and output from the data side drive circuit 30 c are demultiplexed to three initialization signal lines VINIrj, VINIgj, VINIbj. It is configured to give. Therefore, according to the present embodiment, the circuit amount of the data side drive circuit 30c can be significantly reduced while achieving the same effect as that of the first or second embodiment.

<4. Modified example>
The present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the present invention.

For example, the data side drive circuits 30, 30b in the first and second embodiments are not limited to the configurations shown in FIGS. 1 and 5, and can realize the drive method shown in FIG. If there is, it may be another configuration.

Further, in the first to third embodiments, in each pixel circuit Pix (j, i) or Px (j, i) (x = r, g, b), the gate voltage Vg of the drive transistor M1 is a preceding scan signal. Although it is configured to be initialized in the selection period of the line Gi-1 (see FIGS. 2 and 3), the present invention is not limited to this, and a non-emission period (non-selection period for the emission control line Ei) It may be configured to be initialized before the selection period of the corresponding scanning signal line Gi. For example, when the gate voltage Vg of the drive transistor M1 is initialized in a period other than the selection period of the preceding scan signal line Gi-1 in the first embodiment, the data signal delay circuit in the data side drive circuit 30 is 34 does not delay the internal digital signals d (1, i) to d (m, i) by one horizontal period, but according to the temporal relationship between the other period and the selection period of the corresponding scanning signal line Gi. It is configured to be delayed by a predetermined time.

In the first to third embodiments, the pixel circuit having the configuration shown in FIG. 2 using a P-channel transistor as the drive transistor M1 is used. However, the configuration of the pixel circuit is the same as that shown in FIG. The configuration is not limited, and another configuration may be used as long as it is a pixel circuit that performs internal compensation using diode connection, and a configuration using an N-channel transistor as the drive transistor M1 may be used. For example, in the data-side drive circuit 30 in the first embodiment, the initialization signal Vini (j, i) is generated as an analog voltage signal having a value obtained by subtracting the predetermined value ΔV from the data signal D (j, i). However, if another configuration using N-channel drive transistors is adopted in the pixel circuit, a value obtained by adding a predetermined value ΔV to the data signal D (j, i) is used. The initialization signal Vini (j, i) may be generated as an analog voltage signal having. More generally, calculation based on a predetermined value ΔV appropriately determined in advance so that the difference between the data signal D (j, i) and the initialization signal Vini (j, i) becomes the same predetermined value ΔV. The processing generates the initialization signal Vini (j, i).

Further, in the third embodiment, the SSD system with a multiplicity of 3 is adopted (see FIGS. 6 and 7), but the SSD system with a multiplicity of 2 may be adopted, and the multiplicity is 4 The above SSD method may be adopted. For example, in an organic EL display device that displays a color image based on four primary colors of R (red), G (green), B (blue), and W (white), four data signal lines corresponding to the four primary colors A plurality of data signal lines in the display unit may be grouped into m sets of data signal line groups as one set, and an SSD method with a multiplicity of 4 may be adopted. In this case, the plurality of initialization signal lines in the display unit 11c are also grouped into m groups of initialization signal lines, with four initialization signal lines respectively corresponding to the four data signal lines in each set being one set. Be done.

Further, in each demultiplexer 5j in the third embodiment, the same selection control signal SSDx is given to the data selection transistor Mdx and the initialization selection transistor Mix (x = r, g, b), Different selection control signals may be given to the selection transistors Mdx and Mix of FIG. That is, the R data selection control signal to be applied to the control terminals of data selection transistors Mdr, Mdg, and Mdb in R selection control signal SSDr, G selection control signal SSDg, and B selection control signal SSDb in the third embodiment. SSDdr, G data selection control signal SSDdg, and B data selection control signal SSDdb, and R initialization selection control signal SSDir to be supplied to the control terminals of the initialization selection transistors Mir, Mig, Mib, G initialization selection It may be separated into the control signal SSDig and the B initialization option control signal SSDib. In this case, the active period of the initialization selection control signal SSDix can be made different from the active period of the data selection control signal SSDdx (x = r, g, b).

Although each embodiment and its modification have been described above by taking the organic EL display device as an example, the present invention is not limited to the organic EL display device, and a display element driven by current can be used. It is applicable if it is the display apparatus of the used internal compensation system. The display element that can be used here is a display element whose luminance or transmittance is controlled by current, and is, for example, an organic EL element, that is, an organic light emitting diode (Organic Light Emitting Diode (OLED)), an inorganic light emitting diode A quantum dot light emitting diode (QLED) or the like can be used.

10, 10b, 10c ... organic

EL display device

11, 11c ... display unit 15 ... pixel circuit Pix (j, i) ... pixel circuit (i = 1 to n, j = 1 to m)
Pr (j, i) ... R pixel circuit (i = 1 to n, j = 1 to m)
Pg (j, i) ... G pixel circuit (i = 1 to n, j = 1 to m)
Pb (j, i) ... B pixel circuit (i = 1 to n, j = 1 to m)
20 ...

display control circuit

30, 30b, 30c ... data side drive circuit 34 ... data signal delay circuit (digital delay circuit)
34a ... data signal delay circuit (analog delay circuit)
36 ... Look-up table (digital operation circuit)
36a ... Analog subtraction circuit (analog operation circuit)
35 ... data signal line drive circuit 40 ... scanning signal line drive / light emission control circuit 50 ... demultiplexing circuit 51 to 5 m ... demultiplexer Gi ... scanning signal line (i = 1 to n)
Ei ... Light emission control line (i = 1 to n)
Dj ... Data signal line (j = 1 to m)
Drj, Dgj, Dbj ... data signal line (j = 1 to m)
VINIj ... Initialization signal line (j = 1 to m)
VINIrj, VINIgj, VINIbj ... Initialization signal line (j = 1 to m)
Taj ... Data output terminal (j = 1 to m)
Tbj ... Output terminal for initialization (j = 1 to m)
Mdr, Mdg, Mdb: data selection transistors Mir, Mig, Mib: initialization selection transistors M1: drive transistors M2: writing transistors M3: compensation transistors M4: initialization transistors M5: power supply transistors M6 ... Light emission control transistor C1 ... Data holding capacitor (holding capacity)
OLED ... organic EL element SSDx ... selection control signal (x = r, g, b)

Claims

A plurality of data signal lines, a plurality of scanning signal lines intersecting the plurality of data lines, and a plurality of pixel circuits arranged in a matrix along the plurality of data signal lines and the plurality of scanning signal lines A display device having
A plurality of initialization signal lines disposed to correspond to the plurality of data signal lines,
A data signal line drive circuit for driving the plurality of data signal lines;
And a scanning signal line drive circuit for selectively driving the plurality of scanning signal lines,
Each of the plurality of pixel circuits corresponds to any one of the plurality of data signal lines and corresponds to any one of the plurality of scanning signal lines,
Each pixel circuit includes a display element driven by a current, a drive transistor connected in series with the display element to control a drive current of the display element, and a control terminal of the drive transistor connected to a control terminal of the drive transistor. And the voltage of the corresponding initialization signal line is applied to the holding capacitor before the corresponding scanning signal line is in the selected state, and the corresponding scanning signal line is When in the selected state, the drive transistor is diode-connected, and the voltage of the corresponding data signal line is applied to the holding capacitor via the drive transistor.
The data signal line drive circuit is
A plurality of drive data signals in the form of an analog voltage signal generated by delaying a plurality of data signals representing an image to be displayed by a predetermined time are generated, and the plurality of drive data signals are applied to the plurality of data signal lines, respectively. Driving signal generation circuit,
A plurality of initialization signals each having a plurality of values obtained by subtracting or adding the same predetermined value to each value of the plurality of data signals according to the configuration of the pixel circuit in the form of an analog voltage signal And a initialization signal generation circuit that generates and applies the plurality of initialization signals to the plurality of initialization signal lines, respectively.
The driving signal generation circuit
A digital delay circuit that generates, in the form of a digital signal, a plurality of delayed data signals obtained by delaying the plurality of data signals by a predetermined time;
A first DA conversion circuit that generates the plurality of driving data signals by converting the plurality of delayed data signals into analog signals;
The initialization signal generation circuit
A digital operation circuit that generates a plurality of digital initialization signals by subtracting or adding the same digital value as the predetermined value to the digital value indicated by each of the plurality of data signals according to the configuration of the pixel circuit;
The display device according to claim 1, further comprising: a second DA conversion circuit that generates the plurality of initialization signals by converting the plurality of digital initialization signals into an analog signal.
The driving signal generation circuit
A DA conversion circuit that generates a plurality of analog data signals in the form of an analog voltage signal by converting digital signals as the plurality of data signals into analog signals.
And an analog delay circuit that generates the plurality of driving data signals by delaying the plurality of analog data signals by a predetermined time.
The initialization signal generation circuit is an analog that generates the plurality of initialization signals by subtracting or adding the same voltage as the predetermined value to each of the plurality of analog data signals according to the configuration of the pixel circuit. The display device according to claim 1, further comprising an arithmetic circuit.
The driving signal generation circuit
A plurality of data output terminals respectively corresponding to a plurality of sets of data signal lines obtained by grouping the plurality of data signal lines into one set of two or more data signal lines, and each data output When two or more drive data signals to be applied to the two or more data signal lines of the set corresponding to the data output terminal among the plurality of drive data signals are output from the terminal in a time division manner Divided data signal generation circuit,
A plurality of data demultiplexers respectively connected to the plurality of data output terminals and respectively corresponding to the plurality of sets of data signal line groups;
Each data demultiplexer applies the two or more driving data signals output in a time-division manner from the data output terminal connected thereto to the corresponding two or more data signal lines, respectively.
The initialization signal generation circuit
Two or more initialization signal lines corresponding to the two or more data signal lines are taken as one set to respectively correspond to a plurality of sets of initialization signal lines obtained by grouping the plurality of initialization signal lines A plurality of initialization output terminals are provided, and each of the initialization output terminals is applied to two or more initialization signal lines of a group corresponding to the initialization output terminal among the plurality of initialization signals. A time division initialization signal generation circuit that outputs two or more initialization signals in time division;
A plurality of initialization demultiplexers respectively connected to the plurality of initialization output terminals and respectively corresponding to the plurality of sets of initialization signal lines;
Each of the initialization demultiplexers applies the two or more initialization signals output in time division from the initialization output terminal connected thereto to the corresponding set of the two or more initialization signal lines. The display device according to claim 1.
The scan signal line drive circuit drives the plurality of scan signal lines such that the plurality of scan signal lines are sequentially selected.
Each pixel circuit is
An initialization transistor as a switching element having a control terminal connected to a scanning signal line selected in front of a corresponding scanning signal line;
A write transistor as a switching element having a control terminal connected to the corresponding scan signal line;
And a compensation transistor as a switching element having a control terminal connected to the corresponding scanning signal line,
In each pixel circuit,
The control terminal of the drive transistor and the holding capacitor are connected to the corresponding initialization signal line via the initialization transistor,
The first conduction terminal of the drive transistor is connected to the corresponding data signal line via the write transistor,
The display device according to any one of claims 1 to 4, wherein a second conduction terminal of the drive transistor is connected to the control terminal of the drive transistor via the compensation transistor.
A plurality of data signal lines, a plurality of scanning signal lines intersecting the plurality of data lines, and a plurality of pixel circuits arranged in a matrix along the plurality of data signal lines and the plurality of scanning signal lines A driving method of the display device,
The display device further includes a plurality of initialization signal lines arranged to correspond to the plurality of data signal lines,
Each of the plurality of pixel circuits corresponds to any one of the plurality of data signal lines and corresponds to any one of the plurality of scanning signal lines,
Each pixel circuit includes a display element driven by a current, a drive transistor connected in series with the display element to control a drive current of the display element, and a control terminal of the drive transistor connected to a control terminal of the drive transistor. And the voltage of the corresponding initialization signal line is applied to the holding capacitor before the corresponding scanning signal line is in the selected state, and the corresponding scanning signal line is When in the selected state, the drive transistor is diode-connected, and the voltage of the corresponding data signal line is applied to the holding capacitor via the drive transistor.
The driving method is
A data signal line driving step for driving the plurality of data signal lines;
And a scanning signal line driving step for selectively driving the plurality of scanning signal lines,
The data signal line driving step
Generating, in the form of an analog voltage signal, a plurality of driving data signals in which a plurality of data signals representing an image to be displayed are delayed by a predetermined time;
Applying the plurality of driving data signals to the plurality of data signal lines, respectively;
A plurality of initialization signals each having a plurality of values obtained by subtracting or adding the same predetermined value to each value of the plurality of data signals according to the configuration of the pixel circuit in the form of an analog voltage signal Generating steps,
And applying the plurality of generated initialization signals to the plurality of initialization signal lines.