JP2013190526A - Display device and method for driving the same - Google Patents

Display device and method for driving the same Download PDF

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JP2013190526A
JP2013190526A JP2012055611A JP2012055611A JP2013190526A JP 2013190526 A JP2013190526 A JP 2013190526A JP 2012055611 A JP2012055611 A JP 2012055611A JP 2012055611 A JP2012055611 A JP 2012055611A JP 2013190526 A JP2013190526 A JP 2013190526A
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pixel circuit
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JP5797134B2 (en
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Masanori Obara
将紀 小原
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Sharp Corp
シャープ株式会社
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Abstract

PROBLEM TO BE SOLVED: To provide a display device adopting an SSD system, capable of suppressing luminance unevenness as compared with the conventional one.SOLUTION: Each of an R pixel circuit 11r, a G pixel circuit 11g, and a B pixel circuit 11b includes one organic EL element OLED, six transistors M1-M6, and two capacitors C1 and C2. A gate terminal of the transistor M2 for writing in the R pixel circuit 11r is connected to a present R scan line Srj. A gate terminal of the transistor M2 for writing in the G pixel circuit 11g is connected to a present G scan line Sgj. A gate terminal of the transistor M2 for writing in the B pixel circuit 11b is connected to a present B scan line Sbj. The present R scan line Srj is selected after supply of an R data signal to an R data line Dri, the present G scan line Sgj is selected after supply of a G data signal to a G data line Dgi, and the present B scan line Sbj is selected after supply of a B data signal to a B data line Dbi.

Description

  The present invention relates to a display device, and more particularly to a display device including an electro-optic element driven by a current, such as an organic EL display device, and a driving method thereof.

  An organic EL (Electro Luminescence) display device is known as a thin display device with high image quality and low power consumption. In an organic EL display device, a plurality of pixel circuits including an organic EL element which is a self-luminous display element driven by current, a driving transistor, and the like are arranged in a matrix.

  By the way, as one of driving methods for various display devices such as an organic EL display device, a driving method called SSD (Source Shared Driving) (hereinafter referred to as “SSD method”) is known. FIG. 12 is a circuit diagram showing a connection relationship between a pixel circuit and various wirings in an organic EL display device adopting the SSD method disclosed in Patent Document 1. In an organic EL display device adopting this SSD system, color display is performed using RGB three primary colors. Corresponding to the intersection of m × k (m and k are integers of 2 or more) data lines and n (n is an integer of 2 or more) scanning lines, m × k × n pixel circuits 11 are provided. Is provided. In this specification, a pixel circuit corresponding to R (red) is referred to as an “R pixel circuit” and is represented by a reference numeral “11r”. A pixel circuit corresponding to G (green) is referred to as a “G pixel circuit” and is represented by a reference numeral “11g”. A pixel circuit corresponding to B (blue) is referred to as a “B pixel circuit” and is represented by a reference numeral “11b”.

  M output lines Di (i = 1 to m) connected to output terminals of a data driver (not shown) correspond to m demultiplexers 41, respectively. An output line Di corresponding to each demultiplexer 41 is connected to three data lines Dri, Dgi, Dbi via three selection transistors Mr, Mg, Mb included in the demultiplexer 41, respectively. The selection transistors Mr, Mg, and Mb are all P-channel type. The selection transistors Mr, Mg, and Mb correspond to R, G, and B, respectively. The selection transistor Mr is turned on in response to the data control signal SSDr when a data signal corresponding to R (hereinafter referred to as “R data signal”) is to be supplied to the data line Dri. The selection transistor Mg is turned on in response to the data control signal SSDg when a data signal corresponding to G (hereinafter referred to as “G data signal”) is to be supplied to the data line Dgi. The selection transistor Mb is turned on in response to the data control signal SSDb when a data signal corresponding to B (hereinafter referred to as “B data signal”) is to be supplied to the data line Dbi. Hereinafter, the selection transistors Mr, Mg, and Mb are referred to as “R selection transistor”, “G selection transistor”, and “B selection transistor”, respectively. The data control signals SSDr, SSDg, SSDb are referred to as “R data control signal”, “G data control signal”, and “B data control signal”, respectively. The data lines Dri, Dgi, Dbi are referred to as “R data line”, “G data line”, and “B data line”, respectively. The data signal output from the data driver is time-divided by each demultiplexer 41 and is sequentially applied to the R data line Dri, the G data line Dgi, and the B data line Dbi connected to the demultiplexer 41. By adopting such an SSD method, the circuit scale of the data driver can be reduced.

  In the organic EL display device disclosed in Patent Document 1, as shown in FIG. 12, the voltage of the data signal (hereinafter referred to as “data voltage”) is applied to the R data line Dri, the G data line Dgi, and the B data line Dbi. Are connected to data capacitors Cdri, Cdgi, Cdbi, respectively. Hereinafter, the data capacitors Cdri, Cdgi, and Cdbi are referred to as “R data capacitor”, “G data capacitor”, and “B data capacitor”, respectively. Each pixel circuit 11 includes one organic EL element OLED, six transistors M1 to M6, and two capacitors C1 and C2. Transistors M1 to M6 are all P-channel type. The transistor M1 is a driving transistor for controlling a current to be supplied to the organic EL element OLED. The transistor M2 is a writing transistor for writing a voltage of a data signal (hereinafter also referred to as “data voltage”) to the pixel circuit. The transistor M3 is a compensating transistor for compensating for variations in threshold voltage of the driving transistor M1 that cause luminance unevenness. The transistor M4 is an initialization transistor for initializing the gate potential Vg of the driving transistor M1. The transistor M5 is a power supply transistor for controlling the supply of the high level power supply potential ELVDD to the pixel circuit 11. The transistor M6 is a light emission control transistor for controlling the light emission period of the organic EL element OLED. The capacitors C1 and C2 are capacitors for holding the source-gate voltage Vgs of the driving transistor M1. In each of the R pixel circuit 11r, the G pixel circuit 11g, and the B pixel circuit 11b, the gate terminal of the writing transistor M2 is a scanning line Sj along the R pixel circuit 11r, the G pixel circuit 11g, and the B pixel circuit 11b. It is connected to the.

FIG. 13 is a timing chart showing a method for driving the pixel circuit shown in FIG. From time t1 to t2, the initialization transistor M4 is turned on, so that the gate potential Vg of the drive transistor M1 is initialized. From time t2 to t3, the R data signal is supplied to the R data line Dri, and the voltage of the R data signal is held in the R data capacitor Cdri. From time t3 to t4, the G data signal is supplied to the G data line Dgi, and the voltage of the G data signal is held in the G data capacitor Cdgi. From time t4 to t5, the B data signal is supplied to the B data line Dbi, and the voltage of the B data signal is held in the B data capacitor Cdbi. At time t5, the write transistor M2 is turned on in each of the R pixel circuit 11r, the G pixel circuit 11g, and the B pixel circuit 11b, so that the write transistor M2, the drive transistor M1, and the compensation transistor M3 are turned on. The data voltage is applied to the gate terminal of the driving transistor M1 via the. For this reason, the driving transistor M1 is diode-connected. The gate potential Vg of the driving transistor M1 at this time is given by the following equation (1).
Vg = Vdata−Vth (1)
Here, Vdata is a data voltage, and Vth is a threshold voltage of the driving transistor M1.

At time t6, the writing transistor M2 and the compensating transistor M3 are turned off, and the power supply transistor M5 and the light emission controlling transistor M6 are turned on. For this reason, the drive current I given by the following equation (2) is supplied to the organic EL element OLED, and the organic EL element OLED emits light according to the current value of the drive current I.
I = (β / 2) · (Vgs−Vth) 2 (2)
Here, β represents a constant, and Vgs represents a source-gate voltage of the driving transistor M1. The source-gate voltage Vgs of the driving transistor M1 is given by the following equation (3).
Vgs = ELVDD−Vg
= ELVDD-Vdata + Vth (3)

From the equations (2) and (3), the following equation (4) is derived.
I = β / 2 · (ELVDD−Vdata) 2 (4)
In the equation (4), the term of the threshold voltage Vth disappears. This compensates for variations in the threshold voltage Vth of the driving transistor M1. A configuration for compensating for variations in the threshold voltage Vth of the driving transistor M1 is also disclosed in, for example, Patent Document 2. Such variation in the threshold voltage Vth of the driving transistor M1 is a period during which the threshold voltage Vth is compensated by connecting the driving transistor M1 to a diode (referred to as “threshold voltage compensation period” in this specification). It has been conventionally known that the longer it is provided, the more it is suppressed.

Japanese Patent No. 4637070 JP 2005-31630 A

  Incidentally, in the organic EL display device disclosed in Patent Document 1, an R data signal, a G data signal, and a B data signal are sequentially supplied to an R data line Dri, a G data line Dgi, and a B data line Dbi, respectively. . As shown in FIG. 12, the gate terminal of the writing transistor M2 is connected to the scanning line Sj in any of the R pixel circuit 11r, the G pixel circuit 11g, and the B pixel circuit 11b. Therefore, after the supply of the B data signal to the B data line Dbi is completed, the scanning line Sj is selected, and writing of the data voltage is started in each of the R pixel circuit 11r, the G pixel circuit 11g, and the B pixel circuit 11b. . If the scanning line Sj is selected after the supply of the R data signal to the R data line Dri is completed, a desired data voltage is not written to the G pixel circuit 11g and the B pixel circuit 11b. Thus, in the organic EL display device disclosed in Patent Document 1, as shown in FIG. 13, the thresholds of the same length are respectively set in the R pixel circuit 11r, the G pixel circuit 11g, and the B pixel circuit 11b. A value compensation period Tcomp (time t5 to t6) is provided.

  Thus, in the organic EL display device disclosed in Patent Document 1, it is necessary to set the threshold voltage compensation period Tcomp in each pixel circuit in accordance with the writing of the data voltage to the B pixel circuit 11b. For this reason, a sufficient threshold voltage compensation period cannot be secured. As a result, luminance unevenness due to variations in the threshold voltage Vth of the driving transistor M1 cannot be sufficiently suppressed.

  In view of the above, an object of the present invention is to provide a display device that employs an SSD method and that can drive the luminance unevenness more than before, and a driving method thereof.

A first aspect of the present invention is an active matrix display device that performs color display based on a plurality of primary colors by supplying a data signal corresponding to one of the plurality of primary colors to a pixel circuit in a time-sharing manner. ,
A plurality of data lines to which the data signal is supplied;
A plurality of scanning lines each corresponding to one of the plurality of primary colors;
A plurality of pixel circuits provided corresponding to the plurality of data lines and the plurality of scanning lines, each corresponding to one of the plurality of primary colors;
A scanning line driving circuit for starting selection of the scanning line corresponding to the primary color at a timing according to the supply of the data signal corresponding to each primary color to the data line,
The pixel circuit corresponding to each primary color is
An electro-optic element;
A driving transistor for controlling a current flowing through the electro-optic element and having a control terminal and a first conduction terminal electrically connected to each other when a corresponding scanning line is in a selected state;
And a first capacitor for holding a voltage between the control terminal of the driving transistor and the first conduction terminal.

According to a second aspect of the present invention, in the first aspect of the present invention,
A first power supply line and a second power supply line for supplying a power supply potential in common to the plurality of pixel circuits;
The electro-optic element is provided between the first power line and the second power line,
The driving transistor is provided in series with the electro-optical element between the first power supply line and the second power supply line,
The pixel circuit corresponding to each primary color is
A control terminal connected to the scanning line corresponding to the primary color, a writing transistor provided between the second conduction terminal of the driving transistor and the data line;
A control terminal is connected to the scanning line corresponding to the primary color, and further includes a compensation transistor provided between the control terminal of the driving transistor and the first conduction terminal.

According to a third aspect of the present invention, in the second aspect of the present invention,
The scanning line driving circuit is characterized in that the lengths of the selection periods in which the scanning lines are selected are the same for the plurality of primary colors.

According to a fourth aspect of the present invention, in the second aspect of the present invention,
The scanning line driving circuit is characterized in that end timings of selection periods in which the scanning lines are selected are made the same for the plurality of primary colors.

According to a fifth aspect of the present invention, in the second aspect of the present invention,
A plurality of control lines provided along the plurality of scanning lines;
And a control line driving circuit configured to emit an electro-optic element in a pixel circuit corresponding to the scanning line in accordance with the end timing of the selection period of the scanning line.

A sixth aspect of the present invention is the fifth aspect of the present invention,
The pixel circuit includes:
A control terminal connected to the control line, a power supply transistor provided between the first conduction terminal of the driving transistor and the first power supply line;
A control terminal connected to the control line, and further includes a light emission control transistor provided between the second conduction terminal of the driving transistor and one end of the electro-optic element,
The control line driving circuit sets a potential for turning on the power supply transistor and the light emission control transistor in the pixel circuit corresponding to the scanning line in accordance with the end timing of the selection period of the scanning line. It supplies to the said control line, It is characterized by the above-mentioned.

According to a seventh aspect of the present invention, in the second aspect of the present invention,
Each of the plurality of pixel circuits arranged in the extending direction of the scanning line has a control terminal connected to the scanning line immediately before the scanning line to which any of the plurality of pixel circuits corresponds, and the control of the driving transistor It further includes an initialization transistor provided between the terminal and one end of the first capacitor element and an initialization line for supplying an initialization potential.

According to an eighth aspect of the present invention, in the second aspect of the present invention,
The pixel circuit corresponding to each primary color further includes a second capacitor element provided between a scanning line corresponding to the primary color and the control terminal of the driving transistor.

According to a ninth aspect of the present invention, in the second aspect of the present invention,
A plurality of selection output circuits for sequentially supplying data signals corresponding to any of a plurality of primary colors to the plurality of data lines;
And a data line driving circuit for supplying the data signal to each of the plurality of selection output circuits.

According to a tenth aspect of the present invention, in the second aspect of the present invention,
And a data capacitor provided in each data line for holding the data signal.

An eleventh aspect of the present invention is any one of the first to tenth aspects of the present invention,
The scanning line driving circuit includes a plurality of scanning line driving circuits respectively corresponding to the plurality of primary colors,
The scanning line driving circuit corresponding to each primary color is
Selectively driving a plurality of scanning lines corresponding to the primary color,
The selection of the scanning line corresponding to the primary color is started at a timing according to the supply of the data signal corresponding to the primary color to the data line.

According to a twelfth aspect of the present invention, a data signal corresponding to one of a plurality of primary colors is supplied to a pixel circuit in a time division manner, thereby performing color display based on the plurality of primary colors, and the data signal being supplied. A plurality of data lines, a plurality of scanning lines each corresponding to one of the plurality of primary colors, a plurality of data lines and the plurality of scanning lines are provided corresponding to each of the plurality of primary colors. A driving method of an active matrix display device comprising a plurality of corresponding pixel circuits,
A scanning step of starting selection of a scanning line corresponding to the primary color at a timing according to the supply of the data signal corresponding to each primary color to the data line;
The pixel circuit corresponding to each primary color is
An electro-optic element;
A driving transistor for controlling a current flowing through the electro-optic element and having a control terminal and a first conduction terminal electrically connected to each other when a corresponding scanning line is in a selected state;
And a first capacitor for holding a voltage between the control terminal of the driving transistor and the first conduction terminal.

A thirteenth aspect of the present invention is the twelfth aspect of the present invention,
In the scanning step, the length of the selection period in which the scanning lines are selected is made the same for the plurality of primary colors.

A fourteenth aspect of the present invention is the twelfth aspect of the present invention,
In the scanning step, the end timing of the selection period in which the scanning line is selected is made the same for the plurality of primary colors.

  According to the first aspect of the present invention, a plurality of scanning lines corresponding to any of a plurality of primary colors are provided in a display device adopting an SSD method. In addition, the threshold voltage of the driving transistor is compensated by electrically connecting the control terminal and the first conduction terminal when the scanning line is in the selected state. Furthermore, the selection of the scanning line corresponding to the primary color is started at a timing corresponding to the supply of the data signal corresponding to the primary color to the data line. For this reason, the threshold voltage compensation period is longer than that of the conventional pixel circuit corresponding to at least one of the plurality of primary colors. Thereby, the variation in threshold voltage of the driving transistor is suppressed more than in the past. Therefore, the luminance unevenness caused by the variation in the threshold voltage of the driving transistor can be suppressed as compared with the conventional case.

  According to the second aspect of the present invention, when the data voltage is written to the pixel circuit by the writing transistor and the threshold voltage of the driving transistor is compensated by using the compensation transistor, the first aspect of the present invention is applied. The same effect can be achieved.

  According to the third aspect of the present invention, the length of the scanning line selection period corresponding to each primary color is the same. For this reason, in the pixel circuit corresponding to each primary color, the threshold voltage compensation period becomes longer than the conventional one. Thereby, in the pixel circuit corresponding to each primary color, the variation in threshold voltage of the driving transistor is suppressed more than in the past. Therefore, luminance unevenness due to variations in threshold voltage of the driving transistor can be further suppressed.

  According to the fourth aspect of the present invention, by making the end timing of the selection period the same for the scanning lines corresponding to the respective primary colors, the lengths of the selection periods differ for the scanning lines corresponding to the respective primary colors. In such an embodiment, the same effects as in the first aspect of the present invention can be achieved.

  According to the fifth aspect of the present invention, the light emission period of the electro-optic element can be controlled.

  According to the sixth aspect of the present invention, the same effect as that of the fifth aspect of the present invention can be achieved by using the power supply transistor and the light emission control transistor.

  According to the seventh aspect of the present invention, the potential of the control terminal of the driving transistor is initialized by the initializing transistor. For this reason, the data voltage can be reliably written to the pixel circuit.

  According to the eighth aspect of the present invention, the potential of the control terminal of the driving transistor when the scanning line is in the non-selected state can be reliably held using the second capacitor element.

  According to the ninth aspect of the present invention, the SSD system can be realized by using the selection output circuit.

  According to the tenth aspect of the present invention, the data signal supplied to the data signal can be held using the data capacitor.

  According to the eleventh aspect of the present invention, the same effect as any of the first to tenth aspects of the present invention can be achieved by using a plurality of scanning line driving circuits respectively corresponding to a plurality of primary colors. Can do.

  According to the twelfth aspect of the present invention, in the method for driving the display device, the same effect as in the first aspect of the present invention can be achieved.

  According to the thirteenth aspect of the present invention, in the method for driving the display device, the same effect as in the third aspect of the present invention can be achieved.

  According to the fourteenth aspect of the present invention, in the method for driving the display device, the same effect as in the fourth aspect of the present invention can be achieved.

1 is a block diagram illustrating an overall configuration of a display device according to a first embodiment of the present invention. FIG. 3 is a circuit diagram illustrating a connection relationship between a pixel circuit and various wirings in the first embodiment. 3 is a timing chart showing a method for driving the pixel circuit shown in FIG. 2. It is a figure which shows the threshold voltage variation compensation rate with respect to the length of a threshold voltage compensation period. FIG. 6 is a circuit diagram illustrating a connection relationship between a pixel circuit and various wirings in a first modification of the first embodiment. 6 is a timing chart showing a method for driving the pixel circuit shown in FIG. 5. It is a block diagram which shows the whole structure of the display apparatus which concerns on the 2nd modification of the said 1st Embodiment. 6 is a timing chart illustrating a driving method of a pixel circuit according to a second embodiment of the present invention. It is a block diagram which shows the whole structure of the display apparatus which concerns on the modification of the said 2nd Embodiment. It is a circuit diagram which shows the connection relation of the pixel circuit and various wiring in the said 2nd Embodiment. 11 is a timing chart showing a method for driving the pixel circuit shown in FIG. 10. It is a circuit diagram which shows the connection relation of a pixel circuit and various wiring in the conventional organic EL display apparatus. 13 is a timing chart showing a method for driving the pixel circuit shown in FIG. 12.

  Hereinafter, first to third embodiments of the present invention will be described with reference to the accompanying drawings. Note that although all the transistors in each embodiment are described as being P-channel type, the present invention is not limited to this. Moreover, although the transistor in each embodiment is a thin-film transistor, for example, this invention is not limited to this.

<1. First Embodiment>
<1.1 Overall configuration>
FIG. 1 is a block diagram showing the overall configuration of a display device 1 according to the first embodiment of the present invention. The display device 1 is an organic EL display device that performs color display using three primary colors of RGB. As shown in FIG. 1, the display device 1 includes a display driver 10, a display control circuit 20, a data driver 30, a demultiplexer unit 40, a scan driver 50 r (hereinafter referred to as “R scan driver”) and G corresponding to R. A corresponding scanning driver 50g (hereinafter referred to as “G scanning driver”), a scanning driver 50b corresponding to B (hereinafter referred to as “B scanning driver”), and an emission driver 60 are provided. The display device 1 is a display device that employs an SSD system that supplies a data signal from the data driver 30 to the data line via the demultiplexer unit 40. In the present embodiment, a data line driving circuit is realized by the data driver 30, a scanning line driving circuit is realized by the scanning driver, and a control line driving circuit is realized by the emission driver 60. The R scanning driver 50r, the G scanning driver 50g, the B scanning driver 50b, and the emission driver 60 are formed integrally with the display unit 10, for example. However, the present invention is not limited to this.

  The display unit 10 includes m × k (m and k are integers of 2 or more, and in this embodiment, k = 3) data lines Dr1 to Drm, Dg1 to Dgm, Db1 to Dbm, and these N scanning lines Sr1 to Srn corresponding to R (hereinafter referred to as “R scanning lines”), n scanning lines Sg1 to Sgn corresponding to G (hereinafter referred to as “G scanning lines”), And n scanning lines Sb1 to Sbn (hereinafter referred to as “B scanning lines”) corresponding to B and B are arranged. The display unit 10 is provided with m × 3 × n pixel circuits 11 corresponding to the intersections of the data lines, the R scanning lines, the G scanning lines, and the B scanning lines. More specifically, m × n R pixel circuits 11r are provided corresponding to the intersections of m R data lines Dr1 to Drm and n R scanning lines Sr1 to Srn, and m G data lines. M × n G pixel circuits 11g are provided corresponding to the intersections of Dg1 to Dgm and n G scan lines Sg1 to Sgn, and m B data lines Db1 to Dbm and n B scan lines Sb1 are provided. A total of m × 3 × n pixel circuits 11 are provided by providing m × n B pixel circuits 11b corresponding to the intersections with Sbn. Further, the display unit 10 includes n R scanning lines Sr1 to Srn, n G scanning lines Sg1 to Sgn, and n B scanning lines Sb1 to Sbn in parallel with emission lines as n control lines. E1 to En are disposed. The m × k data lines Dr1 to Drm, Dg1 to Dgm, and Db1 to Dbm are connected to the demultiplexer unit 40. The n R scanning lines Sr1 to Srn are connected to the R scanning driver 50r. The n B scanning lines Sb1 to Sbn are connected to the G scanning driver 50g. The n B scanning lines Sb1 to Sbn are connected to the B scanning driver 50b. The n emission lines E1 to En are connected to the emission driver 60.

  The display unit 10 is provided with a power line (not shown) common to the pixel circuits 11. More specifically, a power supply line (hereinafter referred to as “high level power supply line” for supplying a high level potential ELVDD for driving an organic EL element to be described later) and the organic EL. A power supply line for supplying a low level potential ELVSS for driving the element (hereinafter referred to as a “low level power supply line” and denoted by the symbol ELVSS similarly to the low level potential) is provided. Further, an initialization line for supplying an initialization potential Vini for an initialization operation to be described later (same as the initialization potential is denoted by Vini) is provided. These potentials are supplied from a power supply circuit (not shown). In the present embodiment, the first power supply line is realized by the high level power supply line ELVDD, and the second power supply line is realized by the low level power supply line ELVSS.

  m R data capacitors Cdr1 to Cdrm are connected to the m R data lines Dr1 to Drm, respectively. m G data capacitors Cdg1 to Cdgm are connected to the m G data lines Dg1 to Dgm, respectively. m B data capacitors Cdb1 to Cdbm are connected to the m B data lines Db1 to Dbm, respectively. For example, a ground potential is applied to one end (side to which the data line is not connected) of each data capacitor, but the present invention is not limited to this.

  The display control circuit 20 outputs various control signals to the data driver 30, the demultiplexer unit 40, the R scan driver 50r, the G scan driver 50g, the B scan driver 50b, and the emission driver 60. More specifically, the display control circuit 20 outputs a data start pulse DSP, a data clock DCK, display data DA, and a latch pulse LS to the data driver 30. The display data DA includes R data, G data, and B data. The display control circuit 20 also outputs an R data control signal SSDr, a G data control signal SSDg, and a B data control signal SSDb to the demultiplexer unit 40. The display control circuit 20 also outputs an R scan start pulse SSPr and an R scan clock SCKr to the R scan driver 50r, outputs a G scan start pulse SSPg and a G scan clock SCKg to the G scan driver 50g, and outputs to the B scan driver 50b. B scan start pulse SSPb and B scan clock SCKb are output. The display control circuit 20 also outputs an emission start pulse ESP and an emission clock ECK to the emission driver 60.

  The data driver 30 includes an m-bit shift register (not shown), a sampling circuit, a latch circuit, and m D / A converters. The shift register has m bistable circuits connected in cascade with each other, transfers the data start pulse DSP supplied to the first stage in synchronization with the data clock DCK, and outputs a sampling pulse from each stage. In accordance with the output timing of the sampling pulse, display data DA is supplied to the sampling circuit. The sampling circuit stores the display data DA according to the sampling pulse. When the display data DA for one row is stored in the sampling circuit, the display control circuit 20 outputs a latch pulse LP to the latch circuit. When receiving the latch pulse LP, the latch circuit holds the display data DA stored in the sampling circuit. The D / A converter is provided corresponding to m output lines D1 to Dm respectively connected to m output terminals (not shown) of the data driver 30, and the display data DA held in the latch circuit. Is converted to a data signal which is an analog signal, and the obtained data signal is supplied to the output lines D1 to Dm. Since the display device 1 according to the present embodiment performs color display using RGB three primary colors and adopts the SSD method, an R data signal, a G data signal, and a B data signal are sequentially supplied to each output line. .

  The demultiplexer unit 40 includes m demultiplexers 41. The input ends of the m demultiplexers 41 are connected to the m output lines D1 to Dm, respectively. The k (k = 3) output terminals of the i-th demultiplexer 41 (i = 1 to m) are connected to the R data line Dri, the G data line Dgi, and the B data line Dbi, respectively. The demultiplexer 41 supplies the sequentially supplied R data signal, G data signal, and B data signal to the R data line Dri, the G data line Dgi, and the B data line Dbi, respectively. The operation of the demultiplexer 41 is controlled by the R data control signal SSDr, the G data control signal SSDg, and the B data control signal SSDb. In this way, the number of output lines connected to the data driver 30 can be reduced to, for example, 1/3, compared with the case where the SSD method is not adopted. Thereby, since the circuit scale of the data driver 30 is reduced, the manufacturing cost of the data driver 30 can be reduced.

  The R scan driver 50r drives n R scan lines Sr1 to Srn. More specifically, the R scan driver 50r includes a shift register and a buffer (not shown). The shift register sequentially transfers the R scan start pulse SSPr in synchronization with the R scan clock SCKr. A scanning signal that is an output from each stage of the shift register is supplied to the corresponding R scanning line Srj (j = 1 to n) via the buffer. The m R pixel circuits 11r connected to the R scanning line Srj are collectively selected by an active (low level in this embodiment) scanning signal.

  The G scanning driver 50g drives n G scanning lines Sg1 to Sgn. More specifically, like the R scan driver 50r, the G scan driver 50g includes a shift register and a buffer (not shown). The shift register sequentially transfers the G scan start pulse SSPg in synchronization with the G scan clock SCKg. A scanning signal which is an output from each stage of the shift register is supplied to the corresponding G scanning line Sgj via the buffer. By the active scanning signal, m G pixel circuits 11g connected to the G scanning line Sgj are selected at once.

  The B scan driver 50b drives n B scan lines Sb1 to Sbn. More specifically, the B scan driver 50b includes a shift register and a buffer (not shown) as in the R scan driver 50r. The shift register sequentially transfers the B scan start pulse SSPb in synchronization with the B scan clock SCKb. A scanning signal that is an output from each stage of the shift register is supplied to a corresponding B scanning line Sbj via a buffer. By the active scanning signal, m B pixel circuits 11b connected to the B scanning line Sbj are collectively selected.

  In the present embodiment, for example, the pulse widths of the R scan start pulse SSPr, the G scan start pulse SSPg, and the B scan start pulse SSPb are different from each other. That is, the pulse widths of the scanning signals applied to the R scanning line Srj, the G scanning line Sgj, and the B scanning line Sbj are different from each other. For this reason, as described later, the lengths of the selection periods of the R scanning line Srj, the G scanning line Sgj, and the B scanning line Sbj are different from each other.

  The emission driver 60 drives n emission lines E1 to En. More specifically, the emission driver 60 includes a shift register and a buffer (not shown). The shift register sequentially transfers the emission start pulse ESP in synchronization with the emission clock ECK. An emission signal that is an output from each stage of the shift register is supplied to a corresponding emission line Ej via a buffer.

  As shown in FIG. 1, the R scanning driver 50r and the G scanning driver 50g are arranged on one end side of the display unit 10 (left side with respect to the display unit 10 in FIG. 1), and the B scanning driver 50b is on the other end side of the display unit 10. (On the right side of the display unit 10 in FIG. 1). The emission driver 60 is disposed on the other end side of the display unit 10. Thus, various drivers are equally arranged on both sides of the display unit 10.

<1.2 Connection between pixel circuit and various wiring>
FIG. 2 is a circuit diagram showing a connection relationship between a part of the R pixel circuit 11r, the G pixel circuit 11g, and the B pixel circuit 11b and various wirings in the present embodiment. First, the configuration of the demultiplexer 41 will be described. As illustrated in FIG. 2, the demultiplexer 41 includes an R selection transistor Mr, a G selection transistor Mg, and a B selection transistor Mb. The R data control signal SSDr is applied to the gate terminal of the R selection transistor Mr. The G data control signal SSDg is supplied to the gate terminal of the G selection transistor Mg. The B data control signal SSDb is supplied to the gate terminal of the B selection transistor Mb. The output line Di and the R data line Dri are connected to each other via the R selection transistor Mr. The output line Di and the G data line Dgi are connected to each other via the G selection transistor Mg. The output line Di and the B data line Dbi are connected to each other via the B selection transistor Mb.

  Next, the configuration of the pixel circuit will be described. As shown in FIG. 2, the R pixel circuit 11r, the G pixel circuit 11g, and the B pixel circuit 11b are arranged in order in the extending direction of the scanning line. Since the configurations of the R pixel circuit 11r, the G pixel circuit 11g, and the B pixel circuit 11b are basically the same, in the following, the configuration of the R pixel circuit 11r is taken as an example for portions common to these pixel circuits. The different parts of these pixel circuits will be described individually as appropriate.

  The R pixel circuit 11r includes one organic EL element OLED, six transistors M1 to M6, and two capacitors C1 and C2. More specifically, the R pixel circuit 11r includes an organic EL element OLED, a driving transistor M1, a writing transistor M2, a compensating transistor M3, an initialization transistor M4, a power supply transistor M5, a light emission controlling transistor M6, A first capacitor C1 as a one-capacitance element and a second capacitor as a second capacitance element are included. The driving transistor M1 has a gate terminal, a first conduction terminal, and a second conduction terminal. In the driving transistor M1, the first conduction terminal and the second conduction terminal are the source terminal and the drain terminal, respectively, or the first conduction terminal and the second conduction terminal are the drain terminal and the source terminal, respectively, according to the carrier flow. It may become. Each of the G pixel circuit 11g and the B pixel circuit 11b includes the same elements as the R pixel circuit 11r.

  The R pixel circuit 11r includes an R scan line Srj (referred to as “current R scan line” for convenience in the description focusing on the pixel circuit), and an R scan line Srj-1 (focused on the pixel circuit) immediately before the current R scan line Srj. In the description, for the sake of convenience, it is referred to as “previous R scanning line”), an emission line Ej, an R data line Dri, a high level power line ELVDD, a low level power line ELVSS, and an initialization line Vini. Instead of the current R scanning line Srj, a G scanning line Sgj (referred to as “current G scanning line” in the description focusing on the pixel circuit) is connected to the G pixel circuit 11g. Other connections are the same as those of the R pixel circuit 11r. Instead of the current R scanning line Srj, a B scanning line Sbj (referred to as “current B scanning line” for convenience in the description focusing on the pixel circuit) is connected to the B pixel circuit 11b. Other connections are the same as those of the R pixel circuit 11r. As described above, the R data line Cri is connected to the R data line Dri, the G data capacitor Cdgi is connected to the G data line Dgi, and the B data capacitor Cdbi is connected to the B data line Dbi. .

  In the R pixel circuit 11r, the writing transistor M2 has a gate terminal connected to the current R scanning line Srj and a source terminal connected to the R data line Dri. In the G pixel circuit 11g, the writing transistor M2 has a gate terminal connected to the current G scanning line Sgj and a source terminal connected to the G data line Dgi. In the B pixel circuit 11b, the writing transistor M2 has a gate terminal connected to the current B scanning line Sgj and a source terminal connected to the B data line Dbi. The writing transistor M2 supplies the data voltage held in the data capacitor according to the selection of the scanning line.

  The second conduction terminal of the driving transistor M1 is connected to the drain terminal of the writing transistor M2. The driving transistor M1 supplies a driving current I corresponding to the source-gate voltage Vgs to the organic EL element OLED.

  The compensation transistor M3 is provided between the gate terminal of the driving transistor M1 and the first conduction terminal. In the R pixel circuit 11r, the gate terminal of the compensation transistor M3 is connected to the R scanning line Srj. In the G pixel circuit 11g, the gate terminal of the compensation transistor M3 is connected to the G scanning line Sgj. In the B pixel circuit 11b, the gate terminal of the compensating transistor M3 is connected to the B scanning line Sbj. The compensation transistor M3 causes the driving transistor M1 to be diode-connected in accordance with the selection of the scanning line.

  The initialization transistor M4 has a gate terminal connected to the previous R scanning line Srj-1, and is provided between the gate terminal of the driving transistor M1 and the initial line Vini. The initialization transistor M4 initializes the gate potential Vg of the driving transistor M1 in accordance with the selection of the previous R scanning line Srj-1. Note that the connection destination of the gate terminal of the initialization transistor M4 is also the G scan line Sgj-1 immediately before the current G scan line Sgj (referred to as the “previous G scan line Sgj-1” in the description focusing on the pixel circuit). The B scanning line Sbj-1 (referred to as “previous B scanning line Sbj-1” for convenience in the description focusing on the pixel circuit) may be used immediately before the current B scanning line Sbj.

  The power supply transistor M5 has a gate terminal connected to the emission line Ej and is provided between the high-level power supply line ELVDD and the first conduction terminal of the driving transistor. The power supply transistor M5 supplies the high level power supply potential ELVDD to the drain terminal of the drive transistor M1 in accordance with the selection of the emission line Ej.

  The light emission controlling transistor M6 has a gate terminal connected to the emission line Ej and is provided between the second conduction terminal of the driving transistor M1 and the organic EL element OLED. The light emission control transistor M6 transmits the drive current I to the organic EL element OLED according to the selection of the emission line Ej.

  The second terminal of the first capacitor C1 is connected to the high level power line ELVDD. The first capacitor C1 holds the gate potential Vg of the driving transistor M1 when the current scanning line connected to the pixel circuit including the first capacitor C1 is in a non-selected state.

  In the R pixel circuit 11r, the second terminal of the second capacitor C2 is connected to the R data line Dri. In the G pixel circuit 11g, the second terminal of the second capacitor C2 is connected to the G data line Dgi. In the B pixel circuit 11b, the second terminal of the second capacitor C2 is connected to the B data line Dbi. The second capacitor C2 holds the gate potential Vg of the driving transistor M1 when the current scanning line connected to the pixel circuit including the second capacitor C2 is in a non-selected state.

  In the organic EL element OLED, an anode (one end of the organic EL element OLED) is connected to the second conduction terminal of the driving transistor M1, and a cathode (the other end of the organic EL element OLED) is connected to the low-level power line ELVSS. . The organic EL element OLED emits light with a luminance corresponding to the drive current I.

<1.3 Driving method>
FIG. 3 is a timing chart showing a driving method of the pixel circuit shown in FIG. Immediately before time t1, the potential of the emission line Ej changes from the high level to the low level. For this reason, the power supply transistor M5 and the light emission control transistor M6 are turned off. Thereby, organic EL element OLED will be in a non-light-emission state. For example, the potential of the emission line Ej may change from a high level to a low level at time t1.

At time t1, the potential of the previous R scanning line Srj-1 changes from the high level to the low level. For this reason, the initialization transistor M4 is turned on. As a result, the gate potential Vg of the driving transistor is initialized to the initialization potential Vini. Hereinafter, the operation of initializing the gate potential Vg of the driving transistor to the initialization potential Vini may be referred to as “initialization operation”. The initialization potential Vini is a potential that can maintain the driving transistor M1 in the on state when the data voltage is written to the pixel circuit. More specifically, the initialization potential Vini satisfies the following expression (5).
Vini−Vdata <−Vth (5)
By performing such an initialization operation, the data voltage can be reliably written to the pixel circuit.

  At time t2, the potential of the previous R scanning line Srj-1 changes from the low level to the high level. For this reason, the initialization transistor M4 is turned off. The gate potential Vg of the driving transistor M2 is held by the first capacitor C1 and the second capacitor C2. At time t2, the potential of the R data control signal SSDr changes from the high level to the low level. As a result, the R selection transistor Mr is turned on, and the supply of the R data signal to the R data line Dri is started. By supplying the R data signal to the R data line Dri until time t3, the voltage of the R data signal (data voltage Vdata) is written to the R data capacitor Cdri.

  At time t3, the potential of the R data control signal SSDr changes from the low level to the high level. For this reason, the supply of the R data signal to the R data line Dri is stopped. At time t3, the potential of the current R scanning line Srj changes from the high level to the low level. For this reason, in the R pixel circuit 11r, the writing transistor M2 and the compensating transistor M3 are turned on. As a result, the data voltage Vdata held in the R data capacitor Cdri is supplied to the gate terminal of the driving transistor M1 via the writing transistor M2, the driving transistor M1, and the compensation transistor M3. At this time, the first conduction terminal and the second conduction terminal of the driving transistor M1 are a drain terminal and a source terminal, respectively. At this time, the first control terminal and the gate terminal of the driving transistor M1 are electrically connected to each other, so that the driving transistor M1 is diode-connected. While the driving transistor M1 is diode-connected, the gate potential Vg of the driving transistor changes toward the value given by the above equation (1). Strictly speaking, since the charge held in the R data capacitor Cdri is redistributed to the R data capacitor Cdri, the first capacitor C1, and the second capacitor, it is actually supplied to the gate terminal of the driving transistor M1. The voltage may be lower than the data voltage Vdata. However, such an effect is reduced by boosting the gate potential Vg via the second capacitor C2 at time t6 described later. The same applies to the G pixel circuit 11g and the B pixel circuit 11b. At time t3, the potential of the G data control signal SSDg changes from the high level to the low level. For this reason, the G selection transistor Mg is turned on, and supply of the G data signal to the G data line Dgi is started. By supplying the G data signal to the G data line Dgi until time t4, the data voltage of the G data signal is written to the G data capacitor Cdgi.

  At time t4, the potential of the G data control signal SSDg changes from the low level to the high level. For this reason, the supply of the G data signal to the G data line Dgi is stopped. At time t4, the potential of the current G scanning line Sgj changes from the high level to the low level. For this reason, in the G pixel circuit 11g, the writing transistor M2 and the compensating transistor M3 are turned on. As a result, as in the case of the R pixel circuit 11r, the gate potential Vg of the driving transistor changes toward the value given by the above equation (1) while the driving transistor M1 is diode-connected. At time t4, the potential of the B data control signal SSDb changes from the high level to the low level. For this reason, the B selection transistor Mb is turned on, and the supply of the B data signal to the B data line Dbi is started. By supplying the B data signal to the B data line Dbi until time t5, the data voltage of the B data signal is written to the B data capacitor Cdbi.

  At time t5, the potential of the B data control signal SSDb changes from the low level to the high level. For this reason, the supply of the B data signal to the B data line Dbi is stopped. At time t5, the potential of the current B scanning line Sbj changes from the high level to the low level. For this reason, in the B pixel circuit 11b, the writing transistor M2 and the compensating transistor M3 are turned on. As a result, as in the case of the R pixel circuit 11r, the gate potential Vg of the driving transistor changes toward the value given by the above equation (1) while the driving transistor M1 is diode-connected.

  Note that the timing of changing the potential of the current R scanning line Srj from the high level to the low level is not limited to the time t3 but may be between the times t2 and t3. Similarly, the timing for changing the potential of the current G scanning line Sgj from the high level to the low level is not limited to the time t4 but may be between the times t3 and t4. Similarly, the timing for changing the potential of the current B scanning line Sbj from the high level to the low level is not limited to the time t5 but may be between the times t4 and t5.

  At time t6, the potentials of the current R scanning line Srj, the current G scanning line Sgj, and the current B scanning line Sbj change from the low level to the high level. Therefore, in each of the R pixel circuit 11r, the G pixel circuit 11g, and the B pixel circuit 11b, the writing transistor M2 and the compensating transistor M3 are turned off. As shown in FIG. 3, the selection periods of the current R scanning line Srj, the current G scanning line Sgj, and the current B scanning line Sbj are different from each other. The selection period of the current R scanning line Srj is from time t3 to t6, the selection period of the current G scanning line Sgj is from time t4 to t6, and the selection period of the current B scanning line Sbj is from time t5 to t6. The selection period corresponds to the threshold voltage compensation period Tcomp. That is, a threshold voltage compensation period Tcomp (referred to as “R threshold voltage compensation period Tcompr”) in the R pixel circuit 11r is provided at times t3 to t6, and a threshold voltage compensation period Tcomp ( "G threshold voltage compensation period Tcompg") is provided from time t4 to t6, and threshold voltage compensation period Tcomp (referred to as "G threshold voltage compensation period Tcompb") in the B pixel circuit 11b is time. Provided at t5 to t6. The G threshold voltage compensation period Tcomb has the same length as the conventional one, but the R threshold voltage compensation period Tcomr and the B threshold voltage compensation period Tcomb are longer than the conventional one (see FIG. 13). At time t6, the potentials of the current R scanning line Srj, current G scanning line Sgj, and current B scanning line Sbj change from the low level to the high level, so that the gate potential Vg is changed to the second capacitor as described above. Boosted via C2. For this reason, a decrease in the voltage actually supplied to the gate terminal of the driving transistor M1 due to the redistribution of the charge held in the R data capacitor Cdri is reduced.

  At time t6, the potential of the emission line Ej changes from the high level to the low level. For this reason, the power supply transistor M5 and the light emission control transistor M6 are turned on. As a result, the drive current I corresponding to the gate potential Vg of the drive transistor M1 and the high-level power supply line ELVDD is supplied to the organic EL element OLED, and the organic EL element OLED emits light according to the current value of the drive current I. At this time, the first conduction terminal and the second conduction terminal of the driving transistor M1 are a source terminal and a drain terminal, respectively. The drive current I is given by the above equation (4). By repeating the above operation n times in one frame period, an image for one frame is displayed.

<1.4 Discussion>
FIG. 4 shows the length of the threshold voltage compensation period Tcomp [a. u. ] Is a diagram showing a threshold voltage variation compensation rate Rcomp [%] with respect to]. The threshold voltage variation compensation rate Rcomp is given by the following equation (6).
Rcomp = (Vcomp / Vdif) × 100 (6)
Here, Vcomp represents a voltage compensated in the threshold voltage compensation period Tcomp, and Vdif represents a difference between the maximum value and the minimum value of the assumed threshold voltage Vth. As shown in FIG. 4, the longer the threshold voltage compensation period Tcomp, the higher the threshold variation compensation rate Rcomp. That is, as the threshold voltage compensation period Tcomp is longer, the variation in the threshold voltage Vth of the driving transistor M1 can be suppressed.

  Conventionally, the R threshold voltage compensation period Tcompr, the G threshold voltage compensation period Tcompg, and the B threshold voltage compensation period Tcompb have the same length and are provided only at times t5 to t6 (FIG. 13). On the other hand, in the present embodiment, the R threshold voltage compensation period Tcompr is longer than the conventional one at times t3 to t5, and the conventional G threshold voltage compensation period Tcompg is only at time t4 to t5. Longer than. For this reason, in the R pixel circuit 11r and the G pixel circuit 11g, variation in the threshold voltage Vth of the driving transistor M1 is suppressed more than in the past.

<1.5 Effect>
According to this embodiment, in the organic EL display device that adopts the SSD method and compensates for the threshold voltage Vth of the driving transistor M1 in the pixel circuit, the R scanning lines Srj and G scanning lines respectively corresponding to the three primary colors of RGB. Sgj and B scan line Sbj are provided, and an R scan driver 50r, a G scan driver 50g, and a B scan driver 50b are provided for driving these, respectively. The selection period of the R scanning line Srj starts after the supply of the R data signal to the R data line Dri (time t3), and the selection period of the G scanning line Sgj starts after the supply of the G data signal to the G data line Dgi (time Starting at t4), the selection period of the B scanning line Sbj starts after the supply of the B data signal to the B data line Dbi (time t5). Then, each selection period of the R scanning line Srj, the G scanning line Sgj, and the B scanning line Sbj ends after the data voltage is written to the B pixel circuit 11b (time t6). Therefore, the R threshold voltage compensation period Tcompr is provided from time t3 to t6, the G threshold voltage compensation period Tcompg is provided from time t4 to t6, and the B threshold voltage compensation period Tcompb is from time t5 to t6. Is provided. As a result, the R threshold voltage compensation period Tcompr is longer than the conventional one at times t3 to t5, and the G threshold voltage compensation period Tcompg is longer than the conventional one at times t4 to t5. Therefore, in the R pixel circuit 11r and the G pixel circuit 11g, variation in the threshold voltage Vth of the driving transistor M1 is suppressed more than in the past. As a result, luminance unevenness due to variations in the threshold voltage Vth of the driving transistor M1 can be suppressed more than in the past.

  In the present embodiment, an R scan driver 50r, a G scan driver 50g, and a B scan driver 50b are provided to individually drive the R scan line Srj, the G scan line Sgj, and the B scan line Sbj. The invention is not limited to this. For example, one scan driver that comprehensively includes the functions of the R scan driver 50r, the G scan driver 50g, and the B scan driver 50b may be provided.

<1.6 First Modification>
FIG. 5 is a circuit diagram showing a connection relationship between some R pixel circuits 11r, G pixel circuits 11g, and B pixel circuits 11b and various wirings in the first modification of the first embodiment. In the first embodiment, as shown in FIG. 2, the connection destination of the gate terminal of the initialization transistor M4 is the same in the R pixel circuit 11r, the G pixel circuit 11g, and the B pixel circuit 11b. That is, all of the initialization transistors M4 in the R pixel circuit 11r, the G pixel circuit 11g, and the B pixel circuit 11b have their gate terminals connected to the previous R scanning line Srj-1. On the other hand, in the present modification, as shown in FIG. 5, the connection destination of the gate terminal of the initialization transistor M4 is different in the R pixel circuit 11r, the G pixel circuit 11g, and the B pixel circuit 11b. That is, the gate terminal of the initialization transistor M4 in the R pixel circuit 11r is connected to the previous R scanning line Srj-1, and the gate terminal of the initialization transistor M4 in the G pixel circuit 11g is connected to the previous G scanning line Sgj-1. The gate terminal of the initialization transistor M4 in the B pixel circuit 11b is connected to the previous B scanning line Sbj-1. Note that the other configuration of the pixel circuit in this modification is the same as that of the pixel circuit shown in FIG.

  FIG. 6 is a timing chart showing a method for driving the pixel circuit shown in FIG. At time t1, similarly to the example shown in FIG. 3, the potential of the previous R scanning line Srj-1 changes from the high level to the low level. Therefore, in the R pixel circuit 11r, the initialization transistor M4 is turned on, and the gate potential Vg of the drive transistor is initialized to the initialization potential Vini. Next, at time t1a, the potential of the previous G scanning line Sgj-1 changes from the high level to the low level. Therefore, in the G pixel circuit 11g, the initialization transistor M4 is turned on, and the gate potential Vg of the drive transistor is initialized to the initialization potential Vini. Next, at time t1b, the potential of the previous B scan line Sbj-1 changes from the high level to the low level. Therefore, in the B pixel circuit 11b, the initialization transistor M4 is turned on, and the gate potential Vg of the drive transistor is initialized to the initialization potential Vini. At time t2, the potentials of the previous R scanning line Srj-1, the G scanning line Sgj-1, and the previous B scanning line Sbj-1 change from the low level to the high level, respectively. The initialization transistor M4 in the G pixel circuit 11g and the B pixel circuit 11b changes to the off state.

  Similar to the first embodiment, the connection destination of the gate terminal of the initialization transistor M4 may be different in the R pixel circuit 11r, the G pixel circuit 11g, and the B pixel circuit 11b as in the present modification. The initialization operation can be performed. Note that it is not essential that the primary colors corresponding to the previous scanning line to which the initialization transistor M4 is connected correspond to the primary colors corresponding to the pixel circuit including the initialization transistor M4.

<1.7 Second Modification>
FIG. 7 is a block diagram illustrating an overall configuration of the display device 1 according to a second modification of the first embodiment. In the first embodiment, as shown in FIG. 1, the R scanning driver 50r and the G scanning driver 50g are arranged on one end side of the display unit 10 (left side with respect to the display unit 10 in FIG. 1), and the B scanning driver 50b. Is disposed on the other end side of the display unit 10 (on the right side of the display unit 10 in FIG. 1). The emission driver 60 is disposed on the other end side of the display unit 10. That is, various drivers are equally arranged on both sides of the display unit 10. However, it is not essential for the present invention that the various drivers are equally arranged on both sides of the display unit 10 in this way. For example, as in this modification, the R scanning driver 50r, the G scanning driver 50g, and the B scanning driver 50b are arranged on one end side of the display unit 10 (left side with respect to the display unit 10 in FIG. 2), and the emission driver 60 is displayed. You may arrange | position at the other end side (right side with respect to the display part 10 in FIG. 2) of the part 10. FIG. That is, various drivers may be unevenly arranged on both sides of the display unit 10.

<2. Second Embodiment>
<2.1 Operation>
FIG. 8 is a timing chart showing a driving method of the pixel circuit in the second embodiment of the present invention. In addition, since the component of this embodiment is the same as that of the said 1st Embodiment, description is abbreviate | omitted. As shown in FIG. 8, the operations at times t2 to t5 are the same as those in the first embodiment, and the description thereof is omitted. In the present embodiment, for example, the pulse widths of the R scan start pulse SSPr, the G scan start pulse SSPg, and the B scan start pulse SSPb are the same. That is, the pulse widths of the scanning signals applied to the R scanning line Srj, the G scanning line Sgj, and the B scanning line Sbj are the same. For this reason, the lengths of the selection periods of the R scanning line Srj, the G scanning line Sgj, and the B scanning line Sbj are the same.

  At time t6, the potential of the current R scanning line Srj changes from the low level to the high level. For this reason, in the R pixel circuit 11r, the writing transistor M2 and the compensating transistor M3 are turned off. In the present embodiment, as in the first embodiment, the selection period of the current R scanning line Srj is from time t3 to time t6. That is, the R threshold voltage compensation period Tcompr is provided at times t3 to t6. In this modification, at time t6, the potential of the emission line Ej does not change from the high level to the low level.

  At time t6a, the potential of the current G scanning line Sgj changes from the low level to the high level. For this reason, in the G pixel circuit 11g, the writing transistor M2 and the compensating transistor M3 are turned off. In the present embodiment, unlike the first embodiment, the selection period of the current G scanning line Sgj is time t4 to t6a. That is, the G threshold voltage compensation period Tcomg is provided at times t4 to t6a. If the times t3 to t4, t4 to t5, t6 to t6a, and t6a to t6b have the same length, the G threshold voltage compensation period Tcomg has the same length as the R threshold compensation period.

  At time t6b, the potential of the current B scanning line Sbj changes from the low level to the high level. For this reason, in the B pixel circuit 11b, the writing transistor M2 and the compensating transistor M3 are turned off. In the present embodiment, unlike the first embodiment, the selection period of the current B scanning line Sbj is from time t5 to t6b. That is, the B threshold voltage compensation period Tcomb is provided at times t5 to t6b. If the times t3 to t4, t4 to t5, t6 to t6a, and t6a to t6b have the same length, the B threshold voltage compensation period Tcomb has the same length as the R threshold compensation period. At time t6b, the potential of the emission line Ej changes from high level to low level. For this reason, the power supply transistor M5 and the light emission control transistor M6 are turned on. As a result, the drive current I corresponding to the gate potential Vg of the drive transistor M1 and the high-level power supply line ELVDD is supplied to the organic EL element OLED, and the organic EL element OLED emits light according to the current value of the drive current I. This drive current I is given by the above equation (4).

<2.2 Effect>
According to this embodiment, the length of each selection period of the G scanning line Sgj and the B scanning line Sbj is the same as the length of the selection period of the R scanning line Srj. Therefore, the G threshold voltage compensation period Tcompg and the B threshold voltage compensation period Tcompb are the longest R threshold voltage compensation period Tcompr in the threshold voltage compensation period Tcomp in the first embodiment. It becomes the same length. Therefore, in the G pixel circuit 11g and the B pixel circuit 11b, variation in the threshold voltage Vth of the driving transistor M1 is suppressed more than in the first embodiment. In particular, in the B pixel circuit 11b, the degree to which the variation in the threshold voltage Vth of the driving transistor M1 is suppressed is not different from the conventional one in the first embodiment, but in the present embodiment, the driving transistor M1 is not changed. Variation of the threshold voltage Vth is suppressed more than before. As a result, as compared with the first embodiment, the luminance unevenness due to the variation in the threshold voltage Vth of the driving transistor M1 can be further suppressed.

<2.3 Modification>
FIG. 9 is a block diagram showing an overall configuration of a display device 1 according to a modification of the second embodiment of the present invention. In addition, about the component same as the said 1st Embodiment among the components of this embodiment, the same referential mark is attached | subjected and description is abbreviate | omitted suitably. The display device 1 according to the first embodiment includes one emission driver 60, as shown in FIG. On the other hand, the display device 1 according to the present modification includes three emission drivers as shown in FIG. More specifically, an emission driver 60r corresponding to R (hereinafter referred to as “R emission driver”), an emission driver 60g corresponding to G (hereinafter referred to as “G emission driver”), and an emission driver 60b corresponding to B ( (Hereinafter referred to as “B emission driver”).

  The display unit 10 includes n emission lines Er1 to Ern corresponding to R (hereinafter referred to as “R emission lines”) and n emission lines Eg1 to Egn corresponding to G (hereinafter referred to as “G emission lines”). ) And n emission lines Eb1 to Ebn (hereinafter referred to as “B emission lines”) corresponding to B. The n R emission lines Er1 to Ern are connected to the R emission driver 60r, the n G emission lines Eg1 to Egn are connected to the G emission driver 60g, and the n B emission lines Eb1 to Ebn are connected to the B emission driver 60b. It is connected to the.

  The display control circuit 20 outputs the R emission start pulse ESPr and the R emission clock ECKr to the R emission driver 60r, outputs the G emission start pulse ESPg and the G emission clock ECKg to the G emission driver 60g, and outputs the B emission start pulse ESPb and The B emission clock ECKb is output to the B emission driver 60b.

  The R emission driver 60r drives n R emission lines Er1 to Ern. More specifically, the R emission driver 60r includes a shift register and a buffer (not shown). The shift register sequentially transfers the R start pulse ESPr in synchronization with the R emission clock ECKr. An emission signal that is an output from each stage of the shift register is supplied to a corresponding R emission line Erj (j = 1 to n) via a buffer.

  The G emission driver 60g drives n G emission lines Eg1 to Egn. More specifically, the G emission driver 60g includes a shift register and a buffer (not shown). The shift register sequentially transfers the G start pulse ESPg in synchronization with the G emission clock ECKg. An emission signal that is an output from each stage of the shift register is supplied to a corresponding G emission line Egj via a buffer.

  The B emission driver 60b drives n B emission lines Eb1 to Ebn. More specifically, the B emission driver 60b includes a shift register and a buffer (not shown). The shift register sequentially transfers the B start pulse ESPb in synchronization with the B emission clock ECKb. An emission signal that is an output from each stage of the shift register is supplied to a corresponding B emission line Ebj via a buffer.

  As shown in FIG. 9, the R scanning driver 50r, the G scanning driver 50g, and the B scanning driver 50b are arranged on one end side of the display unit 10 (left side with respect to the display unit 10 in FIG. 9). The R emission driver 60r, the G emission driver 60g, and the B emission driver 60b are arranged on the other end side of the display unit 10 (the right side with respect to the display unit 10 in FIG. 9). Thus, various drivers are equally arranged on both sides of the display unit 10. However, it is not essential for the present invention that the various drivers are equally disposed on both sides of the display unit 10, and the various drivers are disposed on both sides of the display unit 10 as in the second modification of the first embodiment. They may be arranged unevenly.

<2.2 Connection between pixel circuit and various wiring>
FIG. 10 is a circuit diagram showing a connection relationship between a part of the R pixel circuit 11r, the G pixel circuit 11g, and the B pixel circuit 11b and various wirings in the present modification. In this modification, as shown in FIG. 10, the connection destinations of the gate terminal of the write transistor M2, the gate terminal of the compensation transistor M3, and the second terminal of the second capacitor are the R pixel circuit 11r and the G pixel, respectively. The circuit 11g and the B pixel circuit 11b are different. That is, the connection destinations of the gate terminal of the writing transistor M2, the gate terminal of the compensating transistor M3, and the second terminal of the second capacitor in the R pixel circuit 11r, the G pixel circuit 11g, and the B pixel circuit 11b are R The pixel circuit 11r is the R emission line Erj, the G pixel circuit 11g is the G emission line Egj, and the B pixel circuit 11b is the B emission line Ebj.

<2.3 Operation>
FIG. 11 is a timing chart showing a driving method of the pixel circuit shown in FIG. Since the operation focusing on each scanning line is the same as that in the second embodiment, description thereof is omitted. At time t6, the potential of the R emission line Erj changes from the high level to the low level. For this reason, in the R pixel circuit 11r, the power supply transistor M5 and the light emission control transistor M6 are turned on. As a result, the drive current I corresponding to the gate potential Vg of the drive transistor M1 and the high-level power supply line ELVDD is supplied to the organic EL element OLED, and the organic EL element OLED emits light according to the current value of the drive current I. This drive current I is given by the above equation (4).

  At time t6a, the potential of the G emission line Egj changes from the high level to the low level. For this reason, in the G pixel circuit 11g, the power supply transistor M5 and the light emission control transistor M6 are turned on. As a result, the drive current I corresponding to the gate potential Vg of the drive transistor M1 and the high-level power supply line ELVDD is supplied to the organic EL element OLED, and the organic EL element OLED emits light according to the current value of the drive current I. This drive current I is given by the above equation (4).

  At time t6b, the potential of the B emission line Ebj changes from the high level to the low level. For this reason, in the B pixel circuit 11b, the power supply transistor M5 and the light emission control transistor M6 are turned on. As a result, the drive current I corresponding to the gate potential Vg of the drive transistor M1 and the high-level power supply line ELVDD is supplied to the organic EL element OLED, and the organic EL element OLED emits light according to the current value of the drive current I. This drive current I is given by the above equation (4).

  Even in an aspect in which an emission driver is provided for each primary color as in this modification, the same effects as in the second embodiment can be obtained. In this modification, the R emission driver 60r, the G emission driver 60g, and the B emission driver 60b are provided in order to individually drive the R emission line Erj, the G emission line Egj, and the B emission line Ebj. However, the present invention is not limited to this. For example, one emission driver that comprehensively includes the functions of the R emission driver 60r, the G emission driver 60g, and the B emission driver 60b may be provided.

<3. Other>
In each of the above-described embodiments, the description has been made on the assumption that color display using the RGB three primary colors is performed using the SSD method, but the present invention is not limited to this. For example, the present invention can be applied to an aspect in which color display is performed using RGBY4 primary colors (Y is yellow). In addition, the above-described embodiments can be variously modified and implemented without departing from the spirit of the present invention.

  As described above, according to the present invention, it is possible to provide a display device that employs the SSD method and that can drive the luminance unevenness, as compared with the related art.

DESCRIPTION OF SYMBOLS 1 ... Display apparatus 10 ... Display part 11 ... Pixel circuit 20 ... Display control circuit 30 ... Data driver (data line drive circuit)
40: Demultiplexer unit 41: Demultiplexer (selection output circuit)
50r, 50g, 50b... Scanning driver (scanning line driving circuit)
60r, 60g, 60b ... Emission driver (control line drive circuit)
Di: output lines Dri, Dgi, Dbi ... data lines Sj, Srj, Sgj, Sbj ... scanning lines Ej, Erj, Egj, Ebj ... emission lines (control lines)
M1 to M6, Mr, Mg, Mb ... transistors C1, C2, Cdri, Cdgi, Cdbi ... capacitors (capacitance elements)
ELVDD ... High level power line (first power line)
ELVSS ... Low level power line (second power line)
Vini ... Initialization line

Claims (14)

An active matrix display device that performs color display based on a plurality of primary colors by supplying a data signal corresponding to one of the plurality of primary colors to the pixel circuit in a time-sharing manner,
A plurality of data lines to which the data signal is supplied;
A plurality of scanning lines each corresponding to one of the plurality of primary colors;
A plurality of pixel circuits provided corresponding to the plurality of data lines and the plurality of scanning lines, each corresponding to one of the plurality of primary colors;
A scanning line driving circuit for starting selection of the scanning line corresponding to the primary color at a timing according to the supply of the data signal corresponding to each primary color to the data line,
The pixel circuit corresponding to each primary color is
An electro-optic element;
A driving transistor for controlling a current flowing through the electro-optic element and having a control terminal and a first conduction terminal electrically connected to each other when a corresponding scanning line is in a selected state;
A display device comprising: a first capacitor element for holding a voltage between the control terminal of the driving transistor and the first conduction terminal.
A first power supply line and a second power supply line for supplying a power supply potential in common to the plurality of pixel circuits;
The electro-optic element is provided between the first power line and the second power line,
The driving transistor is provided in series with the electro-optical element between the first power supply line and the second power supply line,
The pixel circuit corresponding to each primary color is
A control terminal connected to the scanning line corresponding to the primary color, a writing transistor provided between the second conduction terminal of the driving transistor and the data line;
The control terminal is connected to the scanning line corresponding to the primary color, and further includes a compensation transistor provided between the control terminal of the driving transistor and the first conduction terminal. The display device according to 1.
  3. The display device according to claim 2, wherein the scanning line driving circuit sets the lengths of the selection periods in which the scanning lines are selected to be the same for the plurality of primary colors. 4.   3. The display device according to claim 2, wherein the scanning line driving circuit sets the end timings of the selection period in which the scanning lines are selected to be the same for the plurality of primary colors. 4. A plurality of control lines provided along the plurality of scanning lines;
The display according to claim 2, further comprising: a control line driving circuit that emits an electro-optic element in a pixel circuit corresponding to the scanning line according to an end timing of the selection period of the scanning line. apparatus.
The pixel circuit includes:
A control terminal connected to the control line, a power supply transistor provided between the first conduction terminal of the driving transistor and the first power supply line;
A control terminal connected to the control line, and further includes a light emission control transistor provided between the second conduction terminal of the driving transistor and one end of the electro-optic element,
The control line driving circuit sets a potential for turning on the power supply transistor and the light emission control transistor in the pixel circuit corresponding to the scanning line in accordance with the end timing of the selection period of the scanning line. The display device according to claim 5, wherein the display device is supplied to the control line.
  Each of the plurality of pixel circuits arranged in the extending direction of the scanning line has a control terminal connected to the scanning line immediately before the scanning line to which any of the plurality of pixel circuits corresponds, and the control of the driving transistor The display device according to claim 2, further comprising an initialization transistor provided between the terminal and one end of the first capacitor element and an initialization line for supplying an initialization potential. .   The pixel circuit corresponding to each primary color further includes a second capacitor element provided between a scanning line corresponding to the primary color and the control terminal of the driving transistor. Display device. A plurality of selection output circuits for sequentially supplying data signals corresponding to any of a plurality of primary colors to the plurality of data lines;
The display device according to claim 2, further comprising a data line driving circuit for supplying the data signal to each of the plurality of selection output circuits.
  The display device according to claim 2, further comprising a data capacitor provided in each data line for holding the data signal. The scanning line driving circuit includes a plurality of scanning line driving circuits respectively corresponding to the plurality of primary colors,
The scanning line driving circuit corresponding to each primary color is
Selectively driving a plurality of scanning lines corresponding to the primary color,
The selection of a scanning line corresponding to the primary color is started at a timing corresponding to the supply of the data signal corresponding to the primary color to the data line, according to any one of claims 1 to 10. The display device described.
By supplying a data signal corresponding to one of a plurality of primary colors to the pixel circuit in a time-sharing manner, color display based on the plurality of primary colors is performed, and a plurality of data lines to which the data signals are supplied, A plurality of scanning lines corresponding to one of the plurality of primary colors, a plurality of pixel circuits provided corresponding to the plurality of data lines and the plurality of scanning lines, each corresponding to one of the plurality of primary colors; A drive method for an active matrix display device comprising:
A scanning step of starting selection of a scanning line corresponding to the primary color at a timing according to the supply of the data signal corresponding to each primary color to the data line;
The pixel circuit corresponding to each primary color is
An electro-optic element;
A driving transistor for controlling a current flowing through the electro-optic element and having a control terminal and a first conduction terminal electrically connected to each other when a corresponding scanning line is in a selected state;
A method for driving a display device, comprising: a first capacitor for holding a voltage between the control terminal of the driving transistor and the first conduction terminal.
  The driving method according to claim 12, wherein in the scanning step, the lengths of the selection periods in which the scanning lines are selected are made the same for the plurality of primary colors.   The driving method according to claim 12, wherein, in the scanning step, end timings of selection periods in which the scanning lines are selected are made the same for the plurality of primary colors.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015087586A (en) * 2013-10-31 2015-05-07 セイコーエプソン株式会社 Electro-optic device, method for driving electro-optic device, and electronic apparatus
WO2018173280A1 (en) * 2017-03-24 2018-09-27 シャープ株式会社 Display device and driving method thereof
WO2018179077A1 (en) * 2017-03-28 2018-10-04 シャープ株式会社 Display device and driving method thereof
WO2019053834A1 (en) * 2017-09-14 2019-03-21 シャープ株式会社 Display device and drive method therefor
WO2020054039A1 (en) * 2018-09-13 2020-03-19 シャープ株式会社 Display device and method for producing same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004170766A (en) * 2002-11-21 2004-06-17 Seiko Epson Corp Drive circuit, electrooptical device and drive method
JP2007079580A (en) * 2005-09-15 2007-03-29 Samsung Sdi Co Ltd Organic electroluminescent display device
JP2009204882A (en) * 2008-02-28 2009-09-10 Sony Corp El display panel module, el display panel, integrated circuit device, electronic device, and drive control method
JP2010243611A (en) * 2009-04-01 2010-10-28 Seiko Epson Corp Electro-optical apparatus, method of driving the same and electronic device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004170766A (en) * 2002-11-21 2004-06-17 Seiko Epson Corp Drive circuit, electrooptical device and drive method
JP2007079580A (en) * 2005-09-15 2007-03-29 Samsung Sdi Co Ltd Organic electroluminescent display device
JP2009204882A (en) * 2008-02-28 2009-09-10 Sony Corp El display panel module, el display panel, integrated circuit device, electronic device, and drive control method
JP2010243611A (en) * 2009-04-01 2010-10-28 Seiko Epson Corp Electro-optical apparatus, method of driving the same and electronic device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015087586A (en) * 2013-10-31 2015-05-07 セイコーエプソン株式会社 Electro-optic device, method for driving electro-optic device, and electronic apparatus
WO2018173280A1 (en) * 2017-03-24 2018-09-27 シャープ株式会社 Display device and driving method thereof
US10950183B2 (en) 2017-03-24 2021-03-16 Sharp Kabushiki Kaisha Display device and driving method thereof
WO2018179077A1 (en) * 2017-03-28 2018-10-04 シャープ株式会社 Display device and driving method thereof
WO2019053834A1 (en) * 2017-09-14 2019-03-21 シャープ株式会社 Display device and drive method therefor
WO2020054039A1 (en) * 2018-09-13 2020-03-19 シャープ株式会社 Display device and method for producing same

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