WO2019015197A1 - 一种双输入漏电保护器电路 - Google Patents

一种双输入漏电保护器电路 Download PDF

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Publication number
WO2019015197A1
WO2019015197A1 PCT/CN2017/113560 CN2017113560W WO2019015197A1 WO 2019015197 A1 WO2019015197 A1 WO 2019015197A1 CN 2017113560 W CN2017113560 W CN 2017113560W WO 2019015197 A1 WO2019015197 A1 WO 2019015197A1
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diode
circuit
ground
transistor
latch
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PCT/CN2017/113560
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English (en)
French (fr)
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钱加灿
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余姚市嘉荣电子电器有限公司
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Publication of WO2019015197A1 publication Critical patent/WO2019015197A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/26—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents
    • H02H3/32—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents involving comparison of the voltage or current values at corresponding points in different conductors of a single system, e.g. of currents in go and return conductors
    • H02H3/33—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents involving comparison of the voltage or current values at corresponding points in different conductors of a single system, e.g. of currents in go and return conductors using summation current transformers
    • H02H3/337—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents involving comparison of the voltage or current values at corresponding points in different conductors of a single system, e.g. of currents in go and return conductors using summation current transformers avoiding disconnection due to reactive fault currents

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  • the present invention relates to the field of electrical safety, and more particularly to a dual input leakage protector circuit.
  • a leakage monitoring chip for a leakage protector disclosed in the Chinese invention patent CN102723695B includes a power supply voltage stabilization circuit, a reference voltage generator and a latch output circuit, wherein the power supply voltage stabilization circuit provides a reference voltage generator and a latch output circuit.
  • the working voltage is characterized by further comprising: a first amplifying circuit and a second amplifying circuit having the same circuit structure and performance; an input end of the first differential circuit is electrically connected to an input end of the second differential circuit, and the end is used as a common input Terminating the external circuit; the other input end of the first differential circuit is connected to the external circuit, and the other input end of the second differential circuit is connected to the external circuit, and the output end of the first amplifying circuit and the output end of the second amplifying circuit respectively The input end of the latch output circuit is electrically connected; the reference voltage generator circuit provides a reference voltage for the input terminals of the first differential amplifier circuit and the second differential amplifier circuit, respectively.
  • the invention is dual input detection, when one of the amplifiers is amplified When the circuit output is damaged, the other amplifier circuit will not work properly or the leakage protector will fail when the combined output of the amplifier circuit is damaged.
  • the common PE disconnect current type leakage protector on the market has frequent tripping problems.
  • a dual input leakage protector circuit which comprises a power supply voltage stabilization circuit, a voltage reference circuit, a first amplification circuit, a second amplification circuit and a control output circuit
  • the power supply voltage stabilization circuit is a voltage reference circuit, An amplification circuit, a second amplification circuit, and a control output circuit supply power
  • the voltage reference circuit provides a reference voltage for the first amplification circuit and the second amplification circuit
  • the output ends of the first amplification circuit and the second amplification circuit are connected to the control output circuit
  • An amplifying circuit and a second amplifying circuit are independent of each other and have the same function.
  • the power voltage regulator circuit comprises: a first resistor, a second resistor, a first Zener diode, a second Zener diode, a third Zener diode, a fourth Zener diode, a first diode, and a second diode a third diode, a fourth diode, and a first triode, a first resistor, a second resistor, a first Zener diode, a second Zener diode, a third Zener diode, and a fourth Zener diode a first diode, a second diode, a third diode, a fourth diode, and a first triode, the first resistor being connected to the base and the collector of the first triode One end of the second resistor is connected to the collector of the first triode, and the first Zener diode, the second Zener diode, and the third Zener diode are connected in series with the second resistor and the ground in a positive and negative manner.
  • the anode of the third Zener diode is connected to the ground, and the cathode of the fourth Zener diode is connected to the base of the first transistor, the first two The pole tube, the second diode, the third diode, and the fourth diode are connected in a positive and negative polarity A fourth joint between the zener diode and ground, wherein the positive electrode of the positive electrode of the first diode is attached to the fourth zener diode, the anode of the fourth diode is attached to the ground.
  • the voltage reference circuit comprises: a reference voltage generator and a fifth Zener diode, wherein the power input end of the reference voltage generator is connected to the emitter of the first triode, and the reference voltage occurs
  • the grounding end of the device is connected to the ground line
  • the negative pole of the fifth Zener diode is connected to the output end of the reference voltage generator
  • the anode of the fifth Zener diode is connected to the ground line.
  • the first amplifying circuit comprises: a fifth diode, a sixth diode, a first operational amplifier and a first integrator, the negative pole of the fifth diode is connected to the positive pole of the sixth diode, and the fifth diode
  • the positive pole of the tube is connected to the negative pole of the sixth diode
  • the second input of the first operational amplifier that is, the inverting input terminal is connected to the negative terminal of the port CH1 and the sixth diode
  • the third operational amplifier is connected with the in-phase input terminal The positive terminal of the sixth diode, the port VF and the output of the reference voltage generator
  • the 6-pin output of the first operational amplifier is connected to the input end of the first integrator
  • the 7-pin of the first operational amplifier is the ground terminal Connected to the ground
  • the 4th pin of the first operational amplifier is the power input end connected to the emitter of the first triode, and the output end of the first integrator is connected to the base of the fourth triode and the port T1;
  • the first amplifying circuit comprises: a seventh diode, an eighth diode, a second operational amplifier and a second integrator, wherein the anode of the eighth diode is connected to the anode of the seventh diode, and the eighth pole
  • the positive pole of the tube is connected to the negative pole of the seventh diode
  • the second input of the second operational amplifier is the reverse input end connected to the negative terminal of the port CH2 and the seventh diode
  • the third step of the second operational amplifier is the non-inverting input terminal The positive terminal of the seventh diode, the port VF and the output of the reference voltage generator
  • the 6-pin output of the second operational amplifier is connected to the input of the second integrator
  • the 7-pin of the second operational amplifier is the ground terminal Connected to the ground line
  • the second operational amplifier has a 4-pin power supply input connected to the emitter of the first triode, and an output of the second integrator is connected to the base of the second triode and the port T2;
  • the control output circuit includes a first latch output circuit and a second latch output circuit.
  • the emitter of the fourth transistor Q4 is connected to the anode of the tenth diode D10, and the collector of the fourth transistor Q4 is connected to the input of the first latch, the tenth diode D10.
  • the negative pole is connected to the ground, and the 3rd pin of the first latch is connected to the fifth pole.
  • the collector of the tube Q5 and the port OUT; the second pin of the first latch, that is, the power input end is connected to the emitter of the first transistor Q11; the pin 5 of the first latch is connected to the ground, the ground
  • the base of the five transistor Q5 is connected to the 4th pin of the first latch; the emitter of the fifth transistor Q5 is connected to the ground.
  • the emitter of the second transistor Q22 is connected to the anode of the ninth diode D9, and the collector of the ninth transistor Q9 is connected to the input of the second latch, the ninth diode D9.
  • the negative pole is connected to the ground, the output of the second latch is connected to the collector of the third transistor Q3 and the port OUT; the second pin of the second latch is connected to the first three
  • the emitter of the transistor Q11; the ground of the second latch is connected to the ground, the base of the third transistor Q3 is connected to the 4th of the second latch; the third transistor Q3 The emitter is connected to the ground.
  • Port T1 and port T2 are externally connected to the timing capacitor.
  • Port T1 or port T2 is connected to the function expansion circuit.
  • the present invention solves the problem that the prior art one-way amplification circuit fails and the entire protection circuit fails.
  • Figure 1 is a block diagram of the circuit of the present invention
  • Figure 2 is a circuit schematic diagram of the present invention
  • FIG. 3 is a schematic diagram of the basic functional circuit of the present invention.
  • Figure 4 is a schematic diagram of a full functional circuit of the present invention.
  • Figure 5 is a block diagram of a circuit of Embodiment 2 of the present invention.
  • Figure 6 is a schematic diagram of a complete functional circuit of Embodiment 2 of the present invention.
  • Figure 7 is a circuit block diagram of Embodiment 3 of the present invention.
  • the power voltage stabilization circuit As shown in FIG. 1 , the power voltage stabilization circuit, the voltage reference circuit, the first amplification circuit, the second amplification circuit, and the control output circuit are included, and the power voltage stabilization circuit is a voltage reference circuit, a first amplification circuit, a second amplification circuit, and a control.
  • the output circuit supplies power; the voltage reference circuit provides a reference voltage for the first amplifying circuit and the second amplifying circuit; the output ends of the first amplifying circuit and the second amplifying circuit are connected to the control output circuit, wherein the control output circuit internally includes two latches The input of one latch is connected to the first amplifying circuit; the other latch is connected to the second amplifying circuit, and the first amplifying circuit and the second amplifying circuit are independent and functionally identical.
  • the first resistor R1 is connected to the base and the collector of the first transistor Q11, and the second resistor R22 is connected to the collector of the first transistor Q11.
  • the diode ZD1, the second Zener diode ZD2 and the third Zener diode ZD3 are connected in series between the second resistor R22 and the ground in a positive and negative manner, wherein the cathode of the first Zener diode ZD1 is connected to the second resistor.
  • the anode of the third Zener diode ZD3 is connected to the ground
  • the cathode of the fourth Zener diode ZD4 is connected to the base of the first transistor Q11, the first diode D11, the second diode D22, the first
  • the three diodes D3 and the fourth diode D4 are connected in series between the fourth Zener diode ZD4 and the ground line in a manner that the positive and negative poles are sequentially connected, wherein the anode of the first diode D11 is connected to the fourth Zener diode
  • the anode of the ZD4 and the cathode of the fourth diode D4 are connected to the ground.
  • the power input end of the reference voltage generator is connected to the emitter of the first transistor Q11, the ground end of the reference voltage generator is connected to the ground, and the cathode of the fifth Zener diode ZD5 is connected to the output of the reference voltage generator.
  • the anode of the fifth Zener diode ZD5 is connected to the ground.
  • the cathode of the fifth diode D5 is connected to the anode of the sixth diode D6, the anode of the fifth diode D5 is connected to the cathode of the sixth diode D6, and the 2nd pin of the first operational amplifier IC1 is reverse input.
  • the negative terminal of the port CH1 and the sixth diode D6 are connected; the 3-pin, the non-inverting input of the first operational amplifier (IC1) is connected to the positive terminal of the sixth diode D6, the port VF, and the output of the reference voltage generator.
  • the output pin of the first operational amplifier IC1 is connected to the input end of the first integrator; the 7th pin of the first operational amplifier IC1 is connected to the ground; the 4th pin of the first operational amplifier IC1 is the power input.
  • the output of the first integrator is connected to the base of the fourth transistor Q4 and the port T1; the power input of the first integrator is connected to the first transistor Q11
  • the emitter of the first integrator is connected to the ground.
  • the anode of the eighth diode D8 is connected to the anode of the seventh diode D7, the anode of the eighth diode D8 is connected to the cathode of the seventh diode D7, and the second leg of the second operational amplifier IC2 is reverse input.
  • the negative terminal of the port CH2 and the seventh diode D7 is connected; the second operational amplification
  • the 3 pin of the device (IC2) that is, the non-inverting input is connected to the positive terminal of the seventh diode D7, the port VF and the output of the reference voltage generator; the 6-pin output of the second operational amplifier IC2 is connected to the second integrator
  • the input terminal of the second operational amplifier IC2 is connected to the ground line;
  • the 4th pin of the second operational amplifier IC1 is the power input end connected to the emitter of the first transistor Q11, and the output of the second integrator
  • the base of the second transistor Q22 is connected to the port T2; the power input end of the second integrator is connected to the emitter of the first transistor Q11; and the ground of the second integrator is connected to the ground.
  • the emitter of the fourth transistor Q4 is connected to the anode of the tenth diode D10, and the collector of the fourth transistor Q4 is connected to the input terminal of the first latch, and the tenth diode D10
  • the negative pole is connected to the ground line
  • the output pin of the first latch is connected to the collector of the fifth transistor Q5 and the port OUT;
  • the pin 2 of the first latch is connected to the first three poles of the power input end.
  • the emitter of the tube Q11; the 5th pin of the first latch is connected to the ground line, the base of the fifth transistor Q5 is connected to the 4th pin of the first latch; the emission of the fifth transistor Q5 Extremely connected to the ground.
  • the emitter of the second transistor Q22 is connected to the anode of the ninth diode D9, the collector of the ninth transistor Q9 is connected to the input terminal of the second latch, and the ninth diode D9
  • the negative pole is connected to the ground, the output of the second latch is connected to the collector of the third transistor Q3 and the port OUT; the second pin of the second latch is connected to the first three poles.
  • the emitter of the tube Q11; the ground of the second latch is connected to the ground, the base of the third transistor Q3 is connected to the 4th of the second latch; the emission of the third transistor Q3 Extremely connected to the ground.
  • the circuit is a basic functional circuit schematic diagram of the present invention.
  • the port T1 is externally connected to the timing capacitor 1
  • the port T2 is externally connected to the timing capacitor 2
  • the thyristor SCR controls the trip unit S1-S2
  • the ground line abnormality indicating circuit is installed.
  • the zero-sequence current transformer ZCT1 is used to detect the leakage of the neutral line and the live line
  • the ground line transformer ZCT2 is used to detect the ground line leakage.
  • the circuit is a complete functional circuit schematic diagram of the present invention, and the power indicating circuit functions to indicate the working state of the circuit to prevent the occurrence of false touches.
  • the zero-sequence current transformer ZCT1 detects the neutral line or the live line leaks, the induced voltage is input to the VF port and the CH1 port of the first amplifying circuit respectively.
  • the port T1 is given in a constant current manner.
  • Capacitor C4 is charged, when the capacitor voltage reaches a preset value, the first latch in the first latch output circuit is flipped and latched, the OUT pin outputs a high level, and the thyristor SCR is turned on via the diode D2, and the trip coil is turned off. L is energized, causing S1-S2 to be disconnected, thereby achieving the function of zero-sequence leakage protection.
  • the induced voltage is input to the VF port and the CH2 port of the second amplified current respectively.
  • the port T2 charges the capacitor C5 in a constant current manner.
  • the second latch in the second latch output circuit is flipped and latched, the OUT pin outputs a high level, the thyristor SCR is turned on via the diode D2, and the trip coil L is energized.
  • the function of ground leakage protection is realized by disconnecting S1-S2.
  • the structure of the embodiment is basically the same as that of Embodiment 1, except that the T1 and T2 externally connected to the output terminal of the first amplifying circuit or the second amplifying circuit are connected to the transistor Q2 at both ends of the timing capacitor (such as C5).
  • Transistor Q2 is controlled by other functions to extend the application circuit.
  • the circuit is a complete functional circuit schematic of the implementation 2, and the transistor Q2 receives the signal from the function expansion operation circuit.
  • the expansion signal outputs a high level
  • the transistor Q2 is saturatingly turned on, and the port T2 is externally connected with the timing capacitor.
  • the voltage is reduced to 0V due to the saturation conduction of the transistor Q2, so even if the ground line transformer ZCT2 detects the ground leakage
  • the OUT port also has no voltage output; under the premise of effective grounding, the transistor Q2 is controlled to be turned on, so that it is automatically turned off under the premise of effective grounding, which solves the problem that the current market is effectively grounded.
  • the PE disconnect current type leakage protector has frequent tripping due to the ground wire voltage of the socket and the wall forming a loop.
  • the structure of this embodiment is basically the same as that of Embodiment 1, except that the lines of the input reference voltages of the first amplifying circuit and the second amplifying circuit are separated, and other structures are completely the same, and the functions realized are also It's exactly the same.

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Abstract

一种双输入漏电保护器电路，包括电源稳压电路、电压基准电路、第一放大电路、第二放大电路和控制输出电路，电源稳压电路为电压基准电路、第一放大电路、第二放大电路和控制输出电路供电；电压基准电路为第一放大电路和第二放大电路提供基准电压；第一放大电路和第二放大电路的输出端连接着控制输出电路，第一放大电路和第二放大电路相互独立且功能相同。该漏电保护器电路解决了现有技术存在的一路放大电路失效，整个保护电路失效的问题。

Description

一种双输入漏电保护器电路 技术领域
本发明涉及电气安全领域，尤其涉及一种双输入漏电保护器电路。
背景技术
随着生活水平的提高，人们家中的电器也越来越多，对生活用电的安全越来越关注，随之出现了各式各样的漏电保护器，由于用电环境越来越恶劣,当前的地线异常保护已不能满足常规的控制需求,因此漏电保护器需要智能方向发展,地线异常保护需要扩展检测及智能识别方可实现全方位立体保护。
如中国发明专利CN102723695B所公开的一种漏电保护器的漏电监控芯片,包括电源稳压电路、参考电压发生器及锁存输出电路,其中电源稳压电路为参考电压发生器及锁存输出电路提供工作电压；特点是还包括电路结构及性能相同的第一放大电路及第二放大电路,第一差放电路的一输入端与第二差放电路的一输入端电连接,该端作为公共输入端接外电路；第一差放电路的另一输入端接外电路,第二差放电路的另一输入端接外电路,第一放大电路的输出端与第二放大电路的输出端分别与锁存输出电路的输入端电连接；参考电压发生器电路分别为第一差放电路及第二差放电路的输入端提供参考电压，该发明虽然是双输入检测，但是当放大器其中的一路放大电路输出损坏时将造成另一路放大电路也不能正常工作或者当放大电路合并的输出端损坏时,漏电保护器将失效。
而市面上常见的PE断开电流型漏电保护器有频繁跳闸的问题。
发明内容
一、要解决的技术问题
如何解决现有的双输入漏电保护器电路存在的一路放大电路失效，整个保护电路失效的问题。
二、技术方案
为了解决上述问题，特提供一种双输入漏电保护器电路，包括电源稳压电路、电压基准电路、第一放大电路、第二放大电路和控制输出电路，电源稳压电路为电压基准电路、第一放大电路、第二放大电路和控制输出电路供电；电压基准电路为第一放大电路和第二放大电路提供基准电压；第一放大电路和第二放大电路的输出端连接着控制输出电路，第一放大电路和第二放大电路相互独立且功能相同。
其中电源稳压电路包括：第一电阻、第二电阻、第一稳压二极管、第二稳压二极管、第三稳压二极管、第四稳压二极管、第一二极管、第二二极管、第三二极管、第四二极管和第一三极管，第一电阻、第二电阻、第一稳压二极管、第二稳压二极管、第三稳压二极管、第四稳压二极管、第一二极管、第二二极管、第三二极管、第四二极管和第一三极管，第一电阻两端分别连着第一三极管的基极和集电极，第二电阻的一端连着第一三极管的集电极，第一稳压二极管、第二稳压二极管和第三稳压二极管以正负极依次相连的方式串联在第二电阻和地线之间，其中第一稳压二极管的负极连着第二电阻，第三稳压二极管的正极连着地线，第四稳压二极管的负极连着第一三极管的基极，第一二极管、第二二极管、第三二极管和第四二极管以正负极依次相连的方式串联在第四稳压二极管和地线之间，其中第一二极管的正极连着第四稳压二极管的正极，第四二极管的负极连着地线。
其中电压基准电路包括：参考电压发生器和第五稳压二极管，参考电压发生器的电源输入端连着第一三极管的发射极，参考电压发生 器的接地端连着地线，第五稳压二极管的负极连着参考电压发生器的输出端，第五稳压二极管的正极连着地线。
其中第一放大电路包括：第五二极管、第六二极管、第一运算放大器和第一积分器，第五二极管的负极连着第六二极管的正极，第五二极管的正极连着第六二极管的负极，第一运算放大器的2脚即反向输入端连着端口CH1和第六二极管的负极；第一运算放大器的3脚即同相输入端连着第六二极管的正极、端口VF和参考电压发生器的输出端；第一运算放大器的6脚即输出端连着第一积分器的输入端；第一运算放大器的7脚即接地端连着地线；第一运算放大器的4脚即电源输入端连着第一三极管的发射极，第一积分器的输出端连着第四三极管的基极和端口T1；第一积分器的电源输入端连着第一三极管的发射极；第一积分器的接地端连着地线。
其中第一放大电路包括：第七二极管、第八二极管、第二运算放大器和第二积分器，第八二极管的负极连着第七二极管的正极，第八二极管的正极连着第七二极管的负极，第二运算放大器的2脚即反向输入端连着端口CH2和第七二极管的负极；第二运算放大器的3脚即同相输入端连着第七二极管的正极、端口VF和参考电压发生器的输出端；第二运算放大器的6脚即输出端连着第二积分器的输入端；第二运算放大器的7脚即接地端连着地线；第二运算放大器的4脚即电源输入端连着第一三极管的发射极，第二积分器的输出端连着第二三极管的基极和端口T2；第二积分器的电源输入端连着第一三极管的发射极；第二积分器的接地端连着地线。
其中控制输出电路包括第一锁存输出电路和第二锁存输出电路。
其中第四三极管Q4的发射极和第十二极管D10的正极连接，第四三极管Q4的集电极和第一锁存器的1脚即输入端相连，第十二极管D10的负极连着地线，第一锁存器的3脚即输出端连着第五三极 管Q5的集电极和端口OUT；第一锁存器的2脚即电源输入端连着第一三极管Q11的发射极；第一锁存器的5脚即接地端连着地线，第五三极管Q5的基极连着第一锁存器的4脚；第五三极管Q5的发射极连着地线。
其中第二三极管Q22的发射极和第九二极管D9的正极连接，第九三极管Q9的集电极和第二锁存器的1脚即输入端相连，第九二极管D9的负极连着地线，第二锁存器的3脚即输出端连着第三三极管Q3的集电极和端口OUT；第二锁存器的2脚即电源输入端连着第一三极管Q11的发射极；第二锁存器的5脚即接地端连着地线，第三三极管Q3的基极连着第二锁存器的4脚；第三三极管Q3的发射极连着地线。
其中端口T1和端口T2外接定时电容。
其中端口T1或端口T2连着功能扩展电路。
三、本发明的有益效果
与现有技术相比，本发明解决了现有技术存在的一路放大电路失效，整个保护电路失效的问题。
附图说明
图1是本发明的电路方块图；
图2是本发明的电路原理图；
图3是本发明的基本功能电路原理图；
图4是本发明的完整功能电路原理图；
图5是本发明的实施2的电路方块图；
图6是本发明的实施例2的完整功能电路原理图；
图7是本发明的实施例3的电路方块图。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不能用来限制本发明的范围。
实施例1:
如图1所示，包括电源稳压电路、电压基准电路、第一放大电路、第二放大电路和控制输出电路，电源稳压电路为电压基准电路、第一放大电路、第二放大电路和控制输出电路供电；电压基准电路为第一放大电路和第二放大电路提供基准电压；第一放大电路和第二放大电路的输出端连接着控制输出电路，其中控制输出电路内部包含两个锁存器，一个锁存器的输入端连着第一放大电路；另一个锁存器连着第二放大电路，第一放大电路和第二放大电路相互独立且功能相同。
如图2所示，第一电阻R1两端分别连着第一三极管Q11的基极和集电极，第二电阻R22的一端连着第一三极管Q11的集电极，第一稳压二极管ZD1、第二稳压二极管ZD2和第三稳压二极管ZD3以正负极依次相连的方式串联在第二电阻R22和地线之间，其中第一稳压二极管ZD1的负极连着第二电阻R22，第三稳压二极管ZD3的正极连着地线，第四稳压二极管ZD4的负极连着第一三极管Q11的基极，第一二极管D11、第二二极管D22、第三二极管D3和第四二极管D4以正负极依次相连的方式串联在第四稳压二极管ZD4和地线之间，其中第一二极管D11的正极连着第四稳压二极管ZD4的正极，第四二极管D4的负极连着地线。
参考电压发生器的电源输入端连着第一三极管Q11的发射极，参考电压发生器的接地端连着地线，第五稳压二极管ZD5的负极连着参考电压发生器的输出端，第五稳压二极管ZD5的正极连着地线。
第五二极管D5的负极连着第六二极管D6的正极，第五二极管D5的正极连着第六二极管D6的负极，第一运算放大器IC1的2脚即反向输入端连着端口CH1和第六二极管D6的负极；第一运算放大器(IC1)的3脚即同相输入端连着第六二极管D6的正极、端口VF和参考电压发生器的输出端；第一运算放大器IC1的6脚即输出端连着第一积分器的输入端；第一运算放大器IC1的7脚即接地端连着地线；第一运算放大器IC1的4脚即电源输入端连着第一三极管Q11的发射极，第一积分器的输出端连着第四三极管Q4的基极和端口T1；第一积分器的电源输入端连着第一三极管Q11的发射极；第一积分器的接地端连着地线。
第八二极管D8的负极连着第七二极管D7的正极，第八二极管D8的正极连着第七二极管D7的负极，第二运算放大器IC2的2脚即反向输入端连着端口CH2和第七二极管D7的负极；第二运算放大 器(IC2)的3脚即同相输入端连着第七二极管D7的正极、端口VF和参考电压发生器的输出端；第二运算放大器IC2的6脚即输出端连着第二积分器的输入端；第二运算放大器IC2的7脚即接地端连着地线；第二运算放大器IC1的4脚即电源输入端连着第一三极管Q11的发射极，第二积分器的输出端连着第二三极管Q22的基极和端口T2；第二积分器的电源输入端连着第一三极管Q11的发射极；第二积分器的接地端连着地线。
第四三极管Q4的发射极和第十二极管D10的正极连接，第四三极管Q4的集电极和第一锁存器的1脚即输入端相连，第十二极管D10的负极连着地线，第一锁存器的3脚即输出端连着第五三极管Q5的集电极和端口OUT；第一锁存器的2脚即电源输入端连着第一三极管Q11的发射极；第一锁存器的5脚即接地端连着地线，第五三极管Q5的基极连着第一锁存器的4脚；第五三极管Q5的发射极连着地线。
第二三极管Q22的发射极和第九二极管D9的正极连接，第九三极管Q9的集电极和第二锁存器的1脚即输入端相连，第九二极管D9的负极连着地线，第二锁存器的3脚即输出端连着第三三极管Q3的集电极和端口OUT；第二锁存器的2脚即电源输入端连着第一三极管Q11的发射极；第二锁存器的5脚即接地端连着地线，第三三极管Q3的基极连着第二锁存器的4脚；第三三极管Q3的发射极连着地线。
如图3所示，该电路是本发明的基本功能电路原理图，端口T1外接定时电容1，端口T2外接定时电容2，可控硅SCR控制脱扣器S1-S2，地线异常指示电路安装与零线和地线之间，零序电流互感器ZCT1用于检测零线和火线的漏电；地线互感器ZCT2用于检测地线漏电。
如图4所示，该电路是本发明的完整功能电路原理图，电源指示电路起到了指示电路工作状态的作用，防止误触的发生。
当零序电流互感器ZCT1检测到零线或者火线有漏电时，感应电压分别输入第一放大电路的VF端口和CH1端口，当漏电电流强度达到预设值时,端口T1以恒流的方式给电容C4充电，电容电压达到预设值时，第一锁存输出电路中的第一锁存器翻转锁存，OUT脚输出高电平，经二极管D2触发可控硅SCR导通，脱扣线圈L通电，使得S1-S2断开，从而实现零序漏电保护的功能。
当地线电流互感器ZCT2检测到地线有漏电时，感应电压分别输入第二放大电流的VF端口和CH2端口，当漏电电流强度达到预设值时,端口T2以恒流的方式给电容C5充电，电容电压达到预设值时，第二锁存输出电路中的第二锁存器翻转锁存，OUT脚输出高电平，经二极管D2触发可控硅SCR导通，脱扣线圈L通电，使得S1-S2断开，从而实现地线漏电保护的功能。
当电源插头因接触不良等其他原因出现超温现象时，超温保护电路中的热敏电阻RT阻值变小，使得三极管Q1导通，从而使得可控硅SCR导通，脱扣线圈L通电，使得S1-S2断开，实现了超温保护的功能。
实施例2:
如图5所示，本实施例的结构和实施例1基本相同，不同点是：在第一放大电路或第二放大电路输出端的T1，T2外接定时电容(如C5)两端并接三极管Q2,三极管Q2受控于其它功能扩展运用电路，
如图6所示，该电路是实施2的完整功能电路原理图，三极管Q2接受来自于功能扩展运用电路的信号,当扩展信号输出高电平时,三极管Q2饱和导通,端口T2外接定时电容的电压因三极管Q2的饱和导通而降低至0V,因此，即使地线互感器ZCT2检测到地线漏电电 流大小超出预设值时,OUT端口也无电压输出；在有效接地的前提下,三极管Q2受控导通,使其在有效接地的前提下自动关闭，解决了目前市场上因有效接地时，PE断开电流型漏电保护器因插座地线电压与墙体构成回路造成频繁跳闸的问题。
实施例3：
如图7所示，本实施例的结构和实施例1基本相同，不同点是：第一放大电路和第二放大电路的输入基准电压的线路是分开的，其他结构完全相同，实现的功能也完全相同。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴。

Claims (10)

  1. 一种双输入漏电保护器电路，包括电源稳压电路、电压基准电路、第一放大电路、第二放大电路和控制输出电路，其特征在于：所述电源稳压电路为所述电压基准电路、所述第一放大电路、所述第二放大电路和所述控制输出电路供电；电压基准电路为第一放大电路和第二放大电路提供基准电压；第一放大电路和第二放大电路的输出端连接着控制输出电路，第一放大电路和第二放大电路相互独立且功能相同。
  2. 如权利要求1所述的一种双输入漏电保护器电路，其特征在于：所述电源稳压电路包括：第一电阻(R11)、第二电阻(R22)、第一稳压二极管(ZD1)、第二稳压二极管(ZD2)、第三稳压二极管(ZD3)、第四稳压二极管(ZD4)、第一二极管(D11)、第二二极管(D22)、第三二极管(D3)、第四二极管(D4)和第一三极管(Q11)，第一电阻(R11)两端分别连着第一三极管(Q11)的基极和集电极，第二电阻(R22)的一端连着第一三极管(Q11)的集电极，第一稳压二极管(ZD1)、第二稳压二极管(ZD2)和第三稳压二极管(ZD3)以正负极依次相连的方式串联在第二电阻(R22)和地线之间，其中第一稳压二极管(ZD1)的负极连着第二电阻(R22)，第三稳压二极管(ZD3)的正极连着地线，第四稳压二极管(ZD4)的负极连着第一三极管(Q11)的基极，第一二极管(D11)、第二二极管(D22)、第三二极管(D3)和第四二极管(D4)以正负极依次相连的方式串联在第四稳压二极管(ZD4)和地线之间，其中第一二极管(D11)的正极连着第四稳压二极管(ZD4)的正极，第四二极管(D4)的负极连着地线。
  3. 如权利要求1所述的一种双输入漏电保护器电路，其特征在于：所述电压基准电路包括：参考电压发生器和第五稳压二极管 (ZD5)，参考电压发生器的电源输入端连着第一三极管(Q11)的发射极，参考电压发生器的接地端连着地线，第五稳压二极管(ZD5)的负极连着参考电压发生器的输出端，第五稳压二极管(ZD5)的正极连着地线。
  4. 如权利要求1所述的一种双输入漏电保护器电路，其特征在于：所述第一放大电路包括：第五二极管(D5)、第六二极管(D6)、第一运算放大器(IC1)和第一积分器，第五二极管(D5)的负极连着第六二极管(D6)的正极，第五二极管(D5)的正极连着第六二极管(D6)的负极，第一运算放大器(IC1)的2脚即反向输入端连着端口CH1和第六二极管(D6)的负极；第一运算放大器(IC1)的3脚即同相输入端连着第六二极管(D6)的正极、端口VF和参考电压发生器的输出端；第一运算放大器(IC1)的6脚即输出端连着第一积分器的输入端；第一运算放大器(IC1)的7脚即接地端连着地线；第一运算放大器(IC1)的4脚即电源输入端连着第一三极管(Q11)的发射极，第一积分器的输出端连着第四三极管(Q4)的基极和端口T1；第一积分器的电源输入端连着第一三极管(Q11)的发射极；第一积分器的接地端连着地线。
  5. 如权利要求1所述的一种双输入漏电保护器电路，其特征在于：所述第一放大电路包括：第七二极管(D7)、第八二极管(D8)、第二运算放大器(IC2)和第二积分器，第八二极管(D8)的负极连着第七二极管(D7)的正极，第八二极管(D8)的正极连着第七二极管(D7)的负极，第二运算放大器(IC2)的2脚即反向输入端连着端口CH2和第七二极管(D7)的负极；第二运算放大器(IC2)的3脚即同相输入端连着第七二极管(D7)的正极、端口VF和参考电压发生器的输出端；第二运算放大器(IC2)的6脚即输出端连着第二积分器的输入端；第二运算放大器(IC2)的7脚即接地端连着地线；第二运算放大器(IC1)的4脚即电源输入端连着第一三极管(Q11) 的发射极，第二积分器的输出端连着第二三极管(Q22)的基极和端口T2；第二积分器的电源输入端连着第一三极管(Q11)的发射极；第二积分器的接地端连着地线。
  6. 如权利要求1所述的一种双输入漏电保护器电路，其特征在于：所述控制输出电路包括第一锁存输出电路和第二锁存输出电路。
  7. 如权利要求6所述的控制输出电路，其特征在于：所述第一锁存电路包括：第四三极管(Q4)、第十二极管(D10)、第一锁存器和第五三极管(Q5)，第四三极管(Q4)的发射极和第十二极管(D10)的正极连接，第四三极管(Q4)的集电极和第一锁存器的1脚即输入端相连，第十二极管(D10)的负极连着地线，第一锁存器的3脚即输出端连着第五三极管(Q5)的集电极和端口OUT；第一锁存器的2脚即电源输入端连着第一三极管(Q11)的发射极；第一锁存器的5脚即接地端连着地线，第五三极管(Q5)的基极连着第一锁存器的4脚；第五三极管(Q5)的发射极连着地线。
  8. 如权利要求6所述的控制输出电路，其特征在于：所述第二锁存电路包括：第二三极管(Q22)、第九二极管(D9)、第二锁存器和第三三极管(Q3)，第二三极管(Q22)的发射极和第九二极管(D9)的正极连接，第九三极管(Q9)的集电极和第二锁存器的1脚即输入端相连，第九二极管(D9)的负极连着地线，第二锁存器的3脚即输出端连着第三三极管(Q3)的集电极和端口OUT；第二锁存器的2脚即电源输入端连着第一三极管(Q11)的发射极；第二锁存器的5脚即接地端连着地线，第三三极管(Q3)的基极连着第二锁存器的4脚；第三三极管(Q3)的发射极连着地线。
  9. 如权利要1所述的一种双输入漏电保护器电路，其特征在于：所述端口T1和端口T2外接定时电容。
  10. 如权利要9所述的一种双输入漏电保护器电路，其特征在于： 所述端口T1或端口T2连着功能扩展运用电路。
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