WO2019011063A1 - 二乘二取二系统同步方法及计算机设备 - Google Patents

二乘二取二系统同步方法及计算机设备 Download PDF

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WO2019011063A1
WO2019011063A1 PCT/CN2018/088242 CN2018088242W WO2019011063A1 WO 2019011063 A1 WO2019011063 A1 WO 2019011063A1 CN 2018088242 W CN2018088242 W CN 2018088242W WO 2019011063 A1 WO2019011063 A1 WO 2019011063A1
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subsystem
synchronization
determining
task
communication channel
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English (en)
French (fr)
Inventor
胡仁强
余佳健
薄云览
王发平
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BYD Co Ltd
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BYD Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B15/00—Systems controlled by a computer
    • G05B15/02—Systems controlled by a computer electric
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Definitions

  • the present application relates to the field of electronic information technology, and in particular, to a method for synchronizing a two-by-two-two system and a computer device.
  • the present application aims to solve at least one of the technical problems in the related art to some extent.
  • the first object of the present application is to propose a two-by-two-two-system synchronization method, which realizes the square by utilizing the first communication channel between the first subsystem and the second subsystem in the system.
  • the synchronization of the two systems is simple, secure, and reliable.
  • a second object of the present application is to propose a computer device.
  • a third object of the present application is to propose a computer readable storage medium.
  • the first aspect of the present application provides a method for synchronizing a two-by-two-two system, the system including a first subsystem and a second subsystem, and the first subsystem and the The performance of the second subsystem is the same, the method includes: the first subsystem sends a synchronization message by using a first communication channel with the second subsystem when determining that the current subsystem is the primary system; The communication channel acquires an acknowledgement message returned by the second subsystem, and determines that the first subsystem and the second subsystem are in a synchronized state.
  • the synchronization message includes clock information and task information; and determining that the first subsystem is in a synchronized state with the second subsystem includes: determining the The second subsystem is in a clock synchronization and task synchronization state with the first subsystem.
  • the synchronization message includes processing data
  • the determining that the first subsystem is in a synchronized state with the second subsystem comprises: determining the second The subsystem is in a data synchronization state with the first subsystem.
  • the method further includes: updating a synchronization identifier in the first subsystem .
  • the method further includes: if not obtained by the second subsystem And confirming the message, determining an important level of the task corresponding to the task information; and controlling the first subsystem to power off when determining that the important level of the task corresponding to the task information reaches a preset condition.
  • the first subsystem before the determining, by the first subsystem, that the current subsystem is the main system, the first subsystem further includes: the first subsystem acquiring the system recommendation and/or switching the key position information; Determining, according to the tracing suggestion and/or switching key position information, that the first subsystem is the main system; controlling the first relay associated with the first subsystem, wherein the first relay and the second relay Interlocking, the second relay is a relay associated with the second subsystem; after determining that the first relay is successfully closed, determining that the first subsystem is currently the main system.
  • the determining, according to the relationship suggestion and the switching key position information, that the first subsystem is the primary system includes: determining that the cut recommendation score is greater than a threshold, And when the switching key position allows the first subsystem to be the main system, determining that the first subsystem is the main system.
  • the first subsystem and the second subsystem respectively include a primary CPU and a secondary CPU; the primary CPU in the first subsystem passes the first a communication channel that transmits the synchronization message to a primary CPU in the second subsystem.
  • the primary CPU sends a synchronization message to the slave CPU through a second communication channel.
  • the first subsystem synchronizes the first communication channel with the second subsystem when the current subsystem is determined to be the main communication system, and if the first communication channel is used, Obtaining the confirmation message returned by the second subsystem determines that the first subsystem and the second subsystem are in a synchronized state.
  • a second aspect of the present application provides a computer device, including: a memory, a processor, and a computer program stored on the memory and operable on the processor, when the processor executes the program Implementing a two-by-two-two-system synchronization method as described in the first aspect.
  • the third aspect of the present application provides a computer readable storage medium having stored thereon a computer program, the program being executed by the processor to implement the two-by-two system according to the first aspect. Synchronization method.
  • FIG. 1 is a schematic structural diagram of a two-by-two-two system of the related art
  • FIG. 2 is a schematic flow chart of a method for synchronizing a two-by-two-two system according to an embodiment of the present application
  • FIG. 3 is a schematic flow chart of a method for synchronizing a two-by-two-two system according to another embodiment of the present application
  • FIG. 4 is a schematic structural diagram of a two-by-two-two system according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a computer device according to an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a two-by-two-two system of the related art.
  • the two-way two-two system of the related art includes two two-two systems, which are main system and standby system respectively.
  • dual-port random access memory (DPRAM) shared memory is used for data transmission to achieve synchronization; between the main system and the backup system, Dual-port random access memory (DPRAM) shared memory for data transmission for synchronization.
  • DPRAM dual-port random access memory
  • the CPU 1 writes data to the DPRAM
  • the CPU 2 reads data from the DPRAM.
  • the data read by the CPU 2 from the DPRAM is the same as the data of itself, Make sure CPU1 and CPU2 are synchronized.
  • the embodiments of the present application are directed to the deficiencies of the above related technologies, and propose a two-by-two-two-system synchronization method.
  • the method for synchronizing the two-by-two-two system communicates by using the first communication channel between the first subsystem and the second subsystem in the system to determine that the first subsystem and the second subsystem are in
  • the synchronization state realizes the synchronization of the two-by-two-two system, and the implementation is simple, safe, and highly reliable.
  • FIG. 2 is a schematic flow chart of a method for synchronizing a two-by-two-two system according to an embodiment of the present application.
  • the two-way two-two system synchronization method includes:
  • Step 201 The first subsystem sends a synchronization message by using a first communication channel with the second subsystem when determining that the current system is the master system.
  • Step 202 If the confirmation message returned by the second subsystem is obtained through the first communication channel, it is determined that the first subsystem and the second subsystem are in a synchronized state.
  • the method of synchronizing the two-way two-two system provided by the embodiment of the present application can be configured to be executed in any secure computer system to implement synchronization of the system.
  • the first communication channel can adopt a communication bus such as an Ethernet or a serial port.
  • a first communication channel may be set between the first subsystem and the second subsystem, so that when the first subsystem determines that it is currently the primary system, the first communication channel between the first subsystem and the second subsystem may be used.
  • a synchronization message is sent to the second subsystem to determine that the second subsystem and the first subsystem are in a synchronized state.
  • the first subsystem and the second subsystem respectively include a main CPU and a slave CPU.
  • the main CPU is the master clock
  • the slave CPUs are slave clocks
  • the slave clock is based on the master clock. . That is, in the first subsystem and the second subsystem, the slave CPUs are all based on the main CPU. Therefore, when the main CPU of the second subsystem synchronizes with the main CPU of the first subsystem, it can be determined that the two subsystems are synchronized.
  • the main CPU of the first subsystem can send a synchronization message to the main CPU in the second subsystem through the first communication channel to determine the first subsystem and the first subsystem. Whether the second subsystem is in sync.
  • the first subsystem may return to the first subsystem through the first communication channel. Confirm the message. After the first subsystem obtains the confirmation message returned by the second subsystem, it can be determined that the first subsystem and the second subsystem are in a synchronized state.
  • the first subsystem and the second subsystem need to perform a communication handshake to determine whether the clock synchronization between the two subsystems and the task synchronization, that is, the synchronization message may include clock information and tasks. information.
  • determining that the first subsystem and the second subsystem are in a synchronized state may include:
  • the second subsystem is in a clock synchronization and task synchronization state with the first subsystem.
  • the first subsystem may pass the first The communication channel returns an acknowledgement message to the first subsystem. After the first subsystem obtains the confirmation message returned by the second subsystem, it can be determined that the first subsystem and the second subsystem are in a clock synchronization and task synchronization state, so that the task can be started.
  • the clock synchronization may be performed by using a PTP (Precision Time Protocol), a clock synchronization protocol (NTP), or the like.
  • PTP Precision Time Protocol
  • NTP clock synchronization protocol
  • the first subsystem and the second subsystem may perform tasks corresponding to the task information, and acquire the processed data.
  • the end of the task period it is also necessary to determine whether data synchronization between the two subsystems.
  • the processing data can be included in the synchronization message.
  • determining that the first subsystem and the second subsystem are in a synchronized state may include:
  • the first subsystem may go to the first through the first communication channel.
  • the subsystem returns a confirmation message. After the first subsystem obtains the confirmation message returned by the second subsystem, it can be determined that the first subsystem and the second subsystem are in a data synchronization state.
  • first subsystem and the second subsystem when the first subsystem and the second subsystem are in clock synchronization, task synchronization, and data synchronization state, the first subsystem and the second subsystem may be considered to be synchronized; if any condition is not satisfied, the first A subsystem is out of sync with the second subsystem.
  • different task periods may be preset, corresponding to different synchronization identifiers, and at the end of each task period, according to the synchronization status of the first subsystem and the second subsystem, The synchronization identifier corresponding to the task period is updated to analyze the synchronization of the system according to the synchronization identifier.
  • the method may further include:
  • the corresponding synchronization identifier when the first subsystem and the second subsystem are in a synchronized state, the corresponding synchronization identifier is “1”, and when the first subsystem and the second subsystem are in an unsynchronized state, the corresponding synchronization identifier is “ 0”, at the end of a certain task period, if the first subsystem and the second subsystem are in a synchronized state, the synchronization identifier corresponding to the task period may be updated to "1".
  • the first subsystem and the second subsystem may be in a state in which the clock and the task are not synchronized. If the task is continued, the processing data may not be output, or the processing data may be inaccurate. Then, in the embodiment of the present application, whether to perform a task may be determined according to the importance of the task.
  • the method may further include:
  • the first subsystem is controlled to be powered off.
  • the importance level of the task can be set in advance according to the importance of the task.
  • the task can be divided into three important levels: low, medium, and high.
  • the important level corresponding to the less important task is low
  • the important level corresponding to the more important task is medium
  • the important level corresponding to the very important task is high. .
  • the first subsystem and the second subsystem are in a state in which the clock and the task are not synchronized, if the important level of the task is high, the first subsystem is controlled to be powered off. Therefore, when the confirmation message returned by the second subsystem is not obtained, if the importance level of the task corresponding to the task information is high, the first subsystem is controlled to be powered off, and the task is no longer executed; if the task corresponding to the task information is important If the level is low or medium, you can continue with the task.
  • the first subsystem is also required to be synchronized with the master CPU and the slave CPU in the second subsystem. Therefore, in the embodiment of the present application, the first child may be separately A second communication channel is set between the system and the slave CPU and the slave CPU inside the second subsystem to determine that the master CPU and the slave CPU are in a synchronized state through the second communication channel. That is, the method for synchronizing the two-by-two-two system provided by the embodiment of the present application may further include:
  • the main CPU transmits a synchronization message to the slave CPU through the second communication channel.
  • the main CPU may send a synchronization message to the slave CPU through the second communication channel.
  • the confirmation message may be returned to the main CPU through the second communication channel.
  • the main CPU obtains the confirmation message returned from the CPU, it can be determined that the main CPU and the slave CPU are in a synchronized state.
  • the method for synchronizing the two-by-two-two system provided by the embodiment of the present application, when the first subsystem determines that it is currently the main system, sends a synchronization message through the first communication channel with the second subsystem, if the first communication channel is adopted And obtaining an acknowledgement message returned by the second subsystem, determining that the first subsystem and the second subsystem are in a synchronized state.
  • the first subsystem can communicate with the second subsystem through the first communication channel with the second subsystem to determine the first subsystem and the second sub-section when confirming that the current system is the main system.
  • the system is in sync.
  • the process in which the first subsystem confirms that it is currently the main system is described in detail.
  • FIG. 3 is a schematic flow chart of a method for synchronizing a two-by-two-two system according to another embodiment of the present application.
  • the two-way two-system synchronization method may further include:
  • step 301 the first subsystem acquires a cut suggestion and/or switches key location information.
  • the system may provide a recommendation based on factors such as processing speed and fault conditions of the first subsystem and the second subsystem to determine whether to perform the active/standby system. Switch.
  • the first subsystem and the second subsystem may be disposed in the system to share a switching board, and the switching board is provided with a switching key switch.
  • the system can be switched to control by using the switch key switch.
  • a and C are the second communication channels, and B is the first communication channel.
  • the first subsystem or the second subsystem can be forcibly selected as the main system, or the first subsystem and the second subsystem can be automatically cut by automatically placing the switching key in the automatic position.
  • Step 302 Determine, according to the system recommendation and/or the switch key location information, that the first subsystem is the primary system.
  • the cut suggestion may include a score recommendation score of the first subsystem and the second subsystem.
  • the cut-off suggestion score for the failure system is lower than the normal system's cut-off suggestion score.
  • the main system can be determined according to the system recommendation. For example, if the score of the first subsystem is greater than the score of the second subsystem, the first subsystem is determined to be the primary system.
  • the main system can be determined based on the switching key position. For example, if the switch key is located at a location that allows the first subsystem to be the primary system, then the first subsystem is determined to be the primary system.
  • the main system can also be determined based on the system recommendations and the key position.
  • step 302 can be implemented in the following manner:
  • the first subsystem is determined to be the main system.
  • a threshold may be preset. If the first subsystem's cut suggestion score is greater than a preset threshold, and the switch key position allows the first subsystem to be the primary system, the first subsystem may be determined as the primary system.
  • the preset threshold is 90 points. If the first subsystem's cut recommendation score is 95 points, the second subsystem's cut recommendation score is 95 points, and the switch key is located to allow the first subsystem to be the main system. The location of the first subsystem can be determined as the primary system.
  • the score of the first subsystem is not greater than the preset threshold and the switch key is located at the position that allows the first subsystem to be the main system, it can be determined according to the important level of the task to be performed.
  • the first subsystem is determined to be the primary system.
  • the first subsystem can be controlled to be powered off, and the task is no longer executed; if the important level of the task to be executed is low or medium, the first subsystem can be determined.
  • the main system is to continue the task, or according to the classification suggestion of the second subsystem, determine whether to determine the second subsystem as the main system, and so on.
  • Step 303 controlling a first relay pull associated with the first subsystem, wherein the first relay is interlocked with the second relay, and the second relay is a relay associated with the second subsystem.
  • Step 304 after determining that the first relay is successfully closed, determining that the first subsystem is currently the primary system.
  • a first relay associated with the first subsystem and a second relay associated with the second subsystem may be disposed on a switchboard shared by the first subsystem and the second subsystem, and A relay and a second relay are interlocked.
  • the first relay can be controlled to be sucked, and at the same time, the second relay cannot be closed, so that the first subsystem becomes the main system.
  • the first subsystem when it determines that it is currently the main system, it can communicate with the second subsystem through the first communication channel with the second subsystem to determine that the first subsystem and the second subsystem are in Synchronization status.
  • the method for synchronizing the two-by-two-two system can synchronize the state of the standby system with the main system by synchronizing between the primary system and the standby system.
  • the standby system immediately switches to the main system, and has the normal working state before the main system is down, so that the external device communication is not interrupted, the digital output is not interrupted, and the disturbance-free switching is realized.
  • the backup system is faulty, the primary system considers that the standby system is out of synchronization and does not perform the active/standby synchronization function, which saves the running time of the primary system.
  • the first subsystem first obtains the system recommendation and/or switches the key position information, and then determines the first subsystem according to the system recommendation and/or the key position information. Mainly, and then controlling the first relay associated with the first subsystem, after determining that the first relay is successfully closed, it can be determined that the first subsystem is currently the main system, and then the first subsystem in the system is utilized. And a first communication channel between the second subsystem, sending a synchronization message and obtaining an acknowledgement message to determine that the first subsystem and the second subsystem are in a synchronized state.
  • the embodiment of the present application also proposes a computer device.
  • FIG. 5 is a schematic structural diagram of a computer device according to an embodiment of the present application.
  • the computer device includes a memory 41, a processor 42, and a computer program stored on the memory 41 and executable on the processor 42.
  • the processor 42 implements the two-by-two-two-system synchronization method provided in the above embodiments when the program is executed.
  • the computer device further includes:
  • Communication interface 43 is used for communication between memory 41 and processor 42.
  • the memory 41 is for storing a computer program executable on the processor 42.
  • the memory 41 may include a high speed RAM memory and may also include a non-volatile memory such as at least one disk memory.
  • the processor 42 is configured to implement the two-by-two-two-system synchronization method described in the foregoing embodiments when the program is executed.
  • the bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus.
  • ISA Industry Standard Architecture
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • the bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in FIG. 5, but it does not mean that there is only one bus or one type of bus.
  • the memory 41, the processor 42 and the communication interface 43 are integrated and implemented on one chip, the memory 41, the processor 42 and the communication interface 43 can complete communication with each other through the internal interface.
  • the processor 42 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application. .
  • CPU central processing unit
  • ASIC application specific integrated circuit
  • the embodiment of the present application further provides a computer readable storage medium, where the computer program is stored, and when the program is executed by the processor, the method for synchronizing the two-pass two-two system as described in the foregoing embodiment is implemented. .
  • the embodiment of the present application further provides a computer program product, when the instructions in the computer program product are executed by the processor, performing a two-by-two-two system synchronization method as shown in the foregoing embodiment. .
  • portions of the application can be implemented in hardware, software, firmware, or a combination thereof.
  • multiple steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution device.
  • a suitable instruction execution device For example, if implemented in hardware, as in another embodiment, it can be implemented by any one or combination of the following techniques well known in the art: having logic gates for implementing logic functions on data signals. Discrete logic circuits, application specific integrated circuits with suitable combinational logic gates, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.
  • each functional unit in each embodiment of the present application may be integrated into one first processing module, or each unit may exist physically separately, or two or more units may be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or in the form of software functional modules.
  • the integrated modules, if implemented in the form of software functional modules and sold or used as stand-alone products, may also be stored in a computer readable storage medium.
  • the above mentioned storage medium may be a read only memory, a magnetic disk or an optical disk or the like. While the embodiments of the present application have been shown and described above, it is understood that the above-described embodiments are illustrative and are not to be construed as limiting the scope of the present application. The embodiments are subject to variations, modifications, substitutions and variations.

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Abstract

本申请提出一种二乘二取二系统同步方法及计算机设备，其中，所述系统中包含第一子系统和第二子系统，且所述第一子系统与所述第二子系统的性能相同，该方法包括：第一子系统在确定自身当前为主系时，通过与所述第二子系统间的第一通信通道发送同步消息；若通过所述第一通信通道，获取到所述第二子系统返回的确认消息，则确定所述第一子系统与所述第二子系统处于同步状态。

Description

二乘二取二系统同步方法及计算机设备
相关申请的交叉引用
本申请要求比亚迪股份有限公司于2017年7月10日提交的、发明名称为“二乘二取二系统同步方法及计算机设备”的、中国专利申请号“201710557070.0”的优先权。
技术领域
本申请涉及电子信息技术领域，尤其涉及一种二乘二取二系统同步方法及计算机设备。
背景技术
随着电子信息技术的发展，在安全控制领域，安全计算机系统被广泛应用，以实现数据安全、可靠的传输和处理。常见的安全计算机系统架构包括二取二、三取二、二乘二取二等，其中，二乘二取二系统因其具有较好的安全控制性能而得到了广泛应用。而双系之间的同步作为二乘二取二系统的核心因素，对于二乘二取二系统具有重要的意义。
发明内容
本申请旨在至少在一定程度上解决相关技术中的技术问题之一。
为此，本申请的第一个目的在于提出一种二乘二取二系统同步方法，通过利用系统中的第一子系统和第二子系统间的第一通信通道进行通信，实现了二乘二取二系统的同步，实现方式简单、安全，可靠性高。
本申请的第二个目的在于提出一种计算机设备。
本申请的第三个目的在于提出一种计算机可读存储介质。
为达上述目的，本申请第一方面实施例提出了一种二乘二取二系统同步方法，所述系统中包含第一子系统和第二子系统，且所述第一子系统与所述第二子系统的性能相同，所述方法包括：第一子系统在确定自身当前为主系时，通过与所述第二子系统间的第一通信通道发送同步消息；若通过所述第一通信通道，获取到所述第二子系统返回的确认消息，则确定所述第一子系统与所述第二子系统处于同步状态。
在第一方面的一种可能的实现形式中，所述同步消息中包含时钟信息与任务信息；所述确定所述第一子系统与所述第二子系统处于同步状态，包括：确定所述第二子系统与所述第一子系统处于时钟同步和任务同步状态。
在第一方面的另一种可能的实现形式中，所述同步消息中包含处理数据；所述确定所述第一子系统与所述第二子系统处于同步状态，包括：确定所述第二子系统与所述第一子系统 处于数据同步状态。
在第一方面的另一种可能的实现形式中，所述确定所述第二子系统与所述第一子系统处于数据同步状态之后，还包括：更新所述第一子系统中的同步标识。
在第一方面的另一种可能的实现形式中，所述通过与所述第二子系统间的第一通信通道发送同步消息之后，还包括：若未获取到所述第二子系统返回的确认消息，则确定所述任务信息对应的任务的重要等级；在确定所述任务信息对应的任务的重要等级到达预设条件时，控制所述第一子系统下电。
在第一方面的另一种可能的实现形式中，所述第一子系统在确定自身当前为主系之前，还包括：所述第一子系统获取切系建议和/或切换钥匙位置信息；根据所述切系建议和/或切换钥匙位置信息，确定第一子系统为主系；控制与所述第一子系统关联的第一继电器吸合，其中，所述第一继电器与第二继电器互锁，所述第二继电器为与所述第二子系统关联的继电器；在确定所述第一继电器成功闭合后，确定所述第一子系统当前为主系。
在第一方面的另一种可能的实现形式中，所述根据所述切系建议和切换钥匙位置信息，确定第一子系统为主系，包括：在确定所述切系建议得分大于阈值、且所述切换钥匙位置允许所述第一子系统为主系时，确定第一子系统为主系。
在第一方面的另一种可能的实现形式中，所述第一子系统及所述第二子系统中分别包括主CPU和从CPU；所述第一子系统中的主CPU通过所述第一通信通道，向所述第二子系统中的主CPU发送所述同步消息。
在第一方面的另一种可能的实现形式中，所述主CPU通过第二通信通道，向所述从CPU发送同步消息。
本申请实施例的二乘二取二系统同步方法，第一子系统在确定自身当前为主系时，通过与第二子系统间的第一通信通道发送同步消息，若通过第一通信通道，获取到第二子系统返回的确认消息，则确定第一子系统与第二子系统处于同步状态。由此，通过利用系统中的第一子系统和第二子系统间的第一通信通道进行通信，实现了二乘二取二系统的同步，实现方式简单、安全，可靠性高。
为达上述目的，本申请第二方面实施例提出了一种计算机设备，包括：存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述程序时，实现如第一方面所述的二乘二取二系统同步方法。
为达上述目的，本申请第三方面实施例提出了一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现如第一方面所述的二乘二取二系统同步方法。
附图说明
本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1是相关技术的二乘二取二系统的结构示意图；
图2是本申请一个实施例的二乘二取二系统同步方法的流程示意图；
图3是本申请另一个实施例的二乘二取二系统同步方法的流程示意图；
图4是本申请一个实施例的二乘二取二系统的结构示意图；
图5是本申请一个实施例的计算机设备的结构示意图。
具体实施方式
下面详细描述本申请的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本申请，而不能理解为对本申请的限制。
图1是相关技术的二乘二取二系统的结构示意图。如图1所示，相关技术的二乘二取二系统，包括两个二取二系统，分别为主系和备系。每个二取二系统的CPU1和CPU2之间，采用双端口随机存储器(dual-port random access memory，简称DPRAM)的共享内存进行数据传输，以实现同步；主系和备系之间，也采用双端口随机存储器(dual-port random access memory，简称DPRAM)的共享内存进行数据传输，以实现同步。以主系的CPU1与CPU2之间的同步为例，CPU1向DPRAM中写入数据，同时CPU2从DPRAM中读取数据，在CPU2从DPRAM中读取的数据，与其本身的数据相同时，则可以确定CPU1和CPU2同步。
上述方式，由于每个二取二系统的CPU1和CPU2，及主系和备系分别同时对DPRAM进行数据的写入及读取，这就导致了对DPRAM的同一片内存的读写操作复杂度高，且由于需要处理较多的读写冲突，容易出现故障，安全性和可靠性低。
本申请各实施例针对以上相关技术的缺陷，提出一种二乘二取二系统同步方法。
本申请实施例提供的二乘二取二系统同步方法，通过利用系统中的第一子系统和第二子系统间的第一通信通道进行通信，以确定第一子系统和第二子系统处于同步状态，实现了二乘二取二系统的同步，实现方式简单、安全，可靠性高。
下面参考附图描述本申请实施例的二乘二取二系统同步方法及计算机设备。
下面首先对本申请实施例提供的二乘二取二系统同步方法进行说明。
图2是本申请一个实施例的二乘二取二系统同步方法的流程示意图。
如图2所示，该二乘二取二系统同步方法包括：
步骤201，第一子系统在确定自身当前为主系统时，通过与第二子系统间的第一通信通道发送同步消息。
步骤202，若通过第一通信通道，获取到第二子系统返回的确认消息，则确定第一子系统与第二子系统处于同步状态。
具体的，本申请实施例提供的二乘二取二系统同步方法，可以被配置在任意安全计算机 系统中执行，以实现对系统的同步。
其中，第一通信通道，可以采用以太网、串口等通信总线。
具体的，可以在第一子系统与第二子系统间，设置第一通信通道，从而在第一子系统确定自身当前为主系统时，可以通过与第二子系统间的第一通信通道，向第二子系统发送同步消息，以确定第二子系统和第一子系统处于同步状态。
可以理解的是，第一子系统与第二子系统中分别包括主CPU及从CPU，在每个子系统中，主CPU均为主时钟，从CPU均为从时钟，从时钟以主时钟为准。即，第一子系统和第二子系统中，从CPU均以主CPU为准。因此，在第二子系统的主CPU与第一子系统的主CPU同步时，即可确定两个子系统同步。
因此，第一子系统在确定自身当前为主系统时，第一子系统的主CPU可以通过第一通信通道，向第二子系统中的主CPU发送同步消息，以确定第一子系统与第二子系统是否处于同步状态。
具体实现时，第一子系统向第二子系统发送同步消息后，若第二子系统确定同步消息中包括的信息与其自身的信息一致，则可以通过第一通信通道，向第一子系统返回确认消息。第一子系统获取到第二子系统返回的确认消息后，即可确定第一子系统与第二子系统处于同步状态。
可以理解的是，任务周期开始运行时，第一子系统与第二子系统需要进行通信握手，以确定两个子系之间是否时钟同步且任务同步，即，同步消息中可以包括时钟信息与任务信息。
相应的，步骤202中，确定第一子系统与第二子系统处于同步状态，可以包括：
确定第二子系统与第一子系统处于时钟同步和任务同步状态。
具体的，第一子系统向第二子系统发送同步消息后，若第二子系统确定其时钟信息与任务信息与接收到的同步消息中包括的时钟信息与任务信息一致，则可以通过第一通信通道，向第一子系统返回确认消息。第一子系统获取到第二子系统返回的确认消息后，即可确定第一子系统与第二子系统处于时钟同步和任务同步状态，从而可以开始执行任务。
需要说明的是，在本申请实施例中，时钟同步可以采用PTP(Precision Time Protocol)精确时钟同步协议、NTP(Network Time Protocol)时钟同步协议等。
具体的，在确定第一子系统与第二子系统处于时钟同步和任务同步状态后，第一子系统和第二子系统可以执行与任务信息对应的任务，并获取处理后的数据。在本申请实施例中，在任务周期结束后，还需要确定两个子系统之间是否数据同步。
即，同步消息中可以包括处理数据。
相应的，步骤202中，确定第一子系统与第二子系统处于同步状态，可以包括：
确定第二子系统与第一子系统处于数据同步状态。
具体的，第一子系统向第二子系统发送同步消息后，若第二子系统确定其处理数据与接收到的同步消息中包括的处理数据一致，则可以通过第一通信通道，向第一子系统返回确认 消息。第一子系统获取到第二子系统返回的确认消息后，即可确定第一子系统与第二子系统处于数据同步状态。
需要说明的是，在第一子系统与第二子系统处于时钟同步、任务同步及数据同步状态时，可以认为第一子系统与第二子系统同步；若任一条件不满足，则认为第一子系统与第二子系统不同步。
在本申请一种可能的实现形式中，可以预先设置不同的任务周期，对应不同的同步标识，并在每次任务周期结束时，根据第一子系统与第二子系统的同步状态，对该任务周期对应的同步标识进行更新，以便根据同步标识，对系统的同步性进行分析。
即，在确定第二子系统与第一子系统处于数据同步状态之后，还可以包括：
更新第一子系统中的同步标识。
比如，可以预先设置在第一子系统与第二子系统处于同步状态时，对应的同步标识为“1”，第一子系统与第二子系统处于不同步状态时，对应的同步标识为“0”，则某个任务周期结束时，若第一子系统与第二子系统处于同步状态，则可以将该任务周期对应的同步标识更新为“1”。
可以理解的是，第一子系统与第二子系统可能处于时钟与任务不同步状态，若继续执行任务，可能会导致处理数据无法输出，或处理数据不准确等情况。那么，在本申请实施例中，可以根据任务的重要性，确定是否执行任务。
即，在步骤201之后，还可以包括：
若未获取到第二子系统返回的确认消息，则确定任务信息对应的任务的重要等级；
在确定任务信息对应的任务的重要等级到达预设条件时，控制第一子系统下电。
具体的，可以预先根据任务的重要性，设置任务的重要等级。比如，可以预先将任务分为低、中、高三个重要等级，不太重要的任务对应的重要等级为低，比较重要的任务对应的重要等级为中，非常重要的任务对应的重要等级为高。
另外，由于越重要的任务，对任务执行过程的可靠性和执行结果的准确性要求越高，对系统的同步性要求也越高。那么，在本申请实施例中，可以预先设置第一子系统与第二子系统处于时钟与任务不同步状态时，若任务的重要等级为高，则控制第一子系统下电。从而在未获取到第二子系统返回的确认消息时，若任务信息对应的任务的重要等级为高，则控制第一子系统下电，不再执行该任务；若任务信息对应的任务的重要等级为低或中，则可以继续执行该任务。
值得注意的是，在二乘二取二系统中，还要求第一子系统与第二子系统内部的主CPU和从CPU同步，因此，在本申请实施例中，还可以分别在第一子系统和第二子系统内部的主CPU和从CPU之间，设置第二通信通道，以通过第二通信通道，确定主CPU和从CPU处于同步状态。即，本申请实施例提供的二乘二取二系统同步方法，还可以包括：
主CPU通过第二通信通道，向从CPU发送同步消息。
具体的，主CPU可以通过第二通信通道，向从CPU发送同步消息。若从CPU接收到同步消息后，确定同步消息中包括的信息与其自身的信息相同，则可以通过第二通信通道，向主CPU返回确认消息。主CPU获取到从CPU返回的确认消息后，即可确定主CPU和从CPU处于同步状态。
需要说明的是，对主CPU和从CPU之间的同步的实现原理及过程，可以参照对第一子系统与第二子系统之间的同步的详细描述，此处不再赘述。
本申请实施例提供的二乘二取二系统同步方法，第一子系统在确定自身当前为主系统时，通过与第二子系统间的第一通信通道发送同步消息，若通过第一通信通道，获取到第二子系统返回的确认消息，则确定第一子系统与第二子系统处于同步状态。由此，通过利用系统中的第一子系统和第二子系统间的第一通信通道进行通信，实现了二乘二取二系统的同步，实现方式简单、安全，可靠性高。
通过上述分析可知，第一子系统可以在确认自身当前为主系统时，通过与第二子系统间的第一通信通道，与第二子系统进行通信，以确定第一子系统与第二子系统处于同步状态。下面结合图3，对本申请实施例提供的二乘二取二系统同步方法中，第一子系统确认自身当前为主系的过程进行详细说明。
图3是本申请另一个实施例的二乘二取二系统同步方法的流程示意图。
如图3所示，该二乘二取二系统同步方法，还可以包括：
步骤301，第一子系统获取切系建议和/或切换钥匙位置信息。
具体的，在每次任务周期结束，完成数据同步后，系统可以根据第一子系统和第二子系统的处理速度、故障情况等因素，给出切系建议，以确定是否进行主备系统的切换。
另外，如图4所示，可以在系统中设置第一子系统和第二子系统共用一个切换板，切换板上设置有切换钥匙开关。通过利用切换钥匙开关，可以对系统进行切系控制。
其中，图4中，A和C为第二通信通道，B为第一通信通道。
具体的，通过切换钥匙开关，可以强制选择第一子系统或第二子系统作为主系统，也可以通过将切换钥匙置于自动位置，以使第一子系统和第二子系统自动进行切系。
步骤302，根据切系建议和/或切换钥匙位置信息，确定第一子系统为主系。
其中，切系建议中，可以包括第一子系统和第二子系统的切系建议得分。通常，故障系的切系建议得分低于正常系的切系建议得分。
具体的，当切换钥匙位于自动位置时，可以根据切系建议，确定主系。比如，若第一子系统的得分大于第二子系统的得分，则将第一子系统确定为主系统。
当切换钥匙位于非自动位置时，可以根据切换钥匙位置，确定主系统。比如，若切换钥匙位于允许第一子系统为主系统的位置，则将第一子系统确定为主系统。
另外，也可以根据切系建议及切换钥匙位置，确定主系统。
即，步骤302可以通过以下方式实现：
在确定切系建议得分大于阈值、且切换钥匙位置允许第一子系统为主系时，确定第一子系统为主系。
具体的，可以预先设置一个阈值，若第一子系统的切系建议得分大于预设的阈值，且切换钥匙位置允许第一子系统为主系统，则可以将第一子系统确定为主系统。
比如，假设预设的阈值为90分，若第一子系统的切系建议得分为95分，第二子系统的切系建议得分为95分，而切换钥匙位于允许第一子系统为主系的位置，则可以将第一子系统确定为主系统。
值得注意的是，若第一子系统的切系建议得分不大于预设的阈值，而切换钥匙位于允许第一子系统为主系的位置，则可以结合需要执行的任务的重要等级，确定是否将第一子系统确定为主系统。
比如，若需要执行的任务的重要等级为高，则可以控制第一子系统下电，不再执行该任务；若需要执行的任务的重要等级为低或中，则可以将第一子系统确定为主系统，以继续执行任务，或者根据第二子系统的切系建议得分情况，确定是否将第二子系统确定为主系统，等等。
步骤303，控制与第一子系统关联的第一继电器吸合，其中，第一继电器与第二继电器互锁，第二继电器为与第二子系统关联的继电器。
步骤304，在确定第一继电器成功闭合后，确定第一子系统当前为主系统。
具体的，如图4所示，可以在第一子系统和第二子系统共用的切换板上设置与第一子系统关联的第一继电器和与第二子系统关联的第二继电器，而第一继电器和第二继电器互锁。
将第一子系统确定为主系统后，可以控制第一继电器吸合，同时，第二继电器无法吸合，从而使第一子系统成为主系统。
通过利用互锁继电器，可以实现系统中仅一个主系统，防止双系统同时为主系统而导致的冲突，且无需增加额外的通信机制和双主统预防逻辑，实现方式简单，成本低。
具体的，第一子系统在确定自身当前为主系统时，即可通过与第二子系统间的第一通信通道与第二子系统进行通信，以确定第一子系统与第二子系统处于同步状态。
本申请实施例提供的二乘二取二系统同步方法，通过主系统与备系统之间的同步，可以使备系统的状态与主系统一致。当主系统故障时，备系统立即切换为主系统，并具备主系宕机前的正常工作状态，使外部设备通信不中断，数字输出不中断，实现了无扰切换。当备系故障时，主系统认为备系统不同步，不执行主备同步功能，节省了主系统运行时间。
本申请实施例提供的二乘二取二系统同步方法，首先第一子系统获取切系建议和/或切换钥匙位置信息，然后根据切系建议和/或切换钥匙位置信息，确定第一子系统为主系，再控制与第一子系统关联的第一继电器吸合，在确定第一继电器成功闭合后，即可确定第一子系统当前为主系，进而通过利用系统中的第一子系统和第二子系统间的第一通信通道，发送同步消息及获取确认消息，以确定第一子系统和第二子系统处于同步状态。通过利用系统中 的第一子系统和第二子系统间的第一通信通道进行通信，实现了二乘二取二系统的同步，实现方式简单、安全，可靠性高。
为达上述目的，本申请实施例还提出了一种计算机设备。
图5是本申请一个实施例的计算机设备的结构示意图。
如图5所示，该计算机设备包括：存储器41、处理器42及存储在存储器41上并可在处理器42上运行的计算机程序。
处理器42执行所述程序时实现上述实施例中提供的二乘二取二系统同步方法。
进一步地，计算机设备还包括：
通信接口43，用于存储器41和处理器42之间的通信。
存储器41，用于存放可在处理器42上运行的计算机程序。
存储器41可能包含高速RAM存储器，也可能还包括非易失性存储器(non-volatile memory)，例如至少一个磁盘存储器。
处理器42，用于执行所述程序时实现上述实施例所述的二乘二取二系统同步方法。
如果存储器41、处理器42和通信接口43独立实现，则通信接口43、存储器41和处理器42可以通过总线相互连接并完成相互间的通信。所述总线可以是工业标准体系结构(Industry Standard Architecture，简称ISA)总线、外部设备互连(Peripheral Component Interconnect，简称PCI)总线或扩展工业标准体系结构(Extended Industry Standard Architecture，简称EISA)总线等。所述总线可以分为地址总线、数据总线、控制总线等。为便于表示，图5中仅以一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
可选地，在具体实现时，如果存储器41、处理器42及通信接口43，集成在一块芯片上实现，则存储器41、处理器42及通信接口43可以通过内部接口完成相互间的通信。
处理器42可以是一个中央处理器(Central Processing Unit，简称CPU)，或者是特定集成电路(Application Specific Integrated Circuit，简称ASIC)，或者是被配置成实施本申请实施例的一个或多个集成电路。
为达上述目的，本申请实施例还提出了一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现如上述实施例所述的二乘二取二系统同步方法。
为达上述目的，本申请实施例还提出了一种计算机程序产品，当所述计算机程序产品中的指令由处理器执行时，执行如上述实施例中所示的二乘二取二系统同步方法。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。
流程图中或在此以其他方式描述的任何过程或方法描述可以被理解为，表示包括一个或更多个用于实现特定逻辑功能或过程的步骤的可执行指令的代码的模块、片段或部分，并且本申请的优选实施方式的范围包括另外的实现，其中可以不按所示出或讨论的顺序，包括根 据所涉及的功能按基本同时的方式或按相反的顺序，来执行功能，这应被本申请的实施例所属技术领域的技术人员所理解。
应当理解，本申请的各部分可以用硬件、软件、固件或它们的组合来实现。在上述实施方式中，多个步骤或方法可以用存储在存储器中且由合适的指令执行装置执行的软件或固件来实现。例如，如果用硬件来实现，和在另一实施方式中一样，可用本领域公知的下列技术中的任一项或他们的组合来实现：具有用于对数据信号实现逻辑功能的逻辑门电路的离散逻辑电路，具有合适的组合逻辑门电路的专用集成电路，可编程门阵列(PGA)，现场可编程门阵列(FPGA)等。
本技术领域的普通技术人员可以理解实现上述实施例方法携带的全部或部分步骤是可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，该程序在执行时，包括方法实施例的步骤之一或其组合。
此外，在本申请各个实施例中的各功能单元可以集成在一个第一处理模块中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。所述集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。
上述提到的存储介质可以是只读存储器，磁盘或光盘等。尽管上面已经示出和描述了本申请的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本申请的限制，本领域的普通技术人员在本申请的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (11)

  1. 一种二乘二取二系统同步方法，所述系统中包含第一子系统和第二子系统，且所述第一子系统与所述第二子系统的性能相同，其特征在于，包括：
    第一子系统在确定自身当前为主系统时，通过与所述第二子系统间的第一通信通道发送同步消息；
    若通过所述第一通信通道，获取到所述第二子系统返回的确认消息，则确定所述第一子系统与所述第二子系统处于同步状态。
  2. 如权利要求1所述的方法，其特征在于，所述同步消息中包含时钟信息与任务信息；
    所述确定所述第一子系统与所述第二子系统处于同步状态，包括：
    确定所述第二子系统与所述第一子系统处于时钟同步和任务同步状态。
  3. 如权利要求2所述的方法，其特征在于，所述同步消息中包含处理数据；
    所述确定所述第一子系统与所述第二子系统处于同步状态，包括：
    确定所述第二子系统与所述第一子系统处于数据同步状态。
  4. 如权利要求3所述的方法，其特征在于，所述确定所述第二子系统与所述第一子系统处于数据同步状态之后，还包括：
    更新所述第一子系统中的同步标识。
  5. 如权利要求2至4中任一项所述的方法，其特征在于，所述通过与所述第二子系统间的第一通信通道发送同步消息之后，还包括：
    若未获取到所述第二子系统返回的确认消息，则确定所述任务信息对应的任务的重要等级；
    在确定所述任务信息对应的任务的重要等级到达预设条件时，控制所述第一子系统下电。
  6. 如权利要求1至5中任一项所述的方法，其特征在于，所述第一子系统在确定自身当前为主系之前，还包括：
    所述第一子系统获取切系建议和/或切换钥匙位置信息；
    根据所述切系建议和/或切换钥匙位置信息，确定第一子系统为主系；
    控制与所述第一子系统关联的第一继电器吸合，其中，所述第一继电器与第二继电器互锁，所述第二继电器为与所述第二子系统关联的继电器；
    在确定所述第一继电器成功闭合后，确定所述第一子系统当前为主系。
  7. 如权利要求6所述的方法，其特征在于，所述根据所述切系建议和切换钥匙位置信 息，确定第一子系统为主系，包括：
    在确定所述切系建议得分大于阈值、且所述切换钥匙位置允许所述第一子系统为主系时，确定第一子系统为主系。
  8. 如权利要求1-7任一所述的方法，其特征在于，所述第一子系统及所述第二子系统中分别包括主CPU和从CPU；
    所述第一子系统中的主CPU通过所述第一通信通道，向所述第二子系统中的主CPU发送所述同步消息。
  9. 如权利要求8所述的方法，其特征在在于，所述主CPU通过第二通信通道，向所述从CPU发送同步消息。
  10. 一种计算机设备，其特征在于，包括：
    存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述程序时，实现如权利要求1-9中任一所述的二乘二取二系统同步方法。
  11. 一种计算机可读存储介质，其上存储有计算机程序，其特征在于，该程序被处理器执行时实现如权利要求1-9中任一所述的二乘二取二系统同步方法。
PCT/CN2018/088242 2017-07-10 2018-05-24 二乘二取二系统同步方法及计算机设备 Ceased WO2019011063A1 (zh)

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