WO2019010957A1 - 像素单元电路及其驱动方法、像素电路和显示装置 - Google Patents

像素单元电路及其驱动方法、像素电路和显示装置 Download PDF

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Publication number
WO2019010957A1
WO2019010957A1 PCT/CN2018/074426 CN2018074426W WO2019010957A1 WO 2019010957 A1 WO2019010957 A1 WO 2019010957A1 CN 2018074426 W CN2018074426 W CN 2018074426W WO 2019010957 A1 WO2019010957 A1 WO 2019010957A1
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WIPO (PCT)
Prior art keywords
light emitting
control module
emitting element
level input
storage capacitor
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PCT/CN2018/074426
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English (en)
French (fr)
Inventor
玄明花
杨盛际
陈小川
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京东方科技集团股份有限公司
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Priority to US16/078,372 priority Critical patent/US20210217365A1/en
Publication of WO2019010957A1 publication Critical patent/WO2019010957A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0469—Details of the physics of pixel operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/064—Adjustment of display parameters for control of overall brightness by time modulation of the brightness of the illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel unit circuit and a driving method thereof, a pixel circuit, and a display device.
  • the luminescence brightness of a OLED is usually driven by a MOS transistor (Metal-Oxide-Semiconductor-Field Effect Transistor).
  • MOS transistor Metal-Oxide-Semiconductor-Field Effect Transistor
  • the current in the threshold zone is controlled. Since the current of the MOS transistor is proportional to its W/L (width to length ratio), in order to realize a small current of the micro display pixel, it is necessary to design the W/L ratio of the driving MOS transistor to be small, such as L driving the MOS transistor.
  • the (length) design is large.
  • the storage capacitor cannot be made large, and the data voltage cannot be stably maintained, thereby causing the brightness of the OLED to be unstable.
  • the subthreshold current of the MOS transistor is sensitive to the gate-source voltage and the threshold voltage, and the peripheral circuit is complicated. Therefore, for some circuit/electronic components (such as conventional silicon-based pixel circuits) that use sub-threshold driving MOS transistors, it is difficult to reduce the area of the driving MOS transistor, which makes it difficult to apply to ultra-high resolution products.
  • the driving current of the OLED is sensitive to the gate-source voltage and the threshold voltage of the driving MOS transistor, and the peripheral circuit is relatively complicated.
  • a main object of the present disclosure is to provide a pixel unit circuit and a driving method thereof, a pixel circuit, and a display device.
  • the present disclosure provides a pixel unit circuit, including: a first control module, a storage capacitor module, a second control module, and a light emitting component; wherein the first end, the second end, and the third end of the first control module are respectively a row gate line, a column gate line, and a first end of the storage capacitor module and a first end of the second control module, wherein the first control module is configured to be controlled under the control of the row gate line Whether the first end of the second control module and the first end of the storage capacitor module are electrically connected to the column gate line; the second end of the storage capacitor module is connected to the high level input end; The second end, the third end, and the fourth end of the second control module are respectively connected to the first end of the light emitting element, the high level input end and the low level input end, and the second control module is used for The first end of the light emitting element is electrically coupled to the high level input or the low level input by a potential of the first end thereof.
  • the second control module includes: a first PMOS transistor, a gate connected to the third end of the first control module and the first end of the storage capacitor module, the first pole and the high power a flat input terminal, a second pole connected to the first end of the light emitting element; and a first NMOS transistor connected to the third end of the first control module and the first end of the storage capacitor module
  • the first pole is coupled to the low level input and the second pole is coupled to the first end of the light emitting element.
  • the second control module includes: a first NMOS transistor, a gate connected to the third end of the first control module and a first end of the storage capacitor module, the first pole and the light emitting component The first end is connected, the second pole is connected to the high level input terminal; and the first PMOS transistor is connected to the third end of the first control module and the first end of the storage capacitor module The first pole is connected to the first end of the light emitting element, and the second pole is connected to the low level input end.
  • the first control module includes: a second NMOS transistor, a gate connected to the row gate line, a first pole and a gate of the first PMOS transistor, and a gate of the first NMOS transistor The pole and the first end of the storage capacitor module are connected, and the second pole is connected to the column gate line.
  • the first control module includes: a second PMOS transistor, a gate connected to the row gate line, a first pole connected to the column gate line, a second pole and the first PMOS transistor The gate, the gate of the first NMOS transistor, and the first end of the storage capacitor module are connected.
  • the first control module is further configured to control a brightness of the light emitting element by controlling a ratio of an opening and closing time of the first PMOS tube in a frame display time; or the first control module It is also used to control the luminance of the light-emitting element by controlling the ratio of the opening and closing times of the first NMOS transistor in one frame display time.
  • the storage capacitor module includes: a storage capacitor, a first end of which is connected to a third end of the first control module and a first end of the second control module, and a second end and a high level The input is connected.
  • the second end of the light emitting element is connected to the low level input end;
  • the light emitting element comprises an organic light emitting diode;
  • the first end of the light emitting element is an anode of the organic light emitting diode,
  • the second end of the light emitting element is the cathode of the organic light emitting diode.
  • the second end of the light emitting element is connected to the high level input end;
  • the light emitting element comprises an organic light emitting diode;
  • the first end of the light emitting element is a cathode of the organic light emitting diode,
  • the second end of the light emitting element is an anode of the organic light emitting diode.
  • the present disclosure also provides a driving method of a pixel unit circuit for driving any of the above pixel unit circuits, the driving method comprising: the first control module controlling the said under the control of the row gate line Whether the first end of the second control module and the first end of the storage capacitor module are electrically connected to the column gate line; the second control module controls the first of the light emitting element under the potential control of the first end thereof The terminal is connected to the high level input terminal or the low level input terminal to cause the light emitting element to emit light or not to emit light.
  • the first control module includes a second NMOS transistor, and the gate is connected to the row gate line, the first pole and the first end of the second control module and the first end of the storage capacitor module Connecting, the second pole is connected to the column gate line; the first control module controls the first end of the second control module and the first part of the storage capacitor module under the control of the row gate line Whether one end is electrically connected to the column gate line, comprising: when the row gate line outputs a high level signal, the second NMOS transistor is turned on, thereby controlling the first end of the second control module And the first end of the storage capacitor module is connected to the column gate line; when the row gate line outputs a low level signal, the second NMOS transistor is disconnected, thereby controlling the second control module The first end and the first end of the storage capacitor module are not connected to the column gate line.
  • the first control module includes a second PMOS transistor, a gate is connected to the row gate line, a first pole is connected to the column gate line, and a second pole is connected to the second control module.
  • the first end is connected to the first end of the storage capacitor module; the first control module controls the first end of the second control module and the first of the storage capacitor module under the control of the row gate line Whether one end is electrically connected to the column gate line, comprising: when the row gate line outputs a low level signal, the second PMOS transistor is turned on, thereby controlling the first end of the second control module And the first end of the storage capacitor module is connected to the column gate line; when the row gate line outputs a high level signal, the second PMOS transistor is disconnected, thereby controlling the second control module The first end and the first end of the storage capacitor module are not connected to the column gate line.
  • the method wherein, when the second control module includes: a first PMOS transistor, a gate is connected to a third end of the first control module and a first end of the storage capacitor module, a first pole is coupled to the high level input terminal, a second pole is coupled to the first end of the light emitting element; and a first NMOS transistor, a gate and a third end of the first control module, and the The first end of the storage capacitor module is connected, the first pole is connected to the low level input end, the second pole is connected to the first end of the light emitting element, and the second control module is controlled at a potential of the first end thereof Connecting the first end of the light emitting element to the high level input end or the low level input end, comprising: when the potential of the first end of the second control module is a high level, the first PMOS tube Disconnected, the first NMOS transistor is turned on to control the first end of the light emitting element to be connected to the low level input terminal; when the potential of the first end of the second control module is
  • the second control module includes: a first NMOS transistor, a gate connected to the third end of the first control module and a first end of the storage capacitor module, the first pole and the light emitting component The first end is connected, the second pole is connected to the high level input terminal; and the first PMOS transistor is connected to the third end of the first control module and the first end of the storage capacitor module a first pole connected to the first end of the light emitting element, a second pole connected to the low level input end, and a second control module controlling the first light emitting element under the potential control of the first end thereof Connecting the first end to the high level input terminal or the low level input terminal, the first PMOS transistor is turned on when the potential of the first node is low, and the first NMOS transistor is turned off, Controlling that the first end of the light emitting element is connected to the low level input end; when the potential of the first node is high level, the first PMOS transistor is turned off, and the first NMOS transistor is turned on, The first end of the light-emitting
  • the method further includes: the first control module controls a brightness of the light emitting element by controlling a ratio of an opening and closing time of the first PMOS tube within a frame display time; or A control module controls the brightness of the light-emitting elements by controlling a ratio of the on and off times of the first NMOS tube during a frame display time.
  • the second end of the light emitting element is connected to the low level input end;
  • the light emitting element comprises: an organic light emitting diode, the first end of the light emitting element is an anode of the organic light emitting diode, a second end of the light emitting element is a cathode of the organic light emitting diode; in a case where the first end of the light emitting element and the low level input end, the light emitting element does not emit light; In the case of one end and the high level input terminal, the light emitting element emits light.
  • the second end of the light emitting element is connected to the high level input end;
  • the light emitting element comprises: an organic light emitting diode, the first end of the light emitting element is a cathode of the organic light emitting diode, a second end of the light emitting element is an anode of the organic light emitting diode; in a case where the first end of the light emitting element and the low level input end, the light emitting element emits light; at the first of the light emitting element In the case of the terminal and the high level input terminal, the light emitting element does not emit light.
  • the present disclosure further provides a pixel circuit disposed on a silicon substrate, including a plurality of row gate lines, a plurality of column gate lines, and a plurality of array of pixel unit circuits arranged in an array;
  • the pixel unit circuits located in the same row are connected to the same row gate line;
  • the pixel unit circuits located in the same column are connected to the same column gate line.
  • the present disclosure also provides a display device including a silicon substrate and a plurality of row gate lines, a plurality of column gate lines disposed on the silicon substrate, and a plurality of arrays of pixel unit circuits arranged in a plurality of arrays ;
  • the pixel unit circuits located in the same row are connected to the same row gate line;
  • the pixel unit circuits located in the same column are connected to the same column gate line.
  • FIG. 1 is a block diagram of a pixel unit circuit of some embodiments of the present disclosure
  • FIG. 2 is a structural diagram of a pixel unit circuit of some embodiments of the present disclosure
  • FIG. 3 is a structural diagram of a pixel unit circuit of some embodiments of the present disclosure.
  • FIG. 4 is a circuit diagram of a pixel unit circuit of some embodiments of the present disclosure.
  • FIG. 5 is a view showing an exemplary operation timing of the pixel unit circuit shown in FIG. 4;
  • FIG. 6 is another exemplary operational timing diagram showing a specific embodiment of the pixel unit circuit shown in FIG. 4;
  • Fig. 7 is still another exemplary operational timing diagram showing a specific embodiment of the pixel unit circuit shown in Fig. 4.
  • a pixel unit circuit including: a first control module, a storage capacitor module, a second control module, and a light emitting element.
  • the first end, the second end, and the third end of the first control module are respectively connected to the row gate line, the column gate line, and the first end of the storage capacitor module and the first end of the second control module.
  • the first control module is configured to control whether the first end of the second control module and the first end of the storage capacitor module are electrically connected to the column gate line under the control of the row gate line .
  • the second end of the storage capacitor module is connected to the high level input end.
  • the second end, the third end, and the fourth end of the second control module are respectively connected to the first end of the light emitting element, the high level input end, and the low level input end, and the second control module
  • a first end of the light emitting element is electrically connected to the high level input or the low level input by a potential of the first end thereof.
  • the light emitting element comprises an organic light emitting diode.
  • the second end of the light emitting element can be connected to the low level input end.
  • the first end of the light emitting element is an anode of the organic light emitting diode
  • the second end of the light emitting element is a cathode of the organic light emitting diode.
  • the second end of the light emitting element can be connected to the high level input.
  • the first end of the light emitting element is a cathode of the organic light emitting diode
  • the second end of the light emitting element is an anode of the organic light emitting diode.
  • connection point of the third end of the first control module, the first end of the storage capacitor module, and the first end of the second control module is referred to as a first a node; a connection point between the first end of the light emitting element and the second end of the second control module is referred to as a second node, and correspondingly, the first control module is referred to as a first node control module, The second control module is referred to as a second node control module.
  • the pixel unit circuit of the embodiment of the present disclosure includes:
  • the first node control module 11 is respectively connected to a row of gate lines SW, a column of gate lines SEL and a first node Node1 for controlling whether the first node Node1 is under the control of the row gate line SW Describe the gate line SEL connection;
  • the storage capacitor module 12 has a first end connected to the first node Node1 and a second end connected to a high level input terminal inputting a high level VDD;
  • the second node control module 13 is respectively connected to the first node Node1, the second node Node2, the high level input end of the input high level VDD, and the low level input end of the input low level VSS, respectively Controlling, by the control of the first node Node1, the second node Node2 to be connected to a high level input terminal of the input high level VDD or a low level input end of the input low level VSS;
  • the light emitting element D1 has a first end connected to the second node Node2 and a second end connected to the low level input end of the input low level VSS.
  • the light emitting element D1 may include an organic light emitting diode; the first end of the light emitting element D1 is an anode of the organic light emitting diode, and the second end of the light emitting element D1 is the organic light emitting diode cathode.
  • the pixel unit circuit of the embodiment of the present disclosure passes through a turn-on time of a PMOS transistor (Positive Channel Metal Oxide Semiconductor) included in the second node control module 13 and the second node control module 13 includes a matching period of an NMOS transistor (Negative channel Metal Oxide Semiconductor) to control the display luminance of the light-emitting element D1.
  • the pixel unit circuit according to the embodiment of the present disclosure controls the potential of the first node Node1 through the first node control module 11, and controls the PMOS tube included in the second node control module 13 to be turned on or the first level through the potential of the first node Node1.
  • the NMOS transistor included in the two-node control module 13 is turned on, thereby controlling the second node Node2 to access the high level VDD such that the light emitting element D1 emits light, or controlling the second node Node2 to access the low level VSS so that the light emitting element D1 does not emit light.
  • the second end of the light emitting element D1 may also be connected to the high level input end of the input high level VDD, and the PMOS tube included in the second node control module 13 may be controlled to be turned on by the potential of the first node Node1 or The NMOS transistor included in the second node control module 13 is turned on, thereby controlling the second node Node2 to access the high level VDD such that the light emitting element D1 does not emit light, or controlling the second node Node2 to access the low level VSS so that the light emitting element D1 emits light.
  • embodiments of the present disclosure do not limit the connection of the second end of the light emitting element to the high level or low level input.
  • the NMOS transistor and the PMOS transistor included in the second node control module 13 are not operated in the saturation region or are turned off, so the dimension L (length) is not required to be designed very much. Large, so that the pixel unit circuit described in the embodiment of the present disclosure can be applied to a high resolution display product.
  • the NMOS tube and the PMOS tube included in the second node control module 13 only function as a switch, and the brightness of the light is controlled by the ratio of the opening and closing times of the NMOS tube or the PMOS tube, and the light-emitting element D1 is displayed within one frame display time.
  • the operating time of the organic light emitting diode OLED (such as the organic light emitting diode OLED) is the light emitting time of the light emitting element D1, and the operating time and average current of the light emitting element D1 can be reduced.
  • the second node control module may include:
  • a first PMOS transistor a gate connected to the first node, a first pole connected to the high level input terminal, and a second pole connected to the second node;
  • the first NMOS transistor has a gate connected to the first node, a first pole connected to the low level input terminal, and a second pole connected to the second node.
  • the light emitting element comprises an organic light emitting diode OLED, and an anode of the organic light emitting diode OLED is connected to the second node Node2.
  • the cathode of the organic light emitting diode OLED is connected to a low level input terminal of an input low level VSS;
  • the second node control module 13 includes:
  • a first PMOS transistor TP1 having a gate connected to the first node Node1, a source connected to the high level input terminal of the input high level VDD, and a drain connected to the second node Node2;
  • the first NMOS transistor TN1 has a gate connected to the first node Node1, a source connected to the low level input of the input low level VSS, and a second pole connected to the second node Node2.
  • the second node control module may include:
  • a first NMOS transistor a gate connected to the first node, a first pole connected to the second node, and a second pole connected to the high level input terminal;
  • the first PMOS transistor has a gate connected to the first node, a first pole connected to the second node, and a second pole connected to the low level input terminal.
  • the light emitting element includes an organic light emitting diode OLED, and an anode of the organic light emitting diode OLED is connected to the second node Node2.
  • the cathode of the organic light emitting diode OLED is connected to a low level input terminal of an input low level VSS;
  • the second node control module 13 includes:
  • a first NMOS transistor TN1 having a gate connected to the first node Node1, a drain connected to the high level input terminal of the input high level VDD, and a source connected to the second node Node2;
  • the first PMOS transistor TP1 has a gate connected to the first node Node1, a drain connected to the low level input terminal of the input low level VSS, and a source connected to the second node Node2.
  • the first node control module may include: a second NMOS transistor, a gate connected to the row gate line, a first pole connected to the first node, and a second pole and the column gate line connection.
  • the first node control module includes a second NMOS transistor, when the row gate line outputs a high level, the second NMOS transistor is turned on, and the column gate line is connected to the first node; When the row gate line outputs a low level, the second NMOS transistor is turned off, and the column gate line is not connected to the first node.
  • the first node control module may include: a second PMOS transistor, a gate connected to the row gate line, a first pole connected to the column gate line, and a second pole and the first node connection.
  • the first node control module includes a second PMOS transistor, when the row gate line outputs a low level, the second PMOS transistor is turned on, and the column gate line is connected to the first node; When the row gate line outputs a high level, the second PMOS transistor is turned off, and the column gate line is not connected to the first node.
  • the storage capacitor module may include: a storage capacitor, the first end is connected to the first node, and the second end is connected to the high level input end.
  • the pixel unit circuit of the present disclosure will be described below by way of a specific embodiment.
  • a specific embodiment of the pixel unit circuit of the present disclosure includes a first node control module 11, a storage capacitor module 12, a second node control module 13, and an organic light emitting diode OLED.
  • the second node control module 13 includes:
  • a first PMOS transistor TP1 having a gate connected to the first node Node1, a source connected to the high level input terminal of the input high level VDD, and a drain connected to the second node Node2;
  • a first NMOS transistor TN1 having a gate connected to the first node Node1, a source connected to a low level input terminal of the input low level VSS, and a drain connected to the second node Node2;
  • the first node control module 11 includes: a second NMOS transistor TN2, a gate connected to the row gate line SW, a source connected to the first node Node1, and a drain connected to the column gate line SEL;
  • the storage capacitor module 12 includes: a storage capacitor Cst, the first end is connected to the first node Node1, and the second end is connected to the high-level input end of the input high level VDD;
  • the anode of the organic light emitting diode OLED is connected to the second node Node2, and the cathode of the organic light emitting diode OLED is connected to the low level input terminal of the input low level VSS.
  • the present disclosure is an exemplary timing diagram of a particular embodiment of a pixel cell circuit as shown in FIG. 5.
  • SW and SEL both output a high level, TN2 is turned on, Node1 reads the high level of the SEL output, TP1 is turned off, TN1 is turned on, the potential of Node2 is low level VSS, and the potential of the anode of the OLED is The potential of the cathode of the OLED is equal, and the OLED does not emit light, that is, the OLED remains in a "dark" state.
  • SW In the third time period T3, SW outputs a high level, SEL outputs a low level, TN2 turns on, Node1 reads the low level of the SEL output, TP1 turns on, TN1 turns off, the potential of Node2 is high, and the anode of the OLED
  • the voltage difference between the cathodes of the OLED is VDD-VSS, and the OLED emits light, that is, the OLED remains in a "bright" state.
  • the timing of the row strobe signal outputted by the row strobe line SW and the column strobe signal output by the column strobe line SEL Timing cooperation controls the potential of the first node Node1, and determines whether to turn on TP1 or TN2 according to the potential of the first node Node1 to determine that the potential of the second node Node2 is VDD or VSS.
  • TP1 is turned on, the OLED is in a "bright” state; when TN1 is turned on, the OLED is in a "dark" state.
  • TP1 and TN1 When TP1 and TN1 are in operation, they are all in saturation zone or closed, which only acts as a switch; and the ratio of time of opening and closing of TP1 and TN1 is used to control the brightness of the light.
  • the actual working time of the OLED in one frame of display time is only the light. Time reduces the operating time and average current of the OLED.
  • the pixel unit circuit of the embodiment of the present disclosure does not need to control the light emission brightness of the silicon-based OLED (organic light-emitting diode) by driving the current of the MOS transistor in the sub-threshold region, and the MOS in the pixel unit circuit according to the embodiment of the present disclosure
  • the tube only functions as a switch, so the size of the MOS tube can be made small, which is advantageous for achieving high resolution, and the average current flowing through the OLED and the brightness of the OLED can be based on the timing of the row strobe signal output by the row strobe line SW.
  • the timings of the column strobe signals of the column gate line SEL are arbitrarily adjusted to match each other.
  • the waveform of the row strobe signal of the SW output can be fixed, and the period of the column strobe signal output by the SEL can be changed to cause the OLED to emit different brightness.
  • the first time period is T1
  • the second time is T2
  • the third time is T3
  • the fourth time is T4
  • the number is T5.
  • the fifth time period is the sixth time period
  • the number T7 is the seventh time period
  • the number T8 is the eighth time period.
  • the waveform of the row strobe signal output by the SEL can be fixed, and the period of the column strobe signal output by the SW can be changed to make the OLED emit different brightness.
  • the first time period is T1
  • the second time is T2
  • the third time is T3
  • the fourth time is T4
  • the number is T5.
  • the fifth time period is the number T6 is the sixth time period
  • the number T7 is the seventh time period
  • the number T8 is the eighth time period
  • the number T9 is the ninth time period
  • the label is T10.
  • the tenth time period When the timing of the row strobe signal output by the SW and the timing of the column strobe signal of the SEL output are as shown in FIG. 7, the OLED is in a "bright" state at T1-T5, and the OLED is in a "dark" state at T6-T10. .
  • the timing of the row strobe signal output by the row strobe line and the timing of the column strobe signal output by the column strobe line may vary according to actual conditions.
  • a driving method of a pixel unit circuit for driving any of the above pixel unit circuits, the driving method comprising: the first control module controlling the said under the control of the row gate line Whether the first node is electrically connected to the column gate line; the second control module controls the first end of the light emitting element to be connected to the high level input end or the low level input end under the control of the first node, so that The light emitting element emits light or does not emit light.
  • the second node control module controls the second node to be connected to the high level input end, the light emitting element emits light; when the second node control module controls the second node and the low level input When the terminals are connected, the light-emitting elements do not emit light.
  • the light emitting element emits light when the potential of the second node is low, and the light emitting element does not emit light when the potential of the second node is high.
  • the light emitting element does not emit light when the potential of the second node is high.
  • the step of controlling, by the first node control module, whether the first node is connected to the column strobe line under the control of the row strobing line comprises:
  • the second NMOS transistor When the row gate line outputs a high level signal, the second NMOS transistor is turned on, thereby controlling the first node and the column gate line connection;
  • the second NMOS transistor When the row gate line outputs a low level signal, the second NMOS transistor is turned off, thereby controlling the first node and the column gate line not to be connected.
  • the step of controlling, by the first node control module, whether the first node is connected to the column strobe line under the control of the row strobing line includes:
  • the second PMOS transistor When the row gate line outputs a low level signal, the second PMOS transistor is turned on, thereby controlling the first node and the column gate line connection;
  • the second PMOS transistor When the row gate line outputs a high level signal, the second PMOS transistor is turned off, thereby controlling the first node and the column gate line not to be connected.
  • the second node control module includes: a first PMOS transistor, the gate is connected to the first node, the first pole is connected to the high level input end, and the second pole is connected to the second node And connecting, the first NMOS transistor, the gate is connected to the first node, the first pole is connected to the low level input end, and when the second pole is connected to the second node, the Under the control of a node, the second node control module controls the second node to connect with the high level input terminal or the low level input terminal, including:
  • the first PMOS transistor When the potential of the first node is a high level, the first PMOS transistor is turned off, and the first NMOS transistor is turned on to control the second node to be connected to the low-level input terminal, so that the second The potential of the node is low, such that the light emitting element does not emit light;
  • the first PMOS transistor When the potential of the first node is a low level, the first PMOS transistor is turned on, and the first NMOS transistor is turned off to control the second node to be connected to the high level input terminal, so that the second The potential of the node is at a high level, so that the light emitting element emits light.
  • the second node control module includes: a first NMOS transistor, a gate is connected to the first node, a first pole is connected to the second node, and a second pole is connected to the high level And a first PMOS transistor, the gate is connected to the first node, the first pole is connected to the second node, and when the second pole is connected to the low-level input, the Under the control of a node, the second node control module controls the second node to connect with the high level input terminal or the low level input terminal, including:
  • the first PMOS transistor When the potential of the first node is low, the first PMOS transistor is turned on, and the first NMOS transistor is turned off to control the second node to be connected to the low level input, so that the second The potential of the node is low, such that the light emitting element does not emit light;
  • the first PMOS transistor When the potential of the first node is high, the first PMOS transistor is turned off, and the first NMOS transistor is turned on to control the second node to be connected to the high-level input terminal, so that the second The potential of the node is at a high level, so that the light emitting element emits light.
  • the pixel circuit of the embodiment of the present disclosure is disposed on a silicon substrate, and includes a plurality of row gate lines, a plurality of column gate lines, and a plurality of arrays of the pixel unit circuits arranged in an array;
  • the pixel unit circuits located in the same row are connected to the same row gate line;
  • the pixel unit circuits located in the same column are connected to the same column gate line.
  • the display device includes a silicon substrate, a plurality of row gate lines disposed on the silicon substrate, a plurality of column gate lines, and a plurality of arrays of the pixel unit circuits arranged in an array;
  • the pixel unit circuits located in the same row are connected to the same row gate line;
  • the pixel unit circuits located in the same column are connected to the same column gate line.

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Abstract

一种像素单元电路及其驱动方法、像素电路和显示装置。像素单元电路包括：第一控制模块(11)，存储电容模块(12)、第二控制模块(13)和发光元件(D1)；其中，第一控制模块(11)的第一端、第二端以及第三端分别与行选通线(SW)、列选通线(SEL)、以及存储电容模块(12)的第一端和第二控制模块(13)的第一端连接，第一控制模块(11)用于控制第二控制模块(13)的第一端和存储电容模块(12)的第一端是否与列选通线(SEL)电连接；存储电容模块(12)的第二端与高电平输入端(VDD)连接；第二控制模块(13)的第二端、第三端以及第四端分别与发光元件(D1)的第一端、高电平输入端(VDD)以及低电平输入端(VSS)连接，第二控制模块(13)用于控制发光元件(D1)的第一端与高电平输入端(VDD)或低电平输入端(VSS)电连接。

Description

像素单元电路及其驱动方法、像素电路和显示装置
相关申请的交叉引用
本申请要求于2017年7月12日提交中国专利局、申请号为：201710564519.6的优先权，其全部内容据此通过引用并入本申请。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素单元电路及其驱动方法、像素电路和显示装置。
背景技术
硅基OLED(Organic Light-Emitting Diode，有机发光二极管)的发光亮度通常通过驱动MOS管(金属(Metal)—氧化物(Oxide)—半导体(Semiconductor)—场效应晶体管(Field Effect Transistor))的亚阈值区的电流来控制。由于MOS管的电流与它的W/L(宽长比)成正比，为了实现微显示像素的小电流，需要把驱动MOS管的W/L的比值设计很小，如将驱动MOS管的L(长度)设计很大。这样，难以将硅基OLED应用到高分辨率的显示产品，存储电容无法做大，数据电压无法稳定保持，从而导致OLED的亮度不稳定。并且，MOS管的亚阈值电流对栅源电压和阈值电压很敏感，外围电路复杂。因此，对于一些采用工作在亚阈值的驱动MOS管的电路/电子元件(如传统的硅基像素电路)，也很难减少驱动MOS管的面积，由此难以应用到超高分辨率的产品上，并且OLED的驱动电流对驱动MOS管的栅源电压和阈值电压敏感，外围电路相对复杂。
发明内容
本公开的主要目的在于提供一种像素单元电路及其驱动方法、像素电路和显示装置。
本公开提供了一种像素单元电路，包括：第一控制模块，存储电容模块、第二控制模块和发光元件；其中所述第一控制模块的第一端、第二端以及第 三端分别与行选通线、列选通线、以及所述存储电容模块的第一端和第二控制模块的第一端连接，所述第一控制模块用于在所述行选通线的控制下控制所述第二控制模块的第一端和所述存储电容模块的第一端是否与所述列选通线电连接；所述存储电容模块的第二端与高电平输入端连接；所述第二控制模块的第二端、第三端以及第四端分别与所述发光元件的第一端、所述高电平输入端以及低电平输入端连接，所述第二控制模块用于通过其第一端的电位来控制所述发光元件的第一端与所述高电平输入端或所述低电平输入端电连接。
可选地，所述第二控制模块包括：第一PMOS管，栅极与所述第一控制模块的第三端和所述存储电容模块的第一端连接，第一极与所述高电平输入端连接，第二极与所述发光元件的第一端连接；以及，第一NMOS管，栅极与所述第一控制模块的第三端和所述存储电容模块的第一端连接，第一极与所述低电平输入端连接，第二极与所述发光元件的第一端连接。
可选地，所述第二控制模块包括：第一NMOS管，栅极与所述第一控制模块的第三端和所述存储电容模块的第一端连接，第一极与所述发光元件的第一端连接，第二极与所述高电平输入端连接；以及，第一PMOS管，栅极与所述第一控制模块的第三端和所述存储电容模块的第一端连接，第一极与所述发光元件的第一端连接，第二极与所述低电平输入端连接。
可选地，所述第一控制模块包括：第二NMOS管，栅极与所述行选通线连接，第一极与所述第一PMOS管的栅极、所述第一NMOS管的栅极以及所述存储电容模块的第一端连接，第二极与所述列选通线连接。
可选地，所述第一控制模块包括：第二PMOS管，栅极与所述行选通线连接，第一极与所述列选通线连接，第二极与所述第一PMOS管的栅极、所述第一NMOS管的栅极以及所述存储电容模块的第一端连接。
可选地，所述第一控制模块还用于通过控制所述第一PMOS管在一帧显示时间内开启和关闭时间的比例来控制所述发光元件的发光亮度；或者所述第一控制模块还用于通过控制所述第一NMOS管在一帧显示时间内开启和关闭时间的比例来控制所述发光元件的发光亮度。
可选地，所述存储电容模块包括：存储电容，其第一端与所述第一控制 模块的第三端和所述第二控制模块的第一端连接，其第二端与高电平输入端连接。
可选地，所述发光元件的第二端与所述低电平输入端连接；所述发光元件包括有机发光二极管；所述发光元件的第一端为所述有机发光二极管的阳极，所述发光元件的第二端为所述有机发光二极管的阴极。
可选地，所述发光元件的第二端与所述高电平输入端连接；所述发光元件包括有机发光二极管；所述发光元件的第一端为所述有机发光二极管的阴极，所述发光元件的第二端为所述有机发光二极管的阳极。
本公开还提供了一种像素单元电路的驱动方法，用于驱动任一上述的像素单元电路，所述驱动方法包括：所述第一控制模块在所述行选通线的控制下控制所述第二控制模块的第一端和所述存储电容模块的第一端是否与所述列选通线电连接；第二控制模块在其第一端的电位控制下控制所述发光元件的第一端与高电平输入端或低电平输入端连接，以使得所述发光元件发光或不发光。
可选地，所述第一控制模块包括第二NMOS管，栅极与所述行选通线连接，第一极与所述第二控制模块的第一端和所述存储电容模块的第一端连接，第二极与所述列选通线连接；所述第一控制模块在所述行选通线的控制下控制所述第二控制模块的第一端和所述存储电容模块的第一端是否与所述列选通线电连接，包括：当所述行选通线输出高电平信号时，所述第二NMOS管导通，从而控制所述第二控制模块的第一端和所述存储电容模块的第一端与所述列选通线连接；当所述行选通线输出低电平信号时，所述第二NMOS管断开，从而控制所述第二控制模块的第一端和所述存储电容模块的第一端与所述列选通线不连接。
可选地，所述第一控制模块包括第二PMOS管，栅极与所述行选通线连接，第一极与所述列选通线连接，第二极与所述第二控制模块的第一端和所述存储电容模块的第一端连接；所述第一控制模块在所述行选通线的控制下控制所述第二控制模块的第一端和所述存储电容模块的第一端是否与所述列选通线电连接，包括：当所述行选通线输出低电平信号时，所述第二PMOS 管导通，从而控制所述第二控制模块的第一端和所述存储电容模块的第一端与所述列选通线连接；当所述行选通线输出高电平信号时，所述第二PMOS管断开，从而控制所述第二控制模块的第一端和所述存储电容模块的第一端与所述列选通线不连接。
可选地，所述的方法，其中，当所述第二控制模块包括：第一PMOS管，栅极与所述第一控制模块的第三端和所述存储电容模块的第一端连接，第一极与所述高电平输入端连接，第二极与所述发光元件的第一端连接；以及，第一NMOS管，栅极与所述第一控制模块的第三端和所述存储电容模块的第一端连接，第一极与所述低电平输入端连接，第二极与所述发光元件的第一端连接；所述第二控制模块在其第一端的电位控制下控制所述发光元件的第一端与高电平输入端或低电平输入端连接，包括：当所述第二控制模块的第一端的电位为高电平时，所述第一PMOS管断开，所述第一NMOS管导通，以控制所述发光元件的第一端与所述低电平输入端连接；当所述第二控制模块的第一端的电位为低电平时，所述第一PMOS管导通，所述第一NMOS管断开，以控制所述发光元件的第一端与所述高电平输入端连接。
可选地，所述第二控制模块包括：第一NMOS管，栅极与所述第一控制模块的第三端和所述存储电容模块的第一端连接，第一极与所述发光元件的第一端连接，第二极与所述高电平输入端连接；以及，第一PMOS管，栅极与所述第一控制模块的第三端和所述存储电容模块的第一端连接，第一极与所述发光元件的第一端连接，第二极与所述低电平输入端连接；所述第二控制模块在其第一端的电位控制下控制所述发光元件的第一端与高电平输入端或低电平输入端连接，包括：当所述第一节点的电位为低电平时，所述第一PMOS管导通，所述第一NMOS管断开，以控制所述发光元件的第一端与所述低电平输入端连接；当所述第一节点的电位为高电平时，所述第一PMOS管断开，所述第一NMOS管导通，以控制所述发光元件的第一端与所述高电平输入端连接。
可选地，所述方法还包括：所述第一控制模块通过控制所述第一PMOS管在一帧显示时间内开启和关闭时间的比例来控制所述发光元件的发光亮度；或者所述第一控制模块通过控制所述第一NMOS管在一帧显示时间内开启和 关闭时间的比例来控制所述发光元件的发光亮度。
可选地，所述发光元件的第二端与所述低电平输入端连接；所述发光元件包括：有机发光二极管，所述发光元件的第一端为所述有机发光二极管的阳极，所述发光元件的第二端为所述有机发光二极管的阴极；在所述发光元件的第一端与所述低电平输入端的情况下，所述发光元件不发光；在所述发光元件的第一端与所述高电平输入端的情况下，所述发光元件发光。
可选地，所述发光元件的第二端与所述高电平输入端连接；所述发光元件包括：有机发光二极管，所述发光元件的第一端为所述有机发光二极管的阴极，所述发光元件的第二端为所述有机发光二极管的阳极；在所述发光元件的第一端与所述低电平输入端的情况下，所述发光元件发光；在所述发光元件的第一端与所述高电平输入端的情况下，所述发光元件不发光。
本公开还提供了一种像素电路，设置于硅基板上，包括多条行选通线、多条列选通线，以及多个阵列排布的任一上述的像素单元电路；
位于同一行的所述像素单元电路与同一条行选通线连接；
位于同一列的所述像素单元电路与同一条列选通线连接。
本公开还提供了一种显示装置，包括硅基板和设置于所述硅基板上的多条行选通线、多条列选通线，以及多个阵列排布的任一上述的像素单元电路；
位于同一行的所述像素单元电路与同一条行选通线连接；
位于同一列的所述像素单元电路与同一条列选通线连接。
附图说明
图1是本公开一些实施例的像素单元电路的结构图；
图2是本公开一些实施例的像素单元电路的结构图；
图3是本公开一些实施例的像素单元电路的结构图；
图4是本公开一些实施例的像素单元电路的电路图；
图5是示出如图4所示的像素单元电路的一示例性工作时序图；
图6是示出如图4所示的像素单元电路的具体实施例的另一示例性工作时序图；
图7是示出如图4所示的像素单元电路的具体实施例的又一示例性工作 时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
在一些实施例中，提供了一种像素单元电路，包括：第一控制模块，存储电容模块、第二控制模块和发光元件。所述第一控制模块的第一端、第二端以及第三端分别与行选通线、列选通线、以及所述存储电容模块的第一端和第二控制模块的第一端连接，所述第一控制模块用于在所述行选通线的控制下控制所述第二控制模块的第一端和所述存储电容模块的第一端是否与所述列选通线电连接。所述存储电容模块的第二端与高电平输入端连接。所述第二控制模块的第二端、第三端以及第四端分别与所述发光元件的第一端、所述高电平输入端以及低电平输入端连接，所述第二控制模块用于通过其第一端的电位来控制所述发光元件的第一端与所述高电平输入端或所述低电平输入端电连接。
可选地，发光元件包括有机发光二极管。
可选地，所述发光元件的第二端可以与低电平输入端连接。具体地，发光元件的第一端为有机发光二极管的阳极，发光元件的第二端为有机发光二极管的阴极。
可选地，所述发光元件的第二端可以与高电平输入端连接。具体地，发光元件的第一端为有机发光二极管的阴极，发光元件的第二端为有机发光二极管的阳极。
为了方便描述和理解，在下面的实施例中，将所述第一控制模块的第三端、所述存储电容模块的第一端以及第二控制模块的第一端的连接点称为第一节点；将所述发光元件的第一端与所述第二控制模块的第二端之间的某一连接点称为第二节点，相应地，第一控制模块称为第一节点控制模块，第二控制模块称为第二节点控制模块。
如图1所示，本公开实施例所述的像素单元电路包括：
第一节点控制模块11，分别与一行选通线SW、一列选通线SEL和第一节点Node1连接，用于在所述行选通线SW的控制下控制所述第一节点Node1是否与所述列选通线SEL连接；
存储电容模块12，第一端与所述第一节点Node1连接，第二端与输入高电平VDD的高电平输入端连接；
第二节点控制模块13，分别与所述第一节点Node1、第二节点Node2、所述输入高电平VDD的高电平输入端和输入低电平VSS的低电平输入端连接，用于在所述第一节点Node1的控制下，控制所述第二节点Node2与所述输入高电平VDD的高电平输入端或所述输入低电平VSS的低电平输入端连接；以及，
发光元件D1，第一端与所述第二节点Node2连接，第二端与所述输入低电平VSS的低电平输入端连接。
在实际操作时，所述发光元件D1可以包括有机发光二极管；所述发光元件D1的第一端为所述有机发光二极管的阳极，所述发光元件D1的第二端为所述有机发光二极管的阴极。
在本公开实施例所述的像素单元电路通过第二节点控制模块13包括的PMOS管(Positive channel Metal Oxide Semiconductor，P沟道金属氧化物半导体场效应晶体管)的开启时间和该第二节点控制模块13包括的NMOS管(Negative channel Metal Oxide Semiconductor，N沟道金属氧化物半导体场效应晶体管)的开启时间的配合来控制发光元件D1的显示亮度。本公开实施例所述的像素单元电路通过第一节点控制模块11来控制第一节点Node1的电位，通过第一节点Node1的电位控制该第二节点控制模块13包括的PMOS管导通或者该第二节点控制模块13包括的NMOS管导通，从而控制第二节点Node2接入高电平VDD使得发光元件D1发光，或控制第二节点Node2接入低电平VSS使得发光元件D1不发光。
当然，发光元件D1的第二端也可以与所述输入高电平VDD的高电平输入端连接，通过第一节点Node1的电位可以控制该第二节点控制模块13包括的PMOS管导通或者该第二节点控制模块13包括的NMOS管导通，从而控 制第二节点Node2接入高电平VDD使得发光元件D1不发光，或控制第二节点Node2接入低电平VSS使得发光元件D1发光。应理解，本公开实施例对于发光元件的第二端与高电平还是低电平输入端连接不做限制。
在本公开实施例所述的像素单元电路的技术方案中，第二节点控制模块13包括的NMOS管和PMOS管不是工作于饱和区就是关断，因此不需要将尺寸L(长度)设计的很大，从而使得本公开实施例所述的像素单元电路可以应用于高分辨率显示产品中。并且，第二节点控制模块13包括的NMOS管和PMOS管只起到开关的作用，通过该NMOS管或PMOS管开启和关闭时间的比例来控制发光的亮度，一帧显示时间内，发光元件D1(如有机发光二极管OLED)的工作时间即为发光元件D1的发光时间，能够减少了发光元件D1的工作时间和平均电流。
根据一种具体实施方式，所述第二节点控制模块可以包括：
第一PMOS管，栅极与所述第一节点连接，第一极与所述高电平输入端连接，第二极与所述第二节点连接；以及，
第一NMOS管，栅极与所述第一节点连接，第一极与所述低电平输入端连接，第二极与所述第二节点连接。
如图2所示，在图1所示的像素单元电路的实施例的基础上，所述发光元件包括有机发光二极管OLED，所述有机发光二极管OLED的阳极与所述第二节点Node2连接，所述有机发光二极管OLED的阴极与输入低电平VSS的低电平输入端连接；
所述第二节点控制模块13包括：
第一PMOS管TP1，栅极与所述第一节点Node1连接，源极与所述输入高电平VDD的高电平输入端连接，漏极与所述第二节点Node2连接；以及，
第一NMOS管TN1，栅极与所述第一节点Node1连接，源极与所述输入低电平VSS的低电平输入端连接，第二极与所述第二节点Node2连接。
在实际操作时，当所述第一节点Node1的电位为低电平时，TP1打开，TN1关闭，所述第二节点Node2的电位为高电平VDD；当所述第一节点Node1的电位为高电平时，TP1关闭，TN2打开，所述第二节点Node2的电位为低电平VSS。
根据另一种具体实施方式，所述第二节点控制模块可以包括：
第一NMOS管，栅极与所述第一节点连接，第一极与所述第二节点连接，第二极与所述高电平输入端连接；以及，
第一PMOS管，栅极与所述第一节点连接，第一极与所述第二节点连接，第二极与所述低电平输入端连接。
如图3所示，在图1所示的像素单元电路的实施例的基础上，所述发光元件包括有机发光二极管OLED，所述有机发光二极管OLED的阳极与所述第二节点Node2连接，所述有机发光二极管OLED的阴极与输入低电平VSS的低电平输入端连接；
所述第二节点控制模块13包括：
第一NMOS管TN1，栅极与所述第一节点Node1连接，漏极与所述输入高电平VDD的高电平输入端连接，源极与所述第二节点Node2连接；以及，
第一PMOS管TP1，栅极与所述第一节点Node1连接，漏极与所述输入低电平VSS的低电平输入端连接，源极与所述第二节点Node2连接。
在实际操作时，当所述第一节点Node1的电位为低电平时，TP1打开，TN1关闭，所述第二节点Node2的电位为低电平VSS；当所述第一节点Node1的电位为高电平时，TP1关闭，TN2打开，所述第二节点Node2的电位为高电平VDD。
具体的，所述第一节点控制模块可以包括：第二NMOS管，栅极与所述行选通线连接，第一极与所述第一节点连接，第二极与所述列选通线连接。当所述第一节点控制模块包括第二NMOS管时，当所述行选通线输出高电平时，该第二NMOS管打开，所述列选通线与所述第一节点连接；当所述行选通线输出低电平时，该第二NMOS管关闭，所述列选通线与所述第一节点不连接。
具体的，所述第一节点控制模块可以包括：第二PMOS管，栅极与所述行选通线连接，第一极与所述列选通线连接，第二极与所述第一节点连接。当所述第一节点控制模块包括第二PMOS管时，当所述行选通线输出低电平时，该第二PMOS管打开，所述列选通线与所述第一节点连接；当所述行选通线输出高电平时，该第二PMOS管关闭，所述列选通线与所述第一节点不 连接。
具体的，所述存储电容模块可以包括：存储电容，第一端与所述第一节点连接，第二端与高电平输入端连接。
下面通过一具体实施例来说明本公开所述的像素单元电路。
如图4所示，本公开所述的像素单元电路的一具体实施例包括第一节点控制模块11、存储电容模块12、第二节点控制模块13以及有机发光二极管OLED。
所述第二节点控制模块13包括：
第一PMOS管TP1，栅极与第一节点Node1连接，源极与输入高电平VDD的高电平输入端连接，漏极与第二节点Node2连接；以及，
第一NMOS管TN1，栅极与所述第一节点Node1连接，源极与输入低电平VSS的低电平输入端连接，漏极与所述第二节点Node2连接；
所述第一节点控制模块11包括：第二NMOS管TN2，栅极与行选通线SW连接，源极与所述第一节点Node1连接，漏极与列选通线SEL连接；
所述存储电容模块12包括：存储电容Cst，第一端与所述第一节点Node1连接，第二端与所述输入高电平VDD的高电平输入端连接；
所述有机发光二极管OLED的阳极与所述第二节点Node2连接，所述有机发光二极管OLED的阴极与所述输入低电平VSS的低电平输入端连接。
如图5所示，本公开如图4所示的像素单元电路的具体实施例在工作时的示例性时序图。
在第一时间段T1，SW和SEL都输出高电平，TN2打开，Node1读入SEL输出的高电平，TP1关闭，TN1打开，Node2的电位为低电平VSS，OLED的阳极的电位和OLED的阴极的电位相等，OLED不发光，也即OLED保持“暗”态。
在第二时间段T2，SW和SEL都输出低电平，TN2关闭，Node1的电位由Cst的电荷保持下维持为高电平，TP1关闭，TN1打开，Node2的电位为低电平VSS，OLED的阳极的电位和OLED的阴极的电位相等，OLED不发光，也即OLED保持“暗”态。
在第三时间段T3，SW输出高电平，SEL输出低电平，TN2打开，Node1 读入SEL输出的低电平，TP1打开，TN1关闭，Node2的电位为高电平，OLED的阳极和OLED的阴极之间的压差为VDD-VSS，OLED发光，也即OLED保持“亮”态。
在第四时间段T4，SW和SEL都输出低电平，TN2关闭，Node1的电位由Cst维持为低电平，TP1打开，TN1关闭，Node2的电位为高电平，OLED的阳极和OLED的阴极之间的压差为VDD-VSS，OLED发光，也即OLED保持“亮”态。
由上可知，本公开如图4所示的像素单元电路的具体实施例在工作时，通过行选通线SW输出的行选通信号的时序和列选通线SEL输出的列选通信号的时序配合来控制第一节点Node1的电位，根据所述第一节点Node1的电位决定开启TP1或TN2，以确定第二节点Node2的电位为VDD或VSS。当TP1开启时，OLED处于“亮”态；当TN1开启时，OLED处于“暗”态。TP1和TN1在工作时，均处于饱和区或关闭，仅起到开关的作用；且通过TP1和TN1开启和关闭的时间比例来控制发光的亮度，一帧显示时间内OLED实际工作的时间只是发光的时间，减少了OLED的工作时间和平均电流。
本公开实施例所述的像素单元电路不需通过驱动MOS管在亚阈值区的电流来控制硅基OLED(有机发光二极管)的发光亮度，本公开实施例所述的像素单元电路中的各MOS管仅起到开关的作用，故MOS管的尺寸可以做小，有利于实现高分辨率，且流过OLED的平均电流和OLED的亮度可以根据行选通线SW输出的行选通信号的时序和列选通线SEL的列选通信号的时序相互配合而任意调整。
在一些实施例中，如图6所示，可以固定SW输出的行选通信号的波形，而变化SEL输出的列选通信号的周期，即可使得OLED发出不同的亮度。在图6中，标号为T1的为第一时间段、标号为T2的为第二时间段，标号为T3的为第三时间段，标号为T4的为第四时间段，标号为T5的为第五时间段、标号为T6的为第六时间段，标号为T7的为第七时间段，标号为T8的为第八时间段。当SW输出的行选通信号的时序以及SEL输出的列选通信号的时序如图6所示时，在T1-T6，OLED处于“亮”态，在T7-T8，OLED处于“暗”态。
如图7所示，可以固定SEL输出的行选通信号的波形，而变化SW输出的列选通信号的周期，即可使得OLED发出不同的亮度。在图7中，标号为T1的为第一时间段、标号为T2的为第二时间段，标号为T3的为第三时间段，标号为T4的为第四时间段，标号为T5的为第五时间段、标号为T6的为第六时间段，标号为T7的为第七时间段，标号为T8的为第八时间段，标号为T9的为第九时间段，标号为T10的为第十时间段。当SW输出的行选通信号的时序以及SEL输出的列选通信号的时序如图7所示时，在T1-T5，OLED处于“亮”态，在T6-T10，OLED处于“暗”态。
在实际操作时，行选通线输出的行选通信号的时序和列选通线输出的列选通信号的时序可以根据实际情况变化。
本公开实施例所述的像素单元电路的驱动方法，用于驱动任一上述的像素单元电路，所述驱动方法包括：所述第一控制模块在所述行选通线的控制下控制所述第一节点是否与所述列选通线电连接；第二控制模块在第一节点的控制下控制所述发光元件的第一端与高电平输入端或低电平输入端连接，以使得所述发光元件发光或不发光。可选地，当所述第二节点控制模块控制所述第二节点与高电平输入端连接时，发光元件发光；当所述第二节点控制模块控制所述第二节点与低电平输入端连接时，所述发光元件不发光。
应理解，在某些实施例中，当第二节点的电位为低电平时发光元件发光，当第二节点的电位为高电平时发光元件不发光。具体的例子可以参考上述，此处不再赘述。
具体的，当所述第一节点控制模块包括所述第二NMOS管时，所述在行选通线的控制下，第一节点控制模块控制第一节点是否与列选通线连接步骤包括：
当所述行选通线输出高电平信号时，所述第二NMOS管导通，从而控制所述第一节点和所述列选通线连接；
当所述行选通线输出低电平信号时，所述第二NMOS管断开，从而控制所述第一节点和所述列选通线不连接。
具体的，当所述第一节点控制模块包括所述第二PMOS管时，所述在行选通线的控制下，第一节点控制模块控制第一节点是否与列选通线连接步骤 包括：
当所述行选通线输出低电平信号时，所述第二PMOS管导通，从而控制所述第一节点和所述列选通线连接；
当所述行选通线输出高电平信号时，所述第二PMOS管断开，从而控制所述第一节点和所述列选通线不连接。
具体的，当所述第二节点控制模块包括：第一PMOS管，栅极与所述第一节点连接，第一极与所述高电平输入端连接，第二极与所述第二节点连接；以及，第一NMOS管，栅极与所述第一节点连接，第一极与所述低电平输入端连接，第二极与所述第二节点连接时，所述在所述第一节点的控制下，第二节点控制模块控制第二节点与高电平输入端或低电平输入端连接步骤包括：
当所述第一节点的电位为高电平时，第一PMOS管断开，第一NMOS管导通，以控制所述第二节点与所述低电平输入端连接，以使得所述第二节点的电位为低电平，使得所述发光元件不发光；
当所述第一节点的电位为低电平时，第一PMOS管导通，第一NMOS管断开，以控制所述第二节点与所述高电平输入端连接，以使得所述第二节点的电位为高电平，使得所述发光元件发光。
具体的，当所述第二节点控制模块包括：第一NMOS管，栅极与所述第一节点连接，第一极与所述第二节点连接，第二极与所述高电平输入端连接；以及，第一PMOS管，栅极与所述第一节点连接，第一极与所述第二节点连接，第二极与所述低电平输入端连接时，所述在所述第一节点的控制下，第二节点控制模块控制第二节点与高电平输入端或低电平输入端连接步骤包括：
当所述第一节点的电位为低电平时，第一PMOS管导通，第一NMOS管断开，以控制所述第二节点与所述低电平输入端连接，以使得所述第二节点的电位为低电平，使得所述发光元件不发光；
当所述第一节点的电位为高电平时，第一PMOS管断开，第一NMOS管导通，以控制所述第二节点与所述高电平输入端连接，以使得所述第二节点的电位为高电平，使得所述发光元件发光。
本公开实施例所述的像素电路，设置于硅基板上，包括多条行选通线、多条列选通线，以及多个阵列排布的上述的像素单元电路；
位于同一行的所述像素单元电路与同一条行选通线连接；
位于同一列的所述像素单元电路与同一条列选通线连接。
本公开实施例所述的显示装置包括硅基板和设置于所述硅基板上的多条行选通线、多条列选通线，以及多个阵列排布的上述的像素单元电路；
位于同一行的所述像素单元电路与同一条行选通线连接；
位于同一列的所述像素单元电路与同一条列选通线连接。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (19)

  1. 一种像素单元电路，包括：
    第一控制模块，存储电容模块、第二控制模块和发光元件；
    其中：
    所述第一控制模块的第一端、第二端以及第三端分别与行选通线、列选通线、以及所述存储电容模块的第一端和第二控制模块的第一端连接，所述第一控制模块用于在所述行选通线的控制下控制所述第二控制模块的第一端和所述存储电容模块的第一端是否与所述列选通线电连接；
    所述存储电容模块的第二端与高电平输入端连接；
    所述第二控制模块的第二端、第三端以及第四端分别与所述发光元件的第一端、所述高电平输入端以及低电平输入端连接，所述第二控制模块用于通过其第一端的电位来控制所述发光元件的第一端与所述高电平输入端或所述低电平输入端电连接。
  2. 如权利要求1所述的像素单元电路，其中，所述第二控制模块包括：
    第一PMOS管，栅极与所述第一控制模块的第三端和所述存储电容模块的第一端连接，第一极与所述高电平输入端连接，第二极与所述发光元件的第一端连接；以及，
    第一NMOS管，栅极与所述第一控制模块的第三端和所述存储电容模块的第一端连接，第一极与所述低电平输入端连接，第二极与所述发光元件的第一端连接。
  3. 如权利要求1所述的像素单元电路，其中，所述第二控制模块包括：
    第一NMOS管，栅极与所述第一控制模块的第三端和所述存储电容模块的第一端连接，第一极与所述发光元件的第一端连接，第二极与所述高电平输入端连接；以及，
    第一PMOS管，栅极与所述第一控制模块的第三端和所述存储电容模块的第一端连接，第一极与所述发光元件的第一端连接，第二极与所述低电平输入端连接。
  4. 如权利要求2或3所述的像素单元电路，其中，所述第一控制模块包 括：第二NMOS管，栅极与所述行选通线连接，第一极与所述第一PMOS管的栅极、所述第一NMOS管的栅极以及所述存储电容模块的第一端连接，第二极与所述列选通线连接。
  5. 如权利要求2或3所述的像素单元电路，其中，所述第一控制模块包括：第二PMOS管，栅极与所述行选通线连接，第一极与所述列选通线连接，第二极与所述第一PMOS管的栅极、所述第一NMOS管的栅极以及所述存储电容模块的第一端连接。
  6. 如权利要求3-5中任一项所述的像素单元电路，其中，
    所述第一控制模块还用于通过控制所述第一PMOS管在一帧显示时间内开启和关闭时间的比例来控制所述发光元件的发光亮度；或者
    所述第一控制模块还用于通过控制所述第一NMOS管在一帧显示时间内开启和关闭时间的比例来控制所述发光元件的发光亮度。
  7. 如权利要求1至6中任一项所述的像素单元电路，其中，所述存储电容模块包括：
    存储电容，其第一端与所述第一控制模块的第三端和所述第二控制模块的第一端连接，其第二端与高电平输入端连接。
  8. 如权利要求1至7中任一项所述的像素单元电路，其中，
    所述发光元件的第二端与所述低电平输入端连接；所述发光元件包括有机发光二极管；
    所述发光元件的第一端为所述有机发光二极管的阳极，所述发光元件的第二端为所述有机发光二极管的阴极。
  9. 如权利要求1至7中任一项所述的像素单元电路，其中，
    所述发光元件的第二端与所述高电平输入端连接；
    所述发光元件包括有机发光二极管；
    所述发光元件的第一端为所述有机发光二极管的阴极，所述发光元件的第二端为所述有机发光二极管的阳极。
  10. 一种像素单元电路的驱动方法，用于驱动如权利要求1至9中任一项所述的像素单元电路，所述驱动方法包括：
    所述第一控制模块在所述行选通线的控制下控制所述第二控制模块的第 一端和所述存储电容模块的第一端是否与所述列选通线电连接；
    第二控制模块在其第一端的电位控制下控制所述发光元件的第一端与高电平输入端或低电平输入端连接，以使得所述发光元件发光或不发光。
  11. 如权利要求10所述的方法，其中，所述第一控制模块包括第二NMOS管，栅极与所述行选通线连接，第一极与所述第二控制模块的第一端和所述存储电容模块的第一端连接，第二极与所述列选通线连接；所述第一控制模块在所述行选通线的控制下控制所述第二控制模块的第一端和所述存储电容模块的第一端是否与所述列选通线电连接，包括：
    当所述行选通线输出高电平信号时，所述第二NMOS管导通，从而控制所述第二控制模块的第一端和所述存储电容模块的第一端与所述列选通线连接；
    当所述行选通线输出低电平信号时，所述第二NMOS管断开，从而控制所述第二控制模块的第一端和所述存储电容模块的第一端与所述列选通线不连接。
  12. 如权利要求10所述的方法，其中，所述第一控制模块包括第二PMOS管，栅极与所述行选通线连接，第一极与所述列选通线连接，第二极与所述第二控制模块的第一端和所述存储电容模块的第一端连接；
    所述第一控制模块在所述行选通线的控制下控制所述第二控制模块的第一端和所述存储电容模块的第一端是否与所述列选通线电连接，包括：
    当所述行选通线输出低电平信号时，所述第二PMOS管导通，从而控制所述第二控制模块的第一端和所述存储电容模块的第一端与所述列选通线连接；
    当所述行选通线输出高电平信号时，所述第二PMOS管断开，从而控制所述第二控制模块的第一端和所述存储电容模块的第一端与所述列选通线不连接。
  13. 如权利要求10至12中任一项所述的方法，其中，当所述第二控制模块包括：第一PMOS管，栅极与所述第一控制模块的第三端和所述存储电容模块的第一端连接，第一极与所述高电平输入端连接，第二极与所述发光元件的第一端连接；以及，第一NMOS管，栅极与所述第一控制模块的第三 端和所述存储电容模块的第一端连接，第一极与所述低电平输入端连接，第二极与所述发光元件的第一端连接；
    所述第二控制模块在其第一端的电位控制下控制所述发光元件的第一端与高电平输入端或低电平输入端连接，包括：
    当所述第二控制模块的第一端的电位为高电平时，所述第一PMOS管断开，所述第一NMOS管导通，以控制所述发光元件的第一端与所述低电平输入端连接；
    当所述第二控制模块的第一端的电位为低电平时，所述第一PMOS管导通，所述第一NMOS管断开，以控制所述发光元件的第一端与所述高电平输入端连接。
  14. 如权利要求10至12中任一项所述的方法，其中，所述第二控制模块包括：第一NMOS管，栅极与所述第一控制模块的第三端和所述存储电容模块的第一端连接，第一极与所述发光元件的第一端连接，第二极与所述高电平输入端连接；以及，第一PMOS管，栅极与所述第一控制模块的第三端和所述存储电容模块的第一端连接，第一极与所述发光元件的第一端连接，第二极与所述低电平输入端连接；
    所述第二控制模块在其第一端的电位控制下控制所述发光元件的第一端与高电平输入端或低电平输入端连接，包括：当所述第一节点的电位为低电平时，所述第一PMOS管导通，所述第一NMOS管断开，以控制所述发光元件的第一端与所述低电平输入端连接；
    当所述第一节点的电位为高电平时，所述第一PMOS管断开，所述第一NMOS管导通，以控制所述发光元件的第一端与所述高电平输入端连接。
  15. 如权利要求13或14所述的方法，其中，所述方法还包括：
    所述第一控制模块通过控制所述第一PMOS管在一帧显示时间内开启和关闭时间的比例来控制所述发光元件的发光亮度；或者
    所述第一控制模块通过控制所述第一NMOS管在一帧显示时间内开启和关闭时间的比例来控制所述发光元件的发光亮度。
  16. 如权利要求10至15中任一项所述的方法，其中，
    所述发光元件的第二端与所述低电平输入端连接；
    所述发光元件包括：有机发光二极管，所述发光元件的第一端为所述有机发光二极管的阳极，所述发光元件的第二端为所述有机发光二极管的阴极；
    在所述发光元件的第一端与所述低电平输入端的情况下，所述发光元件不发光；在所述发光元件的第一端与所述高电平输入端的情况下，所述发光元件发光。
  17. 如权利要求10至15中任一项所述的方法，其中，
    所述发光元件的第二端与所述高电平输入端连接；
    所述发光元件包括：有机发光二极管，所述发光元件的第一端为所述有机发光二极管的阴极，所述发光元件的第二端为所述有机发光二极管的阳极；
    在所述发光元件的第一端与所述低电平输入端的情况下，所述发光元件发光；在所述发光元件的第一端与所述高电平输入端的情况下，所述发光元件不发光。
  18. 一种像素电路，设置于硅基板上，包括：多条行选通线、多条列选通线，以及多个阵列排布的如权利要求1至9中任一项所述的像素单元电路；其中：
    位于同一行的所述像素单元电路与同一条行选通线连接；
    位于同一列的所述像素单元电路与同一条列选通线连接。
  19. 一种显示装置，包括硅基板和设置于所述硅基板上的多条行选通线、多条列选通线，以及多个阵列排布的如权利要求1至9中任一项所述的像素单元电路；
    位于同一行的所述像素单元电路与同一条行选通线连接；
    位于同一列的所述像素单元电路与同一条列选通线连接。
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