WO2019010858A1 - 一种提高射频功率放大器谐波抑制能力的电路结构及方法 - Google Patents

一种提高射频功率放大器谐波抑制能力的电路结构及方法 Download PDF

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WO2019010858A1
WO2019010858A1 PCT/CN2017/106825 CN2017106825W WO2019010858A1 WO 2019010858 A1 WO2019010858 A1 WO 2019010858A1 CN 2017106825 W CN2017106825 W CN 2017106825W WO 2019010858 A1 WO2019010858 A1 WO 2019010858A1
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harmonic suppression
matching
inductor
power amplifier
resonant
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English (en)
French (fr)
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周佳辉
胡滨
郭嘉帅
宣凯
龙华
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Lansus Technologies Inc
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Lansus Technologies Inc
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Priority to US16/630,513 priority Critical patent/US11139783B2/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/171—A filter circuit coupled to the output of an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/225—Indexing scheme relating to amplifiers the input circuit of an amplifying stage comprising an LC-network
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/387—A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the invention relates to a harmonic suppression circuit structure and method, in particular to a circuit structure and a method for improving harmonic suppression capability of a radio frequency power amplifier.
  • RF power amplifiers are an important part of transmission equipment.
  • the main technical indicators are output power and efficiency.
  • the harmonic components in the output should be as small as possible to avoid interference with other channels.
  • the traditional RF power amplifier output matching uses a low-pass three-stage LC matching structure. This matching structure has limited harmonic suppression capability for the RF power amplifier. Even if a harmonic suppression network is added to the chip Die, it can only be low. The order harmonics are improved and the ability to suppress higher harmonics is limited.
  • the invention provides a circuit structure for improving the harmonic suppression capability of a radio frequency power amplifier.
  • a set of resonant networks is added in the radio frequency power amplifier chip Die, and the resonance effect of the capacitor and the back hole is utilized.
  • the higher harmonics are suppressed to obtain better harmonic suppression than the traditional low-pass three-stage LC matching network.
  • the circuit structure for improving the harmonic suppression capability of the radio frequency power amplifier provided by the invention comprises an output stage unit, a high-order harmonic suppression unit, and a low-order harmonic suppression unit;
  • the output stage unit outputs a signal to be subjected to harmonic suppression
  • the high-order harmonic suppression unit is configured to suppress five or more higher harmonics, including a first filter capacitor and a back hole; and the output stage unit and the first filter capacitor are connected in series to the ground through the back hole;
  • the low-order harmonic suppression unit is electrically connected to the output stage unit to suppress second, third, and fourth harmonics.
  • the low-order harmonic suppression unit includes a second filter capacitor, Four resonant inductors, first, second, and third matching inductors, first, second, and third matching capacitors, first, second, and third resonant inductors;
  • the second filter capacitor is connected in series to the ground through the fourth resonant inductor;
  • the first matched inductor is connected to the output stage unit, and then connected in series with the second and third matched inductors to an output terminal;
  • the first matching capacitor is connected in series with the first resonant inductor to ground, and is connected in parallel between the first matching inductor and the second matched inductor level;
  • the second matching capacitor and the second resonant inductor are connected in series to ground, and are connected in parallel between the second matching inductor and the third matching inductor level;
  • the third matching capacitor is connected in series with the third resonant inductor to ground, and is connected in parallel between the third matching inductor and the output terminal.
  • the first filter capacitor bit is disposed on the back hole, the output stage unit, the high-order harmonic suppression unit, the second filter capacitor are disposed on the chip Die, and the fourth resonant inductor is gold. Line implementation.
  • the present invention also provides a method for improving the harmonic suppression capability of a radio frequency power amplifier by using the circuit structure as described above, comprising the following steps:
  • the output stage unit of the radio frequency power amplifier and the first filter capacitor are connected in series to the ground through the back hole, and the first filter capacitor and the back hole constitute a resonance network in the chip Die, and the radio frequency power amplifier Five or more higher harmonics are suppressed;
  • the low-order harmonic suppression unit is connected to the output stage unit to suppress the second, third, and fourth harmonics.
  • the low-order harmonic suppression unit includes a second filter capacitor, a fourth resonant inductor, first, second, and third matching inductors, first, second, and third matching capacitors, First, second and third resonant inductors; the specific steps are:
  • the second filter capacitor is connected in series to the ground through the fourth resonant inductor, and the second filter capacitor and the fourth resonant inductor form a resonant network to suppress fourth harmonics;
  • the third matching inductor suppresses the third harmonic.
  • the first filter capacitor is disposed on the back hole; and the output stage unit, the high-order harmonic suppression unit, and the second filter capacitor are disposed on a chip Die; the fourth resonant inductor is realized by a gold wire.
  • the present invention has the following advantages:
  • the circuit structure provided by the invention for improving the harmonic suppression capability of the radio frequency power amplifier not only ensures the area of the chip Die but also improves the harmonic suppression capability of the radio frequency power amplifier.
  • the invention has a circuit structure for improving the harmonic suppression capability of a radio frequency power amplifier, and the circuit structure is simple and easy to implement.
  • FIG. 1 is a diagram of an RF power amplifier output matching circuit structure designed by the present invention.
  • FIG. 2 is a comparative simulation diagram of the harmonic suppression capability of the output matching structure of the RF power amplifier of the present invention and the output matching structure of the conventional RF power amplifier.
  • FIG. 3 is a detailed embodiment of the design within the DIE of the present invention.
  • a circuit structure for improving the harmonic suppression capability of a radio frequency power amplifier includes an output stage unit 1, a high-order harmonic suppression unit 2, and a low-order harmonic suppression unit 3.
  • the output stage unit 1 outputs a signal to be subjected to harmonic suppression.
  • the high-order harmonic suppression unit 2 is for suppressing fifth-order or higher harmonics, including the first filter capacitor C1 and the back hole 21.
  • the output stage unit 1 and the first filter capacitor C1 are connected in series to the ground through the back hole 21.
  • the low-order harmonic suppression unit 3 is electrically connected to the output stage unit 1 to suppress the second, third, and fourth harmonics.
  • the low-order harmonic suppression unit 3 includes a second filter capacitor C2, a fourth resonant inductor L4, first, second and third matching inductors L01, L02, L03, first, second and third matching capacitors C01, C02, C03, first , two, three resonant inductors L1, L2, L3.
  • the second filter capacitor C2 is connected in series to the ground through the fourth resonant inductor L4.
  • the first matching inductor L01 is connected to the output stage unit 1, and then connected in series with the second and third matching inductors L02, L03 to the output terminal.
  • the first matching capacitor C01 is connected in series with the first resonant inductor L1 to ground, and is connected in parallel between the first matching inductor L01 and the second matching inductor L02.
  • the second matching capacitor C02 and the second resonant inductor L2 are connected in series to ground, and are connected in parallel between the second matching inductor L02 and the third matching inductor L03.
  • the third matching capacitor C03 and the third resonant inductor L3 are connected in series to the ground and are connected in parallel between the third matching inductor L03 and the output terminal.
  • the first filter capacitor C1 is disposed on the back hole 21, and the output stage unit 1 and the high-order harmonic
  • the suppression unit 2 and the second filter capacitor C2 are disposed on the chip Die, and the fourth resonant inductor L4 is implemented by a gold wire.
  • the present invention also provides a method for suppressing harmonics using the harmonic suppression circuit shown in FIG. 1, comprising the following steps:
  • the output stage unit 1 and the first filter capacitor C1 are connected in series to the ground through the back hole 21, and the first filter capacitor C1 and the back hole 21 constitute a resonance network in the chip Die, and suppress the fifth harmonic harmonics of the RF power amplifier.
  • the main implementation of the resonant network is that the first filter capacitor C1 is designed on the back hole 21, and the resonant circuit is formed by using the first filter capacitor C1 and the parasitic inductance of the back hole 21 and the first filter capacitor C1; Small, the first filter capacitor C1 on the chip Die has a large Q factor, which is easy to form deep resonance and filtering in the high frequency part, thereby effectively suppressing the higher harmonics of the RF power amplifier. Since the first filter capacitor C1 itself is designed on the back hole 21, the introduction of the first filter capacitor C1 does not additionally increase the area of the chip Die.
  • the low-order harmonic suppression unit 2 is electrically connected to the output stage unit 1 to suppress the second, third, and fourth harmonics.
  • the second filter capacitor C2 is connected in series to the ground through the resonant inductor L4, and the second filter capacitor C2 and the fourth resonant inductor L4 form a resonant network to suppress the fourth harmonic.
  • the second harmonic is suppressed by the first matching capacitor C01, the first resonant inductor L1, the second matching capacitor C02, and the second resonant inductor L2 at the second harmonic frequency.
  • the third harmonic is suppressed by the third matching capacitor C03 and the third matching inductor L03 at the third-order harmonic frequency.
  • the first filter capacitor C1 is disposed on the back hole 21, and the output stage unit 1, the high-order harmonic suppression unit 2, and the second filter capacitor C2 are disposed on the chip Die, and the fourth resonant inductor L4 is implemented by a gold wire.
  • FIG. 2 it is a comparative simulation diagram of the harmonic suppression capability of the output matching structure of the RF power amplifier and the output matching structure of the conventional RF power amplifier, the fine curve is the simulation result of the traditional structure, and the thick curve is the circuit structure of the invention. Simulation results. It can be clearly seen that the circuit structure of the present invention has advantages in harmonic suppression capability, especially in the high-order harmonics of m9, m10, m16, and m17.
  • the resonant inductor L4 in FIG. 1 is connected to the ground through a TRAP PAD gold wire, and the Backvia portion corresponds to the back hole in FIG.
  • the capacitance of the TRAP connection corresponds to C1, where OUT is the PA output.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Amplifiers (AREA)

Abstract

一种提高射频功率放大器谐波抑制能力的电路结构，包括输出级单元（1）、高阶谐波抑制单元（2）、低阶谐波抑制单元（3）。所述输出级单元（1）输出待进行谐波抑制的信号；所述高阶谐波抑制单元（2）包括第一滤波电容（C1）、背孔（21），用于对五次及以上高次谐波进行抑制；所述输出级单元（1）与所述第一滤波电容（C1）通过所述背孔（21）串联到地；所述低阶谐波抑制单元（3）与所述输出级单元（1）连接，对二次、三次、四次谐波进行抑制。通过以上设计，提高了射频功率放大器对高次谐波的抑制能力。

Description

一种提高射频功率放大器谐波抑制能力的电路结构及方法 技术领域
本发明涉及一种谐波抑制电路结构及方法，尤其涉及一种提高射频功率放大器谐波抑制能力的电路结构及方法。
背景技术
射频功率放大器是发送设备的重要组成部分，其主要的技术指标是输出功率与效率。除此之外，输出中的谐波分量还应该尽可能地小，以避免对其他频道产生干扰。传统的射频功率放大器输出匹配采用的是低通三段LC匹配结构，这种匹配结构对于射频功率放大器的谐波抑制能力有限，即便在芯片Die内增加一个谐波抑制网络，也只能对于低阶谐波有所改善，对于高次谐波的抑制能力有限。
发明内容
本发明提供一种提高射频功率放大器谐波抑制能力的电路结构，在传统低通三段LC匹配网络基础上，在射频功率放大器芯片Die内增加一组谐振网络，利用电容和背孔的谐振效果对高次谐波进行抑制，以获得比传统低通三段LC匹配网络更好的谐波抑制效果。
本发明所提供的提高射频功率放大器谐波抑制能力的电路结构，包括输出级单元、高阶谐波抑制单元、低阶谐波抑制单元；
所述输出级单元输出待进行谐波抑制的信号；
所述高阶谐波抑制单元用于对五次及以上高次谐波进行抑制，包括第一滤波电容、背孔；所述输出级单元与第一滤波电容通过所述背孔串联到地；
所述低阶谐波抑制单元与所述输出级单元电连接，对二次、三次、四次谐波进行抑制。所述低阶谐波抑制单元包括第二滤波电容、第 四谐振电感，第一、二、三匹配电感，第一、二、三匹配电容，第一、二、三谐振电感；其中，
所述第二滤波电容通过所述第四谐振电感串联到地；所述第一匹配电感与所述输出级单元相连，然后与所述第二、第三匹配电感串联到输出端；
所述第一匹配电容与所述第一谐振电感串联到地，并联于所述第一匹配电感和所述第二匹配电感级间；
所述第二匹配电容与所述第二谐振电感串联到地，并联于所述第二匹配电感和所述第三匹配电感级间；
所述第三匹配电容与所述第三谐振电感串联到地，并联于所述第三匹配电感和输出端间。
所述第一滤波电容位设置于所述背孔上，所述输出级单元、所述高阶谐波抑制单元、所述第二滤波电容设置于芯片Die上，所述第四谐振电感采用金线实现。
本发明还提供一种利用如上所述电路结构提高射频功率放大器谐波抑制能力的方法，，包括以下步骤：
第一，高阶谐波抑制：
将所述射频功率放大器的所述输出级单元与所述第一滤波电容通过所述背孔串联到地，所述第一滤波电容与所述背孔构成芯片Die内谐振网络，对射频功率放大器五次及以上高次谐波进行抑制；
第二，低阶谐波抑制：
利用所述低阶谐波抑制单元与所述输出级单元连接，对二次、三次、四次谐波进行抑制。
所述低阶谐波抑制步骤中，所述低阶谐波抑制单元包括第二滤波电容、第四谐振电感，第一、二、三匹配电感，第一、二、三匹配电容， 第一、二、三谐振电感；具体步骤为：
四次谐波进行抑制：
将所述第二滤波电容通过所述第四谐振电感串联到地，所述第二滤波电容与所述第四谐振电感构成谐振网络，对四次谐波进行抑制；
将所述第一匹配电感与所述输出级单元相连，然后与所述第二、第三匹配电感串联到输出端；
二次谐波进行抑制：
将所述第一匹配电容与所述第一谐振电感串联到地，并联于所述第一匹配电感和所述第二匹配电感级间；将所述第二匹配电容与所述第二谐振电感串联到地，并联于所述第二匹配电感和所述第三匹配电感级间；利用谐振在二阶谐波频点的所述第一匹配电容、所述第一谐振电感以及所述第二匹配电容、所述第二谐振电感，对二次谐波进行抑制；
三次谐波进行抑制：
将所述第三匹配电容与所述第三谐振电感串联到地，并联于所述第三匹配电感和输出端间；利用谐振在三阶谐波频点的所述第三匹配电容、所述第三匹配电感，对三次谐波进行抑制。
所述高阶谐波抑制步骤中，将所述第一滤波电容设置于所述背孔上；将所述输出级单元、所述高阶谐波抑制单元、所述第二滤波电容设置于芯片Die上；所述第四谐振电感采用金线实现。
与现有技术相比，本发明有以下优点：
本发明提供的一种提高射频功率放大器谐波抑制能力的电路结构既保证了芯片Die的面积，又提高了射频功率放大器谐波抑制能力。
本发明一种提高射频功率放大器谐波抑制能力的电路结构，电路结构简单，易于实现。
附图说明
图1是本发明所设计的射频功率放大器输出匹配电路结构。
图2是本发明的射频功率放大器输出匹配结构与传统射频功率放大器输出匹配结构对谐波抑制能力的对比仿真图。
图3是本发明的DIE内设计具体实施方案。
具体实施方式
以下结合附图和实施例，对本发明的具体实施方式进行更加详细的说明，以便能够更好地理解本发明的方案及其各个方面的优点。然而，以下描述的具体实施方式和实施例仅是说明的目的，而不是对本发明的限制。
参见图1，一种提高射频功率放大器谐波抑制能力的电路结构，包括输出级单元1、高阶谐波抑制单元2、低阶谐波抑制单元3。
其中，输出级单元1输出待进行谐波抑制的信号。
高阶谐波抑制单元2用于对五次及以上高次谐波进行抑制，包括第一滤波电容C1、背孔21。所述输出级单元1与第一滤波电容C1通过所述背孔21串联到地。低阶谐波抑制单元3与所述输出级单元1电性连接，对二次、三次、四次谐波进行抑制。
低阶谐波抑制单元3包括第二滤波电容C2、第四谐振电感L4，第一、二、三匹配电感L01、L02、L03，第一、二、三匹配电容C01、C02、C03，第一、二、三谐振电感L1、L2、L3。其中，第二滤波电容C2通过第四谐振电感L4串联到地。第一匹配电感L01与输出级单元1相连，然后与第二、第三匹配电感L02、L03串联到输出端。第一匹配电容C01与第一谐振电感L1串联到地，并联于第一匹配电感L01和第二匹配电感L02间。第二匹配电容C02与第二谐振电感L2串联到地，并联于第二匹配电感L02和所述第三匹配电感L03间。第三匹配电容C03与第三谐振电感L3串联到地，并联于所述第三匹配电感L03和输出端间。另外，第一滤波电容C1设置于背孔21上，输出级单元1、高阶谐波 抑制单元2、第二滤波电容C2设置于芯片Die上，第四谐振电感L4采用金线实现。
本发明还提供利用图1所示的谐波抑制电路对谐波进行抑制的方法，包括以下步骤：
第一，高阶谐波抑制：
将输出级单元1与第一滤波电容C1通过背孔21串联到地，第一滤波电容C1与背孔21构成芯片Die内谐振网络，对射频功率放大器五次及以上高次谐波进行抑制。
所述谐振网络主要实现方式在于第一滤波电容C1设计在背孔21上，利用第一滤波电容C1与背孔21的寄生电感和第一滤波电容C1形成谐振网络；由于背孔21寄生电感较小，芯片Die上第一滤波电容C1品质因数Q值大，容易在高频部分形成较深的谐振及滤波，从而有效抑制射频功率放大器的高次谐波。由于第一滤波电容C1本身设计在背孔21上，所以第一滤波电容C1的引入不会额外增加芯片Die的面积。
第二，低阶谐波抑制：
利用低阶谐波抑制单元2与输出级单元1电性连接，对二次、三次、四次谐波进行抑制。
A.四次谐波进行抑制：
将第二滤波电容C2通过谐振电感L4串联到地，第二滤波电容C2与第四谐振电感L4构成谐振网络，对四次谐波进行抑制。
B.二次谐波进行抑制：
利用谐振在二阶谐波频点的第一匹配电容C01、第一谐振电感L1以及第二匹配电容C02、第二谐振电感L2，对二次谐波进行抑制。
C.三次谐波抑制：
利用谐振在三阶谐波频点的所述第三匹配电容C03、第三匹配电感L03，对三次谐波进行抑制。
另外，将第一滤波电容C1设置于背孔21上，将输出级单元1、高阶谐波抑制单元2、第二滤波电容C2设置于芯片Die上，第四谐振电感L4采用金线实现。
如图2所示，为本发明射频功率放大器输出匹配结构与传统射频功率放大器输出匹配结构对谐波抑制能力的对比仿真图，细曲线为传统结构的仿真结果，粗曲线为本发明的电路结构的仿真结果。可以明显看出本发明的电路结构对谐波抑制能力优势，尤其在m9、m10、m16、m17四处高阶谐波较为明显。
如图3所示，为本发明的DIE内设计具体实施方案，图1中的谐振电感L4通过TRAP PAD打金线与地连接，Backvia部分与图1中的背孔相对应，图中CAP部分与图1电容C2相对应，TRAP连接的电容与C1相对应，图中OUT为PA输出端。
需要说明的是，以上参照附图所描述的各个实施例仅用以说明本发明而非限制本发明的范围，本领域的普通技术人员应当理解，在不脱离本发明的精神和范围的前提下对本发明进行的修改或者等同替换，均应涵盖在本发明的范围之内。此外，除上下文另有所指外，以单数形式出现的词包括复数形式，反之亦然。另外，除非特别说明，那么任何实施例的全部或一部分可结合任何其它实施例的全部或一部分来使用。

Claims (10)

  1. 一种提高射频功率放大器谐波抑制能力的电路结构，包括输出级单元、高阶谐波抑制单元、低阶谐波抑制单元；
    所述输出级单元输出待进行谐波抑制的信号；
    所述高阶谐波抑制单元包括第一滤波电容、背孔，对五次及以上高次谐波进行抑制；
    所述输出级单元与所述第一滤波电容通过所述背孔串联到地；
    所述低阶谐波抑制单元与所述输出级单元电连接，对二次、三次、四次谐波进行抑制。
  2. 如权利要求1所述的提高射频功率放大器谐波抑制能力的电路结构，其特征在于，所述低阶谐波抑制单元包括第二滤波电容、第四谐振电感，第一、二、三匹配电感，第一、二、三匹配电容，第一、二、三谐振电感；其中，
    所述第二滤波电容通过所述第四谐振电感串联到地；所述第一匹配电感与所述输出级单元相连，然后与所述第二、第三匹配电感串联到输出端；
    所述第一匹配电容与所述第一谐振电感串联到地，并联于所述第一匹配电感和所述第二匹配电感级间；
    所述第二匹配电容与所述第二谐振电感串联到地，并联于所述第二匹配电感和所述第三匹配电感级间；
    所述第三匹配电容与所述第三谐振电感串联到地，并联于所述第三匹配电感和输出端间。
  3. 如权利要求1所述的提高射频功率放大器谐波抑制能力的电路结构，其特征在于，所述第一滤波电容设置于所述背孔上。
  4. 如权利要求2所述的提高射频功率放大器谐波抑制能力的电路结构，其特征在于，所述输出级单元、所述高阶谐波抑制单元、所述第 二滤波电容设置于芯片(DIE)内。
  5. 如权利要求2所述的提高射频功率放大器谐波抑制能力的电路结构，其特征在于，所述第四谐振电感采用金线实现。
  6. 利用如权利要求1所述的提高射频功率放大器谐波抑制能力的电路结构，进行谐波抑制的方法，包括以下步骤：
    第一，高阶谐波抑制：
    将射频功率放大器的所述输出级单元与所述第一滤波电容通过所述背孔串联到地，所述第一滤波电容与所述背孔构成芯片内谐振网络，对射频功率放大器五次及以上高次谐波进行抑制；
    第二，低阶谐波抑制：
    利用所述低阶谐波抑制单元与所述输出级单元连接，对二次、三次、四次谐波进行抑制。
  7. 如权利要求6所述的提高射频功率放大器谐波抑制能力的方法，其特征在于，所述低阶谐波抑制步骤中，所述低阶谐波抑制单元包括第二滤波电容、第四谐振电感，第一、二、三匹配电感，第一、二、三匹配电容，第一、二、三谐振电感；具体步骤为：
    四次谐波进行抑制：
    将所述第二滤波电容通过所述第四谐振电感串联到地，所述第二滤波电容与所述第四谐振电感构成谐振网络，对四次谐波进行抑制；
    将所述第一匹配电感与所述输出级单元相连，然后与所述第二、第三匹配电感串联到输出端；
    二次谐波进行抑制：
    将所述第一匹配电容与所述第一谐振电感串联到地，并联于所述第一匹配电感和所述第二匹配电感级间；将所述第二匹配电容与所述第二谐振电感串联到地，并联于所述第二匹配电感和所述第三匹配电感级间；利用谐振在二阶谐波频点的所述第一匹配电容、所述第一谐振电感以及所述第二匹配电容、所述第二谐振电感，对二次谐波进行抑制；
    三次谐波进行抑制：
    将所述第三匹配电容与所述第三谐振电感串联到地，并联于所述第三匹配电感和输出端间；利用谐振在三阶谐波频点的所述第三匹配电容、所述第三谐振电感，对三次谐波进行抑制。
  8. 如权利要求6所述的提高射频功率放大器谐波抑制能力的方法，其特征在于，所述高阶谐波抑制步骤中，将所述第一滤波电容设置于所述背孔上。
  9. 如权利要求7所述的提高射频功率放大器谐波抑制能力的方法，其特征在于，将所述输出级单元、所述高阶谐波抑制单元、所述第二滤波电容设置于芯片上。
  10. 如权利要求7所述的提高射频功率放大器谐波抑制能力的方法，其特征在于，所述第四谐振电感采用金线实现。
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