WO2019007315A1 - 闪存设备中数据写入的方法及设备 - Google Patents

闪存设备中数据写入的方法及设备 Download PDF

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Publication number
WO2019007315A1
WO2019007315A1 PCT/CN2018/094205 CN2018094205W WO2019007315A1 WO 2019007315 A1 WO2019007315 A1 WO 2019007315A1 CN 2018094205 W CN2018094205 W CN 2018094205W WO 2019007315 A1 WO2019007315 A1 WO 2019007315A1
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data
physical page
page address
controller
address
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PCT/CN2018/094205
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English (en)
French (fr)
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郭云格
陈明宇
朱晓静
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华为技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Definitions

  • the present invention relates to the field of information technology, and in particular, to a method and device for writing data in a flash memory device.
  • a flash memory device is a memory that retains stored data information even in the event of a power outage, including but not limited to solid state drives, Secure Digital (SD) cards, and the like. Due to the limitations of the physical characteristics of the flash device, the bit of data written in the flash device can only be changed from 0 to 1, and cannot be changed from 1 to 0. Therefore, after the flash is written, it must be erased before the second write. However, flash devices have an upper limit on the number of erasures, and when the upper limit is reached, the flash device cannot continue to be used.
  • a flash memory device receives a write request and directly encodes the data to be written into a physical page, thereby avoiding data erasure. Since this type of encoding requires a large number of bits to be used to represent the data to be written, the encoding effect is poor.
  • the present application provides a data access method, a host, a non-transitory computer readable storage medium, and a data access device.
  • a physical interface card of a host is not installed with a physical interface card on a virtual machine running on the host. In the case of the driver, data access to the virtual machine is still possible.
  • an embodiment of the present invention provides a data writing scheme in a flash memory device, where the flash memory device includes a controller and a storage medium, where the storage medium includes a plurality of physical pages;
  • the controller receives a data write request; the data write request carries a logical address and first data; wherein the flash device stores a mapping relationship between the logical address and a first physical page address; the controller according to the logical address and the first The mapping relationship of the physical page address reads the second data from the storage space pointed by the first physical page address, performs logical operations on the first data and the second data to obtain the third data, and compresses the third data to obtain the fourth data.
  • Data encoding the fourth data into a storage space of the invalid data physical page to obtain fifth data; the address of the storage space of the invalid data physical page is a second physical page address, and the controller records the second physics storing the encoded data Page address.
  • the logical operation can be an exclusive OR operation or an identical operation.
  • the present scheme logically operates by writing the first data written to the logical address with the second data already written to the same logical address, because the first data written in the same logical address is written to the second data already written to the same logical address. Only part of the change, so the third data obtained through logical operations, such as XOR logic, will contain a large number of 0, a small number of 1, will reduce the amount of data that needs to be encoded into the physical page of invalid data, so you can make full use of invalid Invalid data in the storage space of the data physical page improves the encoding effect, thereby reducing the number of data erasures and prolonging the life of the flash memory device.
  • the controller records the second physical page address, specifically, the controller: storing the second physical page address to the first physical page address The extra space of the physical page where the storage space is pointing.
  • the method further includes: the controller calculates verification data of the fifth data, and the controller performs the verification
  • the data is stored in the extra space of the physical page where the storage space pointed to by the second physical page address is located.
  • the verification data can be used to verify the accuracy of the fifth data by using the verification data when reading the fifth data. For example, if the fifth data is in error, the verification data can be used to recover, and the reliability of the data is improved. .
  • the solution further includes: the controller receiving a data read request; the data read request carrying a logical address; the controller reads the second data from a storage space pointed by the first physical page address according to a mapping relationship between the logical address and the first physical page address, and a storage space pointed to by the first physical page address
  • the additional space of the physical page where the physical page is located reads the second physical page address storing the encoded data, and reads the fifth data from the storage space pointed by the second physical page address according to the second physical page address, and decodes the first
  • the fifth data obtains the fourth data, decompresses the fourth data to obtain the third data, and performs the logic operation on the third data and the second data to obtain the first data.
  • the controller records an address of the second physical page
  • the method includes: the controller establishes a mapping relationship between the logical address and the physical page address, and Generating an identifier; wherein the physical page address includes the first physical page address and the second physical page address, the identifier being used to indicate that data in the storage space pointed by the second physical page address is encoded data.
  • the controller generation identifier may specifically generate a flag to indicate a data type in a storage space pointed to in the second physical page address. For example, 0 is indicated as non-encoded data, and 1 is indicated as encoded data.
  • the controller can also maintain a physical page address table as an identifier indicating the type of data stored in the storage space pointed to by the physical page address.
  • the method further includes: receiving the data read request; the data read request carrying the logical address; The mapping relationship between the logical address and the physical page address reads the second data from the storage space pointed by the first physical page address, and reads the fifth data from the storage space pointed by the second physical page address, according to the identifier Determining that the fifth data is encoded data; the controller decoding the fifth data to obtain the fourth data, decompressing the fourth data to obtain the third data, and performing the logic on the third data and the second data The operation obtains the first data.
  • the method further includes: before the controller compresses the third data to obtain the fourth data, determining that the number of zero bits in the third data is less than a threshold .
  • the method further includes: the controller encoding the fourth data into a storage space of the invalid data physical page to obtain the fifth data, determining the third Data compression was successful.
  • an embodiment of the present invention provides a flash memory device, where the flash memory device includes a controller and a storage medium, where the storage medium includes a plurality of physical pages, wherein the controller is configured to perform the first aspect of the embodiment of the present invention.
  • an embodiment of the present invention provides a controller, where the controller is used in a flash memory device, where the flash memory device further includes a storage medium, where the storage medium includes a plurality of physical pages; wherein the controller includes various units, respectively Used to perform various aspects of the first aspect of the embodiments of the present invention.
  • an embodiment of the present invention further provides a computer program product and a non-transitory computer readable storage medium, wherein the computer program product and the non-transitory computer readable storage medium comprise computer instructions, non-volatile computer instructions
  • the storage medium and computer program product, the controller of the flash memory device executes computer instructions for implementing various aspects of the first aspect of the embodiments of the present invention.
  • Figure 1 is a structural diagram of a flash memory device
  • Figure 3 is a schematic diagram of the encoding process
  • FIG. 4 is a structural diagram of a controller in an embodiment of the present invention.
  • the existing flash memory device structure is as shown in FIG. 1.
  • the flash memory device 100 includes a controller 110 and a storage medium 120.
  • the storage medium is composed of a storage unit (Cell) such as a storage unit 1, a storage unit 2, and a storage unit n.
  • the storage unit is the smallest storage structure of the flash device.
  • a flash memory device in which one storage unit stores 1-bit data is called a single level cell (SLC), and a flash memory device in which a storage unit stores 2-bit data is called a multiple level cell (MLC), one storage.
  • a flash memory device in which a unit stores 3-bit data is referred to as a Triple Level Cell (TLC).
  • a number of memory cells make up a physical page, and several physical pages make up a block. The physical page is the smallest unit of reading and writing of the flash device.
  • the flash memory device 100 functions as a common electronic storage device in which stored data is often modified or deleted. Due to the nature of the flash device, the data in the memory cell can only be changed from 0 to 1. If the data from the memory location is to change from 1 to 0, the data can only be erased first and then the new data written.
  • the basic unit of the erase operation of the flash device 100 is not a storage unit, nor a physical page, but a block.
  • One way to solve the frequent data block erasure is to encode the write data into the invalid data physical page, and reduce the number of data erasures. For this reason, the embodiment of the present invention provides a method for writing data in the flash memory device.
  • the controller 110 of the flash memory device 100 receives a data write request; the data write request carries a logical address and data 1.
  • the controller 110 allocates a physical page address 1 to the data 1 when it queries that the logical address does not have a corresponding physical page address.
  • a logical address without a physical page address of 1 indicates that the logical address is the first time data is written.
  • the controller writes data 1 to the storage space pointed to by the physical page address 1, and establishes a mapping relationship between the logical address and the physical page address 1.
  • the write request is used to modify the data in the physical page address 1.
  • the newly written modified data ie, data 2
  • the modified data is the same as most of the data before the modification, and only part of the data changes. Therefore, the data before the modification and the modified data are logically operated. Taking the XOR operation as an example, the result will contain a large number of "0"s and a small number of "1"s.
  • the logical operation in the embodiment of the present invention may be the same or the operation, which is not limited by the embodiment of the present invention.
  • the controller 110 can also determine whether the number of bits of "0" in the data 3 is at the threshold. When the number of bits of "0" is greater than the threshold, it indicates that the difference between the data 2 and the data 1 is small, and may be compression-encoded to the invalid data physical page, then step 203 is performed; when the data 3 is not greater than the threshold, the data 2 and the data are indicated If the difference between 1 is large, the data 2 is allocated the storage space pointed to by the free physical page address 3, and the data 1 stored in the storage space pointed to by the physical page address 1 is marked as invalid data, and the logical address and the physical page address 1 are The mapping relationship is updated to a mapping relationship between a logical address and a physical page address 3.
  • An invalid physical page in the embodiment of the present invention refers to a physical page that stores invalid data.
  • the embodiment of the present invention obtains a data 3 containing a large number of "0"s and a small number of "1"s, and compressing this type of data further increases the compression ratio.
  • the compression algorithm may be a Run Length Encoding (RLE) or a Huffman compression, which is not limited in this embodiment of the present invention.
  • step 204 it may be determined that the data 3 determines whether the compression is successful.
  • the manner of determining whether the compression is successful includes, but is not limited to, whether the compression ratio is greater than a compression threshold.
  • the compression ratio is the ratio of the number of bits (eg, length, size, etc.) of the data 4 to the number of bits of the data 3. If the compression succeeds, step 204 is performed; if the compression fails, the data 2 is allocated the storage space pointed to by the free physical page address 3, and the data 1 stored in the storage space pointed to by the physical page address 1 is marked as invalid data, and the logical address and the physical are The mapping relationship of the page address 1 is updated to the mapping relationship between the logical address and the physical page address 3.
  • the controller 110 performs steps 201-204 to reduce the amount of data that needs to be encoded into the physical page of the invalid data, and fully utilizes the invalid data in the storage space of the invalid data physical page, thereby improving the encoding effect and thereby reducing the data erasure.
  • the number of times increases the life of the flash device.
  • FIG. 3 is a process of encoding an 8-bit data 4 into the storage space of the invalid data physical page, where the data 4 is data. 3 is obtained by Huffman compression.
  • the data 4 is "00111011”
  • the invalid data 7 stored on the physical page of the invalid data pointed to by the physical page address 2 is "001100100001000000”.
  • Data if there are two "1"s in data 7, skip the two bits "1” and verify whether the data bits after two "1"s are writable; As shown in 302-3, if the two-bit data in the data 7 is the same as the group of data 6 to be written, the two bits are kept unchanged, and the next set of data is written in the next two bits; as shown in FIG. As shown in 302-4, if the two bits in data 7 are different from the data to be written in data 6, and are not "11", write the two bits as "11” and continue writing in the last two bits. Enter the next set of data for data 6.
  • step 301 There are various embodiments for obtaining data 6 in step 301.
  • "1" may be replaced by “01” instead of "0" in data 4.
  • a longer code length can be used, for example, a 3-bit code representation of the 3-bit data in the data 4 to achieve the data 5 obtained by encoding the data 4 into the storage space of the invalid data physical page.
  • the embodiments of the present invention do not limit this.
  • Step 205 Record the physical page address 2 storing the encoded data.
  • the manner in which the controller 110 records the physical page address 2 is different in different types of flash devices. If there is a high probability of memory cell damage in a NAND flash device, the NAND flash device will increase the data check mechanism when storing data.
  • the physical page of a flash device with a verification mechanism including storage space and extra space (spare space or spare area). Extra space refers to a piece of address space allocated on the physical page for storing parity data. The extra space size is generally larger than the size of the check data, so there is usually a writable bit in the extra space.
  • the controller 110 stores the physical page address 2 storing the encoded data to the extra space 1 of the physical page where the storage space pointed to by the physical page address 1 is located. Therefore, when the controller 110 reads the physical page address 2 from the extra space of the physical page in which the storage space pointed to by the physical page address 1 is located, it is determined that the data stored in the physical page address 2 is encoded.
  • the controller 110 receives a data read request, and the data read request carries a logical address.
  • the controller reads data 1 from the storage space pointed to by the physical page address 1 according to the mapping relationship between the logical address and the physical page address 1.
  • the controller reads the physical page address 2 storing the encoded data from the extra space of the physical page where the physical page address 1 is located, and then reads the data 5 stored in the storage space pointed to by the physical page address 2, and decodes the data 5 to obtain the data 4,
  • the decompressed data 4 obtains the data 3, and the data 3 and the data 1 are logically operated to obtain the data 2, and the data 2 is the data requested by the data read request.
  • the controller 110 establishes a mapping relationship between a logical address and a physical page address, and generates an identifier.
  • the physical page address physical page address 1 and physical page address 2 are used to indicate that the data in the storage space pointed to by the physical page address is encoded data. For example, 0 is identified as non-encoded data, and 1 is identified as encoded data.
  • the flag bit can be located in a mapping relationship between a logical address and a physical page address.
  • the controller 110 can also maintain a physical page address table as an identifier for recording the type of data stored in the storage space pointed to by the physical page address.
  • the controller receives a data read request, and the data read request carries a logical address.
  • the controller 110 reads the data 1 from the storage space pointed to by the physical page address 1 and the data 5 from the storage space pointed to by the physical page address 2 based on the mapping relationship between the logical address and the physical page address.
  • the controller 110 determines, according to the identifier of the physical page address 2, that the data 5 stored in the storage space pointed to by the physical page address 2 is the encoded data, the controller 110 decodes the data 5 to obtain the data 4, and decompresses the data 4 to obtain the data 3, and the data 3 Performing a logical operation with data 1 yields data 2, which is the data requested by the data read request.
  • the identifiers may be used to identify the data types stored in the physical page address 1 and the physical page address 2, which are not limited in this embodiment of the present invention.
  • the identifier may be a location in the mapping table, such as a first column recording logical address, a second column recording a physical page address 1 storing the encoded data, and a third column for recording the physical storage of the encoded data.
  • the page address 2 in this implementation manner, generates a mapping relationship between the logical address and the physical address page address, and generates an identifier, which is an entry that generates a mapping relationship between the recorded logical address and the physical page address.
  • the controller 110 in the flash memory device has a specific structure as shown in FIG. 4, and includes a receiving unit 410, a reading unit 420, a logical operation unit 430, a compression processing unit 440, an encoding processing unit 450, and a record generation.
  • Unit 460 The receiving unit 410 is configured to receive a data write request, where the data write request carries the logical address and the first data; and the flash device stores the mapping relationship between the logical address and the first physical page address.
  • the reading unit 420 is configured to read the second data from the storage space pointed by the first physical page address according to the mapping relationship between the logical address and the first physical page address.
  • the logic operation 430 unit is configured to perform logical operations on the first data and the second data to obtain the third data.
  • the compression processing unit 440 is configured to compress the third data to obtain the fourth data.
  • the encoding processing unit 350 is configured to encode the fourth data into the storage space of the invalid data physical page to obtain the fifth data, and the address of the storage space of the invalid data physical page is the second physical page address.
  • the record generation unit 460 is for recording the second physical page address storing the encoded data.
  • the controller 110 is specifically configured to store the second physical page address to the extra space of the physical page where the storage space pointed by the first physical page address is located. Further, the controller 110 further includes a verification unit, configured to calculate verification data of the fifth data, and store the verification data to an additional space of a physical page where the storage space pointed by the second physical page address is located. Further, the receiving unit 410 is further configured to receive a data read request, where the data read request carries a logical address; the reading unit 420 is further configured to point from the first physical page address according to a mapping relationship between the logical address and the first physical page address.
  • the storage space reads the second data, and reads a second physical page address storing the encoded data from an extra space of the physical page where the storage space pointed to by the first physical page address is located, and the second physical page address is from the second physical page address according to the second physical page address
  • the pointed storage space reads the fifth data;
  • the encoding processing unit 350 is further configured to decode the fifth data to obtain the fourth data;
  • the compression processing 440 unit is further configured to decompress the fourth data to obtain the third data;
  • the logical operation unit 430 is further configured to: Performing the logical operation on the third data and the second data to obtain the first data.
  • the record generation unit 460 is specifically configured to establish a mapping relationship between a logical address and a physical page address, and generate an identifier; wherein the physical page address includes the first physical page address and the first The two physical page addresses, the record generation unit marks the first physical page address and the second physical page address, and identifies data in the storage space pointed to by the second physical page address as encoded data.
  • the receiving unit 410 is further configured to receive a data read request, where the data read request carries a logical address; the reading unit 420 is further configured to: according to the mapping relationship between the logical address and the physical page address, the storage space pointed from the first physical page address Reading the second data, reading the fifth data from a storage space pointed by the second physical page address; the record generating unit 460 is configured to determine, according to the identifier, that the fifth data is encoded data; the encoding processing unit 350 is further configured to decode The fifth data is used to obtain the fourth data; the compression processing unit 440 is further configured to decompress the fourth data to obtain the third data; the logic operation unit 430 is further configured to perform the logic operation on the third data and the second data to obtain the The first data is described.
  • the controller 110 shown in FIG. 4 further includes a determining unit, configured to compress the third data to obtain fourth data, and determine that the number of bits of 0 in the third data is less than a threshold.
  • the determining unit is further configured to: before encoding the fourth data into the storage space of the second physical page to obtain the fifth data, determining that the third data compression is successful.
  • each unit can be implemented by a corresponding hardware chip, for example, the receiving unit corresponds to the interface card chip, the reading unit, and the logical operation unit corresponding logical operation.
  • the chip, the compression processing unit corresponds to the compression chip, the encoding processing unit corresponds to the encoding processing chip, and the recording generating unit stores the chip.
  • one or more of the units may be integrated on a single hardware chip.
  • the logical operation unit performs a logical operation on the input data, and the compression processing unit compresses or decompresses the input data, and the encoding processing chip encodes or decodes the input data.
  • controller 110 may also be implemented by a processor executing computer instructions.
  • This embodiment of the present invention does not limit this.
  • an embodiment of the present invention provides a non-volatile storage medium and a computer program product including computer instructions.
  • the processor of the flash memory device executes computer instructions for implementing the solution described in the embodiments of the present invention.
  • the flash memory device in the embodiment of the present invention may be a solid state hard disk, an acceleration card, an SD card, or the like.
  • the flash memory device can also be a storage array composed of a solid state hard disk using an Open Channel.
  • the disclosed apparatus and method may be implemented in other manners.
  • the division of the units described in the device embodiments described above is only one logical function division, and may be further divided in actual implementation, for example, multiple units or components may be combined or may be integrated into another system, or Some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

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Abstract

本方案提供一种闪存设备数据写入的方法和设备：闪存设备接收携带逻辑地址和第一数据的数据写请求，通过逻辑地址对应的物理地址读取第二数据，得到第二数据与第一数据的差值第三数据，压缩第三数据得到第四数据，将第四数据编码为第五数据存储于无效数据物理页。本方案可以充分利用无效数据物理页的存储空间中的无效数据，提高了编码效果，进而减少了数据擦除次数，延长了闪存设备的使用寿命。

Description

闪存设备中数据写入的方法及设备 技术领域
本发明涉及信息技术领域，尤其涉及闪存设备中数据写入的方法及设备。
背景技术
闪存设备是一种在断电情况下仍能保持所存储的数据信息的存储器，其应用包括但不限于固态硬盘、安全数字(Secure Digital,SD)卡等。由于闪存设备的物理特性的限制，闪存设备中数据写入的比特位只能由0变至1，而不能从1变至0。因此，闪存写过之后，在第二次写之前必须对其进行擦除操作。但是，闪存设备的擦除次数有上限，达到上限时，闪存设备无法继续使用。
现有技术中闪存设备收到写请求，将待写入数据直接编码到物理页中，从而避免进行数据擦除。由于该种编码需要用使用大量的比特位来表示待写入数据，编码效果差。
发明内容
本申请提供了一种数据访问的方法、主机、非易失性计算机可读存储介质和数据访问的装置，本申请中，主机的物理接口卡在主机上运行的虚拟机未安装物理接口卡的驱动程序的情况下，仍然能够对虚拟机进行数据访问。
一方面，本发明实施例提供一种闪存设备中数据写入方案，其中该闪存设备包括控制器和存储介质，该存储介质包含多个物理页；该案具体包括：
该控制器接收数据写请求；该数据写请求携带逻辑地址及第一数据；其中，该闪存设备存储有该逻辑地址与第一物理页地址的映射关系；该控制器根据该逻辑地址与该第一物理页地址的映射关系从该第一物理页地址指向的存储空间读取第二数据，将该第一数据与该第二数据进行逻辑运算得到第三数据，压缩该第三数据得到第四数据，将该第四数据编码到无效数据物理页的存储空间得到第五数据；该无效数据物理页的存储空间的地址为第二物理页地址，该控制器记录存储被编码数据的第二物理页地址。其中，该逻辑运算可以为异或运算或同或运算。本方案通过将写入逻辑地址的第一数据与已经写入同一个逻辑地址的第二数据进行逻辑运算，因为写入相同逻辑地址中的第一数据相对已经写入相同逻辑地址的第二数据只有部分发生变化，因此通过逻辑运算，如异或逻辑运算得到的第三数据会包含大量的0，少量的1，将减少了需要编码到无效数据物理页中的数据量，因此可以充分利用无效数据物理页的存储空间中的无效数据，提高了编码效果，进而减少了数据擦除次数，延长了闪存设备的使用寿命。
结合第一方面，在第一方面的第一种可能实现方式中，该控制器记录该第二物理页地址，具体包括：该控制器将该第二物理页地址存储到该第一物理页地址指向的存储空间所在的物理页的额外空间。
结合第一方面的第一种可能实现方式，在第一方面的第二种可能实现方式中，该方案还包括：该控制器计算该第五数据的校验数据，该控制器将该校验数据存储在该 第二物理页地址指向的存储空间所在的物理页的额外空间。校验数据可以用于在在读取第五数据时通过该校验数据验证该第五数据的准确性，如第五数据发生错误，可以通过该校验数据进行恢复，提高了数据的可靠性。
结合第一方面的第一种或第二种可能的实现方式，在第一方面的第三种可能实现方式中，所述方案还包括：该控制器接收数据读请求；该数据读请求携带所述逻辑地址；该控制器根据该逻辑地址与该第一物理页地址的映射关系从该第一物理页地址指向的存储空间读取该第二数据，从该第一物理页地址指向的存储空间所在的物理页的额外空间读取存储该被编码数据的该第二物理页地址，根据该第二物理页地址从该第二物理页地址指向的存储空间读取该第五数据，解码该第五数据得到该第四数据，解压缩该第四数据得到该第三数据，将该第三数据与该第二数据进行该逻辑运算得到该第一数据。
结合第一方面，在第一方面的第四种可能实现方式中，该控制器记录第二物理页的地址，具体包括：该控制器建立所述逻辑地址与该物理页地址的映射关系，并生成标识；其中该物理页地址包含该第一物理页地址和该第二物理页地址，该标识用于指示该第二物理页地址指向的存储空间中的数据为被编码数据。进一步的，控制器生成标识具体可以为生成标识位来指示第二物理页地址中指向的存储空间中的数据类型。例如用0指示为非被编码的数据，1指示为被编码的数据。控制器也可以维护一个物理页地址表作为标识，用于指示物理页地址指向的存储空间中存储的数据类型。
结合第一方面的第四种可能实现方式，在第一方面的第五种可能实现方式中，该方案还包括：该接收数据读请求；该数据读请求携带该逻辑地址；该控制器根据该逻辑地址与该物理页地址的映射关系从该第一物理页地址指向的存储空间中读取该第二数据，从该第二物理页地址指向的存储空间读取该第五数据，根据该标识，确定该第五数据为被编码数据；该控制器解码该第五数据得到该第四数据，解压缩该第四数据得到该第三数据，将该第三数据与该第二数据进行该逻辑运算得到该第一数据。结合第一方面，在第一方面的第六种可能实现方式中，该方案还包括：所述控制器压缩该第三数据得到第四数据之前，确定该第三数据中0的位数小于阈值。
结合第一方面，在第一方面的第七种可能实现方式中，该方案还包括：该控制器将该第四数据编码到无效数据物理页的存储空间得到第五数据之前，确定该第三数据压缩成功。
第二方面，本发明实施例提供了一种闪存设备，该闪存设备包括控制器和存储介质，该存储介质包含多个物理页，其中，该控制器用于执行本发明实施例第一方面中的各种方案。
第三方面，本发明实施例提供了一种控制器，该控制器用于闪存设备，该闪存设备还包括存储介质，该存储介质包含多个物理页；其中，该控制器包含各种单元，分别用于执行本发明实施例第一方面中的各种方案。
第四方面，本发明实施例还提供了计算机程序产品和非易失性计算机可读存储介质，其中计算机程序产品和非易失性计算机可读存储介质中包含计算机指令，计算机指令的非易失性存储介质和计算机程序产品，闪存设备的控制器执行计算机指令用于实现本发明实施例第一方面中的各种方案。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作以简单地介绍。
图1为闪存设备结构图；
图2为数据二次写入的流程图；
图3为编码过程示意图；
图4为本发明实施例中一种控制器结构图。
具体实施方式
现有闪存设备结构如图1所示，闪存设备100包含控制器110和存储介质120。存储介质由存储单元(Cell)构成，如存储单元1、存储单元2、存储单元n。存储单元为闪存设备的最小的存储结构。一个存储单元存储1比特数据的闪存设备称为单级存储单元(Single Level Cell,SLC)，一个存储单元存储2比特数据的闪存设备称为多级存储单元(Multiple Level Cell,MLC)，一个存储单元存储3比特数据的闪存设备称为为三级存储单元(Triple Level Cell，TLC)。若干个存储单元组成物理页，若干个物理页组成块。其中物理页是闪存设备最小的读写单位。
闪存设备100作为常用电子存储设备，其中存储的数据会经常被修改或删除。由于闪存设备的自身的特性，存储单元中的数据只能从0变为1。如果从存储单元中的数据要从1变为0，只能先将数据擦除，再写入新数据。闪存设备100的擦除操作的基本单元不是存储单元，也不是物理页，而是块。解决频繁数据块擦除的一种方式为将写入数据编码到无效数据物理页中，减少数据擦除次数，为此，本发明实施例提供了一种闪存设备中数据写入的方法。
本发明实施例中，闪存设备100的控制器110接收数据写请求；数据写请求携带逻辑地址和数据1。控制器110查询逻辑地址没有对应的物理页地址时，为数据1分配物理页地址1。逻辑地址没有物理页地址1表明该逻辑地址是首次写入数据。控制器将数据1写入物理页地址1指向的存储空间，建立逻辑地址与物理页地址1的映射关系。当闪存设备100的控制器110再次接收携带上述逻辑地址和数据2的写请求，则执行图2中所示的如下流程：
201：根据该逻辑地址与物理页地址1的映射关系从该物理页地址1指向的存储空间读取数据1。
202：将数据1与数据2进行逻辑运算得到数据3。
当控制器110再次接收携带该逻辑地址的写请求，此次写请求用于修改物理页地址1中的数据。在闪存设备中，新写入的修改数据，即数据2，并不覆盖物理页地址1中的数据，而是将数据2写到新的物理页地址中。在实际应用中，修改后的数据与修改前的数据相比，大部分数据相同，只有部分数据发生改变。因此，将修改前的数据与修改后的数据进行逻辑运算，以异或操作为例，结果中会包含大量的“0”，少量的“1”。当然本发明实施例中的逻辑运算也可以为同或操作，本发明实施例对此不作限定。
控制器110还可以判断数据3中“0”的位数是否在于阈值。当“0”的位数大于阈值，则表明数据2与数据1中差异较小，可经过压缩编码到无效数据物理页，则执 行步骤203；当数据3不大于阈值，则表明数据2与数据1中差异较大，则为数据2分配空闲的物理页地址3指向的存储空间，并物理页地址1指向的存储空间中存储的数据1标为无效数据，将逻辑地址与物理页地址1的映射关系更新为逻辑地址与物理页地址3的映射关系。本发明实施例中的无效物理页是指存储无效数据的物理页。
203：压缩数据3得到数据4。
本发明实施例在步骤202的操作中得到包含大量的“0”，少量的“1”的数据3，对这种类型的数据进行压缩会进一步提高压缩率。具体实现中，压缩算法可以为流程长度编码(Run Length Encoding,RLE)或哈夫曼压缩等，本发明实施例对此不作限定。
进一步的，控制器执行步骤204之前，可以判断数据3判断是否压缩成功。判断压缩是否成功的方式包括但不限于压缩率是否大于压缩阈值。其中一种实现方式，压缩率为数据4的位数(如长度、大小等)与数据3的位数的比值。压缩成功则执行步骤204；压缩失败，则为数据2分配空闲的物理页地址3指向的存储空间，并物理页地址1指向的存储空间中存储的数据1标为无效数据，将逻辑地址与物理页地址1的映射关系更新为逻辑地址与物理页地址3的映射关系。
204：将数据4编码到无效数据物理页的存储空间得到数据5，其中，无效数据物理页的存储空间的地址为物理页地址2。
控制器110进行步骤201-204操作，减少了需要编码到无效数据物理页中的数据量，充分利用了无效数据物理页的存储空间中的无效数据，提高了编码效果，进而减少了数据擦除次数，延长了闪存设备的使用寿命。
将数据4编码到无效数据物理页的存储空间得到数据5，一种实现方式如下所示：图3为一段8位的数据4编码到无效数据物理页的存储空间的过程，其中数据4为数据3经哈夫曼压缩得到。图中，数据4为“00111011”，物理页地址2指向的无效数据物理页上存储的无效的数据7为“001100100001000000”。
301：“01”代替数据4中的“0”，“10”代替数据4中的“1”，得到数据6。
302：将数据6中的数据以两位为一组数据写入数据7中的0位，不可写位标记为“11”，得到数据5；除去不可写位，数据5与数据6完全相同。写入过程为：如图3中302-1所示，若数据7中有两位“0”，则在两位“0”中写入数据6的一组数据，并继续写入下一组数据；如图3中302-2所示，若数据7中有两位“1”，则跳过两位“1”，验证两位“1”之后的数据位是否可写；如图3中302-3所示，若数据7中的两位数据与待写入的一组数据6相同，保持这两位不变，并继续在其后两位写入下一组数据；如图3中302-4所示，若数据7中两位与数据6中待写入的一组数据不同，且不为“11”，将这两位写为“11”，并继续在其后两位写入数据6的下一组数据。
步骤301中得到数据6还可以有多种实施例。例如，可以“01”代替数据4中的“1”，“10”代替数据4中的“0”。同时，可采用较长的编码长度，例如用4位编码表示数据4中的3位数据，来实现将数据4编码到无效数据物理页的存储空间得到数据5。本发明实施例对此不做限制。
步骤205：记录存储被编码数据的物理页地址2。
具体实现中，控制器110记录物理页地址2的方式在不同类型的闪存设备中的实 现方式不同。如与非(NAND)闪存设备出现存储单元损坏的概率较大，NAND闪存设备在存储数据时，会增加数据校验机制。具有校验机制的闪存设备的物理页，包括存储空间和额外空间(spare space或spare area)。额外空间，指的是物理页上分配出的用于存储校验数据的一段地址空间。额外空间大小一般大于校验数据的大小，因此额外空间中通常会存在有可写位。因此，在NAND闪存设备中，控制器110会将存储被编码数据的物理页地址2存储到物理页地址1指向的存储空间所在的物理页的额外空间1。因此，当控制器110从物理页地址1指向的存储空间所在的物理页的额外空间读取物理页地址2，则确定物理页地址2中存储的为被编码的数据。
根据上述NAND闪存设备中物理页地址2的存储方式，控制器110接收数据读请求，数据读请求携带逻辑地址。控制器根据逻辑地址与物理页地址1的映射关系，从物理页地址1中指向的存储空间读取数据1。控制器从物理页地址1所在的物理页的额外空间中读取存储被编码数据的物理页地址2，后读取物理页地址2指向的存储空间存储的数据5，解码数据5得到数据4，解压缩数据4得到数据3，将数据3与数据1进行逻辑运算得到数据2，数据2即为数据读请求所请求的数据。
另外一种实现方式，控制器110建立逻辑地址与物理页地址的映射关系，并生成标识。其中，物理页地址物理页地址1和物理页地址2，标识用于指示物理页地址指向的存储空间中的数据为被编码数据。例如用0标识为非被编码数据，1标识被编码数据。该标识位可以位于逻辑地址与物理页地址的映射关系中。控制器110也可以维护一个物理页地址表作为标识，用于记录物理页地址指向的存储空间中存储的数据类型。控制器接收数据读请求，数据读请求携带逻辑地址。控制器110根据逻辑地址与物理页地址的映射关系，从物理页地址1中指向的存储空间读取数据1，从物理页地址2指向的存储空间中数据5。控制器110根据物理页地址2的标识确定物理页地址2指向的存储空间存储的数据5为被编码的数据，控制器110解码数据5得到数据4，解压缩数据4得到数据3，将数据3与数据1进行逻辑运算得到数据2，数据2即为数据读请求所请求的数据。具体实现中，可以分别用标识来标识物理页地址1和物理页地址2中存储的数据类型，本发明实施例对此不作限定。另一种实现，标识可以为映射表中的位置，如第一列记录逻辑地址，第二列记录存储被编码的数据的物理页地址1，第三列用于记录存储被编码的数据的物理页地址2，在这种实现方式中，生成逻辑地址与物理地址页地址的映射关系，并生成标识，是指生成记录逻辑地址与物理页地址的映射关系的表项。
与本发明实施例相对应，闪存设备中的控制器110具体结构如图4所示，包括接收单元410、读取单元420、逻辑运算单元430、压缩处理单元440、编码处理单元450和记录生成单元460。其中，接收单元410用于接收数据写请求，数据写请求携带逻辑地址及第一数据；闪存设备存储有逻辑地址与第一物理页地址的映射关系。读取单元420用于根据逻辑地址与第一物理页地址的映射关系从第一物理页地址指向的存储空间读取第二数据。逻辑运算430单元用于将第一数据与第二数据进行逻辑运算得到第三数据。压缩处理单元440用于压缩第三数据得到第四数据。编码处理单元350用于将第四数据编码到无效数据物理页的存储空间得到第五数据，该无效数据物理页的存储空间的地址为第二物理页地址。记录生成单元460用于记录存储被编码数据的第 二物理页地址。
如图4所示的控制器110，一种实现方式，记录生成单元460具体用于将第二物理页地址存储到第一物理页地址指向的存储空间所在的物理页的额外空间。进一步的，所述控制器110还包括校验单元，用于计算第五数据的校验数据，将校验数据存储到第二物理页地址指向的存储空间所在的物理页的额外空间。进一步的，其中，接收单元410还用于接收数据读请求，数据读请求携带逻辑地址；读取单元420还用于根据逻辑地址与第一物理页地址的映射关系从第一物理页地址指向的存储空间读取第二数据，从第一物理页地址指向的存储空间所在的物理页的额外空间读取存储被编码数据的第二物理页地址，根据第二物理页地址从第二物理页地址指向的存储空间读取第五数据；编码处理单元350还用于解码第五数据得到第四数据；压缩处理440单元还用于解压缩第四数据得到第三数据；逻辑运算单元430还用于将述第三数据与所述第二数据进行所述逻辑运算得到所述第一数据。
如图4所示的控制器110，另一种实现方式，记录生成单元460具体用于建立逻辑地址与物理页地址的映射关系，并生成标识；其中物理页地址包含第一物理页地址和第二物理页地址,记录生成单元标记第一物理页地址和第二物理页地址，标识用于指示第二物理页地址指向的存储空间中的数据为被编码数据。进一步的，其中，接收单元410还用于接收数据读请求，数据读请求携带逻辑地址；读取单元420还用于根据逻辑地址与物理页地址的映射关系从第一物理页地址指向的存储空间读取第二数据，从第二物理页地址指向的存储空间读取所述第五数据；记录生成单元460用于根据标识，确定第五数据为被编码数据；编码处理单元350还用于解码第五数据得到第四数据；压缩处理单元440还用于解压缩第四数据得到第三数据；逻辑运算单元430还用于将述第三数据与所述第二数据进行所述逻辑运算得到所述第一数据。
如图4所示的控制器110，还包括确定单元用于压缩所述第三数据得到第四数据之前，确定第三数据中0的位数小于阈值。所述确定单元还用于将第四数据编码到第二物理页的存储空间得到第五数据之前，确定第三数据压缩成功。
图4中所示的控制器110的具体实现可参考前面实施例中描述，其中各单元可以分别由对应的硬件芯片实现，如接收单元对应接口卡芯片、读取单元、逻辑运算单元对应逻辑运算芯片、压缩处理单元对应压缩芯片、编码处理单元对应编码处理芯片，记录生成单元存储芯片。在另一种实现中，一个或多个单元可以集成在一个硬件芯片上。其中逻辑运算单元对输入的数据进行逻辑运算操作，压缩处理单元对输入的数据进行压缩或解压缩处理，编码处理芯片对输入的数据进行编码或解编码。在另一种实现中，控制器110中的各单元也可以由处理器执行计算机指令实现。本发明实施例对此不作限定。相应的，本发明实施例提供一种包含计算机指令的非易失性存储介质和计算机程序产品，闪存设备的处理器执行计算机指令用于实现本发明实施例所描述的方案。
本发明实施例中的闪存设备可以为固态硬盘、加速卡、SD卡等。闪存设备还可以为使用开放通道(Open Channel)的固态硬盘组成的存储阵列等。
在本发明所提供的几个实施例中，应该理解到，所公开的装置、方法，可以通过其它的方式实现。例如，以上所描述的装置实施例所述单元的划分，仅仅为一种逻辑 功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。

Claims (24)

  1. 一种闪存设备中数据写入的方法，其特征在于，所述闪存设备包括控制器和存储介质，所述存储介质包含多个物理页；所述方法包括：
    所述控制器接收数据写请求；所述数据写请求携带逻辑地址及第一数据；其中，所述闪存设备存储有所述逻辑地址与第一物理页地址的映射关系；
    所述控制器根据所述逻辑地址与所述第一物理页地址的映射关系从所述第一物理页地址指向的存储空间读取第二数据；
    所述控制器将所述第一数据与所述第二数据进行逻辑运算得到第三数据；其中，所述逻辑运算为异或操作或同或操作；
    所述控制器压缩所述第三数据得到第四数据；
    所述控制器将所述第四数据编码到无效数据物理页的存储空间得到第五数据；所述无效数据物理页的存储空间的地址为第二物理页地址；
    所述控制器记录存储被编码数据的所述第二物理页地址。
  2. 如权利要求1所述方法，其特征在于，所述控制器记录存储被编码数据的所述第二物理页地址，具体包括：所述控制器将所述第二物理页地址存储到所述第一物理页地址指向的存储空间所在的物理页的额外空间。
  3. 如权利要求2所述方法，其特征在于，还包括：所述控制器将所述第五数据的校验数据存储在所述第二物理页地址指向的存储空间所在的物理页的额外空间。
  4. 如权利要求2或3所述的方法，其特征在于，所述方法还包括：
    所述控制器接收数据读请求；所述数据读请求携带所述逻辑地址；
    所述控制器根据所述逻辑地址与所述第一物理页地址的映射关系从所述第一物理页地址指向的存储空间读取所述第二数据；
    所述控制器从所述第一物理页地址指向的存储空间所在的物理页的额外空间读取存储所述被编码数据的所述第二物理页地址，；
    所述控制器根据所述第二物理页地址从所述第二物理页地址指向的存储空间读取所述第五数据；
    所述控制器解码所述第五数据得到所述第四数据；
    所述控制器解压缩所述第四数据得到所述第三数据；
    所述控制器将所述第三数据与所述第二数据进行所述逻辑运算得到所述第一数据。
  5. 如权利要求1所述的方法，其特征在于，所述控制器记录存储被编码数据的第二物理页的地址，具体包括：所述控制器建立所述逻辑地址与所述物理页地址的映射关系，并生成标识；其中所述物理页地址包含所述第一物理页地址和所述第二物理页地址，所述标识用于指示所述第二物理页地址指向的存储空间中的数据为被编码数据。
  6. 如权利要求5所述的方法，其特征在于，所述方法还包括：
    所述控制器接收数据读请求；所述数据读请求携带所述逻辑地址；
    所述控制器根据所述逻辑地址与所述物理页地址的映射关系从所述第一物理页地址指向的存储空间中读取所述第二数据，从所述第二物理页地址指向的存储空间读取所述第五数据；
    所述控制器根据所述标识，确定所述第五数据为被编码数据；
    所述控制器解码所述第五数据得到所述第四数据；
    所述控制器解压缩所述第四数据得到所述第三数据；
    所述控制器将所述第三数据与所述第二数据进行所述逻辑运算得到所述第一数据。
  7. 如权利要求1所述的方法，其特征在于，所述方法还包括：所述控制器压缩所述第三数据得到第四数据之前，确定所述第三数据中0的位数小于阈值。
  8. 如权利要求1所述的方法，其特征在于，所述方法还包括：所述控制器将所述第四数据编码到无效数据物理页的存储空间得到第五数据之前，确定所述第三数据压缩成功。
  9. 一种闪存设备，其特征在于，所述闪存设备包括控制器和存储介质，所述存储介质包含多个物理页；其中，所述控制器用于执行如下操作：
    接收数据写请求；所述数据写请求携带逻辑地址及第一数据；其中，所述闪存设备存储有所述逻辑地址与第一物理页地址的映射关系；
    根据所述逻辑地址与所述第一物理页地址的映射关系从所述第一物理页地址指向的存储空间读取第二数据；
    将所述第一数据与所述第二数据进行逻辑运算得到第三数据；其中，所述逻辑运算为异或操作或同或操作；
    压缩所述第三数据得到第四数据；
    将所述第四数据编码到无效数据物理页的存储空间得到第五数据；所述无效数据物理页的存储空间的地址为第二物理页地址；
    记录存储被编码数据的所述第二物理页地址。
  10. 如权利要求9所述的闪存设备，其特征在于，所述控制器具体用于将所述第二物理页地址存储到所述第一物理页地址指向的存储空间所在的物理页的额外空间。
  11. 如权利要求10所述的闪存设备，其特征在于，所述控制器还用于计算所述第五数据的校验数据，将所述校验数据存储在所述第二物理页地址指向的存储空间所在的物理页的额外空间。
  12. 如权利要求10或11所述的闪存设备，其特征在于，所述控制器还用于执行如下操作：
    接收数据读请求；所述数据读请求携带所述逻辑地址；
    根据所述逻辑地址与所述第一物理页地址的映射关系从所述第一物理页地址指向的存储空间读取所述第二数据；
    从所述第一物理页地址指向的存储空间所在的物理页的额外空间读取存储所述被编码数据的所述第二物理页地址；
    根据所述第二物理页地址从所述第二物理页地址指向的存储空间读取所述第五数据；
    解码所述第五数据得到所述第四数据；
    解压缩所述第四数据得到所述第三数据；
    将所述第三数据与所述第二数据进行所述逻辑运算得到所述第一数据。
  13. 如权利要求9所述的闪存设备，其特征在于：所述控制器具体用于建立所述逻辑地址与所述物理页地址的映射关系，并生成标识；其中所述物理页地址包含所述 第一物理页地址和所述第二物理页地址，所述标识用于指示所述第二物理页地址指向的存储空间中的数据为被编码数据。
  14. 如权利要求13所述的闪存设备，其特征在于，所述控制器还用于执行如下操作：
    接收数据读请求；所述数据读请求携带所述逻辑地址；
    根据所述逻辑地址与所述物理页地址的映射关系从所述第一物理页地址指向的存储空间中，读取所述第二数据，从所述第二物理页地址指向的存储空间读取所述第五数据；
    根据所述标识，确定所述第五数据为被编码数据；
    解码所述第五数据得到所述第四数据；
    解压缩所述第四数据得到所述第三数据；
    将所述第三数据与所述第二数据进行所述逻辑运算得到所述第一数据。
  15. 如权利要求9所述的闪存设备，其特征在于：所述控制器还用于压缩所述第三数据得到第四数据之前，确定所述第三数据中0的位数小于阈值。
  16. 如权利要求9所述的闪存设备，其特征在于，所述控制器还用于：将所述第四数据编码到无效数据物理页的存储空间得到第五数据之前，确定所述第三数据压缩成功。
  17. 一种控制器，其特征在于，所述控制器用于闪存设备；所述闪存设备还包括存储介质，所述存储介质包含多个物理页；所述控制器包括接收单元、读取单元、逻辑运算单元、压缩处理单元、编码处理单元和记录生成单元；其中，所述接收单元用于接收数据写请求；所述数据写请求携带逻辑地址及第一数据；所述闪存设备存储有所述逻辑地址与第一物理页地址的映射关系；
    所述读取单元用于根据所述逻辑地址与所述第一物理页地址的映射关系从所述第一物理页地址指向的存储空间读取第二数据；
    所述逻辑运算单元用于将所述第一数据与所述第二数据进行逻辑运算得到第三数据；其中，所述逻辑运算为异或操作或同或操作；
    所述压缩处理单元用于压缩所述第三数据得到第四数据；
    所述编码处理单元用于将所述第四数据编码到无效数据物理页的存储空间得到第五数据；所述无效数据物理页的存储空间的地址为第二物理页地址；
    所述记录生成单元用于记录存储被编码数据的所述第二物理页地址。
  18. 如权利要求17所述的控制器，其特征在于，所述记录生成单元具体用于将所述第二物理页地址存储到所述第一物理页地址指向的存储空间所在的物理页的额外空间。
  19. 如权利要求18所述的控制器，其特征在于，所述控制器还包括校验单元，所述校验单元用于计算所述第五数据的校验数据，将所述校验数据存储到第二物理页地址指向的存储空间所在的物理页的额外空间。
  20. 如权利要求18或19所述的控制器，其特征在于，所述接收单元还用于接收数据读请求；所述数据读请求携带所述逻辑地址；
    所述读取单元还用于根据所述逻辑地址与所述第一物理页地址的映射关系从所述 第一物理页地址指向的存储空间读取所述第二数据，从所述第一物理页地址指向的存储空间所在的物理页的额外空间读取存储所述被编码数据的所述第二物理页地址，根据所述第二物理页地址从所述第二物理页地址指向的存储空间读取所述第五数据；
    所述编码处理单元还用于解码所述第五数据得到所述第四数据；
    所述压缩处理单元还用于解压缩所述第四数据得到所述第三数据；
    所述逻辑运算处理单元还用于将所述第三数据与所述第二数据进行所述逻辑运算得到所述第一数据。
  21. 如权利要求17所述的控制器，其特征在于，所述记录生成单元具体用于建立所述逻辑地址与物理页地址的映射关系，并生成标识；其中物理页地址包含所述第一物理页地址和所述第二物理页地址，所述标识用于指示所述第二物理页地址指向的存储空间中的数据为被编码数据。
  22. 如权利要求21所述的控制器，其特征在于，所述接收单元还用于接收数据读请求，所述数据读请求携带所述逻辑地址；
    所述读取单元还用于根据所述逻辑地址与所述物理页地址的映射关系从所述第一物理页地址指向的存储空间读取所述第二数据，从所述第二物理页地址指向的存储空间读取所述第五数据；
    所述记录生成单元还用于根据所述标识，确定所述第五数据为被编码数据；
    所述编码处理单元还用于解码所述第五数据得到所述第四数据；
    所述压缩处理单元还用于解压缩所述第四数据得到所述第三数据；
    所述逻辑运算处理单元还用于将所述第三数据与所述第二数据进行所述逻辑运算得到所述第一数据。
  23. 如权利要求17所述的控制器，其特征在于：所述控制器还包括确定单元，所述确定单元用于在压缩所述第三数据得到所述第四数据之前，确定所述第三数据中0的位数小于阈值。
  24. 如权利要求17所述的控制器，其特征在于，所述控制器还包括确定单元：所述确定单元将所述第四数据编码到无效数据物理页的存储空间得到第五数据之前，确定所述第三数据压缩成功。
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