WO2019005146A1

WO2019005146A1 - Magnetoelectric spin orbit logic with semi insulating magnet

Info

Publication number: WO2019005146A1
Application number: PCT/US2017/040472
Authority: WO
Inventors: Sasikanth Manipatruni; Dmitri Nikonov; Huichu Liu; Tanay Karnik; Ian Young
Original assignee: Intel Corporation
Priority date: 2017-06-30
Filing date: 2017-06-30
Publication date: 2019-01-03

Abstract

An apparatus is provided which comprises: a first semi-insulating magnet; a first magnet with non-insulating properties adjacent to the first semi-insulating magnet; a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse spin-orbit coupling effect; a second semi-insulating magnet; a second magnet with non-insulating properties adjacent to the second semi-insulating magnet; a magnetoelectric layer adjacent to the second magnet; and a conductor coupled to at least a portion of the stack of layers and the magnetoelectric layer.

Description

MAGNETOELECTRIC SPIN ORBIT LOGIC WITH SEMI INSULATING MAGNET BACKGROUND

[0001] Spintronics is the study of intrinsic spin of the electron and its associated magnetic moment in solid-state devices. Spintronic logic are integrated circuit devices that use a physical variable of magnetization or spin as a computation variable. Such variables can be non-volatile (e.g., preserving a computation state when the power to an integrated circuit is switched off). Non-volatile logic can improve the power and computational efficiency by allowing architects to put a processor to un-powered sleep states more often and therefore reduce energy consumption. Existing spintronic logic generally suffer from high energy and relatively long switching times.

[0002] For example, large write current (e.g., greater than 100 μΑ/bit) and voltage

(e.g., greater than 0.7 V) are needed to switch a magnet (i.e., to write data to the magnet) in Magnetic Tunnel Junctions (MTJs). Existing Magnetic Random Access Memory (MRAM) based on MTJs also suffer from high write error rates (WERs) or low speed switching. For example, to achieve lower WERs, switching time is slowed down which degrades the performance of the MRAM. MTJ based MRAMs also suffer from reliability issues due to tunneling current in the spin filtering tunneling dielectric of the MTJs e.g., magnesium oxide (MgO).

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Fig. 1A illustrates magnetization response to applied magnetic field for a ferromagnet.

[0005] Fig. IB illustrates magnetization response to applied magnetic field for a paramagnet.

[0006] Fig. 1C illustrates magnetization response to applied voltage field for a paramagnet connected to a magnetoelectric layer.

[0007] Fig. 2A illustrates a magnetoelectric spin orbit (MESO) logic using semi- insulating magnets, according to some embodiments of the disclosure. [0008] Fig. 2B illustrates a spin orbit material stack at the input of an interconnect, according to some embodiments of the disclosure.

[0009] Fig. 2C illustrates a magnetoelectric material stack at the output of an interconnect, according to some embodiments of the disclosure.

[0010] Fig. 3 illustrates a MESO logic operable as a repeater, according to some embodiments.

[0011] Fig. 4 illustrates a MESO logic operable as an inverter, according to some embodiments.

[0012] Fig. 5 illustrates a top view of a layout of the MESO logic, according to some embodiments.

[0013] Fig. 6 illustrates a majority gate using MESO devices, according to some embodiments.

[0014] Fig. 7 illustrates a top view of a layout of the majority gate of Fig. 6,

according to some embodiments.

[0015] Fig. 8 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with MESO Logic, according to some embodiments.

DETAILED DESCRIPTION

[0016] The Magnetoelectric (ME) effect has the ability to manipulate the

magnetization (and the associated spin of electrons in the material) by an applied electric field. Since an estimated energy dissipation per unit area per magnet switching event through the ME effect is an order of magnitude smaller than with spin-transfer torque (STT) effect, ME materials have the capability for next-generation memory and logic applications.

[0017] Various embodiments describe a semi-insulating magnet based

Magnetoelectric Spin Orbit Logic (MESO) which is a combination of various physical phenomena for spin-to-charge and charge-to-spin conversion. In some embodiments, spin-to- charge conversion is achieved via a layer with the inverse Rashba-Edelstein effect (or spin Hall effect) wherein a spin current injected from an input semi -insulating magnet produces a charge current. The sign of the charge current is determined by the direction of the injected spin and thus of magnetization. In some embodiments, charge-to-spin conversion is achieved via magnetoelectric effect in which the charge current produces a voltage on a capacitor, comprising a layer with magnetoelectric effect, leading to switching magnetization of an output semi-insulating magnet. In some embodiments, magnetic response of a semi- insulating magnet is according to an applied exchange bias from the magnetoelectric effect. [0018] There are many technical effects of various embodiments. For example, high speed operation of the logic (e.g., 100 picoseconds (ps)) is achieved via the use of magnetoelectric switching operating on semi-insulating nanomagnets. In some examples, switching energy is reduced (e.g., 1-10 attojoules (aJ)) because the current needs to be "on" for a shorter time (e.g., approximately 3 ps) in order to charge the capacitor. In some examples, in contrast to the spin current, here charge current does not attenuate when it flows through an interconnect. In some embodiments, fatigue of ferro-electrics (e.g., a decrease of the maximum absolute value of polarization in switching after multiple cycles of switching) is mitigated by use of semi -insulting materials. In some embodiments, static direct current path is replaced with a capacitor in the spin-to-charge conversion part of the logic device. In some embodiments, voltage in the magnetoelectric module (charge to spin conversion) and the spin-orbit module (spin to charge conversion) adjacent to a magnet can vary

independently and over a wider range due to electrical isolation of these modules. Other technical effects will be evident from various embodiments and figures.

[0019] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0020] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0021] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0022] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0023] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0024] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure. The term "MN" indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.) and the term "MP" indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).

[0025] Fig. 1A illustrates a magnetization hysteresis plot 100 for ferromagnet 101.

The plot shows magnetization response to applied magnetic field for ferromagnet 101. The x-axis of plot 100 is magnetic field 'FT while the y-axis is magnetization 'm'. For ferromagnet (FM) 101, the relationship between 'FT and 'm' is not linear and results in a hysteresis loop as shown by curves 102 and 103. The maximum and minimum magnetic field regions of the hysteresis loop correspond to saturated magnetization configurations 104 and 106, respectively. In saturated magnetization configurations 104 and 106, FM 101 has stable magnetizations. In the zero magnetic field region 105 of the hysteresis loop, FM 101 does not have a definite value of magnetization, but rather depends on the history of applied magnetic fields. For example, the magnetization of FM 101 in configuration 105 can be either in the +x direction or the -x direction for an in-plane FM. As such, changing or switching the state of FM 101 from one magnetization direction (e.g., configuration 104) to another magnetization direction (e.g., configuration 106) is time consuming resulting in slower nanomagnets response time. It is associated with the intrinsic energy of switching proportional to the area in the graph contained between curves 102 and 103. In some embodiments, the above described dependences of magnetization on the applied magnetic field are similar in magnets with high electric conductivity and low electric conductivity.

[0026] Fig. IB illustrates magnetization plot 120 for paramagnet 121. Plot 120 shows the magnetization response to applied magnetic field for paramagnet 121. The x-axis of plot 120 is magnetic field 'FT while the y-axis is magnetization 'm'. A paramagnet, as opposed to a ferromagnet, exhibits magnetization when a magnetic field is applied to it. Paramagnets generally have magnetic permeability greater or equal to one and hence are attracted to magnetic fields. Compared to plot 100, the magnetic plot 120 of Fig. IB does not exhibit hysteresis which allows for faster switching speeds and smaller switching energies between the two saturated magnetization configurations 124 and 126 of curve 122. In the middle region 125, paramagnet 121 does not have any magnetization because there is no applied magnetic field (e.g., H=0). The intrinsic energy associated with switching is absent in this case.

[0027] Fig. 1C illustrates plot 130 showing magnetization response to applied voltage field for a paramagnet 131 connected to a magnetoelectric layer 132. Here, the x-axis is voltage 'V applied across ME layer 132 and y-axis is magnetization 'm'. Ferroelectric polarization 'PFE' is in ME layer 132 is indicated by an arrow. In this example,

magnetization is driven by exchange bias exerted by a ME effect from ME layer 132. When positive voltage is applied to ME layer 132, paramagnet 131 establishes a deterministic magnetization (e.g., in the +x direction by voltage +V_C) as shown by configuration 136. When negative voltage is applied by ME layer 132, paramagnet 131 establishes a

deterministic magnetization (e.g., in the -x direction by voltage -V_c) as shown by

configuration 134. Plot 130 shows that magnetization functions 133a and 133b have hysteresis. In some embodiments, by combining ME layer 132 with paramagnet 131, switching speeds of paramagnet as shown in Fig. IB are achieved. In some embodiments, the hysteresis behavior of FM 131, as shown in Fig. 1C, is associated with the driving force of switching rather than the intrinsic resistance of the magnet to switching. In some embodiments, the above described dependences of magnetization on the applied magnetic field are similar in magnets with high electric conductivity and low electric conductivity.

[0028] Fig. 2A illustrates a MESO logic 200 using semi-insulating or insulating magnets, according to some embodiments of the disclosure. Fig. IB illustrates a material stack at the input of an interconnect, according to some embodiments of the disclosure. Fig. 2C illustrates a magnetoelectric SOL material stack at the output of an interconnect, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 2A-C having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0029] In some embodiments, MESO logic 200 comprises a first semi-insulating magnet 201 , a stack of layers (e.g., layers 202, 203, and 204, also labeled as 202a/b, 203a/b, and 204a/b), interconnecting conductor 205 (e.g., a non-magnetic charge conductor), magnetoelectric (ME) layer 206 (206a/b), second semi-insulating magnet 207, contacts 208a, 208b, 208c, and 208d, first magnet 209a, and second magnet 210a. third magnet 209b, and fourth magnet 210b.

[0030] In some embodiments, first and second semi-insulating magnet 201 and 207, respectively, have in-plane magnetic anisotropy. Here the term "semi-insulating magnet" generally refers to a material that has magnetic properties but has higher resistivity compared to normal ferromagnets. For example, semi-insulating or insulating magnets may not be conductive for charge current, but exhibit magnetic properties. The semi-insulating magnet or insulating magnet may be a magnetic oxide. In some embodiments, materials for semi insulating or insulating magnets include one of: TiO?., Y₃Fe₅0i₂ (YiG), GdsGasO (GGG).

[0031] In some embodiments, the semi-insulating magnet may have a Perovskite crystal structure ABO3. In some embodiments, materials for semi-insulating or insulating magnets include one of: La2MnNi06, La2CoMn06. The semi-insulating magnet or insulating magnet may have a Spinel crystal structure AB2O4. In some embodiments, materials for semi-insulating or insulating magnets include one of: Fe203, C02O3, Co2Fe04, or Ni2Fe04, ZnFe₂04, MgFe₂0₄, MnFe₂Q₄, CoFe₂0, NiFe₂Q4, and Lio.5Fe₂ sQ₄. In some embodiments, elements for semi-insulating or insulating magnets include one or more of: Fe, O, Co or Ni.

[0032] In some embodiments, first semi-insulating magnet 201 comprises first and second portions, wherein the first portion of first semi-insulating magnet 201 is adjacent to first magnet 209a, and wherein the second portion of first semi -insulating magnet 201 is adjacent to third magnet 210b. In some embodiments the direction of magnetization in magnets 201 , 209a, and 210b is approximately the same and stores the value of the logic bit. In some embodiments, second semi-insulating magnet 207 comprises first and second portions, wherein the first portion of second semi -insulating magnet 207 is adjacent to second magnet 210a, and wherein the second portion of second semi-insulating magnet 207 is adjacent to fourth magnet 209b. In some embodiments the direction of magnetization in magnets 207, 209b, and 210a is approximately the same and stores the value of the logic bit.

[0033] In some embodiments, ME layer 206a is adjacent to second magnet 207. In some embodiments, conductor 205 (or charge interconnect) is coupled to at least a portion of the stack of layers and ME layer 206a. For example, conductor 205 is coupled to layer 204a of the stack.

[0034] In some embodiments, the stack of layers is to provide an inverse Rashba-

Edelstein effect (or inverse spin Hall effect). In some embodiments, the stack of layers provide spin-to-charge conversion where a spin current /? (or spin energy J_s) is injected from first magnet 209a and charge current I_c is generated by the stack of layers. This charge current I_c is provided to conductor 205 (e.g., charge interconnect). In contrast to spin current, charge current does not attenuate in conductor 205. The direction of the charge current I_c depends on the direction of magnetization of first magnet 209a.

[0035] In some embodiments, the charge current I_c charges the capacitor around ME layer 206a and switches its polarization. ME layer 206a exerts exchange bias on second magnet layer 210a, and the direction of the exchange bias determines the magnetization of second magnet 210a. In some embodiments, the magnetization of first semi-insulating magnet 201 is determined by the magnetization of third magnet 210b. For example, when third magnet 210b has magnetizations pointing in -y direction, then first semi-insulating magnet 201 has magnetization pointing in the -y direction. In some embodiments, the magnetization of second semi-insulating magnet 207 is determined by the magnetization of second magnet 210a. For example, when second magnet 210a has magnetizations pointing in -y direction, then second semi-insulating magnet 207 has magnetization pointing in the -y direction.

[0036] In this example, the length of first semi-insulating magnet is L_m, the width of conductor 205 is W_c, the length of conductor 205 from the interface of layer 204 to ME layer 206a is Lc, t_c is the thickness of the semi-insulating magnets 201 and 207, and ΪΜΕ is the thickness of ME layer 206a. In some embodiments, conductor 205 comprises a material including one of: Cu, Ag, Al, or Au.

[0037] In some embodiments, the input and output charge conductors (21 l a and

21 1b, respectively) and associated spin-to-charge and charge-to-spin converters are provided. In some embodiments, input charge current Idiarge(iN) is provided on interconnect 21 la (e.g., charge interconnect made of same material as interconnect 205). In some embodiments, interconnect 21 la is coupled to first semi-insulating magnet 201 via ME layer 206b. In some embodiments, interconnect 21 la is orthogonal to first semi-insulating magnet 201. For example, interconnect 211a extends in the +x direction while first semi-insulating magnet 201 extends in the -y direction. In some embodiments, Idiarge(iN) is converted to

corresponding magnetic polarization of 201 by ME layer 206b. The materials for ME layers 206a/b are the same as the materials of ME layer 206.

[0038] In some embodiments, an output interconnect 21 lb is provided to transfer output charge current Icharge(OUT) to another logic or stage. In some embodiments, output interconnect 211b is coupled to second semi -insulating magnet 207 via a stack of layers that exhibit spin Hall effect and/or Rashba Edelstein effect. For example, layers 202b, 203b, and 204b are provided as a stack to couple output interconnect 211b with second semi-insulating magnet 207 via fourth magnet 209b. Material wise, layers 202b, 203b, and 204b are formed of the same material as layers 202a, 203a, and 204a, respectively.

[0039] In some embodiments, a transistor (e.g., p-type transistor MPl) is coupled to contact 208b. In this example, the source terminal of MPl is coupled to a supply Vdd, the gate terminal of MPl is coupled to a control voltage V_ci (e.g., a switching clock signal, which switches between Vdd and ground), and the drain terminal of MPl is coupled to contact 208b. Contacts 202a/b/c/d can me made of any suitable conducting non-magnetic material. For example, Contacts 202a/b/c/d comprise the same material as conductor 205. In some embodiments, the current Idrive from transistor MPl generates spin current into the stack of layers (e.g., layers 202a, 203a, and 204a).

[0040] In some embodiments, along with the p-type transistor MPl connected to Vdd

(or an n-type transistor connected to Vdd but with gate overdrive above Vdd), an n-type transistor MN1 (not shown) is provided which couples to contact 206b, where the n-type transistor is operable to couple ground (or 0V) to contact 206b. In some embodiments, n- type transistor MN2 (not shown) is provided which is operable to couple ground (or 0V) to contact 208c. In some embodiments, additional transistors can be added to discharge/reset the ME stack.

[0041] In some embodiments, p-type transistor MP2 is provided which is operable to couple power supply (Vdd or -Vdd) to contact 208c. For example, when clock is low (e.g., Vci=0V), then transistor MPl is on and Vdd is coupled to contact 208b (e.g., power supply is Vdd) and 0V is coupled to contact 208c. This provides a potential difference for charge current to flow. Continuing with this example, when clock is high (e.g., V_ci=Vdd and power supply is Vdd), then transistor MPl is off, transistor MNl is on, and transistor MN2 is off. As such, 0V is coupled to contact 208b.

[0042] In some embodiments, the power supply is a negative power supply (e.g.,

Vdd). In that case, then transistor MPl 's source is connected to 0V, and transistor MNl 's source is connected to -Vdd, and transistor MN2 is on. When Vd = 0V and power supply is - Vdd , then transistor MNl is on, and transistor MPl is off, and transistor MN2 (whose source is at -Vdd ) is off and MP2 whose source is 0V is on. In this case, -Vdd is coupled to input magnet 201 and 0V is coupled to output magnet 207. This also provides a path for charge current to flow. Continuing with this example, when clock is high (e.g., V_ci=-Vdd and power supply is -Vdd), then transistor MPl is off, transistor MNl is on, and transistor MN2 is off. As such, 0V is coupled to input magnet 201.

[0043] In some embodiments, ME layer 206a/b forms the magnetoelectric capacitor to switch the semi-insulating magnets 201/207 via the non-insulating magnets 210a/b. For example, the conductor 205 forms one plate of the capacitor, semi-insulating magnet 207 forms the other plate of the capacitor, and layer 206a is the magnetic-electric oxide that provides out-of-plane exchange bias to semi-insulating magnet 207 via magnet 210a.

[0044] The first magnet 209a injects a spin polarized current into the high spin-orbit coupling (SOC) material stack (e.g., layers 202a, 203a, and 204a). The spin polarization is determined by the magnetization of first magnet 209a (which is same as magnetization of semi-insulating magnet 201). In some embodiments, the stack comprises i) an interface 203 with a high density 2D (two dimensional) electron gas and with high SOC formed between 202 and 204 materials such as Ag or Bi, or ii) a bulk material 204 with high Spin Hall Effect (SHE) coefficient such as Ta, W, or Pt.

[0045] In some embodiments, a spacer (or template layer) is formed between first semi-insulating magnet 201 and the injection stack. In some embodiments, this spacer is a templating metal layer which provides a template for forming first magnet 209a. In some embodiments, the metal of the spacer which is directly coupled to first magnet 209a is a noble metal (e.g., Ag, Cu, or Au) doped with other elements from Group 4d and/or 5d of the Periodic Table. In some embodiments, first magnet 209a (and by extension first semi- insulating magnet 201) are sufficiently lattice matched to Ag (e.g., a material which is engineered to have a lattice constant close (e.g., within 3%) to that of Ag).

[0046] Here, sufficiently matched atomistic crystalline layers refer to matching of the lattice constant 'a' within a threshold level above which atoms exhibit dislocation which is harmful to the device (for instance, the number and character of dislocations lead to a significant (e.g., greater than 10%) probability of spin flip while an electron traverses the interface layer). For example, the threshold level is within 5% (i.e., threshold levels in the range of 0% to 5% of the relative difference of the lattice constants). As the matching improves (i.e., matching gets closer to perfect matching), spin injection efficiency from spin transfer from first magnet 209a to first ISHE/ISOC stacked layer increases. Poor matching (e.g., matching worse than 5%) implies dislocation of atoms that is harmful for the device.

[0047] Table 1 summarizes transduction mechanisms for converting magnetization to charge current and charge current to magnetization for bulk materials and interfaces.

Table 1: Transduction mechanisms for Spin to Charge and Charge to Spin Conversion

[0048] The following section describes the spin to charge and charge to spin dynamics. In some embodiments, the spin-orbit mechanism responsible for spin-to-charge conversion is described by the inverse Rashba-Edelstein effect in 2D electron gases. The Hamiltonian (energy) of spin-orbit coupling electrons in a 2D electron gas is:

H_R = a_R(kxz). σ

where a_Ris the Rashba-Edelstein coefficient, 'k' is the operator of momentum of electrons, z is a unit vector perpendicular to the 2D electron gas, and σ is the operator of spin of electrons.

[0049] The spin polarized electrons with direction of polarization in-plane (e.g., in the xy -plane) experience an effective magnetic field dependent on the spin direction:

a_R .

B(k)=— (fcxz)

where i_Bis the Bohr magneton

[0050] This results in the generation of a charge current h in interconnect 205 proportional to the spin current (or J_s). The spin-orbit interaction by Ag and Bi interface layers 202 and 204 (e.g., the Inverse Rashba-Edelstein Effect (IREE)) produces a charge current h in the horizontal direction given as: where w_m is width of the input semi -insulating magnet 201, and λ_1ΚΕΕ is the IREE constant (with units of length) proportional to a_R.

[0051] Alternatively, the Inverse Spin Hall Effect in Ta, W, or Pt layer 203 produces the horizontal charge current I_c given as:

2w_m

[0052] Both IREE and ISHE effects produce spin-to-charge current conversion around 0.1 with existing materials at 10 nm (nanometers) magnet width. For scaled nanomagnets (e.g., 5 nm wide magnets) and exploratory SHE materials such as Bi2Se3, the spin-to-charge conversion efficiency can be between 1 and 2.5. The net conversion of the drive charge current Idnve to magnetization dependent charge current is given as:

j _± REEP _{for IREE md I} + OsHEtsHEPIs _foj. _jg_jjg

w_m 2w_m

where 'P' is the dimensionless spin polarization. For this estimate, the drive current Idnve and the charge current I_c = I_d = 100 μΑ is set. As such, when estimating the resistance of the ISHE interface to be equal to R = 100 Ω, then the induced voltage is equal to V_ISHE =

10 mV.

[0053] The charge current I_c, carried by interconnect 205, produces a voltage on the capacitor of ME layer 206a comprising magnetoelectric material dielectric (such as BiFeCb (BFO) or CnCb) in contact with second magnet 210a (which serves as one of the plates of the capacitor) and interconnect 205 (which series as the other of the plates of the capacitor). In some embodiments, magnetoelectric materials are either intrinsic multiferroic or composite multiferroic structures. As the charge accumulates on the magnetoelectric capacitor of ME layer 206a, a strong magnetoelectric interaction causes the switching of magnetization in second magnet 210a (and by extension second semi -insulating magnet 207).

[0054] For the following parameters of the magnetoelectric capacitor: thickness

^ME ⁼ 5 nm, dielectric constant ε = 500, area A = 60 nm x 20 nm. Then the capacitance is given as:

εε_ηΑ

C =—2- « IfF

^ME

[0055] Demonstrated values of the magnetoelectric coefficient is a_ME~10/c , where the speed of light is c. This translates to the effective magnetic field exerted on second semi- insulating magnet 207, which is expressed as:

BME = a_MEE = -0.06Γ

t-ME This is a strong field sufficient to switch magnetization.

[0056] The charge on the capacitor of ME layer 206a is Q =— x lO mV = 10 aC, and the time to fully charge it to the induced voltage is td = 10 y- ~ 1 ps (with the account of decreased voltage difference as the capacitor charges). If the driving voltage is V_d =

100 mV, then the energy E_sw to switch is expressed as:

which is comparable to the switching energy of CMOS transistors. Note that the time to switch t_sw magnetization remains much longer than the charging time and is determined by the magnetization precession rate. The micro-magnetic simulations predict this time to be t_sw~100ps, for example.

[0057] In some embodiments, materials for first and second semi-insulating magnets

201 and 207, respectively, have saturated magnetization M_s and effective anisotropy field Hk. Saturated magnetization M_s is generally the state reached when an increase in applied external magnetic field H cannot increase the magnetization of the material. Anisotropy Hk generally refers material properties that are highly directionally dependent.

[0058] In some embodiments, first and second semi-insulating magnets 201 and 207, respectively, comprise a material which includes one or more of: Co, Fe, No, or O. In some embodiments, the first and second semi-insulating magnets 201 and 207, respectively, comprise a material which includes one or more of: C02O3, Fe203, Co2Fe04,or Ni2Fe04. In some embodiments, first and second semi-insulating magnets 201 and 207 have Spinel crystal structure.

[0059] In some embodiments, magnets 209a/b and 210a/b have non-insulating properties. For example, magnets 209a/b and 210a/b can be paramagnets or ferromagnets.

[0060] A paramagnet, as opposed to a ferromagnet, exhibits magnetization when a magnetic field is applied to it. Paramagnets generally have magnetic permeability greater or equal to one and hence are attracted to magnetic fields. In some embodiments, magnets 209a/b and 210a/b comprise a material which includes one or more of: Platinum(Pt), Palladium (Pd), Tungsten (W), Cerium (Ce), Aluminum (Al), Lithium (Li), Magnesium (Mg), Sodium (Na), CnC (chromium oxide), CoO (cobalt oxide), Dysprosium (Dy), Dy20 (dysprosium oxide), Erbium (Er), EnCb (Erbium oxide), Europium (Eu), EmCb (Europium oxide), Gadolinium (Gd), Gadolinium oxide (Gd2C ), FeO and Fe203 (Iron oxide),

Neodymium (Nd), Nd203 (Neodymium oxide), KO2 (potassium superoxide), praseodymium (Pr), Samarium (Sm), SrmC (samarium oxide), Terbium (Tb), Tb203 (Terbium oxide), Thulium (Tm), T1T12O3 (Thulium oxide), and V2O3 (Vanadium oxide). In some embodiments, the first and second paramagnets 201 and 207 comprise dopants selected from a group consisting of: Ce, Cr, Mn, Nb, Mo, Tc, Re, Nd, Gd, Tb, Dy, Ho, Er, Tm, and Yb.

[0061] In some embodiments, magnets 209a/b and 210a/b are ferromagnets. In some embodiments, magnets 209a/b and 210a/b comprise one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, Cu₂MnAl, Cu₂MnIn, Cu₂MnSn, Ni₂MnAl, Ni₂MnIn, Ni₂MnSn, Ni₂MnSb, Ni₂MnGa Co₂MnAl, Co₂MnSi, Co₂MnGa,

Co₂MnGe, PdJVInAl, Pd₂MnIn, PdJVInSn, PdJVInSb, Co₂FeSi, Co₂FeAl, Fe₂VAl, Mn₂VGa, Co₂FeGe, MnGa, MnGaRu, or Mn3X, where 'X' is one of Ga or Ge.

[0062] In some embodiments, the stack of layers comprises: a first layer 202a/b comprising Ag, wherein the first layer is adjacent to first magnet 209a/b; and a second layer 204a/b comprising Bi or W, wherein second layer 204a/b is adjacent to first layer 202a/b and to a conductor (e.g., 205, 211b). In some embodiments, a third layer 203a/b (having material which is one or more of Ta, W, or Pt) is sandwiched between first layer 202a/b and second layer 204a/b as shown. In some embodiments, the stack of layers comprises a material which includes one of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[0063] In some embodiments, ME layer 206a/b is formed of a material which includes one of: CnO and multiferroic material. In some embodiments, ME layer 206 comprises Cr and O. In some embodiments, the multiferroic material comprises BFO (e.g., BiFeC ), LFO (LuFeC , LuFe204), or La doped BiFeC . In some embodiments, the multiferroic material includes one of: Bi, Fe, O, Lu, or La. In some embodiments, ME layer 206a/b comprises one of: dielectric, para-electric, or ferro-electric material.

[0064] Fig. 3 illustrates MESO logic 300 operable as a repeater (or buffer), according to some embodiments. It is pointed out that those elements of Fig. 3 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. In some embodiments, to configure the SOL as a repeater, a portion of the stack of the layers (e.g., layer 204) is coupled to ground, contact 208b is coupled to a negative supply (e.g., -Vdd), and contact 208d is coupled to constant voltage V_m. In some embodiments, for repeater MESO logic 300, the magnetization direction of first semi -insulating magnet 201 is the same as the magnetization direction of second semi-insulating magnet 207. For example, the magnetization direction of first semi-insulating magnet 201 is in the +y direction while the magnetization direction of second semi-insulating magnet 207 is also in the +y direction.

[0065] Fig. 4 illustrates MESO logic 400 operable as an inverter, according to some embodiments. It is pointed out that those elements of Fig. 4 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. In some embodiments, to configure the SOL as an inverter, a portion of the stack of the layers (e.g., layer 204) is coupled to ground, contact 208b is coupled to a positive supply (e.g., +Vdd), and contact 208d is coupled to constant voltage Vm. In some embodiments, for inverter MESO logic 400, the magnetization direction of first semi-insulating magnet 201 is opposite compared to the magnetization direction of second semi-insulating magnets 207. For example, the magnetization direction of first semi -insulating magnet 201 is in the +y direction while the magnetization direction of second semi-insulating magnet 207 is in the -y direction.

[0066] SOL devices of various embodiments provide logic cascadability and unidirectional signal propagation (e.g., input-output isolation). The unidirectional nature of logic is ensured due to large difference in impedance for injection path versus detection path, in accordance with some embodiments. In some embodiments, the injector is essentially a metallic spin valve with spin to charge transduction with RA (resistance area) products of approximately 10 mOhrarnicron². In some embodiments, the detection path is a low leakage capacitance with RA products much larger than 1 MOhm. micron² in series with the resistance of the FM capacitor plate with estimated resistance greater than 500 Ohms.

[0067] Fig. 5 illustrates a top view of layout 500 of MESO logic 200, according to some embodiments. An integration scheme for SOL devices with CMOS drivers for power supply and clocking is shown in the top view. Here, transistor MP1 is formed in the active region 501, and power supply is provided via metal layer 3 (M3) indicated as 506. The gate terminal 504 of transistor MP1 is coupled to a supply interconnect 505 through via or contact 503. In some embodiments, M3 layer 507 is coupled to ground which provides ground supply to layer 204. In some embodiments, another transistor can be formed in active region 503 with gate terminal 510. Here, 508 and 509 are contact vias coupled to power supply line. In some embodiments, the density of integration of the devices exceeds that of CMOS since an inverter operation can be achieved within 2.5P x 2M0. In some embodiments, since the power transistor MP1 can be shared among all the devices at the same clock phases, vertical integration can also be used to increase the logic density as described with reference to Fig. 6, in accordance with some embodiments. [0068] Fig. 6 illustrates majority gate 600 using MESO logic devices, according to some embodiments. It is pointed out that those elements of Fig. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. A charge mediated majority gate is proposed using the spin orbit coupling and magnetoelectric switching. A charge mediated majority gate is shown in Fig. 6. Majority gate 600 comprises at least three input stages 601 , 602, and 603 with their respective charge conductors 2051, 2052, and 2053 coupled to summing interconnect 604. In some embodiments, summing interconnect 604 is made of the same materials as interconnect 205. In some embodiments, summing interconnect 604 is coupled to output stage 605 which includes the second semi-insulating magnet 507 (like 207). The three input stages 601 , 602, and 603 share a common power/clock region therefore the power/clock gating transistor can be shared among the three inputs of the majority gate, in accordance with some embodiments. The input stages 601, 602, and 603 can also be stacked vertically to improve the logic density, in accordance with some embodiments. The charge current at the output (Icharge(OUT)) is the sum of currents I_Chi, Ich2, and I_Ch3.

[0069] Fig. 7 illustrates a top view of layout 700 of the majority gate, according to some embodiments. It is pointed out that those elements of Fig. 7 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Majority gate 700 comprises at least three input stages 601/701 , 602/702, and 603/703 with their respective conductors 205i, 2052, and 2053 coupled to summing interconnect 604/702.

[0070] Fig. 8 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with MESO logic, according to some embodiments. It is pointed out that those elements of Fig. 8 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0071] Fig. 8 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0072] In some embodiments, computing device 1600 includes first processor 1610 with MESO logic, according to some embodiments discussed. Other blocks of the computing device 1600 may also include a magnetoelectric SOL, according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0073] In some embodiments, processor 1610 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0074] In some embodiments, computing device 1600 includes audio subsystem

1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0075] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0076] In some embodiments, computing device 1600 comprises I/O controller 1640.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0077] As mentioned above, I/O controller 1640 can interact with audio subsystem

1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[0078] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0079] In some embodiments, computing device 1600 includes power management

1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[0080] Elements of embodiments are also provided as a machine-readable medium

(e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0081] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0082] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[0083] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[0084] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0085] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[0086] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0087] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[0088] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting. [0089] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0090] Example 1 is an apparatus comprising: a first semi-insulating magnet; a first magnet with non-insulating properties adjacent to the first semi -insulating magnet; a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse spin-orbit coupling effect; a second semi-insulating magnet; a second magnet with non-insulating properties adjacent to the second semi-insulating magnet; a magnetoelectric layer adjacent to the second magnet; and a conductor coupled to at least a portion of the stack of layers and the magnetoelectric layer.

[0091] Example 2 includes all features of example 1, wherein the first and second semi-insulating magnets comprises a material which includes one or more of: Co, Fe, Ni, or O.

[0092] Example 3 includes all features of example 1, wherein the first and second semi-insulating magnets comprises a material which includes one or more of: C02O3, Fe203,

[0093] Example 4 includes all features of example 1, wherein the first and second magnets are paramagnets.

[0094] Example 5 is according to any one of examples 1 to 4, wherein the first and second magnets comprises a material which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr₂0₃, CoO, Dy, Dy₂0, Er, Er₂0₃, Eu, Eu₂0₃, Gd, Gd₂0₃, FeO, Fe₂0₃, Nd, Nd₂0₃, KO2, Pr, Sm, Sm₂0₃, Tb, Tb₂0₃, Tm, Tm₂0₃, V, or V₂0₃.

[0095] Example 6 includes all features of example 1, wherein the first and second magnets are ferromagnets.

[0096] Example 7 is according to any one of claims 1 to 3, wherein the first and second magnets comprise one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), or wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, Cu₂MnAl, Cu₂MnIn, Cu₂MnSn, NiJVInAl, Ni₂MnIn, Ni₂MnSn, Ni₂MnSb, Ni₂MnGa Co₂MnAl, Co₂MnSi, Co₂MnGa, Co₂MnGe, Pd₂MnAl, Pd₂MnIn, PdJVInSn, PdJVInSb, Co₂FeSi, Co₂FeAl, Fe₂VAl, Mn₂VGa, Co₂FeGe, MnGa, MnGaRu, or Mn₃X, where 'X' is one of Ga or Ge.

[0097] Example 8 is according to any one of claims 1 to 3, wherein the stack of layers comprises: a first layer comprising Ag, wherein the first layer is adjacent to the first semi- insulating magnet; and a second layer comprising Bi or W, wherein the second layer is adjacent to the first layer and to the conductor.

[0098] Example 9 includes all features of example 1, wherein the conductor includes one or more of: Cu, Ag, Al, or Au.

[0099] Example 10 includes all features of example 1, wherein the magnetoelectric layer includes one of: Cr, O, Cr₂Cb, or multiferroic material.

[00100] Example 11 includes all features of example 10, wherein the multiferroic material includes one of: BiFeC , LuFeC , LuFe204, or La doped BiFeC .

[00101] Example 12 includes all features of example 10, wherein the multiferroic material includes one of: Bi, Fe, O, Lu, or La.

[00102] Example 13 is according to any one of preceding claims, wherein the stack of layers comprises a material which comprises one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[00103] Example 14 includes all features of example 1, and comprises a transistor coupled to the first semi-insulating magnet.

[00104] Example 15 is according to any one of preceding claims, wherein a portion of the stack of the layers is coupled to ground, wherein a contact adjacent to the first magnet is coupled to a negative supply, and wherein a contact adjacent to the second magnet is coupled to ground.

[00105] Example 16 is according to any one of preceding claims, wherein a portion of the stack of the layers is coupled to ground, wherein a contact adjacent to the first magnet is coupled to a positive supply, and wherein a contact adjacent to the second magnet is coupled to ground.

[00106] Example 17 is according to any one of preceding claims, wherein the first and second semi-insulating magnets, and first and second magnets have in-plane magnetic anisotropy.

[00107] Example 18 is an apparatus which comprises: a semi-insulating magnet having a first portion and a second portion; a magnet with non-insulating properties adjacent to the first portion of the semi-insulating magnet; a stack of layers, a portion of which is adjacent to the magnet, wherein the stack of layers is to provide an inverse spin orbit coupling effect; a magnetoelectric layer adjacent to the second portion of the semi-insulating magnet; and a conductor adjacent to the magnetoelectric layer. [00108] Example 19 includes all features of example 18, wherein the semi-insulating magnet includes one or more of: Co, Fe, Ni, or O.

[00109] Example 20 includes features of examples 19 or 20, wherein the semi- insulating magnet includes one or more of: C02O3, Fe203, Co2Fe04, or Ni2Fe04.

[00110] Example 21 is according to any one of examples 18 to 20, wherein the magnetoelectric layer includes one or more of: Cr₂Cb or multiferroic material.

[00111] Example 22 is according to any one of examples 18 to 21, wherein the magnetoelectric layer includes one of: Cr, O, Cr₂Cb or multiferroic material.

[00112] Example 23 includes all features of example 22, wherein the multiferroic material includes one of: BiFeC , LuFeC , LuFe204, or La doped BiFeC .

[00113] Example 24 includes all features of example 22, wherein the multiferroic material includes one of: Bi, Fe, O, Lu, or La.

[00114] Example 25 includes all features of example 18, wherein the stack of layers comprises includes one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[00115] Example 26 is a system which comprises: a memory; a processor coupled to the memory, the processor including an apparatus according to any one of apparatus examples 1 to 17 or apparatus examples 18 to 25; and a wireless interface to allow the processor to communicate with another device.

[00116] Example 27 is a method which comprises: forming a first semi-insulating magnet; forming a first magnet with non-insulating properties adjacent to the first semi- insulating magnet; forming a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse spin-orbit coupling effect;

forming a second semi-insulating magnet; forming a second magnet with non-insulating properties adjacent to the second semi-insulating magnet; forming a magnetoelectric layer adjacent to the second magnet; and forming a conductor coupled to at least a portion of the stack of layers and the magnetoelectric layer.

[00117] Example 28 includes all features of example 27, wherein the first and second semi-insulating magnets includes one or more of: Co, Fe, Ni, or O.

[00118] Example 29 includes all features of example 27, wherein the first and second semi-insulating magnets includes one or more of: C02O3, Fe2Cb, Co2Fe04, or Ni2Fe04.

[00119] Example 30 includes all features of example 29, wherein the first and second magnets are paramagnets. [00120] Example 31 is according to any one of examples 27 to 30, wherein the first and second magnets comprises a material which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr₂0₃, CoO, Dy, Dy₂0, Er, Er₂0₃, Eu, Eu₂0₃, Gd, Gd₂0₃, FeO, Fe₂0₃, Nd, Nd₂0₃, K0₂, Pr, Sm, Sm₂0₃, Tb, Tb₂0₃, Tm, Tm₂0₃, V, or V₂0₃.

[00121] Example 32 includes all features of example 29, wherein the first and second magnets are ferromagnets.

[00122] Example 33 includes all features of example 27, wherein the first and second magnets comprise one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, Cu₂MnAl, Cu₂MnIn, Cu₂MnSn, Ni₂MnAl, Ni₂MnIn, Ni₂MnSn, Ni₂MnSb, Ni₂MnGa Co₂MnAl, Co₂MnSi, Co₂MnGa, Co₂MnGe, Pd₂MnAl, Pd₂MnIn, Pd₂MnSn, Pd₂MnSb, Co₂FeSi, Co₂FeAl, Fe₂VAl, Mn₂VGa, Co₂FeGe, MnGa, MnGaRu, or Mn₃X, where 'X' is one of Ga or Ge.

[00123] Example 34 is according to any one of examples 27 to 33, wherein forming the stack of layers comprises: forming a first layer comprising Ag, wherein the first layer is adjacent to the first semi-insulating magnet; and forming a second layer comprising Bi or W, wherein the second layer is adjacent to the first layer and to the conductor.

[00124] Example 35 is according to any one of examples 27 to 34, wherein the conductor includes one or more of: Cu, Ag, Al, or Au.

[00125] Example 36 is according to any one of examples 27 to 35, wherein the magnetoelectric layer includes one of: Cr, O, Cr₂0₃ or multiferroic material.

[00126] Example 37 includes all features of example 36, wherein the multiferroic material includes: BiFeCb, LuFeC , LuFe204, or La doped BiFeCb.

[00127] Example 38 includes all features of example 36, wherein the multiferroic material includes one of: Bi, Fe, O, Lu, or La.

[00128] Example 39 includes all features of example 27, wherein the stack of layers comprises a material which comprises one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[00129] Example 40 includes all features of example 27, and comprises fabricating a transistor coupled to the first semi-insulating magnet.

[00130] Example 41 includes all features example 27, and comprises: coupling a portion of the stack of the layers to ground; coupling a contact adjacent to the first magnet to a negative supply, and coupling a contact adjacent to the second semi-insulating magnet to ground.

[00131] Example 42 includes all features of example 27, and comprises: coupling a portion of the stack of the layers to ground; coupling a contact adj acent to the first magnet to a positive supply, and coupling a contact adj acent to the second magnet is coupled to ground.

[00132] Example 43 is according to any one of examples 27 to 42, wherein the first and second semi-insulating magnets, and first and second magnets have in-plane magnetic anisotropy.

[00133] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS We claim:

1. An apparatus comprising:

a first semi-insulating magnet;

a first magnet with non-insulating properties adjacent to the first semi-insulating magnet;

a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse spin-orbit coupling effect;

a second semi-insulating magnet;

a second magnet with non-insulating properties adjacent to the second semi- insulating magnet;

a magnetoelectric layer adjacent to the second magnet; and

a conductor coupled to at least a portion of the stack of layers and the magnetoelectric layer.

2. The apparatus of claim 1, wherein the first and second semi -insulating magnets comprises a material which includes one or more of: Co, Fe, Ni, or O.

3. The apparatus of claim 1, wherein the first and second semi -insulating magnets comprises a material which includes one or more of: C02O3, Fe203, Co2Fe04, or Ni2Fe04.

4. The apparatus of claim 1, wherein the first and second magnets are paramagnets.

5. The apparatus according to any one of claims 1 to 4, wherein the first and second magnets comprises a material which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr₂0₃, CoO, Dy, Dy₂0, Er, Er₂0₃, Eu, Eu₂0₃, Gd, Gd₂0₃, FeO, Fe₂0₃, Nd, Nd₂0₃, KO2, Pr, Sm, Sm₂0₃, Tb, Tb₂0₃, Tm, Tm₂0₃, V, or V₂0₃.

6. The apparatus claim 1, wherein the first and second magnets are ferromagnets.

7. The apparatus according to any one of claims 1 to 3, wherein the first and second magnets comprise one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), or wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, Cu₂MnAl, Cu₂MnIn, Cu₂MnSn, Ni₂MnAl, NiJVInln, Ni₂MnSn, Ni₂MnSb, Ni₂MnGa Co₂MnAl, Co₂MnSi, Co₂MnGa, Co₂MnGe, Pd₂MnAl, Pd₂MnIn, Pd₂MnSn, Pd₂MnSb, Co₂FeSi, Co₂FeAl, Fe₂VAl, Mn₂VGa, Co₂FeGe, MnGa, MnGaRu, or Mn3X, where 'X' is one of Ga or Ge.

8. The apparatus according to any one of claims 1 to 3, wherein the stack of layers

comprises:

a first layer comprising Ag, wherein the first layer is adjacent to the first semi- insulating magnet; and

a second layer comprising Bi or W, wherein the second layer is adjacent to the first layer and to the conductor.

9. The apparatus of claim 1, wherein the conductor includes one or more of: Cu, Ag, Al, or Au.

10. The apparatus of claim 1, wherein the magnetoelectric layer includes one of: Cr, O, CnCb, or multiferroic material.

11. The apparatus of claim 10, wherein the multiferroic material includes one of: BiFeC , LuFeC , LuFe204, or La doped BiFeC .

12. The apparatus of claim 10, wherein the multiferroic material includes one of: Bi, Fe, O, Lu, or La.

13. The apparatus according to any one of preceding claims, wherein the stack of layers comprises a material which comprises one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

14. The apparatus of claim 1 comprises a transistor coupled to the first semi-insulating

magnet.

15. The apparatus according to any one of preceding claims, wherein a portion of the stack of the layers is coupled to ground, wherein a contact adjacent to the first magnet is coupled to a negative supply, and wherein a contact adjacent to the second magnet is coupled to ground.

16. The apparatus according to any one of preceding claims, wherein a portion of the stack of the layers is coupled to ground, wherein a contact adjacent to the first magnet is coupled to a positive supply, and wherein a contact adjacent to the second magnet is coupled to ground.

17. The apparatus according to any one of preceding claims, wherein the first and second semi-insulating magnets, and first and second magnets have in-plane magnetic anisotropy.

18. An apparatus comprising:

a semi-insulating magnet having a first portion and a second portion; a magnet with non-insulating properties adjacent to the first portion of the semi- insulating magnet;

a stack of layers, a portion of which is adjacent to the magnet, wherein the stack of layers is to provide an inverse spin orbit coupling effect;

a magnetoelectric layer adjacent to the second portion of the semi-insulating magnet; and

a conductor adjacent to the magnetoelectric layer.

19. The apparatus of claim 18, wherein the semi-insulating magnet includes one or more of:

Co, Fe, Ni, or O.

20. The apparatus of claims 19 or 20, wherein the semi -insulating magnet includes one or more of: C02O3, Fe2Cb, Co2Fe04, or Ni2Fe04.

21. The apparatus according to any one of claims 18 to 20, wherein the magnetoelectric layer includes one or more of: Cr₂Cb or multiferroic material.

22. The apparatus according to any one of claims 18 to 21, wherein the magnetoelectric layer includes one of: Cr, O, Cr₂Cb or multiferroic material.

23. The apparatus of claim 22 wherein the multiferroic material includes one of: BiFeC , LuFeC , LuFe204, or La doped BiFeC , or wherein the multiferroic material includes one of: Bi, Fe, O, Lu, or La.

24. The apparatus of claim 18, wherein the stack of layers comprises includes one or more β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

25. A system comprising: a memory; a processor coupled to the memory, the processor including an apparatus according to any one of apparatus claims 1 to 17 or apparatus claims 18 to 24; and a wireless interface to allow the processor to communicate with another device.