WO2019005031A1 - Diodes à hétérojonction au nitrure de groupe iii n polaire - Google Patents

Diodes à hétérojonction au nitrure de groupe iii n polaire Download PDF

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WO2019005031A1
WO2019005031A1 PCT/US2017/039699 US2017039699W WO2019005031A1 WO 2019005031 A1 WO2019005031 A1 WO 2019005031A1 US 2017039699 W US2017039699 W US 2017039699W WO 2019005031 A1 WO2019005031 A1 WO 2019005031A1
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layer
iii
metal
face
diode structure
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PCT/US2017/039699
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English (en)
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Han Wui Then
Sansaptak DASGUPTA
Marko Radosavljevic
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Intel Corporation
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28581—Deposition of Schottky electrodes
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Definitions

  • Diodes are a common circuit element used in integrated circuits (ICs). Schottky diodes employing a rectifying metal-semiconductor junction are particularly useful for protecting circuitry from over-voltages, such as those associated with electrostatic discharge (ESD) events, because of their relatively low forward voltage. Absent a protection circuit, discharge through a device such as a transistor, can cause catastrophic damage to an IC. Diodic protection circuits may therefore be configured as part of a functional IC to shunt surges in potential away from circuitry that could otherwise be damaged. Group Ill-Nitride (IUPAC 13-N) semiconductor materials offer the benefit of a relatively wide bandgap ( ⁇ 3.4eV), enabling higher breakdown voltages than Si-based devices.
  • IUPAC 13-N Group Ill-Nitride
  • III-N materials also offer high carrier mobility.
  • III-N diodes with sufficiently low on-resistance tend to be an area-intensive circuit element.
  • III-N diode structures offering lower on-resistance for a given area are therefore advantageous at least for enabling dimensional scaling of the device platforms that employ them.
  • FIG. 1 is a schematic of an ESD protection circuit including at least one III-N heteroj unction diode, in accordance with some embodiments;
  • FIG. 2 is a cross-sectional view an exemplary heteroj unction transistor, in accordance with some embodiments;
  • FIG. 3 is a schematic illustrating a Ga-polarity crystal employed in the heteroj unction transistor of FIG. 2, in accordance with some embodiments;
  • FIG. 4 is a schematic illustrating an N-polarity crystal employed in a heteroj unction diode, in accordance with some embodiments;
  • FIG. 5A is a cross-sectional view of III-N heteroj unction diode diodes, in accordance with some embodiments.
  • FIG. 5B is a plan view of III-N heteroj unction diode diodes, in accordance with some embodiments.
  • FIG. 5C is a plan view of III-N heteroj unction diode diodes, in accordance with some embodiments.
  • FIG. 6 is a cross-sectional view of III-N heteroj unction diodes, in accordance with some embodiments.
  • FIG. 7 is a flow diagram illustrating methods of forming a III-N heteroj unction diode, in accordance with some embodiments;
  • FIG. 8 is a cross-sectional view of a N-polar III-N heterostructure, in accordance with some embodiments.
  • FIG. 9A and 9B are cross-sectional views illustrating exposure of an N-face of a III-N heterostructure, in accordance with some embodiments.
  • FIG. 10 is a cross-sectional view illustrating masking of a N-polar III-N
  • heterostructure for a first terminal contact in accordance with some embodiments.
  • FIG. 11 A is a cross-sectional view illustrating formation of a first terminal contact including a non-rectifying metal-semiconductor junction, in accordance with some embodiments;
  • FIG. 1 IB is a cross-sectional view illustrating formation of a first terminal contact including a semiconductor-semiconductor junction, in accordance with some embodiments;
  • FIG. 12A and 12B are cross-sectional views illustrating masking of a N-polar III-N heterostructure for a second terminal contact, in accordance with some embodiments;
  • FIG. 13 A and 13B are cross-sectional views illustrating formation of a second terminal contact including a rectifying metal-semiconductor junction, in accordance with some embodiments;
  • FIG. 14 is a cross-sectional view illustrating formation of a first terminal contact including a non-rectifying metal-semiconductor junction, in accordance with some embodiments;
  • FIG. 15 illustrates a mobile computing platform and a data server machine employing an IC having a III-N heterostructure diode, in accordance with embodiments.
  • FIG. 16 is a functional block diagram of an electronic computing device, in accordance with some embodiments.
  • Coupled may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other.
  • Connected may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other.
  • Coupled may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).
  • over refers to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy.
  • one material or material disposed over or under another may be directly in contact or may have one or more intervening materials.
  • one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers.
  • a first material "on” a second material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies.
  • Diodes employing a Group Ill-Nitride heterostructure are described herein. Diodes in accordance with one or more of the embodiments described herein may provide lower on- resistance for a given diode area relative to conventional diode structures. As described further below, a III-N heterostructure that includes a heteroj unction between a first (upper) layer or lamella of a III-N material on the N-face of a second (lower) layer of a III-N material is employed within a diode.
  • a two-dimensional charge carrier sheet (e.g., 2D electron gas) may be induced within the first III-N material layer, rather than buried below the heteroj unction as for a Ga-polarity III-N material layer.
  • a two-dimensional charge carrier sheet e.g., 2D electron gas
  • top-side terminal contacts may access the two-dimensional charge carrier sheet without any need to first etch a recess through a III- N layer.
  • N-polarity top-side terminal contacts may be landed directly onto a pristine surface of the first III-N layer.
  • the charge carrier sheet present within the first III-N material layer may be contacted at a first location by a first top-side metal that forms a non-rectifying metal-semiconductor junction.
  • an impurity-doped semiconductor e.g., having n-type conductivity
  • the charge carrier sheet present within the first III-N material layer may be further contacted at a second location by another metal suitable for forming a rectifying metal-semiconductor (i.e., Schottky) barrier with the N-polar face of the first III-N material layer.
  • the terminal contacts may access the 2D charge carrier sheet over the entire footprint of the terminal contacts rather than relying on access through an edge of the 2D charge carrier sheet, which may have a thickness of only a few nanometers.
  • the diode current injected into and extracted from the 2D charge carrier sheet over a larger area lower on-state resistance may be achieved.
  • quality and/or control of the rectifying metal - semiconductor junction may be improved by landing a work function metal directly on a pristine (e.g., as-grown) N-face of the first III-N material layer rather than forming a metal- semiconductor junction with an etched surface of a III-N material layer.
  • FIG. 1 is schematic of an electrical circuit 100 including at least one III-N
  • Circuit 100 may, for example, be implemented by one or more IC chip, discrete components and combinations thereof. Circuit 100 may be implemented in any electronic device, such as, but not limited to, smartphones, ultrabook computers, embedded devices (e.g., internet of things, automotive applications, etc.), wearables, and the like. In circuit 100, one or more transistors 105 are to be protected from electrical surges by diodes 1 1 1 , 1 12, and 1 13.
  • Transistors 105 include a first terminal (e.g., source) coupled to a first supply rail 106 maintained at a nominal supply voltage (e.g., Vcc), and a second terminal (e.g., drain) coupled to second supply rail 107 maintained at a nominal reference voltage (e.g., Vss).
  • a third terminal (e.g., gate) of transistors 105 is coupled to a signal input 108, which conveys an input voltage Vin.
  • transistors 105 are protected by diodes 1 1 1 and 1 12 connecting signal input 108 to the supply rails 106, 107 (e.g., Vcc and Vss, respectively), and by diode 1 13 connecting supply rail 106 to supply rail 107.
  • diodes 1 1 1, 1 12 and 1 13 are maintained in the off-state (e.g., reverse biased) such that signal input 108 is effectively disconnected from supply rails 106, 107 while transistors 105 are driven by the supply voltage across rails 106, 107.
  • the transient upon experiencing a potential surge between signal input 108 and supply rails 106 and 107, the transient will forward bias one or more of diodes 1 1 1, 1 12 and 1 13, turning them on.
  • Which of diodes 1 1 1, 1 12 and 1 13 become forward biased is dependent on the charge polarity of the surge relative to the supply rail potentials. Charge accumulated at voltage input 108 is thereby dissipated or shunted through the diode path around transistors 105.
  • one or more diodes of a protection circuit employ a III-N heteroj unction having one or more of the features described further below.
  • the lower on-resistance of such diodes may reduce the footprint of circuit 100.
  • transistors 105 are silicon-based, based on another group IV semiconductor, based on a III-V semiconductor, or based on a III-N material
  • at least one of diodes 1 1 1, 1 12 and 1 13 that employ a III-N heteroj unction in accordance with embodiments herein are implemented as discrete devices (i.e., not monolithic with transistors 105).
  • transistors 105 are silicon-based, based on another group IV semiconductor, or based on a III-V semiconductor
  • at least one of diodes 1 1 1, 112 and 1 13 that employ a III-N heteroj unction in accordance with embodiments herein are implemented monolithically with transistor 105 as portions of an IC.
  • any of the III-N heteroj unction diodes described further herein may be employed in circuit 100. Any of the III-N heteroj unction diodes described further herein may also be employed in any other suitable protection circuit designs. Any of the III-N heteroj unction diodes described further herein may also be employed in circuits having functions other than ESD protection (e.g., high voltage power management circuitry).
  • FIG. 2 is a cross-sectional view an exemplary heteroj unction field effect transistor (HFET) 201, in accordance with some embodiments.
  • HFET 201 may be transistor 105 (FIG. 1) that is protected by protection circuitry 100, for example.
  • HFET 201 is a high electron mobility transistors (HEMT), and more specifically, is a metal oxide semiconductor (MOS) HEMT with a top-side gate electrode 251 and a gate dielectric 252.
  • HFET 201 includes a polarization layer 230 over a channel layer 220.
  • Polarization layer 230 may be
  • polarization field strength e.g., spontaneous and/or piezoelectric
  • spontaneous and/or piezoelectric polarization field strengths are sufficiently different between polarization layer 230 and channel semiconductor layer
  • a two-dimensional charge carrier sheet 241 (e.g., 2D electron gas or "2DEG") is formed within channel layer 220 near the heteroj unction with polarization layer 230 in the absence of any externally applied field.
  • 2DEG 2D electron gas
  • top-side gate electrode 251 is recessed into polarization layer 230 to tune threshold voltage (Vt) of the transistor.
  • Vt threshold voltage
  • recessed gate electrode 251 may ensure a positive Vt for an enhancement mode n-type transistor.
  • an impurity-doped source and drain semiconductor 231 is also recessed through polarization layer 230 to access an edge thickness of 2D charge carrier sheet 241 buried below the heteroj unction between polarization layer 230 and channel semiconductor layer 220.
  • Impurity-doped semiconductor 231 is advantageously heavily doped (e.g., with Si for n-type) and is in physical contact with a oplane of channel semiconductor layer 220. Notably however, impurity-doped semiconductor 231 is recessed through a top-side thickness of channel semiconductor layer 220 to ensure a sidewall of impurity-doped semiconductor 231 makes contact with channel semiconductor layer 220 over a thickness within which 2D charge carrier sheet 241 resides. This sidewall coupling results in a lateral injection and collection of charge carriers during operation of transistor 201. With such an architecture it is not necessary to etch through polarization layer 230 in a manner that stops exactly on channel semiconductor layer 220, which may be technically challenging.
  • FIG. 3 is a schematic further illustrating the structure of a Ga-polarity III-N crystal suitable for forming HFET 201, in accordance with some embodiments.
  • III-N heterostructures have monocrystalline
  • microstructure e.g., Wurtzite
  • crystal quality of a III-N crystal may vary dramatically, for example as a function of the techniques employed to form the crystal.
  • dislocation density with layers of a III-N heterostructure ranges between 10 8 -10 n /cm 2 .
  • the Wurtzite crystalline III-N material layers 220 and 230 lack inversion symmetry, and more particularly the ⁇ 0001 ⁇ planes are not equivalent.
  • One of the ⁇ 0001 ⁇ planes is typically referred to as the Ga-face (+c polarity) and the other referred to as the N-face (-c polarity).
  • the oaxis of the III-N materials layers 220 and 230 is shown in FIG. 3 as being substantially normal (e.g., within 5° of normal) to, or "out-of-the-plane" of these layers and/or their interfaces.
  • the illustrated embodiment may be referred to as Ga polarity (+c) because the three bonds of Ga (or other group III element) in material layers 220 and 230 point away from top-side electrode 251 (i.e., toward an underlying substrate or bottom side).
  • the (000-1) plane of III-N layer 230 is proximal to the (0001) plane of III-N material layer 220.
  • 2D charge carrier sheet 241 is formed within material layer 220, for example at about 3-4 nm of the heteroj unction formed with the overlying polarization material layer 230.
  • polarization layer 230 has a higher Al content than channel layer 220.
  • Polarization layer 230 may be binary AIN, as in the example shown in FIG. 3.
  • Polarization layer 230 may also be an AlGaN alloy.
  • Polarization layer 230 may also be an InAIN alloy or a quaternary alloy.
  • Channel layer 220 may be binary GaN, as in the example shown in FIG. 3.
  • Channel layer 220 may also be an AlGaN or InAIN alloy, or even a quaternary alloy, as long as the polarization field strength difference between layers 230 and 220 is sufficient to induce formation of 2D charge carrier sheet 241 within channel layer 220.
  • a III-N heteroj unction diode in accordance with some advantageous embodiments herein includes a III-N crystal with N-polarity.
  • a diode may, for example, be employed as any of the diodes 1 11 , 1 12, or 113 (FIG. 1).
  • FIG. 4 is a schematic further illustrating a III-N crystal with N-polarity. The oaxis orientation of the N-polar crystal is shown in FIG. 4.
  • N-polarity With N-polarity (-c), the three bonds of Ga (or other group III element) in material layers 420 and 430 point toward top-side electrode 451 (or away from an underlying substrate that is not depicted in FIG. 4).
  • the (000-1) plane of underlying III-N layer 430 is proximal to the (0001) plane of overlying III-N material layer 420.
  • 2D charge carrier sheet 241 is formed within material layer 420, for example within about 3-4 nm of the heteroj unction formed with the underlying polarization material layer 430.
  • FIG. 5A is cross-sectional view of III-N heterostructure diodes 501 , in accordance with some embodiments. Any of diodes 1 11 , 1 12, or 113 (FIG. 1) may have one or more of the features further described in the context of III-N heteroj unction diodes 501 , for example. As shown in FIG. 5A, III-N heteroj unction diodes 501 comprise two diodes sharing in common a first terminal (e.g., anode) and having separate second terminals (e.g., cathodes). Although three diode terminals are illustrated in FIG. 5A, various features described in the context of FIG. 5A are also applicable to a single III-N heteroj unction diode having two terminals (cathode and anode).
  • first terminal e.g., anode
  • second terminals e.g., cathodes
  • III-N heteroj unction diodes 501 have a first terminal (e.g., cathode) that includes a metal 451.
  • Metal 451 may be any elemental metal or a metal alloy that forms a suitable metal-semiconductor junction with III-N material layer 420, for example as further described below.
  • Diodes 501 have a second terminal (e.g., anode) that includes a metal 551.
  • Metal 551 may be any elemental metal or a metal alloy that forms a suitable metal-semiconductor junction, for example as further described below.
  • Diodes 501 further include an N-polar crystal having at least one heteroj unction, which is illustrated in FIG.
  • III-N material layer 420 may be considered part of the same diode terminal metal 451, with a rectifying junction between metal 551 and III-N material layer 420.
  • III-N material layer 430 has at least a higher Al content than material layer 420.
  • III-N material layer 430 may be binary A1N, for example.
  • III-N material layer 430 may also be an AlGaN alloy. Exemplary AlGaN embodiments include 25-40% Al (Al x Gai- x N where 0.25 ⁇ x ⁇ 0.4).
  • III-N material layer 430 may alternatively be an InAIN alloy, which is also suitable as a polarization material and may offer advantages with respect to tuning the lattice constant to better match that of one or more other material layers (e.g., layers 420 or 510).
  • Exemplary InAIN embodiments include less than 20% In (In x Ah- x N where 0 ⁇ x ⁇ 0.2), with 17% In having the advantage of an exceptional lattice match with binary GaN.
  • material layer 420 is binary GaN.
  • material layer 420 may alternatively be a tertiary (e.g., InAIN or AlGaN), or a quaternary III-N compound with variations in the group three species and/or the group III concentration varying between material layers 430 and 420 by an amount sufficient to induce 2D charge carrier sheet 241 within material layer 420.
  • quaternary alloys such as In x Ga y Ah- x - y N where 0 ⁇ x ⁇ 0.2, 0 ⁇ y ⁇ 0.2 are also possible for either or both of III-N material layers 420 and 430.
  • At least III-N material layer 420 is intrinsic and not intentionally doped with impurities associated with a particular conductivity type.
  • Material layer 420 in the intrinsic state can be expected to have higher charge carrier mobility than is possible for materials of higher impurity doping.
  • Intrinsic impurity (e.g., Si) levels in material layer 420 is advantageously less than lel7 atoms/cm 3 , and in some exemplary embodiments is between lel4 and lel6 atoms/cm 3 .
  • material layer 420 is intrinsic binary GaN (i-GaN).
  • Material layer 430 may also be intrinsic and not intentionally doped with impurities, for example to simplify formation the III-N heterostructure. Differences in composition within a III-N heterostructure may induce strain within the
  • III-N material layers where lattice constants are not well-matched. Strain levels may be managed through control of material layer composition and thickness so as to avoid film cracking (i.e., relaxation) within a III-N heterostructure. In some exemplary embodiments where III-N material lattice constants are not matched, material layer thicknesses are below the critical thickness to avoid strain relaxation. In other exemplary embodiments where the material layer lattice constant remains the same between different material layers, material layer thicknesses need not be so constrained. As illustrated in FIG. 5A, layer 420 is of a uniform thickness and not recessed at the interfaces of top-side metals 451 and 551.
  • Thickness Tl may therefore be limited to ensure metal 451 and/or metal 551 has a low- resistance coupling with charge carrier sheet 241.
  • III-N material layer 420 has a thickness Tl of at least 3-4 nm to accommodate 2D charge carrier sheet 241. Material layer 420 may be thicker however, particularly to avoid depleting the 2D charge carrier sheet at any Schottky metal-semiconductor junctions formed with III-N material layer 420. Thickness Tl may therefore depend on the metal-semiconductor workfunction difference associated with a Schottky metal-semiconductor junction formed with III-N material layer 420. Thickness Tl may therefore range from 5 nm to 20 nm.
  • Such a thickness range can be readily accommodated where lattice mismatch between layers 420 and 430 is not extreme.
  • metal 451 or metal 551 forms a metal- semiconductor alloy contact that moves the metal-semiconductor interface from a top surface of material layer 420 towards 2D charge carrier sheet 241
  • the upper limit on thickness Tl may be relaxed (e.g., to 15-20 nm). Alloying a contact of one diode terminal may be particularly advantageous where the other diode terminal employs a rectifying contact that requires a greater thickness Tl to avoid charge carrier sheet depletion.
  • the alloying may reduce access resistance that would otherwise result from a greater thickness Tl needed to accommodate a strongly depleting Schottky contact metal.
  • the upper limit on thickness Tl may be lower (e.g., less than 10 nm) with the Schottky contact metal (e.g., metal 451) then selected to have lower depletion width so that 2D charge carrier sheet 241 is not depleted in the vicinity of metal 451.
  • III-N material layer 430 has a thickness T2 of at least 3-4 nm.
  • Material layer 430 may be considerably thicker however, particularly where lattice mismatch between layers 420 and 430 is not extreme.
  • Material layer 430 may be constrained to a lattice mismatch-based critical thickness relative to any underlay er, such as III-N material layer 510.
  • III-N material layer 510 is i-GaN
  • a material layer 430 of binary A1N would be limited to a thickness T2 of only 1 -3 nm.
  • III-N material layer 510 is at least part of a buffer structure upon which material layers 430 and 420 were grown.
  • III-N material layer 510 is also N-polar and may be one of multiple buffer structure layers.
  • III-N material layer 510 may be lattice matched to either of III-N material layer 430 and 420.
  • III-N material layer 510 may be also be mismatched to both of material layers 430 and 420 (e.g., having a lattice constant somewhere between those of layers 430 and 420).
  • thickness T2 may vary widely (e.g., 3-30 nm) as a function of the layer composition within a III-N heterostructure.
  • III-N material layer 510 may further be disposed over any substrate suitable for hosting III-N crystals.
  • material layers 430 and 420 are disposed over a SiC substrate.
  • the substrate is a cubic semiconductor, such as monocrystalline silicon.
  • template structures may be formed on a cubic substrate surface, such as a (100) surface.
  • III-N crystals may also be grown on other surfaces (e.g., 110, 1 11 , miscut or off cut, for example 2- 10° toward [1 10] etc.).
  • Material layers 430, 420 and 510 may also be over a host substrate material upon which the III-N crystal has been bonded, in which case the host substrate may be crystalline, or not (e.g., glass, polymer, etc.).
  • III-N heteroj unction diodes 501 include a first terminal at a first location over the N- polar III-N crystal.
  • This first terminal includes a rectifying metal semiconductor junction (e.g., a semiconductor Schottky barrier).
  • the rectifying metal- semiconductor junction is between the first terminal metal and III-N material within which the 2D charge carrier sheet resides.
  • the 2D charge carrier sheet is a 2D electron gas (2DEG)
  • the III-N material layer 420 within which 2D charge carrier sheet 241 resides is operable as the cathode while top-side metal 451 forms an n-type semiconductor Schottky barrier and is operable as the anode.
  • a 2D charge carrier sheet is a 2D hole gas (2DHG)
  • a III-N material layer within which a 2DHG resides is operable as the anode while the Schottky metal contacting the III-N material layer forms a p-type semiconductor Schottky barrier and is operable as the cathode. Therefore, the composition of metal 451 may be selected based on the metal- semiconductor workfunction difference and surface states of material layer 420 to provide the desired Schottky barrier height relative to the energy level of charge carrier sheet 241. It is also noted that metal 551 may alternatively provide the rectifying metal semiconductor junction in the same manner as is illustrated herein in the context of metal 451.
  • top-side metal 451 makes contact to a top surface of III-N material layer 420
  • the Schottky barrier height may be well-controlled through the metal composition where the top surface of III-N material layer 420 is in pristine "as-grown" condition.
  • Diodes 501 may therefore display I-V curves closer to ideal because, at least in part, metal 451 may contact a surface that has not been previously exposed to damaging processes (e.g., etches) that can introduce uncontrolled surface states (leading to surface pinning, etc.).
  • top-side metal 451 advantageously includes at least one of Ni, W, Pt, or TiN.
  • each of these metals or metallic compounds may be associated with a particular work function (or metal-semiconductor work function difference) that has an impact on layer thickness Tl .
  • Other metals/metallic compounds known to make ohmic contacts to p-type III-N materials may also be suitable for making a rectifying (n-type semiconductor Schottky barrier) contact to a GaN material layer 420.
  • metal 451 is illustrated as homogeneous in FIG. 5A, a stack or laminate of metals may also be employed as the rectifying terminal.
  • III-N heteroj unction diodes 501 include a second terminal at a second location over the N-polar III-N crystal.
  • This second terminal includes a non-rectifying metal semiconductor contact (e.g., an ohmic metal-semiconductor junction or a tunneling junction contact) between top-side metal 451 and III-N material layer 420.
  • top-side metal 451 advantageously includes at least one of Ti, Al, or W.
  • Other metals or metallic compounds known to make ohmic contact to n-type III-N materials may also be suitable for making a ohmic contact to a GaN material layer 420.
  • metal 451 is an alloying contact that forms an alloy 552 with the III-N material layer 420 and is located within thickness Tl .
  • Dielectric material 260 is over III-N material layer 420.
  • Dielectric material 260 may be of any composition known to be suitable as a passivation and/or protective encapsulant of III-N devices, such as, but not limited to silicon oxides (SiO), silicon nitrides (SiN), silicon oxynitrides (SiON), silicon carbonitrides (SiCN), or low-k materials (e.g., carbon doped silicon dioxide (SiOC), porous dielectrics, etc.), and metal oxides (e.g., AI2O3)
  • SiO silicon oxides
  • SiN silicon nitrides
  • SiON silicon oxynitrides
  • SiCN silicon carbonitrides
  • low-k materials e.g., carbon doped silicon dioxide (SiOC), porous dielectrics, etc.
  • metal oxides e.g., AI2O3
  • FIG. 5B and FIG 5C are plan views of III-N heteroj unction diodes 501, in accordance with some embodiments.
  • the dot-dashed A-A' line in FIG. 5B and FIG. 5C denotes the cross-sectional plane illustrated in FIG. 5A.
  • the length (e.g., y-dimension) of diode terminal metals 451 and 551 may be varied to achieve a given on-state resistance. Additionally, or in the alternative, a given on-state resistance may be achieved by varying the number of diode terminal metals 451 and 551 operated in electrical parallel. In either case however, the footprint (area) of the diode will vary as the x or y dimension(s) of the diode terminals vary.
  • Top-side metals 451, 551 may therefore inject/extract charge carriers into/from III-N material layer 420 vertically (e.g., z- axis in FIG. 5A) over the entire area of metal 451, 551.
  • On-state resistance of diodes 501 may therefore scale with the footprint or area of metal 451 and 551, whereas on-state resistance of diodes that rely on a sidewall interface with a 2D charge carrier sheet (e.g., of the type that may be employed for diodes employing Ga-polar III-N crystal) may only scale with the perimeter of their metal contacts.
  • a 2D charge carrier sheet e.g., of the type that may be employed for diodes employing Ga-polar III-N crystal
  • FIG. 6 is a cross-sectional view of III-N heteroj unction diodes 601, in accordance with some alternative embodiments.
  • III-N heteroj unction diodes 601 share many of the structural features of III-N heteroj unction diodes 501 (e.g., FIG. 5A), with the shared features having the same reference number.
  • One terminal of III-N heteroj unction diodes 601 further includes a semiconductor terminal 631 including dopants, which may be employed to form a low resistance non-rectifying contact to III-N material layer 420.
  • a metal 651 forms a metal-semiconductor junction with semiconductor terminal 631. The presence of semiconductor terminal 631 may relax constraints on the composition of metal 651 relative to metal 551 (FIG.
  • impurity-doped semiconductor terminal 631 again lands on a top surface of III-N material layer 420 such that a portion of 2D charge carrier sheet 241 equal to the footprint of impurity-doped semiconductor terminal 631 is accessible at the first terminal.
  • the conductivity type of semiconductor terminal 631 matches the conductivity type of charge carrier sheet 241.
  • III-N material layer 420 is binary GaN and charge carrier sheet 241 is a 2DEG
  • semiconductor terminal 631 has n-type conductivity. Impurity doping levels are advantageously as high as practical (e.g., N+) for lowest diode on-state resistance.
  • n-type doping may be in the form of Si or Ge impurities, for example. Impurity doping levels are advantageously at least lel 7 atom/cm 3 , and more advantageously at least l ei 8 atom/cm 3 .
  • metal 651 may include at least one of Ti, Al, or W, for example. Other metals known to make ohmic contacts to n-type III-N materials may also be suitable for making a ohmic contact to semiconductor terminal 631.
  • Semiconductor terminal 631 also makes contact to a top surface of III-N material layer 420.
  • Semiconductor terminal 631 may have any composition, but is advantageously also a III-N material.
  • impurity-doped semiconductor terminal 631 is epitaxial, having the same crystallinity and orientation as III-N material layer 420.
  • semiconductor terminal 631 has a narrower band gap than that of III-N material layer 420.
  • semiconductor terminal 631 may be an III-N alloy that includes more Indium (In) than material layer 420.
  • semiconductor terminal 631 is InGaN.
  • Exemplary InGaN embodiments include 5-20% In (In x Gai- x N with 5% ⁇ x ⁇ 20%).
  • the III-N alloy composition may be constant or graded between III-N material layer 420 and metal 651.
  • FIG. 7 is a flow diagram illustrating methods 701 for forming III-N heterostructure diodes, in accordance with some embodiments.
  • Methods 701 begin at operation 705 where a substrate including a crystalline seed layer is received.
  • the substrate received at operation 705 may be any of those described above, for example.
  • a III-N epitaxial growth process is employed to grow an N-polar III-N crystal on the substrate seeding surface.
  • Such epitaxial growth may form continuous crystals over an entire surface of a substrate, or may be limited to islands or mesas occupying only a portion of a substrate surface as controlled through a templating pattern.
  • an N-face of III-N crystal grown with any polarity is exposed at operation 710.
  • a III-N crystal may be first grown with Ga-polarity over a substrate, and the substrate then removed to expose the N-face to subsequent processing.
  • Methods 701 continue at operation 715 where a III-N heteroj unction with a 2D sheet charge in the top III-N layer is formed over the N-face of the III-N structure that was provided in operation 710.
  • a III-N polarization layer is first formed and then another III-N material layer in which the charge carrier sheet is to reside is then formed over the III-N polarization layer. Any growth technique may be employed to form any of the layer compositions described above, for example.
  • Methods 701 continue where a non-rectifying (ohmic or tunneling) metal
  • semiconductor contact junction is formed at the exposed surface of the topmost layer of the III-N heterostructure formed at operation 715.
  • Any deposition process suitable for the chosen metal may be employed at operation 720.
  • physical vapor deposition, chemical vapor deposition, or atomic layer deposition may be employed to deposit one or more of the metals or metallic compounds described elsewhere herein.
  • Methods 701 continue at operation 730 where a rectifying (Schottky) metal- semiconductor junction is formed at the exposed surface of the topmost layer of the III-N heterostructure formed at operation 715.
  • Any deposition process suitable for the chosen metal may be employed at operation 720.
  • Methods 701 complete at operation 740 where one or more interlay er dielectrics (ILDs) and/or interconnect routing levels are formed using any techniques known to be suitable for the purpose.
  • ILDs interlay er dielectrics
  • BEOL back-end-of-line
  • transistor 105 is a silicon or III-V transistor and an N-polar III-N crystal has been grown over a portion of a substrate hosting the silicon or III-V transistor
  • one or more interconnect levels may be employed to form a monolithic protection circuit (e.g., circuit 100) that includes the silicon or III-V transistor and the N-polar diode fabricated by methods 701.
  • a monolithic protection circuit e.g., circuit 100
  • an IC including III-N heteroj unction diodes, or discrete III-N heteroj unction diodes is substantially complete and may be singulated and packaged following any suitable techniques.
  • FIG. 8-14 are cross-sectional views of III-N heteroj unction diodes 501 evolving as selected operations in the methods 701 are performed, in accordance with some
  • III-N heterostructure 815 has been epitaxially grown over a crystalline seeding surface of substrate 805 to have N-polarity (-c). III-N heterostructure 815 may have been grown within an opening of amorphous material (not depicted) defining any suitable template structure.
  • the seeding surface is SiC. In other embodiments, the seeding surface is a (100) cubic semiconductor surface is exposed within trenches extending in a ⁇ 110> direction of the substrate.
  • III-N heterostructure 815 may include deposition of a seed layer (not depicted) and further include growth of intrinsic GaN using first epitaxial growth conditions (e.g., a first growth pressure, a first growth temperature, and a first V/III growth precursor ratio) to form III-N material layer 510. Following an initial growth period, growth conditions may be changed to a second growth pressure, temperature, and/or a second V/III growth precursor ratio to form III-N material layer 430. Following this second growth period, growth conditions may be changed back to the first (GaN) growth conditions, or changed to a third growth pressure, temperature, and/or a third V/III growth precursor ratio to form III-N material layer 420. As grown, III-N material layer 420 has thickness Tl .
  • first epitaxial growth conditions e.g., a first growth pressure, a first growth temperature, and a first V/III growth precursor ratio
  • III-N material growths may be by any known technique, such as, but not limited to metal-organic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE), or molecular beam epitaxy (MBE).
  • MOCVD metal-organic chemical vapor deposition
  • VPE vapor phase epitaxy
  • MBE molecular beam epitaxy
  • elevated temperatures of 900 °C, or more, are employed.
  • FIG. 9A and 9B illustrate alternative embodiments where heterostructure 915 is grown on a donor substrate 905.
  • III-N heterostructure 915 has been epitaxially grown over a crystalline seeding surface of substrate 905 to have Ga-polarity (c).
  • III-N heterostructure 915 may have been grown within an opening of amorphous material (not depicted) defining any suitable template structure.
  • the seeding surface is SiC.
  • the seeding surface is a (100) cubic semiconductor surface is exposed within trenches extending in a ⁇ 110> direction of the substrate.
  • III-N heterostructure 915 may include deposition of a seed layer (not depicted) and further include growth of intrinsic GaN using first epitaxial growth conditions (e.g., a first growth pressure, a first growth temperature, and a first V/III growth precursor ratio) to form III-N material layer 420. As grown, III-N material layer 420 has thickness T3. Following an initial growth period, growth conditions may be changed to a second growth pressure, temperature, and/or a second V/III growth precursor ratio to form III-N material layer 430.
  • These III-N material growths may be by any known technique, such as, but not limited to metal-organic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE), or molecular beam epitaxy (MBE). In some embodiments, elevated temperatures of 900 °C, or more, are employed.
  • MOCVD metal-organic chemical vapor deposition
  • VPE vapor phase epitaxy
  • MBE molecular beam epitaxy
  • heterostructure 915 is transferred to a host substrate 910.
  • the transfer process inverts the crystal, exposing the N- face of III-N material layer 420 in preparation for diode fabrication.
  • III-N material layer 430 may be bonded to any suitable carrier using any techniques (e.g., thermo-compression bonding).
  • Various interfacial layers may be employed to perfect the bond to host substrate 910.
  • Donor substrate 905 is then removed to expose the N-face of III-N material layer 420.
  • III-N material layer 420 has thickness Tl, which may be less than thickness T3 as the result of a polish or other treatment performed to remove donor substrate 905).
  • FIG. 10 is a cross-sectional view of masking of an N-polar III-N heterostructure for a first terminal contact, in accordance with some embodiments.
  • FIG 10 is applicable to either heterostructure 815 or 915.
  • a dielectric material 260 has been deposited over III-N material layer 420 using any suitable technique.
  • a lithographic patterning process then defines a trench or via pattern, and openings 1005 are etched into dielectric material 260. Openings 1005 may be separated by a distance of around 100 nm, or less, for example. Openings 1005 may be defined with a first lithographic masking process followed by an anisotropic (e.g., dry/plasma) etch through dielectric material 260 with the etch stopping on a top surface of III-N material layer 420.
  • anisotropic e.g., dry/plasma
  • FIG. 1 1 A is a cross-sectional view illustrating formation of a first terminal contact including a non-rectifying metal-semiconductor junction, in accordance with some alloyed contact embodiments.
  • metal 551 has been deposited on the surface of III-N material layer 420 exposed within openings 1005. Any deposition process known to be suitable for the desired metal or metallic compound may be employed. Following metal deposition, a thermal anneal may then be performed to form alloy 552 between metal 551 and III-N material layer 420.
  • FIG. 1 IB is a cross-sectional view illustrating formation of a first terminal contact including a semiconductor-semiconductor junction, in accordance with some alternative embodiments where semiconductor material 631 is epitaxially grown within openings 1005 to at least partially backfill the recesses formed in dielectric material 260.
  • Semiconductor material 631 may be epitaxially grown from the N-face of III-N material layer 420.
  • openings 1005 are backfilled with InGaN material that is doped with n-type impurities in-situ during epitaxial growth.
  • n-type impurities may be implanted subsequent to growth and then made electrically active, for example with a thermal anneal.
  • FIG. 12A and 12B are cross- sectional views illustrating masking of a N-polar III-N heterostructure in preparation for a second terminal contact, in accordance with some embodiments.
  • a second opening 1205 has been etched through dielectric material 260 exposing the top surface of III-N material layer 420 at a second location.
  • Opening 1205 may be defined with a second lithographic masking process defining an opening with a lateral dimension of 50 nm, or less, for example. As shown, opening 1205 is aligned to the first openings to bifurcate the N-polar III-N material layer 420 disposed between two adjacent features of metal 551. Opening 1205 may be formed with an anisotropic (e.g., dry/plasma) etch that stops on III-N material layer 420. Opening 1205 may also be finished with a wet chemical etch or other surface treatment to improve the quality of the top surface of III-N material layer 420 where the Schottky junction is to be formed. Another embodiment is shown in FIG.
  • anisotropic e.g., dry/plasma
  • opening 1205 may be defined with a second lithographic masking process defining an opening with a lateral dimension of 50 nm, or less, for example. As illustrated in FIG. 12B, opening 1205 has been aligned to the first openings to bifurcate the N-polar III-N material layer 420 disposed between two adjacent impurity-doped
  • Opening 1205 may be formed with an anisotropic (e.g., dry/plasma) etch that stops on III-N material layer 420. Opening 1205 may also be finished with a wet chemical etch or other surface treatment to improve the quality of the top surface of III-N material layer 420 where the Schottky junction is to be formed.
  • FIG. 13 A and 13B are cross-sectional views illustrating formation of a second terminal contact including a rectifying metal-semiconductor junction, in accordance with some embodiments. As shown, metal 451 has been deposited to at least partially backfill opening 1205, contacting a top surface of III-N material layer 420.
  • Any metal deposition process such as, but not limited to, physical vapor deposition, chemical vapor deposition, atomic layer deposition, and the like, may be employed to deposit a suitable metal 451, such as any of those examples described elsewhere herein.
  • a suitable metal 451 such as any of those examples described elsewhere herein.
  • third openings may then be etched into dielectric material 260 overlying semiconductor terminal 631 to complete the diode structure as illustrated in FIG. 14.
  • metal 651 may be deposited with any suitable process and planarized with metal 451 and/or dielectric material 260 to arrive at III-N heteroj unction diodes 601.
  • FIG. 15 illustrates a system 1500 in which a mobile computing platform 1505 and/or a data server machine 1506 employs circuitry including at least one III-N heteroj unction diode, in accordance with some embodiments.
  • the server machine 1506 may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes a circuitry 1550.
  • the mobile computing platform 1505 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like.
  • the mobile computing platform 1505 may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 1510, and a battery 1515.
  • a display screen e.g., a capacitive, inductive, resistive, or optical touchscreen
  • a chip-level or package-level integrated system 1510 e.g., a battery 1515.
  • the circuit includes at least one III-N heterostructure diode, for example as describe elsewhere herein.
  • Circuitry 1550 may be further attached to a board, a substrate, or an interposer 1560 along with a power management integrated circuit (PMIC).
  • PMIC 1530 may perform battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to battery 1515 and with an output providing a current supply to other functional modules.
  • Circuitry 1550 includes RF (wireless) integrated circuitry (RFIC) further including a wideband RF (wireless) transmitter and/or receiver (TX/RX including a digital baseband and an analog front end module comprising a power amplifier on a transmit path and a low noise amplifier on a receive path).
  • RFIC includes at least one III-N heterostructure diode, for example in a over-voltage protection circuit as describe elsewhere herein.
  • the RFIC has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • FIG. 16 is a functional block diagram of a computing device 1600, arranged in accordance with at least some implementations of the present disclosure. Computing device 1600 may be found inside platform 1505 or server machine 1506, for example.
  • Device 1600 further includes a motherboard 1602 hosting a number of components, such as, but not limited to, a processor 1604 (e.g., an applications processor), which may further incorporate at least one III-N heterostructure diode, in accordance with embodiments of the present invention.
  • processor 1604 may be physically and/or electrically coupled to motherboard 1602.
  • processor 1604 includes an integrated circuit die packaged within the processor 1604.
  • the term "processor” or “microprocessor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory.
  • one or more communication chips 1606 may also be physically and/or electrically coupled to the motherboard 1602. In further implementations, communication chips 1606 may be part of processor 1604. Depending on its applications, computing device 1600 may include other components that may or may not be physically and electrically coupled to motherboard 1602.
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, touchscreen display, touchscreen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (such as hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like.
  • Communication chips 1606 may enable wireless communications for the transfer of data to and from the computing device 1600.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • Communication chips 1606 may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device 1600 may include a plurality of communication chips 1606. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless
  • a Group Ill-Nitride (III-N) diode structure comprises a first layer over a second layer, wherein the first layer comprises a first III-N material and the second layer comprises a second III-N material, the second III-N material having higher Al content than the first III-N material.
  • the structure comprises a first contact comprising a first metal coupled through an N-face of the first layer at a first location.
  • the structure comprises a second contact comprising a second metal coupled through the N-face of the first layer at a second location different than the first location.
  • a diode structure further comprises a semiconductor terminal with impurity doping.
  • the semiconductor terminal contacts the N-face of the first layer at the first location.
  • the first metal contacts the semiconductor terminal.
  • the second metal forms a Schottky barrier with the first layer.
  • the semiconductor terminal comprises a III-N material, and the first metal contacts an N-face of the semiconductor terminal.
  • the semiconductor terminal comprises In x Gai- x N with x between 0.05 and 0.2, and the semiconductor terminal has an impurity concentration of at least l el 8 atoms/cm 3 .
  • the first layer comprises binary GaN
  • the second layer comprises Al x Gai- x N, In y Ah- y N, or In y Ali- y-zGa z N.
  • x is between 0.25 and 0.4, y is less than 0.2, or z is less than 0.2.
  • the second layer comprises Ino.17Alo.83N.
  • the second layer is on an N-face of a third layer, the third layer comprising a third III-N material, the second layer having higher Al content than the third layer.
  • the third layer comprises binary GaN.
  • the first layer has a thickness less than that of the second layer.
  • the first layer thickness is less than l Onm and the second layer thickness is over 30 nm.
  • a thickness of the first layer in a region between the first and second metals is within 3nm of a thickness of the first layer where it is contacted by the second metal, and the first thickness is no more than 3 nm greater than the second thickness.
  • the second metal comprises at least one of Ni, Pt, or TIN.
  • the first metal comprises at least one of Al, Ti, or W.
  • a computer platform includes one or more RF transceiver, and an antenna coupled to the RF transceiver, wherein the RF transceiver has one or more signal input coupled to the first or second terminal of the diode structure in any of the first through fourteenth examples.
  • the system includes a processor communicatively coupled to the RF transceiver, and a battery coupled to at least one of the processor and RF transceiver.
  • a group Ill-Nitride (III-N) diode structure comprises a first layer comprising a first III-N material and over an N-face of a second layer comprising a second III-N material having higher Al content than the first III-N material.
  • a pair of first contacts are coupled through an N-face of the first layer at first locations.
  • a second contact is coupled through the N-face of the first III-N material layer at a second location between the first locations.
  • the second layer is on an N-face of a third layer comprising a third III-N material, the second III-N material having higher Al content than the third III-N material.
  • the first layer comprises binary GaN
  • the second layer comprises Al x Gai- x N, InyAli-yN, or In y Ali- y - z GazN
  • x is between 0.25 and 0.4
  • y is less than 0.2
  • z is less than 0.2
  • the second layer comprises Ino.17Alo.83N.
  • a method of forming a Group Ill-Nitride (III-N) diode structure comprises forming a non-rectifying metal-semiconductor junction comprising a first metal at a first location over an N-face of a first layer comprising a first III-N material that is over an N-face of a second layer comprising a second III-N material that has higher Al content than the first III-N material.
  • the method comprises forming a rectifying metal- semiconductor junction comprising a second metal and the N-face of the first layer at a second location.
  • the method further comprises epitaxially growing an N-polar crystal comprising a III-N material over a substrate, epitaxially growing the second layer over the N-face of the N-polar crystal, and epitaxially growing the first layer over the N-face of the second layer.
  • epitaxially growing the N-polar crystal further comprises growing a layer of binary GaN
  • epitaxially growing the second layer further comprises growing a layer of Al x Gai- x N, In y Ah- y N, or In y Ali- y -zGazN on an N-face of the binary GaN
  • epitaxially growing the first layer further comprises growing binary GaN on an N-face of the Al x Gai- x N, In y Ah- y N, or In y Ali -y- zGa z N.
  • non-rectifying metal-semiconductor junction further comprises growing in-situ doped n-type In x Gai- x N on an N-face of the first layer, with x between 0.05 and 0.2.
  • forming the rectifying metal-semiconductor junction further comprises depositing at least one of Ni, Pt, or TiN in contact with the N-face of the first layer.
  • the method further comprises depositing a dielectric layer over the first layer, and wherein forming the rectifying metal-semiconductor junction further comprises etching a trench into the dielectric layer that exposes the N-face of the first layer, the trench having an opening with a lateral dimension no more than 50 nm.
  • the above embodiments are not limited in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed.
  • the scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

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Abstract

L'invention concerne des diodes utilisant des hétérostructures au nitrure du groupe III N polaires qui peuvent fournir une faible résistance à l'état passant pour une empreinte de diode donnée. Une hétérostructure au N III N polaire peut comprendre une première couche de matériau N III sur une face N d'une seconde couche de matériau N III. Au moyen de l'ajustement de la composition de matériau N III des première et seconde couches, une feuille de support de charge bidimensionnelle (par exemple, un gaz électronique 2D) peut être induite à l'intérieur de la première couche. Avec une polarité N, un contact redresseur et un contact non redresseur peuvent chacun accéder à la feuille de support de charge 2D sans formation de motif ni de retrait sur la première couche de matériau N III.
PCT/US2017/039699 2017-06-28 2017-06-28 Diodes à hétérojonction au nitrure de groupe iii n polaire WO2019005031A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110140172A1 (en) * 2009-12-10 2011-06-16 Transphorm Inc. Reverse side engineered iii-nitride devices
US20110189837A1 (en) * 2008-07-21 2011-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Realizing N-Face III-Nitride Semiconductors by Nitridation Treatment
US20130056744A1 (en) * 2011-09-06 2013-03-07 Transphorm Inc. Semiconductor Devices with Guard Rings
US8680564B2 (en) * 2011-07-21 2014-03-25 Toyoda Gosei Co., Ltd. Group III nitride semiconductor light-emitting device
KR101535852B1 (ko) * 2014-02-11 2015-07-13 포항공과대학교 산학협력단 나노구조체 전사를 이용한 발광다이오드 제조방법과 그 발광다이오드

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110189837A1 (en) * 2008-07-21 2011-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Realizing N-Face III-Nitride Semiconductors by Nitridation Treatment
US20110140172A1 (en) * 2009-12-10 2011-06-16 Transphorm Inc. Reverse side engineered iii-nitride devices
US8680564B2 (en) * 2011-07-21 2014-03-25 Toyoda Gosei Co., Ltd. Group III nitride semiconductor light-emitting device
US20130056744A1 (en) * 2011-09-06 2013-03-07 Transphorm Inc. Semiconductor Devices with Guard Rings
KR101535852B1 (ko) * 2014-02-11 2015-07-13 포항공과대학교 산학협력단 나노구조체 전사를 이용한 발광다이오드 제조방법과 그 발광다이오드

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