WO2019003671A1

WO2019003671A1 - Aggregate substrate

Info

Publication number: WO2019003671A1
Application number: PCT/JP2018/018560
Authority: WO
Inventors: 政明金尾; 佐々木　純; 知大古村; 亜伊宮林; 勝己谷口
Original assignee: 株式会社村田製作所
Priority date: 2017-06-30
Filing date: 2018-05-14
Publication date: 2019-01-03
Also published as: CN211352582U

Abstract

This aggregate substrate (10) has a plurality of slave substrate regions (11), and a plurality of slave substrates are formed by separating the plurality of slave substrate regions (11). An RFIC arrangement region (9) is provided in a region that surrounds, with sides along outer edges of the aggregate substrate (10), the plurality of slave substrate regions (11). An RFIC in which information pertaining to the aggregate substrate (10) is recorded is mounted in the RFIC arrangement region (9). According to this structure, an aggregate substrate is configured in which a connection part of the RFIC or the RFIC itself is not easily damaged during a manufacturing process.

Description

Assembly substrate

The present invention relates to a collective substrate having a plurality of child substrate areas, and more particularly to a collective substrate provided with an RFIC chip on which information on the collective substrate is recorded.

When manufacturing a substrate on which a predetermined circuit is to be manufactured, a manufacturing method is generally used such as manufacturing in a collective substrate state having a plurality of child substrates and separating each child substrate at the final stage. Identification information is given to the RFIC chip and it is being used in the manufacturing process.

For example, Patent Document 1 discloses that a loop portion is formed on an edge conductor pattern of a collective substrate, and an RFIC chip is mounted on the loop portion.

International Publication No. 2016/060073

The structure of the collective substrate shown in Patent Document 1 has an advantage that the RFIC chip can be provided without substantially affecting the plurality of child substrate regions.

However, mounting a relatively large chip component at the edge of the collective substrate is highly difficult in the manufacturing process of the collective substrate. Further, since stress is easily applied to the edge of the collective substrate, the connection part of the chip part or the chip part itself is easily damaged in the manufacturing process.

Therefore, an object of the present invention is to provide a collective substrate in which the connection portion of the RFIC or the RFIC itself is not easily damaged in the manufacturing process.

(1) The collective substrate of the present invention is
A collective substrate having a plurality of child substrate areas and an outer edge, and separating the plurality of child substrate areas to form a plurality of child substrates,
An RFIC in which information on the collective substrate is recorded;
The RFIC is provided in an area surrounding the plurality of child substrate areas on the side along the outer edge,
It is characterized by

According to the above configuration, the stress applied to the RFIC is alleviated, and damage in the manufacturing process of the connection portion of the RFIC or the RFIC itself is prevented.

(2) It is preferable that the RFIC be provided inside a minimum range surrounding all the child substrate regions in plan view. Since the plurality of child substrate areas is originally an area spaced inwardly from the edge of the collective substrate, the inside of the minimum range surrounding all the child substrate areas in plan view is thus from the edge of the collective substrate It is an inward stressed area. By providing the RFIC chip in this region, the stress applied to the RFIC is relaxed, and breakage in the manufacturing process of the connection portion of the RFIC or the RFIC itself is prevented.

(3) It is preferable that the area | region in which said RFIC was provided is an area | region pinched | interposed by two child board | substrate area | regions among said some child board | substrate area | regions. According to this structure, the stress applied to the RFIC is further alleviated, and the breakage of the connection portion of the RFIC or the manufacturing process of the RFIC itself is effectively prevented.

(4) The RFIC is preferably incorporated in the thickness direction of the collective substrate. According to this structure, the RFIC is protected by the base of the collective substrate, the stress applied to the RFIC is relieved, and the breakage of the connection portion of the RFIC or the manufacturing process of the RFIC itself is prevented.

(5) The radiator may be a conductor pattern formed on an edge of the collective substrate, the radiator being connected to the RFIC, the radiator being outside the region where the RFIC is provided. According to this structure, the stress applied to the connection portion of the RFIC or the RFIC itself is suppressed, and the edge of the collective substrate is effectively used.

According to the present invention, it is possible to obtain a collective substrate in which the connection portion of the RFIC or the RFIC itself is not easily damaged in the manufacturing process.

FIG. 1 is a perspective view of a collective substrate 10 according to the first embodiment. FIG. 2 is a plan view of the RFIC placement area 9. FIG. 3A is a cross-sectional view of a plurality of base materials of the collective substrate 10 before lamination. FIG. 3B is a cross-sectional view of the plurality of substrates of the collective substrate 10 after lamination. FIG. 4 is a cross-sectional view across the entire width of the collective substrate 10. FIG. 5 is a circuit diagram of the RFIC 20. As shown in FIG. FIG. 6 is a perspective view of another collective substrate 10 according to the first embodiment. FIGS. 7A and 7B are plan views showing the relationship between the area surrounding a plurality of child substrate areas and the RFIC arrangement area 9 in the collective substrate 10 according to the second embodiment. 8A and 8B are plan views of the collective substrate 10 according to the third embodiment.

Hereinafter, some specific examples will be described with reference to the drawings to show a plurality of modes for carrying out the present invention. The same reference numerals are given to the same parts in each figure. In the second and subsequent embodiments, descriptions of matters in common with the first embodiment will be omitted, and different points will be described. In particular, the same operation and effect by the same configuration will not be sequentially referred to in each embodiment.

First Embodiment
FIG. 1 is a perspective view of a collective substrate 10 according to the first embodiment. The collective substrate 10 has a plurality of child substrate areas 11 arranged in a lattice. The collective substrate 10 has a multilayer structure formed by laminating thermoplastic resin layers such as LCP (Liquid Crystal Polymer) and TPI (thermoplastic polyimide). Each thermoplastic resin layer is flexible, and the collective substrate 10 is flexible. A plurality of sub-substrate regions 11 are separated from the collective substrate 10 by cutting the region indicated by the two-dot chain line in FIG. That is, a plurality of child substrates are obtained.

The collective substrate 10 includes an RFIC placement area 9 where the RFIC is placed, in addition to the daughter board area 11. In the present embodiment, the RFIC placement area 9 has the same size as the child substrate area 11, and corresponds to one of the vertical and horizontal arrangement positions of the plurality of child substrate areas.

FIG. 2 is a plan view of the RFIC placement area 9. A planar conductor 15 is formed in the RFIC placement area 9. Further, an opening 15AP is formed in a part of the planar conductor 15, and a slit 15SL connecting the opening 15AP and the outer edge is formed. The RFIC 20 is electrically connected to straddle the slit 15SL. Various information on manufacturing of the collective substrate 10 is recorded in the RFIC 20.

Arrows along the edge of the planar conductor 15 in FIG. 2 indicate a schematic path of current flowing in the planar conductor pattern. The planar conductor 15 acts as a radiator of a communication circuit using the RFIC 20. That is, the RF IC 20 and the planar conductor 15 constitute an RFID tag.

FIG. 3A is a cross-sectional view of a plurality of base materials of the collective substrate 10 before lamination. FIG. 3 (B) is a cross-sectional view after lamination.

The collective substrate 10 has a structure in which a plurality of thermoplastic resin layers including

thermoplastic resin layers

10A, 10B, 10C, 10D, 10E and 10F are stacked. A cavity 14 is formed in the

thermoplastic resin layers

10B and 10C, and the RFIC 20 is embedded in the cavity 14.

A planar conductor 15 is formed on the top surface of the thermoplastic resin layer 10A, and a via conductor 13 is formed inside the thermoplastic resin layer 10A.

The RFIC 20 is packaged including the IC chip 24 and the circuit pattern 22. The RFIC 20 has a structure in which an IC chip 24 is mounted on the surface of a substrate 21. A protective layer 25 is formed around the IC chip 24.

The base 21 is a laminate of the thermoplastic resin layer of the collective substrate 10 and a thermoplastic resin layer of the same material. The circuit pattern 22 is formed inside the base 21, and the terminal electrode 23 is formed on the upper surface of the base 21. The circuit pattern 22 includes an inductor or a capacitor with an in-plane conductor pattern, an interlayer conductor pattern, or the like. The circuit pattern 22 includes a resonant circuit having a predetermined resonant frequency, and constitutes a wide band matching circuit capable of impedance matching in a wide band.

By laminating the RFIC 20 together with the thermoplastic resin layers 10A to 10F and heating and pressing them, as shown in FIG. 3B, the thermoplastic resin layers 10A to 10F are thermocompression-bonded between adjacent layers. Further, the resin layers 10A and 10B and the base 21 of the RFIC 20 are thermocompression-bonded, and the resin layers 10C and 10D and the protective layer 25 of the RFIC 20 are thermocompression-bonded. Furthermore, the via conductor 13 conducts to the terminal electrode 23 of the RFIC 20. The temperature at the time of the said thermocompression bonding is 300 degreeC, for example.

FIG. 4 is a cross-sectional view across the entire width of the collective substrate 10. In the present embodiment, the RFIC placement area 9 is located between the two subsidiary substrate areas 11 in plan view. Since the circuit pattern 32 is formed in the daughter substrate region 11, the average hardness of the daughter substrate region 11 is harder than the thermoplastic resin layer alone of the collective substrate 10. Therefore, according to this structure, the stress applied to the RFIC 20 is further relieved, and breakage of the connection portion of the RFIC 20 or the RFIC 20 itself in the manufacturing process is effectively prevented.

FIG. 5 is a circuit diagram of the RFIC 20. As shown in FIG. In the RFIC 20, as illustrated in FIG. 5, a matching circuit including inductors L1 and L2 and capacitors C1 and C2 is formed between the IC chip 24 and the terminal electrode 23. Inductor L1 is inserted between one terminal of IC chip 24 and one terminal electrode 23, and inductor L2 is inserted between one terminal and the other terminal of IC chip 24 (in the example of FIG. 5, inductor L2 is , Inserted between the one terminal and the other terminal of the IC chip 24 via the inductor L1). The inductor L1 and the inductor L2 are coupled via the magnetic field M. Capacitor C1 is inserted between one terminal of IC chip 24 and one terminal electrode 23 (in the example of FIG. 5, capacitor C1 is one terminal of IC chip 24 and one terminal electrode 23 via inductor L1. Inserted between). The capacitor C 2 is inserted between the other terminal of the IC chip 24 and the other terminal electrode 23. A feed circuit having a plurality of resonance frequencies is constituted by these capacitors and inductors, and a wide band can be realized. The resonant frequency of the resonant circuit substantially corresponds to the communication frequency of the wireless communication device.

FIG. 6 is a perspective view of another collective substrate 10 according to the first embodiment. Unlike the collective substrate 10 shown in FIG. 1, the RFIC placement area 9 is provided at an angular position among the vertical and horizontal arrangement positions of the plurality of child substrate areas. As described above, the RFIC placement area 9 may be an area spaced inward from the edge of the collective substrate 10. In addition, the RFIC placement area 9 may be provided at an internal position such as the center among the arrangement positions of the plurality of sub substrate areas in the vertical and horizontal directions.

According to this embodiment, the stress applied to the RFIC 20 is relieved, and the breakage of the connection portion of the RFIC or the manufacturing process of the RFIC itself is prevented.

Second Embodiment
In the second embodiment, several relationships between a plurality of child substrate areas and an RFIC arrangement area are shown. In addition, an example in which the RFIC placement area has a size different from that of the child substrate area will be described.

FIGS. 7A and 7B are plan views showing the relationship between the area surrounding a plurality of child substrate areas and the RFIC arrangement area 9 in the collective substrate 10 according to the second embodiment.

In FIG. 7A, a surrounding region CR1 indicated by a two-dot chain line is a rectangular region surrounding a plurality of sub substrate regions 11 by the side along the outer edge of the collective substrate 10. In the example shown in FIG. 7A, the RFIC placement area 9 is provided in the surrounding area CR1 and at a position other than the daughter board area 11.

In FIG. 7B, the encircled area CR2 indicated by a two-dot chain line is a minimum area surrounding all the child substrate areas 11 in a plan view. In the example shown in FIG. 7B, the RFIC placement area 9 is provided in the surrounding area CR2 and at a position other than the daughter board area 11.

As described above, if the RFIC placement area 9 is provided in the surrounding area CR1 which is an area surrounding the plurality of sub substrate areas 11 by the side along the outer edge of the collective substrate 10, the stress applied to the RFIC is relaxed and the connection of the RFIC Damage in the manufacturing process of parts or the RFIC itself is prevented.

Further, if the RFIC placement area 9 is provided in the enclosing area CR2 which is the minimum area surrounding all the child substrate areas 11 in plan view, the stress applied to the RFIC is further relieved, and the manufacturing process of the connection part of RFIC or RFIC itself The damage prevention effect at

Third Embodiment
The third embodiment shows an example in which the radiator connected to the RFIC is outside the RFIC arrangement area.

8A and 8B are plan views of the collective substrate 10 according to the third embodiment. In each of FIGS. 8A and 8B, the collective substrate 10 includes a plurality of (eight) daughter substrate areas 11 and one RFIC arrangement area 9. Further, an edge conductor pattern 12 is formed at the edge of the collective substrate 10. Furthermore, the planar conductor 15 continuous from the edge conductor pattern 12 is intruding into the RFIC placement area 9.

In the example shown in FIG. 8A, an opening 15AP is formed in the planar conductor 15 in the RFIC placement area 9. Further, in the planar conductor 15, a slit 15 </ b> SL connecting the opening 15 AP and the inside of the RFIC arrangement region 9 is formed. The RFIC 20 is electrically connected to straddle the slit 15SL.

In the example shown in FIG. 8B, the planar conductor 15 in the RFIC placement area 9 is formed with an opening 15AP and a slit 15SL connecting the opening 15AP and the outer edge. The RFIC 20 is electrically connected to straddle the slit 15SL.

The edge conductor pattern 12 mainly functions as a radiator, and the planar conductor 15 formed in the opening 15AP and the slit 15SL is mainly used as an impedance matching portion for matching the impedance of the RFIC 20 and the edge conductor pattern 12 Works.

According to the present embodiment, since the RFIC 20 is disposed inside the edge of the collective substrate 10, the stress applied to the connection portion of the RFIC 20 or the RFIC 20 itself is suppressed. In addition, the edge conductor pattern 12 formed at the edge of the collective substrate 10 is effectively used as a radiator to obtain high communication characteristics.

The edge conductor pattern 12 is not limited to a loop, and may be, for example, a dipole radiator.

In each embodiment shown above, although the example which incorporated RFIC20 in the inside of the thickness direction of collective substrate 10 was shown, this RFIC20 may be mounted on the surface of collective substrate 10. FIG.

Finally, the description of the above embodiments is illustrative in all respects and not restrictive. Modifications and variations are possible as appropriate to those skilled in the art. The scope of the present invention is indicated not by the embodiments described above but by the claims. Furthermore, the scope of the present invention includes modifications from the embodiments within the scope of the claims and equivalents.

C1, C2: Capacitors CR1, CR2: Enclosure region L1, L2: Inductor 9: RFIC arrangement region 10:

Aggregate substrate

10A, 10B, 10C, 10D, 10E, 10F: Thermoplastic resin layer 11: Child substrate region 12: Edge portion Conductor pattern 13 ... via conductor 14 ... cavity 15 ... planar conductor 15AP ... opening 15SL ... slit 20 ... RFIC
21 Base material 22 Circuit pattern 23 Terminal electrode 24 IC chip 25 Protective layer 32 Circuit pattern

Claims

A collective substrate having a plurality of child substrate areas and an outer edge, and separating the plurality of child substrate areas to form a plurality of child substrates,
An RFIC in which information on the collective substrate is recorded;
The RFIC is provided in an area surrounding the plurality of child substrate areas on the side along the outer edge,
Collective substrate.
The RFIC is provided inside a minimum range surrounding all the child substrate regions in plan view,
The collective substrate according to claim 1.
The area provided with the RFIC is an area sandwiched by two sub substrate areas among the plurality of sub substrate areas,
The collective substrate according to claim 1.
The RFIC is built in the thickness direction of the collective substrate,
The collective substrate according to any one of claims 1 to 3.
A conductor pattern formed at an edge of the collective substrate, the radiator comprising a radiator connected to the RFIC, the radiator being outside the region provided with the RFIC;
The collective substrate according to any one of claims 1 to 4.