CN211352582U

CN211352582U - Collective substrate

Info

Publication number: CN211352582U
Application number: CN201890000826.XU
Authority: CN
Inventors: 金尾政明; 佐佐木纯; 古村知大; 宫林亚伊; 谷口胜己
Original assignee: Murata Manufacturing Co Ltd
Current assignee: Murata Manufacturing Co Ltd
Priority date: 2017-06-30
Filing date: 2018-05-14
Publication date: 2020-08-25
Anticipated expiration: 2028-05-14
Also published as: WO2019003671A1

Abstract

The utility model provides an aggregate substrate has a plurality of sub-base plate regions and outer fringe, forms a plurality of sub-base plates through regional separation with these a plurality of sub-base plate, aggregate substrate possesses the RFIC who has recorded with aggregate substrate's relevant information, RFIC sets up by the limit along the outer fringe surrounds in the regional encirclement zone of a plurality of sub-base plates. According to the present invention, the connecting portion of the RFIC or the RFIC itself can be obtained as the collective substrate which is not easily broken in the manufacturing process.

Description

Collective substrate

Technical Field

The present invention relates to an aggregate substrate having a plurality of sub-substrate regions, and more particularly to an aggregate substrate having RFIC chips in which information relating to the aggregate substrate is recorded.

Background

In manufacturing a substrate constituting a given circuit, a manufacturing method is common in which manufacturing is performed in a state of an aggregate substrate having a plurality of sub-substrates, and the sub-substrates are separated at a final stage, and identification information is given to an RFIC chip with respect to the aggregate substrate and is utilized in the manufacturing process.

For example, patent document 1 discloses a configuration in which a loop portion is formed in a conductor pattern at an edge portion of an aggregate substrate, and an RFIC chip is mounted on the loop portion.

Prior art documents

Patent document

Patent document 1: international publication No. 2016/060073

SUMMERY OF THE UTILITY MODEL

Problem to be solved by utility model

The structure of the collective substrate disclosed in patent document 1 has an advantage that RFIC chips can be provided without substantially affecting a plurality of sub-substrate regions.

However, mounting relatively large chip components on the edge of the aggregate substrate is difficult and easy in the manufacturing process of the aggregate substrate. Further, since stress is easily applied to the edge portion of the collective substrate, the connection portion of the chip component or the chip component itself is easily broken in the manufacturing process.

Therefore, an object of the present invention is to provide a collective substrate in which a connection portion of an RFIC or the RFIC itself is not easily broken during a manufacturing process.

Means for solving the problems

(1) The collective substrate of the present invention has a plurality of sub-substrate regions and an outer edge, and a plurality of sub-substrates are formed by separating the plurality of sub-substrate regions, and is characterized in that,

an RFIC having information on the collective substrate recorded therein,

the RFIC is disposed within an enclosure region that encloses the plurality of submount areas by edges along the outer edge.

According to the above configuration, stress applied to the RFIC can be relaxed, and breakage of the connection portion of the RFIC or the RFIC itself during the manufacturing process can be prevented.

(2) Preferably, the RFIC is provided inside a minimum range surrounding all of the submount area in a plan view. Since the plurality of sub-substrate regions are originally regions separated from the edge portion of the collective substrate to the inside, the inside of the minimum range surrounding all the sub-substrate regions in a plan view is a region separated from the edge portion of the collective substrate to the inside and not likely to be subjected to stress. By providing the RFIC chip in this area, stress applied to the RFIC can be relaxed, and breakage of the RFIC connection portion or the RFIC itself during the manufacturing process can be prevented.

(3) Preferably, the RFIC is provided in a region sandwiched between two of the plurality of sub-substrate regions. According to this configuration, stress applied to the RFIC can be relaxed, and breakage of the connection portion of the RFIC or the RFIC itself during the manufacturing process can be effectively prevented.

(4) Preferably, the RFIC is built in the thickness direction of the collective substrate. According to this structure, the RFIC is protected by the base material of the collective substrate, stress applied to the RFIC can be relaxed, and the connection portion of the RFIC or the RFIC itself can be prevented from being broken during the manufacturing process.

(5) The integrated circuit may further include a radiator connected to the RFIC, the radiator being a conductor pattern formed on an edge portion of the aggregate substrate outside an area where the RFIC is provided. According to this structure, stress applied to the connection portion of the RFIC or the RFIC itself can be suppressed, and the edge portion of the collective substrate can be effectively used.

Effect of the utility model

According to the present invention, the connecting portion of the RFIC or the RFIC itself can be obtained as the collective substrate which is not easily broken in the manufacturing process.

Drawings

Fig. 1 is a perspective view of an aggregate substrate 10 according to embodiment 1.

Fig. 2 is a plan view of the RFIC disposition area 9.

Fig. 3(a) is a cross-sectional view of the collective substrate 10 before stacking a plurality of base materials. Fig. 3(B) is a cross-sectional view of the stacked substrates of the aggregate substrate 10.

Fig. 4 is a cross-sectional view across the entire width of the collective substrate 10.

Fig. 5 is a circuit diagram of RFIC 20.

Fig. 6 is a perspective view of another collective substrate 10 according to embodiment 1.

Fig. 7(a) and 7(B) are plan views showing the relationship between the RFIC placement region 9 and the region surrounding the plurality of sub-substrate regions of the aggregate substrate 10 according to embodiment 2.

Fig. 8(a) and 8(B) are plan views of the collective substrate 10 according to embodiment 3.

Detailed Description

Hereinafter, a plurality of modes for carrying out the present invention will be described with reference to the drawings and by way of specific examples. In the drawings, the same reference numerals are given to the same parts. In embodiment 2 and thereafter, descriptions of common matters with embodiment 1 are omitted, and only differences will be described. In particular, the same operational effects based on the same structure will not be mentioned in each embodiment.

EXAMPLE 1 embodiment

Fig. 1 is a perspective view of an aggregate substrate 10 according to embodiment 1. The aggregate substrate 10 has a plurality of sub-substrate regions 11 arranged in a lattice shape. The aggregate substrate 10 has a multilayer structure in which thermoplastic resin layers such as LCP (Liquid Crystal Polymer) and TPI (thermoplastic polyimide) are laminated. Each thermoplastic resin layer has flexibility, and the collective substrate 10 has flexibility. The plurality of sub-substrate regions 11 are separated from the collective substrate 10 by cutting the regions indicated by the two-dot chain lines in fig. 1. That is, a plurality of sub-substrates are obtained.

The collective substrate 10 includes an RFIC placement region 9 in which RFICs are placed, outside the sub-substrate region 11. In the present embodiment, the RFIC placement region 9 has the same size as the submount region 11 and corresponds to one position of the vertical and horizontal arrangement positions of the plurality of submount regions.

Fig. 2 is a plan view of the RFIC disposition area 9. A planar conductor 15 is formed in the RFIC placement region 9. An opening 15AP is formed in a part of the planar conductor 15, and a slit 15SL is formed to connect the opening 15AP and the outer edge. Further, RFIC20 is electrically connected so as to straddle this slit 15SL. Various kinds of information on the manufacturing of the collective substrate 10 are recorded in the RFIC 20.

Arrows along the edges of the planar conductor 15 in fig. 2 show schematic paths of currents flowing through the planar conductor pattern. The planar conductor 15 functions as a radiator of a communication circuit using the RFIC 20. That is, the RFIC20 and the planar conductor 15 constitute an RFID tag.

Fig. 3(a) is a cross-sectional view of the collective substrate 10 before stacking a plurality of base materials. Fig. 3(B) is a cross-sectional view after lamination.

The collective substrate 10 has a structure in which a plurality of thermoplastic resin layers including

thermoplastic resin layers

10A, 10B, 10C, 10D, 10E, and 10F are laminated. A cavity 14 is formed in the thermoplastic resin layers 10B and 10C, and RFIC20 is embedded in the cavity 14.

A planar conductor 15 is formed on the upper surface of the thermoplastic resin layer 10A, and a via conductor 13 is formed inside the thermoplastic resin layer 10A.

The RFIC20 is formed by packaging the IC chip 24 and the circuit pattern 22. The RFIC20 has a structure in which the IC chip 24 is mounted on the surface of the base material 21. A protective layer 25 is formed around the IC chip 24.

The base 21 is a laminate of thermoplastic resin layers of the same material as the thermoplastic resin layers of the collective substrate 10. A circuit pattern 22 is formed inside the base material 21, and a terminal electrode 23 is formed on the upper surface of the base material 21. The circuit pattern 22 includes an inductor or a capacitor based on an in-plane conductor pattern, an interlayer conductor pattern, or the like. The circuit pattern 22 includes a resonance circuit having a predetermined resonance frequency, and constitutes a wide-band matching circuit capable of impedance matching over a wide band.

The RFIC20 is laminated together with the thermoplastic resin layers 10A to 10F, and then heated and pressed, whereby adjacent layers of the thermoplastic resin layers 10A to 10F are thermocompression bonded as shown in fig. 3 (B). The resin layers 10A and 10B are thermally compression bonded to the base material 21 of the RFIC20, and the resin layers 10C and 10D are thermally compression bonded to the protective layer 25 of the RFIC 20. Further, the via conductor 13 is in conduction with the terminal electrode 23 of the RFIC 20. The temperature at the time of the thermocompression bonding is, for example, 300 ℃.

Fig. 4 is a cross-sectional view across the entire width of the collective substrate 10. In the present embodiment, the RFIC placement region 9 is located between the two sub-substrate regions 11 in a plan view. Since the circuit pattern 32 is formed in the sub-substrate region 11, the average hardness of the sub-substrate region 11 is harder than that of the thermoplastic resin layer alone of the aggregate substrate 10. Thus, according to this configuration, stress applied to the RFIC20 can be further relaxed, and breakage of the connection portion of the RFIC20 or the RFIC20 itself in the manufacturing process can be effectively prevented.

Fig. 5 is a circuit diagram of RFIC 20. As shown in fig. 5, the RFIC20 forms a matching circuit including inductors L1, L2 and capacitors C1, C2 between the IC chip 24 and the terminal electrodes 23. An inductor L1 is interposed between one terminal of the IC chip 24 and one terminal electrode 23, and an inductor L2 is interposed between one terminal and the other terminal of the IC chip 24 (in the example of fig. 5, an inductor L2 is interposed between one terminal and the other terminal of the IC chip 24 via an inductor L1). Inductor L1 and inductor L2 are coupled via magnetic field M. A capacitor C1 is inserted between one terminal of the IC chip 24 and one terminal electrode 23 (in the example of fig. 5, a capacitor C1 is inserted between one terminal of the IC chip 24 and one terminal electrode 23 via an inductor L1). The capacitor C2 is interposed between the other terminal of the IC chip 24 and the other terminal electrode 23. The capacitor and the inductor constitute a power supply circuit having a plurality of resonance frequencies, and a wide frequency band can be achieved. The resonant frequency of the resonant circuit substantially corresponds to the communication frequency of the wireless communication device.

Fig. 6 is a perspective view of another collective substrate 10 according to embodiment 1. Unlike the collective substrate 10 shown in fig. 1, the RFIC placement region 9 is provided at an angular position among the arrangement positions of the vertical and horizontal directions of the plurality of sub-substrate regions. As described above, the RFIC placement region 9 may be a region that is spaced inward from the edge of the collective substrate 10. The RFIC placement region 9 may be provided at an inner position such as the center among the vertical and horizontal arrangement positions of the plurality of sub-substrate regions.

According to this embodiment, stress applied to the RFIC20 can be relaxed, and breakage of the RFIC connection portion or the RFIC itself during the manufacturing process can be prevented.

EXAMPLE 2 EXAMPLE

In embodiment 2, several relationships between a plurality of submount areas and an RFIC placement area are shown. Further, an example in which the RFIC placement area is a different size from the submount area is shown.

In fig. 7(a), a surrounding region CR1 shown by a two-dot chain line is a rectangular region that surrounds the plurality of sub-substrate regions 11 by a side along the outer edge of the aggregate substrate 10. In the example shown in fig. 7(a), the RFIC placement region 9 is provided in the surrounding region CR1 and at a position other than the sub-substrate region 11.

In fig. 7(B), the enclosed region CR2 shown by the two-dot chain line is the minimum range surrounding all the sub-substrate regions 11 in a plan view. In the example shown in fig. 7(B), the RFIC placement region 9 is provided in the surrounding region CR2 and at a position other than the sub-substrate region 11.

In this way, if the RFIC placement region 9 is provided in the surrounding region CR1, which is a region surrounding the plurality of sub-substrate regions 11 along the edge of the outer edge of the collective substrate 10, stress applied to the RFIC can be relaxed, and damage to the connection portion of the RFIC or the RFIC itself during the manufacturing process can be prevented.

Further, if the RFIC placement region 9 is provided in the surrounding region CR2, which is the minimum range surrounding all the sub-substrate regions 11 in a plan view, stress applied to the RFIC can be further relaxed, and the effect of preventing the RFIC from being damaged during the connection portion of the RFIC or the RFIC itself can be further improved.

EXAMPLE 3

In embodiment 3, an example is shown in which a radiator connected to an RFIC is located outside an RFIC placement area.

Fig. 8(a) and 8(B) are plan views of the collective substrate 10 according to embodiment 3. In fig. 8 a and 8B, the collective substrate 10 includes a plurality of (8) sub-substrate regions 11 and one RFIC placement region 9. Further, an edge conductor pattern 12 is formed on the edge of the aggregate substrate 10. Further, the planar conductor 15 continuous from the edge conductor pattern 12 enters the RFIC placement region 9.

In the example shown in fig. 8(a), an opening 15AP is formed in the planar conductor 15 in the RFIC placement region 9. In addition, the planar conductor 15 is formed with a slit 15SL connecting the opening 15AP and the RFIC placement region 9. Further, RFIC20 is electrically connected so as to straddle this slit 15SL.

In the example shown in fig. 8(B), the planar conductor 15 in the RFIC placement region 9 is formed with an opening 15AP and a slit 15SL connecting the opening 15AP and the outer edge. Further, RFIC20 is electrically connected so as to straddle this slit 15SL.

The edge conductor pattern 12 mainly functions as a radiator, and the planar conductor 15 formed in the opening 15AP and the slit 15SL mainly functions as an impedance matching unit for matching the impedances of the RFIC20 and the edge conductor pattern 12.

According to this embodiment, since the RFIC20 is disposed further inside than the edge portion of the collective substrate 10, stress applied to the connection portion of the RFIC20 or the RFIC20 itself can be suppressed. Further, the edge conductor pattern 12 formed at the edge of the aggregate substrate 10 is effectively used as a radiator, and high communication characteristics can be obtained.

The edge conductor pattern 12 is not limited to a ring shape, and may be a dipole (dipole) type radiator, for example.

In the above-described embodiments, the RFIC20 is embedded inside the aggregate substrate 10 in the thickness direction, but the RFIC20 may be attached to the surface of the aggregate substrate 10.

Finally, the above description of the embodiments is illustrative in all respects and not restrictive. It is obvious to those skilled in the art that the modifications and variations can be appropriately made. The scope of the present invention is shown not by the above-described embodiments but by the claims. Further, the scope of the present invention includes modifications from the embodiments within the scope equivalent to the claims.

Description of the reference numerals

C1, C2... capacitor;

CR1, cr2.. circumscribe the region;

l1, L2.. inductor;

an RFIC deployment area;

assembling a substrate;

10A, 10B, 10C, 10D, 10E, 10f.. thermoplastic resin layers;

a submount area;

an edge conductor pattern;

a via conductor;

a cavity;

a planar conductor;

15AP... opening;

15SL... gap;

20...RFIC；

a substrate;

a circuit pattern;

a terminal electrode;

an IC chip;

a protective layer;

a circuit pattern.

Claims

1. An aggregate substrate having a plurality of sub-substrate regions and an outer edge, the plurality of sub-substrates being formed by separating the plurality of sub-substrate regions, the aggregate substrate being characterized in that,

an RFIC having information on the collective substrate recorded therein,

2. The collective substrate of claim 1,

the surrounding region is a minimum region obtained by connecting the outermost sub-substrate regions with a straight line.

3. The collective substrate according to claim 1 or 2,

the RFIC is configured to be completely accommodated in a region sandwiched by two sub-substrate regions among the plurality of sub-substrate regions.

4. The collective substrate according to claim 1 or 2,

the RFIC is internally arranged in the thickness direction of the aggregate substrate.

5. The collective substrate according to claim 1 or 2,

the radio frequency integrated circuit device is provided with a radiator connected to the RFIC, and the radiator is formed outside the surrounding area.