WO2018223967A1

WO2018223967A1 - Semiconductor device structures and fabrication methods thereof

Info

Publication number: WO2018223967A1
Application number: PCT/CN2018/089987
Authority: WO
Inventors: Rongfu ZHU
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2017-06-05
Filing date: 2018-06-05
Publication date: 2018-12-13
Anticipated expiration: 2019-12-05
Also published as: CN107221495B; CN107221495A; CN108807163A

Abstract

Semiconductor device structures and fabrication methods thereof are provided. The fabrication method may include providing a silicon layer (110); forming an intermediate layer on the silicon layer (120), wherein the intermediate layer includes a first metal layer, made of a first metal and formed on an upper surface of the silicon layer; and a second metal layer, made of a second metal and formed on the first metal layer; forming an insulating layer on an upper surface of the intermediate layer under a predetermined temperature (130), thereby at least partial of the first metal layer and at least partial of the silicon layer together forming a first metal silicide layer on the silicon layer.

Description

SEMICONDUCTOR DEVICE STRUCTURES AND FABRICATION METHODS THEREOF

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No. 201710411778. 5 filed on June 5, 2017, the contents of which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

The present disclosure generally relates to integrated circuits fabrication techniques, and in particular, to multi-layer semiconductor device structures and fabrication methods thereof.

BACKGROUND

In current semiconductor industry, silicon-containing materials are widely used to make a substrate of a semiconductor (e.g., transistors, diodes, wirelines) . Meanwhile, aluminum (Al) is used in many aspects of semiconductor manufacturing. As aluminum has a low resistance, and is easy to be etched and deposited, it is commonly used as a material of the aluminum metal lines, which are the main conductor between components of an integrated circuits. It is further noted that a thin film formed by doping a certain percentage of silicon to aluminum has good adherence to the silicon-containing material and low resistance, and can be used as the conducting lines in addition to a contact layer to the substrate.

However, due to a shortened process of the semiconductor fabrication, the step coverage ratio needs to be increased. Thus, Chemical Vapor Deposition (CVD) techniques are widely used in current semiconductor industry. Aluminum cannot endure the high temperature of the CVD process due to its relatively low melting point (about 660℃) .

Further, in existing stacked gates fabrication technology, a tungsten/polycrystalline silicon gate may include a polycrystalline silicon layer, a tungsten nitride layer, and a tungsten layer stacked from bottom to top. A resistance of the tungsten/polycrystalline silicon gate may be relatively lower than a stacked-gate structure including a polycrystalline silicon layer and a tungsten silicide layer. However, during a high-temperature process or a subsequent annealing process in forming the tungsten/polycrystalline silicon gate, tungsten nitride and polycrystalline silicon may proceed a silicification reaction and produce a thin layer of silicon-nitrogen bonds (Si-N) . When the tungsten/polycrystalline silicon gate operates at a relatively low voltage, the thin layer of Si-N bonds may cause delay errors of signals.

Therefore, it is desirable to provide semiconductor structures with low resistance in contacting with the silicon substrate and high-temperature endurance, and fabrication methods thereof.

SUMMARY

According to a first aspect of the present disclosure, a fabrication method for a semiconductor device structure is provided. The method may include: providing a silicon layer; forming an intermediate layer on the silicon layer, wherein the intermediate layer includes a first conductive layer formed on the silicon layer; and forming an insulating layer on the intermediate layer under a predetermined temperature, thereby at least partial of the first conductive layer and at least partial of the silicon layer together forming a transition layer on the silicon layer.

In some embodiments, the method may further include forming a first control layer on the first conductive layer. The first conductive layer may be made of a first material, and the first control layer may be made of a nitride of the first material.

In some embodiments, forming the intermediate layer on the silicon layer may further include forming a second control layer on the first control layer. The second control layer may be made of a silicide of a second material.

In some embodiments, forming the intermediate layer on the silicon layer may further include forming a second conductive layer on the second control layer. The second conductive layer may be made of the second material.

In some embodiments, the insulating layer may be formed on the second conductive layer.

In some embodiments, the silicon layer may have a thickness of 10 nm to 120 nm.

In some embodiments, the first conductive layer may have a thickness of 1 nm to 30 nm.

In some embodiments, the insulating layer may have a thickness of 50 nm to 400 nm.

In some embodiments, the predetermined temperature may be 550 ℃ to 880 ℃.

In some embodiment, the insulating layer may be formed by chemical vapor deposition.

In some embodiments, the first material may be selected from a group comprising tantalum, palladium, platinum, cobalt, zirconium, nickel, titanium, and molybdenum.

In some embodiments, the first control layer may have a thickness of 3 nm to 50 nm.

In some embodiments, the second control layer may have a thickness of 1 nm to 30 nm.

In some embodiments, the first material may be different from the second material.

In some embodiment, the second material may be selected from a group comprising tantalum, palladium, platinum, cobalt, zirconium, nickel, titanium, and molybdenum.

In some embodiments, the second conductive layer may have a thickness of 10 nm to 100 nm.

According to a second aspect of the present disclosure, a fabrication method for a semiconductor device structure is provided. The method may include: providing a silicon layer; forming an intermediate layer on the silicon layer, wherein the intermediate layer includes a first metal layer, made of a first metal and formed on an upper surface of the silicon layer; and a second metal layer, made of a second metal and formed on the first metal layer; forming an insulating layer on an upper surface of the intermediate layer under a predetermined temperature, thereby at least partial of the first metal layer and at least partial of the silicon layer together forming a first metal silicide layer on the silicon layer.

According to a third aspect of the present disclosure, a semiconductor device structure is provided. The semiconductor device structure may include: a silicon layer; an intermediate layer on the silicon layer, wherein the intermediate layer includes a first metal layer, made of a first metal and formed on an upper surface of the silicon layer; and a second metal layer, made of a second metal and formed on the first metal layer; an insulating layer on an upper surface of the intermediate layer formed under a predetermined temperature, thereby at least partial of the first metal layer and at least partial of the silicon layer together forming a first metal silicide layer on the silicon layer.

According to a fourth aspect of the present disclosure, a stacked-gate storage device is provided. The stacked-gate storage device may include: a substrate including at least a silicon layer; and a control gate located on the substrate, wherein the control gate includes a silicon layer, an intermediate layer on the silicon layer, wherein the intermediate layer includes a first metal layer, made of a first metal and formed on an upper surface of the silicon layer; and a second metal layer, made of a second metal and formed on the first metal layer; an insulating layer on an upper surface of the intermediate layer formed under a predetermined temperature, thereby at least partial of the first metal layer and at least partial of the silicon layer together forming a first metal silicide layer on the silicon layer.

Additional features will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and the accompanying drawings or may be learned by production or operation of the examples. The features of the present disclosure may be realized and attained by practice or use of various aspects of the methodologies, instrumentalities, and combinations set forth in the detailed examples discussed below.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is further described in terms of exemplary embodiments. These exemplary embodiments are described in detail with reference to the drawings. These embodiments are non-limiting exemplary embodiments, in which like reference numerals represent similar structures throughout the several views of the drawings, and wherein:

FIG. 1 is a flowchart illustrating an exemplary process for fabricating a semiconductor device structure according to some embodiments of the present disclosure;

FIG. 2 is a schematic diagram illustrating an exemplary silicon layer of the semiconductor device structure according to some embodiments of the present disclosure;

FIG. 3 is schematic diagram illustrating an exemplary structure of a silicon layer and an intermediate structure of the semiconductor device structure according to some embodiments of the present disclosure;

FIG. 4 is a schematic diagram illustrating an exemplary semiconductor device structure according to some embodiments of the present disclosure;

FIG. 5 is a schematic diagram illustrating an exemplary semiconductor device structure according to some embodiments of the present disclosure;

FIG. 6 is a schematic diagram illustrating an exemplary semiconductor device structure according to some embodiments of the present disclosure;

FIG. 7 is a schematic diagram illustrating an exemplary semiconductor device structure according to some embodiments of the present disclosure;

FIG. 8 is a schematic diagram illustrating an exemplary semiconductor device structure according to some embodiments of the present disclosure;

FIG. 9 is a schematic diagram illustrating an exemplary stacked-gate storage device according to some embodiments of the present disclosure;

FIG. 10 is a flowchart illustrating an exemplary process for fabricating a semiconductor device structure according to some embodiments of the present disclosure;

FIG. 11 is a schematic diagram illustrating an exemplary first partial of the semiconductor device structure according to some embodiments of the present disclosure;

FIGs 12-15 are schematic diagrams illustrating exemplary second partials of the semiconductor device structure according to some embodiments of the present disclosure; and

FIG. 16 is a schematic diagram illustrating an exemplary semiconductor device structure according to some embodiments of the present disclosure.

DETAILED DESCRIPTION

The following description is presented to enable any person skilled in the art to make and use the present disclosure and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Thus, the present disclosure is not limited to some embodiments shown but is to be accorded the widest scope consistent with the claims.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms “a, ” “an, ” and “the” may be intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise, ” “comprises, ” and/or “comprising, ” “include, ” “includes, ” and/or “including, ” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

These and other features, and characteristics of the present disclosure, as well as the methods of operation and functions of the related elements of structure and the combination of parts and economies of manufacture, may become more apparent upon consideration of the following description with reference to the accompanying drawings, all of which form a part of this disclosure. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only and are not intended to limit the scope of the present disclosure. It is understood that the drawings are not to scale.

The flowcharts used in the present disclosure illustrate operations that systems implement according to some embodiments of the present disclosure. It is to be expressly understood, the operations of the flowchart may be implemented not in order. Conversely, the operations may be implemented in inverted order, or simultaneously. Moreover, one or more other operations may be added to the flowcharts. One or more operations may be removed from the flowcharts.

An aspect of the present disclosure relates to fabricating semiconductor device structures. The semiconductor device structure may be formed by a substrate made of a silicon-containing material, an intermediate structure including a first conductive layer and an insulating layer from bottom to top. The insulating layer may be formed on the intermediate structure at a predetermined temperature. In the meanwhile, at least partial of the first conductive layer and at least partial of the substrate may together form a transition layer on the substrate. The transition layer may reduce a contact resistance between the substrate and the intermediate structure. In some cases, the intermediate structure may also include at least one of: a first control layer, a second control layer, and a second conductive layer. The first control layer and/or the second control layer may be used to control the contact resistance between the substrate and the intermediate structure.

FIG. 1 is a flowchart illustrating an exemplary process for fabricating a semiconductor device structure according to some embodiments of the present disclosure. The operations of the illustrated process presented below are intended to be illustrative. In some embodiments, the process 100 may be accomplished with one or more additional operations not described and/or without one or more of the operations herein discussed. Additionally, the order in which the operations of the process as illustrated in FIG. 1 and described below is not intended to be limiting.

In operation 110, a silicon layer (e.g., a silicon layer 11 as illustrated in FIGs. 2-8) may be provided. In some embodiments, the silicon layer may be made of any silicon-containing material, such as monocrystalline silicon, polycrystalline silicon, non-crystalline amorphous silicon, Silicon-Germanium (Si-Ge) materials. For example, the silicon layer may be a polycrystalline Si-Ge layer. In some embodiments, the silicon layer may be made of any doped silicon–containing material, e.g., intrinsic silicon, P-type silicon, N-type silicon, etc. It should be appreciated that the materials of the silicon layer described above are for illustration purpose. The present disclosure is not intended to be limiting.

The silicon layer may be a laminated structure including at least two layers of different materials. For example, the silicon layer may be a laminated structure including a polycrystalline silicon layer with an N-type dopant and a polycrystalline silicon layer with a P-type dopant. In some embodiments, the silicon layer may have a thickness of 10 nm to 120 nm, or 30 nm to 80 nm, etc. In some embodiments, the thickness of the silicon layer may be 50 nm.

In operation 120, an intermediate structure (e.g., an intermediate structure 12 as illustrated in FIGs. 3-9) may be formed on an upper surface of the silicon layer. The intermediate structure may include at least a first metal layer. The first metal layer may be formed on top of the upper surface of the silicon layer.

The material of the first metal layer may include but not limited to Tantalum (Ta) , Palladium (Pd) , Platinum (Pt) , Cobalt (Co) , Zirconium (Zr) , Nickel (Ni) , Titanium (Ti) , Molybdenum (Mo) , etc. For example, the first metal layer may be made of Ta. The first metal layer may be formed by Physical Vapor Deposition (PVD, e.g., evaporation deposition, electrodeposition, sputter deposition) , Chemical Vapor Deposition (CVD) , or Atomic Layer Deposition (ALD) , etc. The first metal layer may have a thickness of 1 nm to 30 nm, or 1 nm to 10 nm, or 1 nm to 20 nm, etc. In some embodiments, the thickness of the first metal layer may be 15 nm.

In some embodiments, the intermediate structure may further include a second metal layer. The second metal layer may be formed on top of the first metal layer. The second metal layer may be configured as a conducting layer. A material of the second metal layer may include but not limited to Titanium (Ti) , Tantalum (Ta) , Palladium (Pd) , Nickel (Ni) , Platinum (Pt) , Cobalt (Co) , tungsten (W) , Zirconium (Zr) , , Molybdenum (Mo) , etc. The second metal layer may be formed by Physical Vapor Deposition (PVD, e.g., evaporation deposition, electrodeposition, sputter deposition) , Chemical Vapor Deposition (CVD) , Atomic Layer Deposition (ALD) , etc. The second metal layer may have a thickness of 10 nm to 100 nm, 20 nm to 80 nm, or 30 nm to 60 nm, etc. In some embodiments, the thickness of the second metal layer may be 50 nm. The material of the first metal layer may be different from the material of the second metal layer. For example, the first metal layer may be made of Ta, and the second metal layer may be made of Ti. It should be appreciated that the material of the first metal layer and the material of the second metal layer may be selected according to actual needs in various fabrication scenarios, and the material of the first metal layer and the material of the second metal layer described above are for illustration purpose. The present disclosure is not intended to be limiting.

In operation 130, an insulating layer (e.g., an insulating layer as illustrated in FIGs. 4-9) may be formed on an upper surface of the intermediate structure at a predetermined temperature. During the forming of the insulating layer, the first metal layer may react with the silicon layer at the predetermined temperature, causing partial of the first metal layer and partial of the silicon layer that are directly contacted with each other to form a first metal silicide layer. The first metal silicide layer may be sandwiched between the silicon layer and the first metal layer.

The material of the insulating layer may include but not limited to silicon nitride. In some embodiments, the insulating layer may be formed by Chemical Vapor Deposition (CVD) , Atomic Layer Deposition (ALD) , etc. The insulating layer may have a thickness of 50 nm to 400 nm, or 150 nm to 300 nm etc. In some embodiments, the thickness of the insulating layer may be 200 nm.

The insulating layer may be formed to protect the semiconductor device structure underneath the insulating layer from oxidation due to exposure to the air. Further, as the first metal layer and the silicon layer may proceed a silicification reaction to produce the metal silicide layer between the silicon layer and the first metal layer, a contact resistance between the silicon layer and the first metal layer may be reduced. In some embodiments, the semiconductor device structure formed as illustrated above may be used as heat-resistant wirelines.

The predetermined temperature may be configured as a temperature range, such as 550 ℃ to 880 ℃, or 600 ℃ to 750 ℃, etc. In some embodiments, the predetermined temperature may be configured as a temperature value, such as 650 ℃. A predetermined temperature lower than 550 ℃ may be not high enough for the silicification reaction between the silicon layer and the first metal layer. On the other hand, a predetermined temperature greater than 800 ℃ may cause overreaction between the silicon layer and the first metal layer, leading the metal silicide aggregated into blocks, which in turn increasing the contact resistance.

FIG. 2 is a schematic diagram illustrating an exemplary silicon layer of the semiconductor device structure provided in 110, and FIG. 3 is schematic diagram illustrating an exemplary structure of a silicon layer and an intermediate structure of the semiconductor device structure based on operation 110-120 according to some embodiments of the present disclosure.

According to the embodiment shown in FIG. 2, after operation 110 is performed, the semiconductor device structure includes a silicon layer 11.

According to the embodiment shown in FIG. 3, after operation 110 and operation 120 are performed, the semiconductor device structure includes the silicon layer 11, a first metal layer 121, and a second metal layer 124. The first metal layer 121 stacks on the silicon layer 11. The second metal layer 124 stacks on the first metal layer 121. An intermediate structure includes the first metal layer 121 and the second metal layer 124.

FIG. 4 is a schematic diagram illustrating an exemplary semiconductor device structure according to some embodiments of the present disclosure. The semiconductor device structure 400 may be fabricated based on process 100 described above.

According to the embodiment shown in FIG. 4, the semiconductor device structure 400 includes the silicon layer 11, the intermediate structure 12, and the insulating layer 13. The intermediate structure 12 includes a first metal silicide layer 126 and a second metal layer 124. The first metal silicide layer 126 may be formed on an upper surface of the silicon layer 11. The insulating layer 13 may be formed on an upper surface of the intermediate structure 12. As used herein, the first metal silicide layer 126 may be formed during the process of forming the insulating layer 13 at a predetermined temperature. The first metal layer 121 (as shown in FIG. 3) and the silicon layer 11 reacts at the predetermined temperature to produce the first metal silicide layer 126. The second metal layer 124 may be formed between the first metal silicide layer 126 and the insulating layer 13. The second layer 124 may have a different metallic element from the first metal silicide layer 126.

In some embodiments, the first metal silicide layer 126 may include a metallic element same as that of the first metal layer 121 because the first metal silicide layer 126 is formed by a silicification reaction between the silicon layer 11 and the first metal layer 121 (as shown in FIG. 3) . In some embodiments, the first metal silicide layer 126 may be evenly formed on the upper surface of the silicon layer 11. In some embodiments, the silicification reaction between the first metal layer 121 and the silicon layer 11 may be incomplete, and thus, the first metal silicide layer 126 may be incorporated in the silicon layer 11 and contact with the first metal layer 121. Alternatively, the first metal silicide layer 126 may be incorporated in the first metal layer 121 and contact with the silicon layer 11. It should be appreciated that the first metal silicide layer 126 may be formed in any location between the first metal layer 121 and the silicon layer 11 to reduce a contact resistance. The examples of forming the first metal silicide layer 126 described above is for illustration purpose. The present disclosure is not intended to be limiting. Further, the first metal silicide layer 126 may have a thickness of 1 nm to 30 nm, 1 nm to 10 nm, or 1 nm to 20 nm, etc. In some embodiments, the thickness of the first metal silicide layer 126 may be 15 nm.

The second metal layer 124 may be used as a conductor. A material of the second metal layer 124 may include but not limited to Titanium (Ti) , Tantalum (Ta) , Palladium (Pd) , Nickel (Ni) , Platinum (Pt) , Cobalt (Co) , tungsten (W) , Zirconium (Zr) , Molybdenum (Mo) , etc. Further, the second metal layer 124 may have a thickness of 10 nm to 100 nm, 20 nm to 80 nm, 30 nm to 60 nm, 50 nm, etc. In some embodiments, the first metal silicide layer 126 may be made of a metallic material different from that of the second metal layer 124. For example, the first metal silicide layer 126 may be made of tantalum silicide, and the second metal layer 124 may be made of titanium. The material of the first metal silicide layer 126 and the material of the second metal layer 124 may be selected according to actual needs in various fabrication scenarios, and the material of the first metal layer 121 and the material of the second metal layer 124 described above are for illustration purpose. The present disclosure is not intended to be limiting.

FIG. 5 is a schematic diagram illustrating an exemplary semiconductor device structure according to some embodiments of the present disclosure. As shown in FIG. 5, the semiconductor device structure 500 may be similar to the semiconductor device structure 400 except that the intermediate structure 12 may further include a metal nitride layer 122. Accordingly, the present disclosure provides a process for fabricating the semiconductor device structure 500. The process for fabricating the semiconductor device structure 500 may be similar to the process 100 but including a further operation to form a first metal nitride layer 122 between the first metal layer 121 and the second metal layer 124.

The material of the first metal nitride layer 122 may include but not limited to tantalum nitride, palladium nitride, platinum nitride, cobalt nitride, zirconium nitride, nickel nitride, titanium nitride, molybdenum nitride, etc. The first metal nitride layer 122 may be formed by Physical Vapor Deposition (PVD, e.g., evaporation deposition, electrodeposition, sputter deposition) , Chemical Vapor Deposition (CVD) , Atomic Layer Deposition (ALD) , etc. Further, the first metal nitride layer 122 may have a thickness of 3 nm to 50 nm, 5 nm to 30 nm, or 10 nm to 20 nm, etc. In some embodiments, the thickness of the first metal nitride layer 122 may be 15 nm.

The first metal nitride layer 122 may be used to control the silicification reaction between the first metal layer 121 and the silicon layer 11 at the predetermined temperature. With the first metal nitride layer 122, the silicification reaction between the first metal layer 121 and the silicon layer 11 may not be overreacted, and thus, protecting the metal silicide from aggregating into blocks. As such, an increasing of the contact resistance between the silicon layer 11 and the first metal layer 121 due to the metal silicide aggregation may be avoided.

In some embodiments, the first metal nitride layer 122 may include a same metallic element as the first metal layer 121. The fact that the first metal nitride layer 122 includes a same metallic element as the first metal layer 121 may lead to better adhesion between the first metal nitride layer 122 and the first metal layer 121. Further, the first metal nitride layer 122 including a same metallic element as the first metal layer 121 may lead to better adhesion between the first metal nitride layer 122 and the first metal silicide 126 formed by the silicification reaction between the first metal layer 121 and the silicon layer 11.

As shown in FIG. 5, the semiconductor device structure 500 may include the silicon layer 11, the intermediate layer 12, and the insulating layer 13. The intermediate layer 12 may include at least the first metal silicide layer 126. The first metal silicide layer126 may be formed on the upper surface of the silicon layer 11. The insulating layer 13 may be formed on the upper surface of the intermediate structure 12.

As used herein, the first metal silicide layer 126 may be formed during the process of forming the insulating layer 13 at a predetermined temperature. The first metal layer 121 and the silicon layer 11 may react to produce the first metal silicide layer 126. The intermediate structure 12 may further include the second metal layer 124. The second metal layer 124 may be formed between the first metal silicide layer 126 and the insulating layer 13.

In some embodiments, the intermediate structure 12 may further include a first metal nitride layer 122. The first metal nitride layer 122 may be formed between the first metal silicide layer 126 and the second metal layer 124. The first metal nitride layer 122 may include a same metallic element as the first metal silicide 126. The first metal nitride layer 122 may be made of a material including but not limited to tantalum nitride, palladium nitride, platinum nitride, cobalt nitride, zirconium nitride, nickel nitride, titanium nitride, or molybdenum nitride, etc. Further, the first metal nitride layer 122 may have a thickness of 3 nm to 50 nm, 5 nm to 30 nm, or 10 nm to 20 nm. In some embodiments, the thickness of the first metal nitride layer 122 may be 15 nm. The first metal silicide 126 including a same metallic element as the first metal nitride layer 122 may lead to better adhesion between the first metal nitride layer 122 and the first metal silicide 126.

FIG. 6 is a schematic diagram illustrating an exemplary semiconductor device structure according to some embodiments of the present disclosure. The semiconductor device structure 600 may be similar to the semiconductor device structure 500 except that the intermediate structure 12 may further include a second metal nitride layer 125. Accordingly, the present disclosure provides a process for fabricating the semiconductor device structure 600. The process for fabricating the semiconductor device structure 600 may be similar to the process for fabricating the semiconductor device structure 500 but including a further operation to form the second metal nitride layer 125 between the first metal nitride layer 122 and the second metal layer 124.

In some embodiments, the second metal nitride layer 125 may be made of a material including but not limited to tungsten nitride, a material containing W, Si, or N, etc. The second metal nitride layer 125 may be formed by Physical Vapor Deposition (PVD, e.g., evaporation deposition, electrodeposition, sputter deposition) , Chemical Vapor Deposition (CVD) , Atomic Layer Deposition (ALD) , etc. Further, the second metal nitride layer 125 may have a thickness of 1 nm to 6 nm, or 2 nm to 4 nm, etc. In some embodiments, the thickness of the second metal nitride layer 125 may be 3 nm.

According to the present disclosure, the silicon layer 11 may be made of polycrystalline silicon, the first metal layer 121 may be made of titanium, the first metal nitride layer 122 may be made of titanium nitride, the second metal nitride 125 may be made of tungsten nitride, the second metal layer 124 may be made of tungsten, and the insulating layer 13 may be made of silicon nitride. The semiconductor device structure, i.e., the silicon layer 11, the first metal layer 121, the first metal nitride layer 122, the second metal nitride 125, the second metal layer 124, and the insulating layer 121 as illustrated above may form a stacked-gate structure. Further, the semiconductor device structure may be used to form various metallic interconnection lines, e.g., bit line, metallic line, or a capacitor motor including an intermediate structure, etc. Further, the semiconductor device structure may be used in double polycrystalline silicon gates. The double polycrystalline silicon gate may include a substrate, a floating gate on the substrate, a dielectric layer on the floating gate, and a control gate on the dielectric layer. As used herein, the control gate may be made of the semiconductor device structure 600 or any other semiconductor device structure described in the present disclosure (e.g., the semiconductor device structure 400, the semiconductor device structure 500, the semiconductor device structure 700, or the semiconductor device structure 800) .

Further, in existing stacked gates fabricating technology, a tungsten/polycrystalline silicon gate may include a polycrystalline silicon layer, a tungsten nitride layer, and a tungsten layer stacked from bottom to top. A resistance of the tungsten/polycrystalline silicon gate may be relatively lower than a stacked-gate structure including a polycrystalline silicon layer and a tungsten silicide layer. However, during a high-temperature process or a subsequent annealing process in forming the tungsten/polycrystalline silicon gate, tungsten nitride and polycrystalline silicon may proceed a silicification reaction and produce a thin layer of silicon-nitrogen bonds (Si-N) . When the tungsten/polycrystalline silicon gate operates at a relatively low voltage, the thin layer of Si-N bonds may cause delay errors of signals. Therefore, a titanium layer may be added between the polycrystalline silicon layer and the tungsten nitride layer to reduce the delay errors of signal. On one hand, tungsten nitride and titanium may react to produce titanium nitride, which may prevent nitrogen of tungsten nitride from diffusing into the polycrystalline silicon layer to produce the Si-N bonds. On the other hand, titanium and polycrystalline silicon may proceed a silicification reaction when an insulating layer is formed, which may decrease a contact resistance between the polycrystalline silicon and the tungsten nitride layer. However, the titanium/tungsten nitride layer may cause a resistance of the tungsten layer to increase, which may influence the efficiency of the stacked gate. Therefore, a titanium nitride layer may be added between the titanium layer and the tungsten nitride layer. The forming of the titanium nitride layer between the titanium layer and the tungsten nitride layer may decrease the resistance of the tungsten layer and control the silicification reaction between the titanium layer and the polycrystalline silicon layer at a predetermined temperature when the insulating layer is formed, thus achieving a stacked gate with better performance.

As shown in FIG. 6, the semiconductor device structure 600 may include the silicon layer 11, the intermediate layer 12, and the insulating layer 13. The intermediate layer 12 may include at least the first metal silicide layer 126. The first metal silicide layer 126 may be formed on the upper surface of the silicon layer 11. The insulating layer 13 may be formed on the upper surface of the intermediate structure 12.

As used herein, the first metal silicide layer 126 may be formed via the silicification reaction between the first metal layer 121 and the silicon layer 11 during the process of forming the insulating layer 13 at a predetermined temperature. The intermediate structure 12 may further include the second metal layer 124. The second metal layer 124 may be formed between the first metal silicide layer 126 and the insulating layer 13. The second metal layer 124 may include a different metallic element from the first metal silicide 126. In some embodiments, the intermediate structure 12 may further include the first metal nitride layer 122 and the second metal layer 124. The first metal nitride layer 122 may be formed between the first metal silicide layer 126 and the second metal layer 124.

FIGs. 7-8 are schematic diagram illustrating exemplary semiconductor device structures according to some embodiments. The semiconductor device structure 700 may be similar to the semiconductor device structure 400 except that the intermediate structure 12 may further include a second metal silicide layer 123. The semiconductor device structure 800 may be similar to the semiconductor device structure 500 except that the intermediate structure 12 may further include the second metal silicide layer 123 and a first metal nitride layer 122. Accordingly, processes for fabricating the

semiconductor device structure

700 or 800 may be provided. The process for fabricating the semiconductor device structure 700 may be similar to the process 100 but including a further operation to form the second metal silicide layer 123 on a lower surface of the second metal layer 124. The process for fabricating the semiconductor device structure 800 may be similar to the process for fabricating the semiconductor device structure 500 but including a further operation to form the second metal silicide layer 123 on a lower surface of the second metal layer 124 and the first metal nitride layer 122 on a lower surface of the second metal silicide layer 123.

In some embodiments, the second metal silicide layer 123 may be made of a material including titanium silicide, tantalum silicide, palladium silicide, nickel silicide, platinum silicide, cobalt silicide, tungsten silicide, zirconium silicide, or molybdenum silicide, etc. The second metal silicide layer 123 may be formed by Physical Vapor Deposition (PVD, e.g., evaporation deposition, electrodeposition, sputter deposition) , Chemical Vapor Deposition (CVD) , Atomic Layer Deposition (ALD) , etc. Further, the second metal silicide layer 123 may have a thickness of 1 nm to 30 nm, or 5 nm to 20 nm, etc. In some embodiments, the thickness of the first metal nitride layer 122 may be 10 nm.

According to the present disclosure, the second metal silicide layer 123 may be used to deposit a film with a relatively large lattice structure. As such, the second metal layer 124 formed subsequent to the second metal silicide layer 123 may be deposited along the lattice structure of the second metal silicide layer 123 without being affected by a layer beneath the second metal layer 124 (e.g., the first metal nitride layer 122) and generating high resistance. According to the present disclosure, the second metal silicide layer 123 may be formed on the lower surface of the second metal layer 124 and fully cover the lower surface of the second metal layer 124. The second metal silicide layer 123 may be sandwiched between the second metal layer 124 and a layer beneath the second metal layer 124.

In some embodiments, the second metal silicide layer 123 may include a same metallic element as the second metal layer 124, which leads to better adhesion between the second metal silicon layer 123 and the second metal layer 124.

As shown in FIG. 7, the semiconductor device structure 700 may include the silicon layer 11, the intermediate layer 12, and the insulating layer 13. The intermediate layer 12 may include at least the first metal silicide layer 126. The first metal silicide layer 126 may be formed on the upper surface of the silicon layer 11.

As used herein, the first metal silicide layer 126 may be formed via the silicification reaction between the first metal layer 121 and the silicon layer 11 during the process of forming the insulating layer 13 at a predetermined temperature. The intermediate structure 12 may further include the second metal layer 124. The second metal layer 124 may be formed between the first metal silicide layer 126 and the insulating layer 13. The second metal layer 124 may include a different metallic element from the first metal silicide layer 126.

In some embodiments, the intermediate structure 12 may further include the second metal silicide layer 123. The second metal silicide layer 123 may be formed on a lower surface of the second metal layer 124 and between the second metal layer 124 and the first metal silicide layer 126.

Further, as shown in FIG. 8, the semiconductor device structure 800 may include the silicon layer 11, the intermediate structure 12, and the insulating layer 13. The intermediate structure 12 may include the first metal silicide layer 126. The first metal silicide layer 126 may be formed on the upper surface of the first metal silicide layer 126. The insulating layer 13 may be formed on the upper surface of the intermediate structure 12.

In some embodiments, the intermediate structure 12 may further include the first metal nitride layer 122. The first metal nitride layer 122 may be formed between the first metal silicide layer 126 and the second metal layer 124.

In some embodiments, the intermediate structure 12 may further include the second metal silicide layer 123. The second metal silicide layer 123 may be formed on the lower surface of the second metal layer 124 and between the second metal layer 124 and the first metal silicide layer 126. In some embodiments, the second metal silicide layer 123 may include a same metallic element as the second metal layer 122.

FIG. 9 is a schematic diagram illustrating an exemplary stacked-gate storage device according to some embodiments of the present disclosure. As shown in FIG. 9, the stacked-gate storage device may include a substrate 127, a control gate and the insulating layer 13. The substrate 127 may include at least a silicon layer (e.g., the silicon layer 11 shown in FIGs. 2-8) . The control gate may be formed on an upper surface of the substrate 127. The control gate may include any intermediate structure 12 described elsewhere in the present disclosure (e.g., FIGs. 4-8 and the descriptions thereof) . The intermediate structure 12 may include at least a first metal silicide layer 126. The first metal silicide layer 126 may be formed on the upper surface of the substrate 127. The insulating layer 13 may be formed on an upper surface of the intermediate structure 12.

As used herein, the first metal silicide layer 126 may be formed via the silicification reaction between the first metal layer 121 and the silicon layer 11 during the process of forming the insulating layer 13 at a predetermined temperature. The intermediate structure 12 may further include the second metal layer 124 formed between the first metal silicide layer 126 and the insulating layer 13. The second metal layer 124 may include a different metallic element from the first metal silicide layer 126.

In some embodiments, the intermediate structure 12 may further include the first metal nitride layer 122 formed between the first metal silicide layer 126 and the second metal layer 124. The first metal nitride layer 122 may include a same metallic element as the first metal silicide layer 126.

In some embodiments, the intermediate structure 12 may further include the second metal silicide layer 123 formed on a lower surface of the second metal layer 124. The second metal silicide layer 123 may include a same metallic element as the second metal layer 124.

In some embodiments, the stacked-gate storage device may further include a floating gate 129 and a dielectric layer 130. The floating gate 129 may be formed on the upper surface of the substrate 127. The dielectric layer 130 may be formed on an upper surface of the floating gate 129. The control gate may be formed on an upper surface of the dielectric layer 130.

In some embodiments, the present disclosure may provide a stacked-gate flash storage device comprising the semiconductor device structure described above. According to the present embodiment, an oxide layer 128 may be formed between the floating gate 129 and the substrate 127 and act as a first polycrystalline silicon electrode of the floating gate 129. Further, the dielectric layer 130 may be formed on the oxide layer 128, i.e., the first polycrystalline silicon electrode of the floating gate 129. The silicon layer may act as a second polycrystalline silicon electrode of the floating gate 129, and any semiconductor device structure described in the present disclosure may stack on the dielectric layer. Subsequently, an electrode (e.g., tungsten) may be formed. Finally, a mask layer (e.g., silicon nitride) 131 of the semiconductor device structure may be formed. Therefore, the stacked-gate flash storage device may be provided.

The present disclosure provides semiconductor device structures and fabrication processes of the semiconductor device structures. The fabrication process may include providing a silicon layer. The fabrication process may include forming an intermediate structure on an upper surface of the silicon layer. The intermediate structure may include at least a first metal layer. The first metal layer may be formed on the upper surface of the silicon layer. The intermediate structure may further include a second metal layer. The second metal layer may be formed on an upper surface of the first metal layer. The first metal layer may be made of a material different from that of the second metal layer. The fabrication process may include forming an insulating layer on an upper surface of the intermediate structure at a predetermined temperature. The first metal layer and the silicon layer may react to produce a first metal silicide layer at the predetermined temperature. The semiconductor device structure described in the present disclosure and the silicon layer may have a relatively low contact resistance. The semiconductor device structures according to the present disclosure may be used as heat-resistant wirelines. The semiconductor device structure according to the present disclosure may reduce a contact resistance associated with a stacked-gate and ameliorate the efficiency of the stacked-gate. Therefore, the semiconductor device structure according to the present disclosure may overcome the disadvantages of current semiconductor devices structure.

FIG. 10 is a flowchart illustrating an exemplary process for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

In 1010, a silicon layer (e.g., the silicon layer 11 as illustrated in FIGs. 2-8, a silicon layer 21 as illustrated in FIGs. 11-16) may be provided. As described in FIG. 1, the silicon layer may be made of any silicon-containing material, such as monocrystalline silicon, polycrystalline silicon, non-crystalline amorphous silicon, or Silicon-Germanium (Si-Ge) materials, etc. For example, the silicon layer may be a polycrystalline Si-Ge layer. In some embodiments, the silicon layer may be made of any doped silicon–containing material, e.g., intrinsic silicon, P-type silicon, or N-type silicon, etc. It should be appreciated that the materials of the silicon layer described above are for illustration purpose and the present disclosure is not intended to be limiting.

In some embodiments, the silicon layer may be a laminated structure including at least two layers of different materials. For example, the silicon layer may be a laminated structure including a polycrystalline silicon layer with an N-type dopant and a polycrystalline silicon layer with a P-type dopant. In some embodiments, the silicon layer may have a thickness of 10 nm to 120 nm, or 30 nm to 80 nm, etc. In some embodiments, the thickness of the silicon layer may be 50 nm.

In 1020, an intermediate structure (e.g., the intermediate structure 12 as illustrated in FIGs. 3-9, an intermediate structure 22 as illustrated in FIGs. 13-16) may be formed on the silicon layer. The intermediate layer may include a first conductive layer (e.g., the first metal layer as illustrated in FIGs. 3, a first conductive layer 222 as illustrated in FIGs. 12-15) formed on the silicon layer 21. The first conductive layer may be used to decrease a contact resistance between the silicon layer and the intermediate structure. Specifically, the first conductive layer may react with the silicon layer to produce a transition layer (e.g., a metal nitride layer) at a predetermined temperature.

In some embodiments, the first conductive layer may be made of a first material. The first material may include Tantalum (Ta) , Palladium (Pd) , Platinum (Pt) , Cobalt (Co) , Zirconium (Zr) , Nickel (Ni) , Titanium (Ti) , or Molybdenum (Mo) , etc. For example, the first conductive layer may be made of Ta.

In some embodiments, the first conductive layer may be formed by Physical Vapor Deposition (PVD, e.g., evaporation deposition, electrodeposition, sputter deposition) , Chemical Vapor Deposition (CVD) , Atomic Layer Deposition (ALD) , etc. In some embodiments, the first conductive layer may have a thickness of 1 nm to 30 nm, 1 nm to 10 nm, 11 nm to 20 nm, etc. In some embodiments, the thickness of the first conductive layer may be 15 nm.

In some embodiments, the intermediate structure may also include a first control layer (e.g., the first metal nitride layer 122 as illustrated in FIGs. 5, 6, and 8, the first control layer 224 as illustrated in FIGs. 13-16, etc. ) . The first control layer may be formed on the first conductive layer. The first control layer may be used to control the reaction between the silicon layer and the first conductive layer. If the silicon layer and the first conductive layer is overreacted, the metal silicide in the transition layer may aggregate into blocks, thus, increasing the contact resistance between the silicon layer and the intermediate structure.

In some embodiments, the first control layer may be made of a nitride of the first material, i.e., the first control layer may have the same metallic element of the first conductive layer. Therefore, an adhesion between the first control layer and the first conductive layer may be relatively good. The nitride of the first material may include tantalum nitride, palladium nitride, platinum nitride, cobalt nitride, zirconium nitride, nickel nitride, titanium nitride, or molybdenum nitride, etc.

In some embodiment, the first control layer may be formed by Physical Vapor Deposition (PVD, e.g., evaporation deposition, electrodeposition, sputter deposition) , Chemical Vapor Deposition (CVD) , Atomic Layer Deposition (ALD) , etc. Further, the first control layer may have a thickness of 3 nm to 50 nm, 5 nm to 30 nm, or 10 nm to 20 nm, etc. In some embodiments, the thickness of the first control layer may be 15 nm.

In some embodiments, the intermediate structure may also include a second control layer (e.g., the first metal nitride layer 123 as illustrated in FIGs. 4, 7, and 8, a second control layer 226 as illustrated in FIGs. 14-16, etc. ) . The second control layer may be formed on the first control layer. In some embodiments, the second control layer may be deposited on the first control layer as a film with a relatively large lattice structure. Therefore, a subsequent layer may be deposited along the lattice structure without being affected by the first control layer underneath.

In some embodiments, the second control layer may be made of a silicide of a second material. The second material may be selected from tantalum, palladium, platinum, cobalt, zirconium, nickel, titanium, and molybdenum, etc. In some embodiments, the second material may be different from the first material. For example, the first material may be Ta, and the second material may be Ti. The first material and the second material may be selected according to actual needs in various fabrication scenarios. It should be appreciated that the first material and the second material described above are for illustration purpose and the present disclosure is not intended to be limiting.

In some embodiments, the second control layer may be formed by Physical Vapor Deposition (PVD, e.g., evaporation deposition, electrodeposition, sputter deposition) , Chemical Vapor Deposition (CVD) , Atomic Layer Deposition (ALD) , etc. In some embodiments, the second control layer may have a thickness of 1 nm to 30 nm, or 5 nm to 20 nm, etc. In some embodiments, the thickness of the second control layer may be 10 nm.

In some embodiments, the intermediate structure may also include a second conductive layer (e.g., the second metal layer 124 as illustrated in FIGs. 3-9, a second metal layer 228 as illustrated in FIGs. 15-16 ) . The second conductive layer may be formed on the second control layer.

In some embodiments, the second conductive layer may be made of the second material described above, i.e., the second conductive layer may have a same metallic element as the second control layer. Accordingly, an adhesion between the second conductive layer and the second control layer may be relatively good.

In some embodiments, the second conductive layer may be formed by Physical Vapor Deposition (PVD, e.g., evaporation deposition, electrodeposition, sputter deposition) , Chemical Vapor Deposition (CVD) , Atomic Layer Deposition (ALD) , etc. Further, the second conductive layer may have a thickness of 10 nm to 100 nm, 20 nm to 80 nm, 30 nm to 60 nm, etc. In some embodiments, the thickness of the second conductive layer may be 50 nm.

In 1030, an insulating layer (e.g., the insulating layer 13 as illustrated in FIGs. 4-9, an insulating layer as illustrated in FIGs. 15-16) may be formed on the intermediate layer under a predetermined temperature. The insulating layer may be used to protect a structure (e.g., the intermediate structure and the silicon layer) of the semiconductor device structure underneath the insulating layer from oxidation due to exposure to the air. Further, when the insulating layer is formed at the predetermined temperature, the first conductive layer and the silicon layer may proceed a silicification reaction to produce the transition layer, which may reduce a contact resistance between the silicon layer and the first conductive layer.

In some embodiments, the predetermined temperature may be a temperature range such as, 550° to 880℃, or 600℃ to 750℃, etc. In some embodiments, the predetermined temperature may be a temperature value such as, 650℃. A predetermined temperature lower than 550℃ may be not high enough for the silicification reaction between the silicon layer and the first conductive layer. On the other hand, a predetermined temperature greater than 800℃ may cause overreaction between the silicon layer and the first metal layer, causing the metal silicide in the transition layer to aggregate into blocks, which in turn increasing the contact resistance.

In some embodiments, the insulating layer may be made of silicon nitride. Further, the insulating layer may be formed by Chemical Vapor Deposition (CVD) , Atomic Layer Deposition (ALD) , etc. Further, the insulating layer 126 may have a thickness of 50nm to 400 nm, or 150 nm to 300 nm, etc. In some embodiments, the thickness of the insulating layer 13 may be 200 nm.

It should be noted that the above description is merely provided for the purposes of illustration, and not intended to limit the scope of the present disclosure. For persons having ordinary skills in the art, multiple variations or modifications may be made under the teachings of the present disclosure. However, those variations and modifications do not depart from the scope of the present disclosure.

FIG. 11 is a schematic diagram illustrating an exemplary first partial of the semiconductor device structure formed based on operation 1010 according to some embodiments of the present disclosure.

As shown in FIG. 11, after operation 1010 is performed, the first partial of the semiconductor device structure includes a silicon layer 21.

FIGs 12-15 are schematic diagrams illustrating exemplary second partials of the semiconductor device structure based on operation 1010-1020 according to some embodiments of the present disclosure.

According to the embodiment shown in FIG. 12, after operation 1010 and operation 1020 are performed, the second partial of the semiconductor device structure includes the silicon layer 21 and a first conductive layer 222. The first conductive layer 222 may stacks on the silicon layer 21.

According to the embodiment shown in FIG. 13, after operation 1010 and operation 1020 are performed, the second partial of the semiconductor device structure includes the silicon layer 21, the first conductive layer 222, and a first control layer 224. The first control layer 224 stacks on the first conductive layer 222. The intermediate structure 22 may include the first conductive layer 222 and the first control layer 224.

According to the embodiment shown in FIG. 14, after operation 1010 and operation 1020 are performed, the second partial of the semiconductor device structure includes the silicon layer 21, the first conductive layer 222, the first control layer 224 and a second control layer 226. The second control layer 226 stacks on the first control layer 224. The intermediate structure 22 may include the first conductive layer 222, the first control layer 224, and the second control layer 226.

According to the embodiment shown in FIG. 15, after operation 1010 and operation 1020 are performed, the second partial of the semiconductor device structure may include the silicon layer 21, the first conductive layer 222, the first control layer 224, the second control layer 226 and a second conductive layer 228. The second conductive layer 228 stacks on the second control layer 226. The intermediate structure 22 may include the first conductive layer 222, the first control layer 224, the second control layer 226, and the second conductive layer 228.

FIG. 16 is a schematic diagram illustrating an exemplary semiconductor device structure based on the process 1000.

According to the embodiment shown in FIG. 16, the semiconductor device structure includes the silicon layer 21, the first conductive layer 222, the first control layer 224, the second control layer 226, the second conductive layer 228 and an insulating layer 23. The insulating layer 23 stacks on the second conductive layer 228. The intermediate structure 22 may include the first conductive layer 222, the first control layer 224, the second control layer 226, and the second conductive layer 228.

It should be noted is merely provided for the purposes of illustration, and not intended to limit the scope of the present disclosure. For persons having ordinary skills in the art, multiple variations or modifications may be made under the teachings of the present disclosure. However, those variations and modifications do not depart from the scope of the present disclosure. In some embodiments, the intermediate structure 22 may include any intermediate structure 12 described in the present disclosure (e.g., the intermediate structure 12 as illustrated in FIGs. 3-9) . For example, the intermediate structure 22 may include the transition layer and the second conductive layer. As another example, the intermediate structure 22 may include the first control layer, the second conductive layer and the transition layer.

Having thus described the basic concepts, it may be rather apparent to those skilled in the art after reading this detailed disclosure that the foregoing detailed disclosure is intended to be presented by way of example only and is not limiting. Various alterations, improvements, and modifications may occur and are intended to those skilled in the art, though not expressly stated herein. These alterations, improvements, and modifications are intended to be suggested by this disclosure and are within the spirit and scope of the exemplary embodiments of this disclosure.

Moreover, certain terminology has been used to describe embodiments of the present disclosure. For example, the terms “one embodiment, ” “an embodiment, ” and/or “some embodiments” mean that a particular feature, structure or characteristic described in connection with some embodiments is included in at least one embodiment of the present disclosure. Therefore, it is emphasized and should be appreciated that two or more references to “an embodiment” or “one embodiment” or “an alternative embodiment” in various portions of this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined as suitable in one or more embodiments of the present disclosure.

Further, it will be appreciated by one skilled in the art, aspects of the present disclosure may be illustrated and described herein in any of a number of patentable classes or context including any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof.

Furthermore, the recited order of processing elements or sequences, or the use of numbers, letters, or other designations, therefore, is not intended to limit the claimed processes and methods to any order except as may be specified in the claims. Although the above disclosure discusses through various examples what is currently considered to be a variety of useful embodiments of the disclosure, it is to be understood that such detail is solely for that purpose and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover modifications and equivalent arrangements that are within the spirit and scope of the disclosed embodiments. For example, although the implementation of various components described above may be embodied in a hardware device, it may further be implemented as a software-only solution, e.g., an installation on an existing server or mobile device.

Similarly, it should be appreciated that in the foregoing description of embodiments of the present disclosure, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various embodiments. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed subject matter requires more features than are expressly recited in each claim. Rather, claimed subject matter may lie in less than all features of a single foregoing disclosed embodiment.

Claims

A fabrication method for a semiconductor device structure, comprising:

providing a silicon layer;

forming an intermediate layer on the silicon layer, wherein the intermediate layer includes a first conductive layer formed on the silicon layer; and

forming an insulating layer on the intermediate layer under a predetermined temperature, thereby at least partial of the first conductive layer and at least partial of the silicon layer together forming a transition layer on the silicon layer.
The method of claim 1, wherein forming the intermediate layer on the silicon layer further comprises:

forming a first control layer on the first conductive layer, wherein

the first conductive layer is made of a first material, and the first control layer is made of a nitride of the first material.
The method of claim 2, wherein forming the intermediate layer on the silicon layer further comprises:

forming a second control layer on the first control layer, wherein

the second control layer is made of a silicide of a second material.
The method of claim 3, wherein forming the intermediate layer on the silicon layer further comprises:

forming a second conductive layer on the second control layer, wherein

the second conductive layer is made of the second material.
The method of claim 4, wherein the insulating layer is formed on the second conductive layer.
The method of claim 1, wherein the silicon layer has a thickness of 10 nm to 120 nm.
The method of claim 1, wherein the first conductive layer has a thickness of 1 nm to 30 nm.
The method of claim 1, wherein the insulating layer has a thickness of 50 nm to 400 nm.
The method of claim 1, wherein the predetermined temperature is 550 ℃ to 880 ℃.
The method of claim 1, wherein the insulating layer is formed by chemical vapor deposition.
The method of claim 2, wherein the first material is selected from a group comprising tantalum, palladium, platinum, cobalt, zirconium, nickel, titanium, and molybdenum.
The method of claim 2, wherein the first control layer has a thickness of 3 nm to 50 nm.
The method of claim 3, wherein the second control layer has a thickness of 1 nm to 30 nm.
The method of claim 4, wherein the first material is different from the second material.
The method of claim 4, wherein the second material is selected from a group comprising tantalum, palladium, platinum, cobalt, zirconium, nickel, titanium, and molybdenum.
The method of claim 4, wherein the second conductive layer has a thickness of 10 nm to 100 nm.
A fabrication method for a semiconductor device structure, comprising:

providing a silicon layer;

forming an intermediate layer on the silicon layer, wherein the intermediate layer includes

a first metal layer, made of a first metal and formed on an upper surface of the silicon layer; and

a second metal layer, made of a second metal and formed on the first metal layer;

forming an insulating layer on an upper surface of the intermediate layer under a predetermined temperature, thereby at least partial of the first metal layer and at least partial of the silicon layer together forming a first metal silicide layer on the silicon layer.
The method of claim 17, wherein the intermediate layer further includes:

a second metal silicide layer, made of a silicide of the second metal and formed between the second metal layer and the first metal layer.
The method of claim 17, wherein the intermediate layer further includes:

a metal nitride layer formed between the first metal layer and the second metal silicide layer.
The method of claim 19, wherein the metal nitride layer is made of a nitride of the first metal.
The method of claim 17, wherein the predetermined temperature is 550 ℃ to 880 ℃.
A semiconductor device structure, comprising:

a silicon layer;

an intermediate layer on the silicon layer, wherein the intermediate layer includes

a first metal layer, made of a first metal and formed on an upper surface of the silicon layer; and

a second metal layer, made of a second metal and formed on the first metal layer;

an insulating layer on an upper surface of the intermediate layer formed under a predetermined temperature, thereby at least partial of the first metal layer and at least partial of the silicon layer together forming a first metal silicide layer on the silicon layer.
The device of claim 22, wherein the intermediate layer further includes:

a second metal silicide layer, made of a silicide of the second metal and formed between the second metal layer and the first metal layer.
The device of claim 22, wherein the intermediate layer further includes:

a metal nitride layer formed between the first metal layer and the second metal silicide layer.
The device of claim 24, wherein the metal nitride layer is made of a nitride of the first metal.
The device of claim 22, wherein the predetermined temperature is 550 ℃ to 880 ℃.
A stacked-gate storage device, comprising:

a substrate including at least a silicon layer; and,

a control gate located on the substrate, wherein the control gate includes

a silicon layer;

an intermediate layer on the silicon layer, wherein the intermediate layer includes

a first metal layer, made of a first metal and formed on an upper surface of the silicon layer; and

a second metal layer, made of a second metal and formed on the first metal layer;

an insulating layer on an upper surface of the intermediate layer formed under a predetermined temperature, thereby at least partial of the first metal layer and at least partial of the silicon layer together forming a first metal silicide layer on the silicon layer.
The stacked-gate storage device of claim 27, further comprising:

a floating gate located on an upper surface of the substrate; and

a dielectric layer located on an upper surface of the floating gate, wherein the control gate is formed on an upper surface of the dielectric layer.