WO2018220973A1 - Etching method - Google Patents

Etching method Download PDF

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Publication number
WO2018220973A1
WO2018220973A1 PCT/JP2018/012689 JP2018012689W WO2018220973A1 WO 2018220973 A1 WO2018220973 A1 WO 2018220973A1 JP 2018012689 W JP2018012689 W JP 2018012689W WO 2018220973 A1 WO2018220973 A1 WO 2018220973A1
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Prior art keywords
film
etching
gas
silicon
wafer
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PCT/JP2018/012689
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French (fr)
Japanese (ja)
Inventor
麗紅 笹原
戸田 聡
阿部 拓也
祖虹 黄
淑恵 小澤
健 中込
賢一 中畑
健史郎 旭
Original Assignee
東京エレクトロン株式会社
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Priority claimed from JP2017162179A external-priority patent/JP7109165B2/en
Application filed by 東京エレクトロン株式会社 filed Critical 東京エレクトロン株式会社
Priority to KR1020197037632A priority Critical patent/KR102441239B1/en
Priority to US16/617,992 priority patent/US11127597B2/en
Publication of WO2018220973A1 publication Critical patent/WO2018220973A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/0206Cleaning during device manufacture during, before or after processing of insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02359Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the surface groups of the insulating layer
    • HELECTRICITY
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • H01L21/67063Apparatus for fluid treatment for etching
    • H01L21/67075Apparatus for fluid treatment for etching for wet etching
    • H01L21/6708Apparatus for fluid treatment for etching for wet etching using mainly spraying means, e.g. nozzles
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • H01L21/67063Apparatus for fluid treatment for etching
    • H01L21/67075Apparatus for fluid treatment for etching for wet etching
    • H01L21/67086Apparatus for fluid treatment for etching for wet etching with the semiconductor substrates being dipped in baths or vessels
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H01L21/31056Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask

Definitions

  • the present disclosure relates to an etching method.
  • etching is performed in the manufacturing process of a semiconductor device.
  • a chemical etching technique capable of performing low damage etching has attracted attention.
  • a chemical oxide removal process (Chemical Oxide Removal; using a mixed gas of hydrogen fluoride (HF) gas and ammonia (NH 3 ) gas as a processing gas; COR) technology is used (for example, Patent Documents 1 and 2).
  • Patent Document 3 Since it is often SiN film which is adjacent to the SiO 2 film, a selectively technique for etching the SiN film against the SiO 2 film, Patent Document 3, and HF gas, and F 2 gas, inert It describes that etching is performed by supplying a gas and O 2 gas in an excited state.
  • the present disclosure provides an etching method capable of etching a silicon nitride (SiN) film with high selectivity to a silicon oxide (SiO 2 ) film, silicon (Si), and silicon germanium (SiGe).
  • An etching method includes a step of placing a substrate to be processed having a silicon nitride film, a silicon oxide film, silicon, and silicon germanium in a chamber, a step of setting the pressure in the chamber to 1333 Pa or more, Supplying hydrogen fluoride gas into the chamber, and selectively etching the silicon nitride film with respect to the silicon oxide film, silicon, and silicon germanium.
  • an etching method capable of etching a silicon nitride (SiN) film with high selectivity with respect to a silicon oxide (SiO 2 ) film, silicon (Si), and silicon germanium (SiGe). .
  • Patent Document 3 In the case of etching a SiN film in a semiconductor device using Si and SiGe such as a CMOS transistor, for example, the technique disclosed in Patent Document 3 has sufficient selectivity for all of the SiO 2 film, Si and SiGe. It is difficult to etch the SiN film.
  • the SiO 2 film may be damaged when the SiN film is etched in Patent Document 3 described above.
  • the inventors have conducted various studies to eliminate these points. As a result, it is possible to etch with high selectivity to a silicon oxide (SiO 2 ) film, silicon (Si) and silicon germanium (SiGe) by etching the silicon nitride film at a high pressure using HF gas. I found it. Further, when the SiN film is etched on the substrate to be processed having the SiN film and the SiO 2 film, it is effective to perform a surface modification process for removing impurities and the like in the film prior to the etching of the silicon nitride film. I found out.
  • FIG. 1 is a process cross-sectional view when an SiN film is etched with respect to an example of a structure to which the etching method of the first embodiment is applied.
  • FIG. 1A is an example of a structure to which the etching method of this embodiment is applied.
  • a pole-like Si film 12 and a SiGe film 13 are formed on a silicon substrate 11.
  • the first SiO 2 film 14 is formed around the periphery and SiGe film 13 of the Si film 12, on the first ambient and Si film 12 and the SiGe film 13 of SiO 2 film 14, SiN film 15 Is formed.
  • a second SiO 2 film 16 is formed between the SiN film 15 around the Si side and the SiN film 15 around the SiGe side.
  • the SiN film 15 having the structure shown in FIG. 1A is etched to form a desired semiconductor device. In this case, ideally, only the SiN film 15 is removed as shown in FIG. That is, it is required to etch the SiN film 15 with a high selectivity with respect to the Si film 12, the SiGe film 13, and the first and second SiO 2 films 14 and 16.
  • FIG. 2 is a process cross-sectional view when the SiN film is etched with respect to another example of the structure to which the etching method of the first embodiment is applied.
  • FIG. 2A shows another example of a structure to which the etching method of this embodiment is applied.
  • a first Si film 22a, a second Si film 22b, and a third Si film 22c having a pole shape from the left side are provided on the silicon substrate 21, and a pole shape is formed on the right side.
  • a formed SiGe film 23 is formed.
  • a hard mask 24 remains on the first to third Si films 22 a to 22 c and the SiGe film 23.
  • An SiO 2 film 25 is formed on the silicon substrate 21 from the periphery of the first Si film 22a and the end on the first Si film 22a side to the third Si film 22c.
  • a SiN film 26 is provided on the SiO 2 film 25 and around the second Si film 22b.
  • the SiN film 26 having the structure shown in FIG. 2A is etched to form a desired semiconductor device. At this time, ideally, only the SiN film 26 is removed as shown in FIG. That is, it is required to etch the SiN film 26 with a high selectivity with respect to the first to third Si films 22a to 22c, the SiGe film 23, and the SiO 2 film 25.
  • the selection ratio to SiO 2 is required to be 5 or more, and the selection ratio to Si and SiGe is required to be 50 or more.
  • the Si film 12 the first to third Si films 22a to 22c, and the SiGe films 13 and 23, for example, those formed by epitaxial growth or polycrystalline films formed by CVD can be used.
  • the first and second SiO 2 films 14 and 16 and the SiO 2 film 25 are formed by chemical vapor deposition (CVD), they are formed by atomic layer deposition (ALD). Or may be a thermal oxide film.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • thermal oxide film There are various methods for forming a SiO 2 film by CVD, and the amount of hydrogen (H), carbon (C), nitrogen (N), etc. contained as impurities differs depending on the method, and low grade CVD.
  • the -SiO 2 film contains a relatively large amount of impurities.
  • the ALD-SiO 2 film contains these impurities.
  • thermal oxide film there are few such impurities.
  • the SiN film to be etched is formed by thermal CVD, plasma CVD, silane-based gas such as SiH 4 gas, SiH 2 Cl 2 , Si 2 Cl 6 and nitrogen-containing gas such as NH 3 gas or N 2 gas.
  • silane-based gas such as SiH 4 gas, SiH 2 Cl 2 , Si 2 Cl 6 and nitrogen-containing gas such as NH 3 gas or N 2 gas.
  • the film is formed by ALD or the like.
  • SiN film etching of the first embodiment When the SiN film shown in the above device example is formed adjacent to SiO 2 , Si and SiGe, as an attempt to etch the SiN film with a high selectivity, (1) HF gas or HF gas + NH 3 A method of etching with a COR device using a gas, (2) a method of etching by adding F 2 to the gas system, and (3) a method by radical SiN etching have been performed.
  • the SiN / SiO 2 selection ratio is smaller than 2.
  • the SiN / SiO 2 selection ratio is improved, the selection ratio for Si cannot be obtained.
  • (3) radical SiN etching the SiN / SiO 2 selectivity can be obtained, but the SiN / SiGe selectivity cannot be obtained.
  • a semiconductor wafer having the above-described structure (also simply referred to as a wafer) is accommodated in a chamber, and only HF gas or a mixed gas of HF gas and inert gas is contained in the chamber. It is done by introducing.
  • the inert gas N 2 gas or a rare gas such as Ar or He can be used.
  • the gas flow rate at this time is preferably HF gas: 200 to 3000 sccm, and inert gas: 200 to 3000 sccm.
  • the pressure in the chamber at this time is set to a high pressure of 1333 Pa (10 Torr) or more as described above. It is preferably 1333 to 11997 Pa (10 to 90 Torr). More preferably, it is 1333 to 5332 Pa (10 to 40 Torr).
  • the wafer temperature is preferably 10 to 120 ° C. Below 10 ° C. and above 120 ° C., it may be difficult to obtain a desired selection ratio. More preferably, it is 30 to 80 ° C.
  • Etching of the SiN film is performed for a predetermined time according to the thickness of the SiN film under the above conditions, so that the SiN film has a high selectivity with a selectivity of 5 or more with respect to SiO 2 and a selectivity of 50 or more with respect to Si and SiGe.
  • the film can be etched.
  • the selection ratio to SiO 2 is preferably 15 or more and the selection ratio to Si and SiGe is preferably 100 or more.
  • FIG. 3 is a schematic configuration diagram illustrating an example of a processing system used in the first embodiment.
  • the processing system 100 includes a carry-in / out unit 102, two load lock chambers 103, two heat treatment apparatuses 104, two etching apparatuses 105, and a control unit 106.
  • the loading / unloading unit 102 is for loading / unloading the wafer W having the structure shown in the above structure example.
  • the two load lock chambers 103 are provided adjacent to the carry-in / out section 102.
  • the two heat treatment apparatuses 104 are provided adjacent to each load lock chamber 103, and are for performing heat treatment on the wafer W.
  • the two etching apparatuses 105 are provided adjacent to the respective heat treatment apparatuses 104 and perform etching on the wafer W.
  • the loading / unloading unit 102 has a transfer chamber 112 in which a first wafer transfer mechanism 111 for transferring the wafer W is provided.
  • the first wafer transfer mechanism 111 has two transfer arms 111a and 111b that hold the wafer W substantially horizontally.
  • a mounting table 113 is provided on the side of the transfer chamber 112 in the longitudinal direction.
  • three carriers C that accommodate a plurality of wafers W such as FOUP can be connected to the mounting table 113.
  • An alignment chamber 114 for aligning the wafer W is provided adjacent to the transfer chamber 112.
  • the wafer W is held by the transfer arms 111 a and 111 b, and is moved to a desired position by moving straight and moving up and down substantially in a horizontal plane by driving the first wafer transfer mechanism 111. Then, the transfer arms 111 a and 111 b are moved forward and backward with respect to the carrier C, the alignment chamber 114, and the load lock chamber 103 on the mounting table 113, respectively, so that they can be carried in and out.
  • the two load lock chambers 103 are connected to the transfer chamber 112 with the gate valve 116 interposed between the two load lock chambers 103.
  • a second wafer transfer mechanism 117 for transferring the wafer W is provided in each load lock chamber 103.
  • the load lock chamber 103 is configured to be evacuated to a predetermined degree of vacuum.
  • the second wafer transfer mechanism 117 has an articulated arm structure and has a pick for holding the wafer W substantially horizontally.
  • the pick is positioned in the load lock chamber 103 with the articulated arm contracted, and the pick reaches the heat treatment apparatus 104 by extending the articulated arm and further extends. It is possible to reach the etching apparatus 105, and the wafer W can be transferred between the load lock chamber 103, the heat treatment apparatus 104, and the etching apparatus 105.
  • the control unit 106 is typically a computer, and includes a main control unit having a CPU that controls each component of the processing system 100, an input device (keyboard, mouse, etc.), an output device (printer, etc.), and a display device ( Display) and a storage device (storage medium).
  • the main control unit of the control unit 106 causes the processing system 100 to execute a predetermined operation based on a processing recipe stored in a storage medium built in the storage device or a storage medium set in the storage device. .
  • a plurality of wafers W on which the above structure is formed are stored in a carrier C and transferred to the processing system 100.
  • a single wafer W is loaded from the carrier C of the loading / unloading unit 102 by the transfer arms 111 a and 111 b of the first wafer transfer mechanism 111 with the atmosphere-side gate valve 116 opened.
  • the second wafer transfer mechanism 117 in the load lock chamber 103 To the pick of the second wafer transfer mechanism 117 in the load lock chamber 103.
  • the gate valve 116 on the atmosphere side is closed and the load lock chamber 103 is evacuated, then the gate valve 154 is opened, the pick is extended to the etching apparatus 105, and the wafer W is transferred to the etching apparatus 105.
  • the pick is returned to the load lock chamber 103, the gate valve 154 is closed, and the SiN film is etched in the etching apparatus 105 by the etching method described above.
  • the gate valves 122 and 154 are opened, the wafer W after the etching process is transferred to the heat treatment apparatus 104 by the pick of the second wafer transfer mechanism 117, and the etching residue and the like are removed by heating.
  • the heat treatment in the heat treatment apparatus 104 After the heat treatment in the heat treatment apparatus 104 is completed, it is returned to the carrier C by one of the transfer arms 111a and 111b of the first wafer transfer mechanism 111. Thereby, processing of one wafer is completed.
  • the wafer W after the etching process is finished is load-locked by the pick of the second wafer transfer mechanism 117. It may be retracted to the chamber 103 and returned to the carrier C by one of the transfer arms 111a and 111b of the first wafer transfer mechanism 111.
  • FIG. 4 is a cross-sectional view showing an example of the etching apparatus 105.
  • the etching apparatus 105 includes a sealed chamber 140, and a mounting table 142 for mounting the wafer W in a substantially horizontal state is provided inside the chamber 140.
  • the etching apparatus 105 also includes a gas supply mechanism 143 that supplies an etching gas to the chamber 140 and an exhaust mechanism 144 that exhausts the inside of the chamber 140.
  • the chamber 140 includes a chamber main body 151 and a lid 152.
  • the chamber main body 151 has a substantially cylindrical side wall portion 151 a and a bottom portion 151 b, and an upper portion is an opening, and the opening is closed by a lid portion 152.
  • the side wall portion 151a and the lid portion 152 are sealed by a seal member (not shown), and airtightness in the chamber 140 is ensured.
  • the lid portion 152 includes a lid member 155 that constitutes the outside, and a shower head 156 that is fitted inside the lid member 155 and faces the mounting table 142.
  • the shower head 156 includes a main body 157 having a cylindrical side wall 157a and an upper wall 157b, and a shower plate 158 provided at the bottom of the main body 157.
  • a space 159 is formed between the main body 157 and the shower plate 158.
  • a gas introduction path 161 is formed through the cover member 155 and the upper wall 157b of the main body 157 to the space 159, and an HF gas supply pipe 171 of a gas supply mechanism 143, which will be described later, is connected to the gas introduction path 161. ing.
  • a plurality of gas discharge holes 162 are formed in the shower plate 158, and the gas introduced into the space 159 through the gas supply pipe 171 and the gas introduction path 161 is discharged from the gas discharge hole 162 into the space in the chamber 140. .
  • the side wall 151 a is provided with a loading / unloading port 153 for loading / unloading the wafer W to / from the heat treatment apparatus 104, and the loading / unloading port 153 can be opened and closed by a gate valve 154.
  • the mounting table 142 has a substantially circular shape in plan view, and is fixed to the bottom 151 b of the chamber 140. Inside the mounting table 142, a temperature controller 165 for adjusting the temperature of the mounting table 142 is provided.
  • the temperature controller 165 includes, for example, a pipe line through which a temperature adjusting medium (for example, water) circulates, and heat exchange is performed with the temperature adjusting medium flowing in the pipe line, thereby the mounting table 142. The temperature of the wafer W on the mounting table 142 is controlled.
  • a temperature adjusting medium for example, water
  • the gas supply mechanism 143 includes an HF gas supply source 175 that supplies HF gas and an inert gas supply source 176 that supplies inert gas. These include an HF gas supply pipe 171 and an inert gas supply pipe, respectively. One end of 172 is connected.
  • the HF gas supply pipe 171 and the inert gas supply pipe 172 are provided with a flow rate controller 179 that performs opening / closing operation of the flow path and flow rate control.
  • the flow rate controller 179 includes, for example, an on-off valve and a mass flow controller.
  • the other end of the HF gas supply pipe 171 is connected to the gas introduction path 161 as described above.
  • the other end of the inert gas supply pipe 172 is connected to the HF gas supply pipe 171.
  • the HF gas is supplied from the HF gas supply source 175 through the HF gas supply pipe 171 into the shower head 156, and the inert gas is supplied from the inert gas supply source 176 to the inert gas supply pipe 172 and the HF gas supply pipe. 171 is supplied to the shower head 156. These gases are discharged from the gas discharge holes 162 of the shower head 156 toward the wafer W in the chamber 140.
  • HF gas is a reactive gas
  • an inert gas is used as a dilution gas and a purge gas. Desired etching performance can be obtained by supplying HF gas alone or by mixing HF gas and inert gas.
  • the exhaust mechanism 144 has an exhaust pipe 182 connected to an exhaust port 181 formed in the bottom portion 151 b of the chamber 140.
  • the exhaust mechanism 144 further includes an automatic pressure control valve (APC) 183 provided on the exhaust pipe 182 for controlling the pressure in the chamber 140 and a vacuum pump 184 for exhausting the interior of the chamber 140.
  • APC automatic pressure control valve
  • two capacitance manometers 186a and 186b are provided so as to be inserted into the chamber 140 as pressure gauges for measuring the pressure in the chamber 140.
  • the capacitance manometer 186a is for high pressure
  • the capacitance manometer 186b is for low pressure.
  • a temperature sensor (not shown) for detecting the temperature of the wafer W is provided in the vicinity of the wafer W mounted on the mounting table 142.
  • the wafer W having the above-described structure is loaded into the chamber 140 and placed on the mounting table 142.
  • the temperature controller 165 of the mounting table 142 sets the wafer W to preferably 10 to 120 ° C., more preferably 30 to 80 ° C.
  • the pressure in the chamber 140 is 1333 Pa (10 Torr) or more, preferably 1333 to 11997 Pa (10 to 90 Torr), more preferably 1333 to 5332 Pa (10 to 40 Torr).
  • HF gas and inert gas are preferably supplied at a flow rate of 200 to 3000 sccm to etch the SiN film.
  • This embodiment includes a step of removing the SiN film by etching, as in the first embodiment.
  • This embodiment also contain impurities such as N and H on SiO 2 film adjacent to the SiN film, damage to the SiO 2 film when etching the SiN film is described hardly etching method generated .
  • the SiO 2 film If it contains impurities such as H and N in the SiO 2 film, it is etched by SiN film directly HF gas adjacent thereto, the gas components such as H and N in the impurities contained in the SiO 2 film However, it was found to react with HF during the etching of the SiN film. If such a gas component reacts with HF during etching of the SiN film, the SiO 2 film is etched unevenly, and damage such as pitting (holes) or surface roughness may occur. For example, in the case of a SiO 2 film formed by CVD or ALD, H, N, C, etc. derived from the film forming source gas are present in the film, and there is a risk of damage during etching of the SiN film. .
  • the SiO 2 interlayer insulating film formed by CVD or ALD when the annealing temperature of the SiO 2 interlayer insulating film formed by CVD or ALD is low, in addition to the presence of the impurities, the density is low and the SiN film is susceptible to damage during etching.
  • the SiO 2 film formed by fluid chemical vapor deposition (F-CVD) is also susceptible to damage during etching of the SiN film because it contains many impurities as described above and has a low density.
  • the SiO 2 film adjacent to the SiN film is etched, in addition to the impurities originally contained, the components that enter the film during etching and the wafers W adhere to the wafer W without being completely removed. Gas components are present.
  • the SiN film is etched, the HF and the attached gas component are easily damaged by the etching of the SiO 2 film.
  • the SiO 2 film is removed by COR, the film contains NH 3 and F in the gas component in addition to impurities such as H, N, and C, and further, NH 4 and HF 2 , etc. There is a possibility that a highly reactive by-product is attached to the wafer W.
  • the SiO 2 film Since these coexist with HF during the etching of the SiN film, the SiO 2 film is easily etched. As described above, when the SiO 2 film is a CVD film or an ALD film, impurities are present, and depending on the film formation method, there are many impurities in the film and the density tends to be low. Therefore, gas components present during the SiO 2 film etching or reaction products coupled with damage of the SiO 2 film by etching the SiN film becomes more larger.
  • FIG. 5 is a diagram for explaining a mechanism that causes damage to the SiO 2 film when the SiN film adjacent to the SiO 2 film containing impurities is etched with HF gas.
  • A the deposited by FCVD on the Si substrate 40, SiO 2 film 41 is etched by the COR, C as an impurity into the surface layer portion of the film, F, it is included NH 3 or the like.
  • HF gas as the etching gas in this state
  • HF as the etching gas and NH 3 in the film react with Si in SiO 2.
  • Ammonium fluorosilicate ((NH 4 ) 2 SiF 6 ; AFS) is produced.
  • ammonium fluorosilicate is volatilized and a pitting 42 is formed in the SiO 2 film 41. This also causes surface roughness on the surface of the SiO 2 film 41. Similarly, when a by-product such as NH 4 or HF 2 adheres to the SiO 2 film 41, pitting or surface roughness occurs.
  • the wafer is first subjected to surface modification processing (step 1), and then the SiN film is etched with HF gas (step 1). 2).
  • the surface modification treatment in Step 1 is for removing impurities such as NH 3 , F, and C in the film and by-products such as NH 4 and HF 2 adhering to the wafer W. By removing these by the surface modification treatment, the SiO 2 film becomes difficult to be etched by the subsequent SiN film etching.
  • Examples of the surface modification treatment include dry treatment in which heat treatment is performed in an inert atmosphere.
  • the temperature at this time is preferably 150 to 400 ° C., for example, 250 ° C.
  • impurities such as NH 3 , F, and C in the film and by-products such as NH 4 and HF 2 adhering to the wafer W can be removed by thermal decomposition or volatilization.
  • a dry process other processes, such as a radical process, can also be used.
  • a surface modification treatment include those to perform the reaction process using H 2 O.
  • impurities in the film and by-products attached to the wafer W can be removed by reacting with H 2 O.
  • the temperature at this time is preferably 20 to 100 ° C., more preferably 20 to 80 ° C.
  • the reaction process using of H 2 O may be performed in a dry process by an atmosphere containing H 2 O vapor, or immersed in H 2 O (deionized water) of the liquid, the liquid H 2 O (deionized You may carry out by the wet process which supplies water.
  • the surface modification treatment can be performed by a treatment including a step of adsorbing a surfactant on the wafer surface and a wet cleaning step using H 2 O (pure water).
  • FIG. 7 is a diagram for explaining the function of the surfactant used for the surface modification treatment.
  • the surfactant has a hydrophobic group and a hydrophilic group in one molecule, and has a function of making a hydrophobic state compatible with water via the hydrophobic group.
  • the entire surface of the SiO 2 film surface can be hydrophilic group is adsorbed so as to be arranged in the outside.
  • H 2 O deionized water
  • the step of adsorbing the surfactant onto the wafer can be performed by immersing the wafer in the surfactant or by applying the surfactant.
  • the surfactant may be a stock solution or an aqueous solution.
  • the wet cleaning step using H 2 O (pure water) can be performed by immersing the wafer in pure water or supplying pure water to the wafer.
  • Etching of the SiN film in step 2 is performed by introducing only HF gas or a mixed gas of HF gas and inert gas into the chamber and setting the pressure to a high pressure of 1333 Pa (10 Torr) or more as in the first embodiment. Is called. It is preferably 1333 to 11997 Pa (10 to 90 Torr). More preferably, it is 1333 to 5332 Pa (10 to 40 Torr).
  • the inert gas N 2 gas or a rare gas such as Ar or He can be used.
  • the gas flow rates at this time are preferably HF gas: 200 to 3000 sccm, inert gas: 200 to 3000 sccm, and the wafer temperature is preferably 10 to 120 ° C., 30 to 80 ° C. is more preferable.
  • the SiN film can be etched with a high selection ratio of 50 or more as in the first embodiment.
  • FIG. 8 (Structural example to which the second example is applied) As an example of the structure to which the etching method of the second example of the present embodiment is applied, the structure shown in FIG. 8 can be cited.
  • a pole-like Si film 32 and a SiGe film 33 are formed on a silicon substrate 31, and a thin SiN film 34 is formed around the Si film 32 and around the SiGe film 33.
  • An SiO 2 film 35 is formed so as to fill the entire periphery of the substrate.
  • the SiO 2 film 35 in FIG. 8 is etched (step 11).
  • the etching of the SiO 2 film 35 can be performed by COR with a wafer having a structure as shown in FIG. 8 in a chamber and using HF gas and NH 3 gas.
  • the pressure is preferably 133 to 400 Pa (1 to 3 Torr)
  • the processing temperature is 10 to 130 ° C.
  • the HF gas flow rate is 20 to 1000 sccm
  • the NH 3 gas flow rate is 20 to 1000 sccm
  • the inert gas flow rate is 20 to 1000 sccm.
  • ammonium fluorosilicate (NH 4 ) 2 SiF 6 ; AFS) is generated, so that the AFS is sublimated by heating to complete the etching.
  • AFS sublimation may be performed with a separate heating apparatus, or etching and heat treatment may be repeatedly performed in the COR chamber, and AFS may be removed therein.
  • the etching of the SiO 2 film 35 may be performed by radical treatment.
  • F radicals and N radicals formed by activating a mixed gas of NF 3 and NH 3 can be used as the radicals.
  • the SiO 2 film 35 is etched away to a predetermined height position, and the SiN film 34 remains up to a position higher than the predetermined height position. Therefore, etching (de-footing) for removing the footing region of the SiN film 34 is performed.
  • the film when the SiO 2 film 35 is removed by COR, the film contains NH 3 and F in the gas component in addition to impurities such as H, N, and C, and further NH 4 and HF 2. There is a possibility that such a by-product with high reactivity adheres to the wafer W, and the SiO 2 film 35 is likely to be etched by coexistence with HF during the etching of the SiN film.
  • the SiO 2 film is a film formed by CVD or ALD, depending on the film forming method, there is a tendency that the impurity in the film is large and the density is low, and thus this tendency is remarkable. .
  • a surface modification process is performed (step 12).
  • the surface modification treatment is for removing impurities in the film and by-products such as NH 4 and HF 2 adhering to the wafer W. This makes it difficult for the SiO 2 film 35 to be etched during the subsequent etching of the SiN film 34.
  • the surface modification treatment includes heat treatment in an inert atmosphere, reaction treatment using H 2 O, a step of adsorbing a surfactant on the wafer surface, and H 2 O (pure water). And a wet cleaning step.
  • other treatment such as radical treatment can be used.
  • etching (de-footing) of the footing region of the SiN film 34 is performed (step 13).
  • a wafer having a structure shown in FIG. 10A is accommodated in the chamber, and, as in the first embodiment, only HF gas or a mixed gas of HF gas and inert gas is introduced into the chamber.
  • the pressure is set at a high pressure of 1333 Pa (10 Torr) or more. It is preferably 1333 to 11997 Pa (10 to 90 Torr). More preferably, it is 1333 to 5332 Pa (10 to 40 Torr).
  • the inert gas N 2 gas or a rare gas such as Ar or He can be used.
  • the surface modification process is performed, particularly when the etching of the SiO 2 film 35 is performed by a radical process, the selectivity ratio is low even if it is lower than 1333 Pa (10 Torr). There is a possibility that high SiN film etching can be performed.
  • the gas flow rates are preferably HF gas: 200 to 3000 sccm, inert gas: 200 to 3000 sccm, and the wafer temperature is 10 to 120 ° C. Preferably, 30 to 80 ° C. is more preferable.
  • the footing region of the SiN film 34 can be removed by etching to obtain a desired semiconductor device.
  • SiO 2 film 35 SiN film 34 After removing the SiO 2 film 35 by etching, impurities in the film and by-products such as NH 4 and HF 2 adhering to the wafer W are removed by a surface modification process.
  • SiO 2 film 35 SiN film 34 by these effects in a state in which damage SiO 2 film 35 is etched (roughened pitting or surface) is prevented from occurring, SiO 2 film 35 SiN film 34
  • the Si film 32 and the SiGe film 33 can be etched with a high selectivity.
  • the selection ratio at this time is 5 or more, preferably 15 or more with respect to SiO 2 , and 50 or more, preferably 100 or more, with respect to Si and SiGe. Therefore, a semiconductor element having the structure shown in FIG.
  • the SiO 2 film 35 is formed by CVD (for example, FCVD), which has a relatively large amount of impurities and a low density, etching of the SiO 2 film 35 can be suppressed, and the SiN film The selectivity ratio of 34 to the SiO 2 film 35 can be increased.
  • CVD for example, FCVD
  • FIG. 11 is a schematic configuration diagram illustrating an example of a processing system used in the etching method of the second example of the second embodiment.
  • the processing system 200 includes a vacuum transfer chamber 201 having a rectangular cross section, and an oxide film etching device 202 for etching a SiO 2 film on one side of the long side of the vacuum transfer chamber 201, a surface modification processing device 203, And a SiN film etching apparatus 204 are connected via a gate valve G.
  • an oxide film etching device 202, a surface modification processing device 203, and a SiN film etching device 204 are connected to the other side of the long side of the vacuum transfer chamber 201 via a gate valve G.
  • the inside of the vacuum transfer chamber 201 is evacuated by a vacuum pump and maintained at a predetermined degree of vacuum.
  • the oxide film etching apparatus 202 can be configured as a COR apparatus that performs etching of the SiO 2 film by COR. Further, the oxide film etching apparatus 202 may be a radical processing apparatus.
  • the surface modification processing apparatus 203 can be configured as a heat treatment apparatus that heat-treats the wafer W at a relatively high temperature.
  • the wafer W may be the H 2 O gas treatment apparatus for heat treatment with H 2 O gas atmosphere.
  • another treatment apparatus such as a radical treatment apparatus can be used.
  • the SiN film etching apparatus 204 can be configured in the same manner as the etching apparatus 105 in the first embodiment.
  • two load lock chambers 205 are connected to one side of the short side of the vacuum transfer chamber 201 via a gate valve G1.
  • An atmospheric transfer chamber 206 is provided on the opposite side of the vacuum transfer chamber 201 across the load lock chamber 205.
  • the load lock chamber 205 is connected to the atmospheric transfer chamber 206 via a gate valve G2.
  • the load lock chamber 205 controls the pressure between the atmospheric pressure and the vacuum when the wafer W is transferred between the atmospheric transfer chamber 206 and the vacuum transfer chamber 201.
  • the atmospheric transfer chamber 206 On the wall portion opposite to the load lock chamber 205 mounting wall portion of the atmospheric transfer chamber 206, there are three carrier mounting ports 207 for mounting a carrier C containing a plurality of wafers W such as FOUP.
  • An alignment chamber 208 for aligning the wafer W is provided on the side wall of the atmospheric transfer chamber 206. A downflow of clean air is formed in the atmospheric transfer chamber 206.
  • One wafer transfer mechanism 210 includes an oxide film etching apparatus 202, a surface modification processing apparatus 203, a SiN film etching apparatus 204, and one load lock chamber 205 connected to one side of the long side of the vacuum transfer chamber 201.
  • the wafer W can be loaded and unloaded.
  • the other wafer transfer mechanism 210 is connected to the oxide film etching device 202, the surface modification processing device 203, the SiN film etching device 204, and the other load lock chamber 205 connected to the other side of the long side of the vacuum transfer chamber 201.
  • the wafer W can be loaded and unloaded.
  • a wafer transfer mechanism 211 is provided in the atmospheric transfer chamber 206.
  • the transfer mechanism 211 transfers the wafer W to the carrier C, the load lock chamber 205, and the alignment chamber 208.
  • the processing system 200 also has a control unit 212.
  • the control unit 212 is typically a computer, and includes a main control unit having a CPU that controls each component of the processing system 200, an input device (keyboard, mouse, etc.), an output device (printer, etc.), and a display device ( Display) and a storage device (storage medium).
  • the main control unit of the control unit 212 causes the processing system 200 to execute a predetermined operation based on, for example, a processing medium stored in a storage device or a processing recipe stored in the storage medium set in the storage device. .
  • a plurality of wafers having the structure shown in FIG. 8 are stored in the carrier C and transferred to the processing system 200.
  • the wafer W is taken out from the carrier C connected to the atmospheric transfer chamber 206 by the wafer transfer mechanism 211, and the gate valve G2 of any one of the load lock chambers 205 is opened to transfer the wafer W to the load lock chamber 205. Carry in. After the gate valve G2 is closed, the load lock chamber 205 is evacuated.
  • the gate valve G1 is opened, and the wafer W is taken out of the load lock chamber 205 by the wafer transfer mechanism 210. Then, the gate valve G of the oxide film etching apparatus 202 is opened, the wafer W is loaded into the oxide film etching apparatus 202, and the SiO 2 film is etched.
  • the etching of the SiO 2 film is performed by the COR process, AFS is generated as described above. Therefore, in order to sublimate it, the heat treatment is performed by the surface modification apparatus 203 or a heat treatment apparatus provided separately. Alternatively, etching and heat treatment may be repeatedly performed in the oxide film etching apparatus 202, and AFS may be removed therein.
  • the wafer W is taken out by the wafer transfer mechanism 210, the gate valve G of the surface modification processing apparatus 203 is opened, and the wafer W is carried into the surface modification processing apparatus 203, and the surface modification is performed. Process.
  • the wafer is taken out by the wafer transfer mechanism 210, the gate valve G of the SiN film etching apparatus 204 is opened, the wafer W is carried into the SiN film etching apparatus 204, and the SiN film is etched. I do.
  • the etching residue is removed by the surface modification processing apparatus 203 or a heat treatment apparatus provided separately as necessary.
  • the gate valve G1 of the load lock chamber 205 is opened, the wafer W after the SiN film etching is carried into the load lock chamber 205 by the wafer transfer mechanism 210, the gate valve G1 is closed, and the inside of the load lock chamber 205 is brought to atmospheric pressure. return. Thereafter, the gate valve G2 is opened, and the wafer W in the load lock chamber 205 is returned to the carrier C by the wafer transfer mechanism 211.
  • the above processing is performed simultaneously on a plurality of wafers W to complete the processing of a predetermined number of wafers W.
  • the SiN film etching apparatus 204 has the same configuration as the etching apparatus 105 of the first embodiment, description thereof is omitted.
  • FIG. 12 is a cross-sectional view showing an example of the oxide film etching apparatus 202.
  • a COR processing apparatus that etches a SiO 2 film by COR processing will be described as an example.
  • the basic configuration of the apparatus is the same as that of the etching apparatus 105 in the first embodiment, the same components as those in FIG.
  • a gas introduction path 162 is formed in addition to the gas introduction path 161 through the lid member 155 and the upper wall 157 b of the main body 157 to the space 159 of the shower head 156.
  • An HF gas supply pipe 171 of a gas supply mechanism 143 ′, which will be described later, is connected to the gas introduction path 161.
  • An NH 3 gas supply pipe 191 is connected to the gas introduction path 162.
  • the gas supply mechanism 143 ′ includes an HF gas supply source 175 for supplying HF gas and an inert gas supply source 176 for supplying inert gas, which include an HF gas supply pipe 171 and an inert gas supply, respectively.
  • One end of the pipe 172 is connected.
  • a flow rate controller 179 is provided in the HF gas supply pipe 171 and the inert gas supply pipe 172.
  • the other end of the HF gas supply pipe 171 is connected to the gas introduction path 161.
  • the other end of the inert gas supply pipe 172 is connected to the HF gas supply pipe 171.
  • the gas supply mechanism 143 ′ also has an NH 3 gas supply source 195 for supplying NH 3 gas and an inert gas supply source 196 for supplying inert gas, which include NH 3 gas supply pipe 191 and One end of the inert gas supply pipe 192 is connected.
  • the NH 3 gas supply pipe 191 and the inert gas supply pipe 192 are provided with a flow rate controller 199 configured similarly to the flow rate controller 179.
  • the other end of the NH 3 gas supply pipe 191 is connected to the gas introduction path 162.
  • the other end of the inert gas supply pipe 192 is connected to the NH 3 gas supply pipe 191.
  • HF gas from the HF gas supply source 175 via a HF gas supply pipe 171 is supplied into the shower head 156, NH 3 gas, the shower head 156 through the NH 3 gas supply line 191 from the NH 3 gas supply source 195 Supplied in.
  • the inert gas is supplied from the inert gas supply sources 176 and 196 to the HF gas supply pipe 171 and the NH 3 gas supply pipe 191 through the inert gas supply pipes 172 and 192, respectively, and is supplied to the shower head 156. .
  • These gases are discharged from the gas discharge hole 162 of the shower head 156 toward the wafer W in the chamber 140.
  • HF gas and NH 3 gas are used as reaction gas, and inert gas is used as dilution gas and purge gas.
  • a desired reaction can be caused by supplying HF gas and NH 3 gas, or a mixture thereof with an inert gas.
  • the wafer W having the structure shown in FIG. 8 is loaded into the chamber 140 and mounted on the mounting table 142.
  • the pressure in the chamber 140 is preferably 133 to 400 Pa (1 to 3 Torr), and the processing temperature is preferably 10 to 130 ° C.
  • the HF gas flow rate, NH 3 gas flow rate, and inert gas flow rate are preferably set to 20 to 1000 sccm, and these gases are supplied to react the HF gas, NH 3 gas, and SiO 2 to react with AFS. Generate. Then, the SiO 2 film is removed by heating the wafer W in an appropriate apparatus.
  • FIG. 13 is a cross-sectional view showing an example of the surface modification treatment apparatus 203.
  • a heat treatment apparatus that removes impurities and by-products in the film by heat treatment will be described as an example of the surface modification treatment apparatus 203.
  • the surface modification processing apparatus 203 has a chamber 220 that can be evacuated and a mounting table 223 on which the wafer W is mounted.
  • a heater 224 is embedded in the mounting table 223, and the wafer W after the etching process of the SiO 2 film is heated by the heater 224 to heat impurities existing in the film and by-products attached to the surface of the wafer W. Objects are removed by thermal decomposition or volatilization.
  • a loading / unloading port 234 for transferring a wafer to / from the vacuum transfer chamber 201 is provided on the side surface of the chamber 220, and the loading / unloading port 234 can be opened and closed by a gate valve G.
  • a gas supply path 225 is connected to the upper portion of the side wall of the chamber 220, and the gas supply path 225 is connected to an inert gas supply source 230.
  • An exhaust path 227 is connected to the bottom wall of the chamber 220, and the exhaust path 227 is connected to the vacuum pump 233.
  • the gas supply path 225 is provided with a flow rate adjusting valve 231, and the exhaust path 227 is provided with a pressure adjusting valve 232. By adjusting these valves, the inside of the chamber 220 is filled with an N 2 gas atmosphere at a predetermined pressure. Then, heat treatment is performed.
  • the inert gas a rare gas such as N 2 gas or Ar gas can be used.
  • the wafer W having the structure of FIG. 10A is carried into the chamber 220 by the SiO 2 film etching and placed on the mounting table 223. Then, the wafer W is heated to 150 to 400 ° C., for example, 250 ° C. by the heater 224 while introducing an inert gas such as N 2 gas into the chamber 220 to make a predetermined reduced pressure atmosphere. Thereby, impurities in the film and by-products such as NH 4 and HF 2 adhering to the wafer W can be thermally decomposed or volatilized.
  • an inert gas such as N 2 gas
  • a cluster type system is used as the processing system 200, and the SiO 2 film etching, the surface modification process, and the SiN film etching are performed in-situ. It may be used alone and performed ex-situ.
  • the surface modification processing apparatus 250 has a liquid processing tank 251 for storing and processing the liquid L.
  • a plurality of wafers W held by the wafer holding member 252 are immersed in the liquid L stored in the liquid processing tank 251.
  • the wafer holding member 252 has a plurality of wafer holding bars 252a, and a plurality of wafers W are held by these wafer holding bars 252a.
  • the wafer holding member 252 is moved up and down and horizontally by a transfer device (not shown) so that a plurality of held wafers W are transferred.
  • a nozzle 253 is provided in the liquid treatment tank 251, and a liquid supply pipe 254 is connected to the nozzle 253.
  • a predetermined liquid can be supplied from the liquid supply mechanism 255 to the liquid supply pipe 254.
  • a drainage pipe 256 is connected to the bottom of the liquid treatment tank 251, and the liquid in the liquid treatment tank 251 is drained via the drainage pipe 256 by the drainage mechanism 257.
  • pure water is used as the liquid supplied from the liquid supply mechanism 255.
  • a surface modification process when a process including a step of adsorbing a surfactant on the wafer surface and a wet cleaning process using H 2 O (pure water) is performed, the liquid supplied from the liquid supply mechanism 255 is used. Use pure water and surfactant. Then, these can be selectively supplied, or two types of liquid treatment layers 251 for pure water and a surfactant are prepared.
  • the surface modification treatment when the surface modification treatment is a treatment with liquid H 2 O (pure water), pure water is supplied into the liquid treatment tank 251 and stored. This is performed by immersing a plurality of wafers W in pure water.
  • the surface modification process is a process including a step of adsorbing a surfactant on the wafer surface and a wet cleaning step using H 2 O (pure water)
  • the surface modification treatment is performed as follows. That is, first, a surfactant is supplied into the liquid processing tank 251 and stored, so that a plurality of wafers W are immersed in the surfactant, and then the liquid supplied into the liquid processing tank 251 is purified water.
  • a plurality of wafers W are immersed in pure water in a state where the pure water is stored by switching to the above.
  • a plurality of wafers W are immersed in pure water in a state where pure water is supplied and stored in another liquid processing tank 251.
  • the surface modification processing device 260 includes a chamber 261, a spin chuck 262, a motor 263, a nozzle 264, and a liquid supply mechanism 265.
  • the spin chuck 262 rotatably holds the wafer W in the chamber 261.
  • the motor 263 rotates the spin chuck 262.
  • the nozzle 264 discharges liquid onto the wafer W held by the spin chuck 262.
  • the liquid supply mechanism 265 supplies a liquid to the nozzle 264. Liquid is supplied from the liquid supply mechanism 265 to the nozzle 264 through a liquid supply pipe 266. A predetermined liquid can be supplied from the liquid supply mechanism 265.
  • the surface modification treatment when performing the processing by H 2 O (deionized water) of the liquid, pure water is used as the liquid supplied from the liquid supply mechanism 265.
  • the liquid supplied from the liquid supply mechanism 265 is used as a surface modification process. Using pure water and a surfactant, these can be selectively supplied.
  • a cup 267 for covering the wafer W held by the spin chuck 262 is provided in the chamber 261.
  • An exhaust / drain pipe 268 for exhaust and drainage is provided at the bottom of the cup 267 so as to extend below the chamber 261.
  • a loading / unloading port 269 for loading and unloading the wafer W is provided on the side wall of the chamber 261.
  • a single wafer W is loaded into the chamber 261 by a transfer apparatus (not shown) and mounted on the spin chuck 262.
  • the liquid is discharged from the nozzle 264 from the liquid supply mechanism 265 through the liquid supply pipe 266 to supply the liquid to the entire surface of the wafer W.
  • liquid H 2 O pure water
  • pure water is supplied from the liquid supply mechanism 265 to the rotating wafer W via the liquid supply pipe 266 and the nozzle 264. Then, pure water is spread over the entire surface of the wafer W.
  • the surface modification treatment includes a step of adsorbing a surfactant on the wafer surface and a wet cleaning step using H 2 O (pure water)
  • the surface modification treatment is performed as follows. That is, first, a surfactant is supplied from the liquid supply mechanism 265 to the rotating wafer W via the liquid supply pipe 266 and the nozzle 264, and the surfactant is spread and adsorbed on the entire surface of the wafer W. Next, the liquid supplied from the liquid supply mechanism 265 is switched to pure water, and pure water is supplied onto the wafer to perform wet cleaning.
  • Example 1 Here, the SiN film, the thermal oxide film (SiO 2 film), and the polysilicon film formed by CVD using dichlorosilane (Si 2 H 2 Cl 2 ) gas and NH 3 gas as the SiN film are etched. It was. Etching was performed using HF gas as an etching gas and changing the temperature and pressure. The etching conditions were as follows: HF gas flow rate: 1500 sccm, pressure: 30 Torr (4000 Pa) and 50 Torr (6665 Pa), temperature: 50 to 150 ° C.
  • FIG. 16 is a diagram showing the relationship between the pressure, the etching amount (nm) of each film, the selection ratio of the SiN film to the thermal oxide film, and the selection ratio of the SiN film to the polysilicon film at a temperature of 70 ° C. .
  • FIG. 17 is a diagram showing the relationship between the temperature, the etching amount (nm) of each film, and the selectivity of the SiN film to the thermal oxide film and the polysilicon film when the pressure is 50 Torr.
  • the temperature range of 50 to 120 ° C. is an allowable range of the selection ratio.
  • the etching amount of the SiN film increases at 70 ° C., and the selection ratio of the SiN film to the thermal oxide film and the SiN film It can be seen that the selectivity of the film to the polysilicon film is high.
  • the SiN film has a high selectivity ratio of 15 or more and the SiN film has a selectivity ratio of 100 or more.
  • the SiGe film shows the same tendency as the polysilicon film, and the selectivity of the SiGe film to the SiN film is 100 or more at a pressure of 50 Torr and a temperature of 70 ° C. A value was obtained.
  • Example 2 the wafer with the SiO 2 film formed by CVD is first subjected to COR treatment of the SiO 2 film using HF gas and NH 3 gas under the conditions of pressure: 333 Pa (2.5 Torr) and temperature: 100 ° C. It was. Next, AFS was removed by heat treatment at 250 ° C., and SiO 2 film etching was performed. Thereafter, a sample (sample 1) was prepared by performing the SiN film etching condition treatment (HF gas treatment + heat treatment) on the wafer as it was.
  • HF gas treatment + heat treatment SiN film etching condition treatment
  • sample 3 A sample (sample 3) subjected to SiN film etching conditions was also prepared. For these samples, the surface state of the SiO 2 film was investigated.
  • the SiN film etching conditions are as follows: gas treatment is performed under the conditions of HF gas flow rate: 2000 sccm, pressure: 1333 to 1995 Pa (10 to 15 Torr), temperature: 50 to 75 ° C., and then heat treatment at 250 ° C. .
  • the structural example of the above embodiment is merely an example, and any structure can be applied as long as the SiN film coexists with SiO 2 , Si, and SiGe.
  • the structure of the processing system and the individual apparatuses are merely examples, and the etching method of the present disclosure can be performed by systems and apparatuses having various configurations.
  • SiN Film 100, 200; processing system, 105; etching apparatus, 202; oxide film etching apparatus, 203, 250, 260; surface modification processing apparatus, 204; SiN film etching apparatus, W; wafer

Abstract

Provided is an etching method having: a step for disposing a substrate to be processed in a chamber, the substrate having a silicon nitride film, a silicon oxide film, silicon, and silicon germanium; a step for bringing the pressure inside the chamber to 1,333 Pa or more; and a step for supplying hydrogen fluoride gas into the chamber and selectively etching the silicon nitride film with respect to the silicon oxide film, the silicon, and the silicon germanium.

Description

エッチング方法Etching method
 本開示は、エッチング方法に関する。 The present disclosure relates to an etching method.
 近時、半導体デバイスの製造過程で、微細化エッチングが行われるが、従来のプラズマエッチングに代わるドライエッチング技術として、低ダメージのエッチングが可能な化学的エッチング技術が注目されている。例えば、酸化シリコン(SiO)膜のエッチングには、処理ガスとして、フッ化水素(HF)ガスとアンモニア(NH)ガスとの混合ガスを用いた化学的酸化物除去処理(Chemical Oxide Removal;COR)技術が用いられている(例えば特許文献1、2)。 Recently, fine etching is performed in the manufacturing process of a semiconductor device. As a dry etching technique that replaces the conventional plasma etching, a chemical etching technique capable of performing low damage etching has attracted attention. For example, for etching a silicon oxide (SiO 2 ) film, a chemical oxide removal process (Chemical Oxide Removal; using a mixed gas of hydrogen fluoride (HF) gas and ammonia (NH 3 ) gas as a processing gas; COR) technology is used (for example, Patent Documents 1 and 2).
 最近では、このような化学的エッチング技術を窒化シリコン(SiN)膜のエッチングに適用することが検討されている。 Recently, application of such a chemical etching technique to etching of a silicon nitride (SiN) film has been studied.
 SiN膜はSiO膜と隣接していることが多いため、SiO膜に対して選択的にSiN膜をエッチングする技術として、特許文献3には、HFガスと、Fガスと、不活性ガスと、Oガスとを、励起した状態で供給して、エッチングすることが記載されている。 Since it is often SiN film which is adjacent to the SiO 2 film, a selectively technique for etching the SiN film against the SiO 2 film, Patent Document 3, and HF gas, and F 2 gas, inert It describes that etching is performed by supplying a gas and O 2 gas in an excited state.
特開2005-39185号公報JP 2005-39185 A 特開2008-160000号公報JP 2008-160000 A 特開2015-73035号公報Japanese Patent Laid-Open No. 2015-73035
 本開示は、窒化シリコン(SiN)膜を、酸化シリコン(SiO)膜、シリコン(Si)およびシリコンゲルマニウム(SiGe)に対して高い選択性でエッチングすることができるエッチング方法を提供する。 The present disclosure provides an etching method capable of etching a silicon nitride (SiN) film with high selectivity to a silicon oxide (SiO 2 ) film, silicon (Si), and silicon germanium (SiGe).
 本開示の一態様に係るエッチング方法は、窒化シリコン膜、酸化シリコン膜、シリコンおよびシリコンゲルマニウムを有する被処理基板をチャンバー内に配置する工程と、前記チャンバー内の圧力を1333Pa以上にする工程と、前記チャンバー内にフッ化水素ガスを供給し、前記窒化シリコン膜を、前記酸化シリコン膜、シリコンおよびシリコンゲルマニウムに対して選択的にエッチングする工程と、を有する。 An etching method according to one embodiment of the present disclosure includes a step of placing a substrate to be processed having a silicon nitride film, a silicon oxide film, silicon, and silicon germanium in a chamber, a step of setting the pressure in the chamber to 1333 Pa or more, Supplying hydrogen fluoride gas into the chamber, and selectively etching the silicon nitride film with respect to the silicon oxide film, silicon, and silicon germanium.
 本開示によれば、窒化シリコン(SiN)膜を、酸化シリコン(SiO)膜、シリコン(Si)およびシリコンゲルマニウム(SiGe)に対して高い選択性でエッチングすることができるエッチング方法が提供される。 According to the present disclosure, there is provided an etching method capable of etching a silicon nitride (SiN) film with high selectivity with respect to a silicon oxide (SiO 2 ) film, silicon (Si), and silicon germanium (SiGe). .
第1の実施形態のエッチング方法が適用される構造の一例に対し、SiN膜のエッチングを行った際の工程断面図である。It is process sectional drawing at the time of etching a SiN film | membrane with respect to an example of the structure where the etching method of 1st Embodiment is applied. 第1の実施形態のエッチング方法が適用される構造の他の例に対し、SiN膜のエッチングを行った際の工程断面図である。It is process sectional drawing at the time of etching a SiN film | membrane with respect to the other example of the structure where the etching method of 1st Embodiment is applied. 第1の実施形態のエッチング方法に用いる処理システムの一例を示す概略構成図である。It is a schematic block diagram which shows an example of the processing system used for the etching method of 1st Embodiment. 図3の処理システムに搭載されたエッチング装置を示す断面図である。It is sectional drawing which shows the etching apparatus mounted in the processing system of FIG. 不純物を含むSiO膜と隣接したSiN膜をHFガスによりエッチングする際に、SiO膜にダメージが発生するメカニズムを説明するための図である。The SiN film adjacent to the SiO 2 film containing an impurity at the time of etching by HF gas, which is a diagram for explaining the mechanism of damage is generated in the SiO 2 film. 第2の実施形態のエッチング方法の第1の例を示すフローチャートである。It is a flowchart which shows the 1st example of the etching method of 2nd Embodiment. 表面改質処理に用いる界面活性剤の機能を説明するための図である。It is a figure for demonstrating the function of surfactant used for a surface modification process. 第2の実施形態のエッチング方法の第2の例が適用される構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure where the 2nd example of the etching method of 2nd Embodiment is applied. 第2の実施形態のエッチング方法の第2の例を示すフローチャートである。It is a flowchart which shows the 2nd example of the etching method of 2nd Embodiment. 第2の実施形態のエッチング方法の第2の例における工程断面図である。It is process sectional drawing in the 2nd example of the etching method of 2nd Embodiment. 第2の実施形態の第2の例のエッチング方法に用いる処理システムの一例を示す概略構成図である。It is a schematic block diagram which shows an example of the processing system used for the etching method of the 2nd example of 2nd Embodiment. 図11の処理システムに搭載された酸化膜エッチング装置を示す断面図である。It is sectional drawing which shows the oxide film etching apparatus mounted in the processing system of FIG. 図11の処理システムに搭載された表面改質処理装置を示す断面図である。It is sectional drawing which shows the surface modification processing apparatus mounted in the processing system of FIG. 表面改質処理装置の他の例を示す断面図である。It is sectional drawing which shows the other example of a surface modification processing apparatus. 表面改質処理装置のさらに他の例を示す断面図である。It is sectional drawing which shows the further another example of a surface modification processing apparatus. 実験例において、SiN膜、熱酸化膜、ポリシリコン膜を、温度70℃で圧力を変化させてエッチングしたときの、圧力と、各膜のエッチング量(nm)ならびにSiN膜の熱酸化膜に対する選択比およびSiN膜のポリシリコン膜に対する選択比との関係を示す図である。In the experimental example, when the SiN film, the thermal oxide film, and the polysilicon film were etched while changing the pressure at a temperature of 70 ° C., the pressure, the etching amount (nm) of each film, and the selection of the SiN film with respect to the thermal oxide film It is a figure which shows the relationship between the ratio and the selective ratio of the SiN film to the polysilicon film. 実験例において、SiN膜、熱酸化膜、ポリシリコン膜を、圧力50Torrで温度を変化させてエッチングしたときの、温度と、各膜のエッチング量(nm)ならびにSiN膜の熱酸化膜に対する選択比およびSiN膜のポリシリコン膜に対する選択比との関係を示す図である。In the experimental example, when the SiN film, the thermal oxide film, and the polysilicon film were etched while changing the temperature at a pressure of 50 Torr, the temperature, the etching amount of each film (nm), and the selectivity ratio of the SiN film to the thermal oxide film It is a figure which shows the relationship with the selection ratio with respect to the polysilicon film of SiN film.
 以下、図面を参照しながら、本発明の実施の形態について説明する。
 <経緯>
 最初に、本開示のエッチング方法に至った経緯について説明する。
 上述したように、近時、COR技術と同様の化学的エッチングによりSiN膜のエッチングを行うことが検討されている。例えば、特許文献3には、HFガスと、Fガスと、不活性ガスと、Oガスとを、励起した状態で供給して、SiO膜に対して選択的にSiN膜をエッチングする技術が記載されている。
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
<Background>
First, the background to the etching method of the present disclosure will be described.
As described above, recently, etching of the SiN film by chemical etching similar to the COR technique has been studied. For example, in Patent Document 3, HF gas, F 2 gas, inert gas, and O 2 gas are supplied in an excited state, and the SiN film is selectively etched with respect to the SiO 2 film. The technology is described.
 しかし、例えばCMOSトランジスタのような、SiおよびSiGeを用いた半導体デバイスにおいて、SiN膜をエッチングする場合、上記特許文献3の技術では、SiO膜、SiおよびSiGeの全てに対して十分な選択性でSiN膜をエッチングすることは困難である。 However, in the case of etching a SiN film in a semiconductor device using Si and SiGe such as a CMOS transistor, for example, the technique disclosed in Patent Document 3 has sufficient selectivity for all of the SiO 2 film, Si and SiGe. It is difficult to etch the SiN film.
 また、SiO膜にHやN等の不純物が含まれている場合は、上述した特許文献3でSiN膜をエッチングする際に、SiO膜にダメージが発生することがある。 Further, when the SiO 2 film contains impurities such as H and N, the SiO 2 film may be damaged when the SiN film is etched in Patent Document 3 described above.
 そこで、発明者らは、これらの点を解消すべく種々の検討を行った。その結果、HFガスを用いて高圧で窒化シリコン膜をエッチングすることにより、酸化シリコン(SiO)膜、シリコン(Si)およびシリコンゲルマニウム(SiGe)に対して高い選択性でエッチングすることができることを見出した。また、SiN膜およびSiO膜を有する被処理基板についてSiN膜をエッチングする際に、窒化シリコン膜のエッチングに先立って、膜中の不純物等を除去する表面改質処理を行うことが有効であることを見出した。 Therefore, the inventors have conducted various studies to eliminate these points. As a result, it is possible to etch with high selectivity to a silicon oxide (SiO 2 ) film, silicon (Si) and silicon germanium (SiGe) by etching the silicon nitride film at a high pressure using HF gas. I found it. Further, when the SiN film is etched on the substrate to be processed having the SiN film and the SiO 2 film, it is effective to perform a surface modification process for removing impurities and the like in the film prior to the etching of the silicon nitride film. I found out.
 <第1の実施形態>
 次に、本発明の第1の実施形態について説明する。
 本実施形態では、SiO、SiおよびSiGeに隣接して形成されたSiN膜をエッチング除去する方法について説明する。
<First Embodiment>
Next, a first embodiment of the present invention will be described.
In the present embodiment, a method for etching and removing a SiN film formed adjacent to SiO 2 , Si and SiGe will be described.
  [第1の実施形態のエッチング方法が適用される構造例]
 図1は、第1の実施形態のエッチング方法が適用される構造の一例に対し、SiN膜のエッチングを行った際の工程断面図である。図1の(a)は、本実施形態のエッチング方法が適用される構造の一例である。(a)の構造では、シリコン基板11上にポール状のSi膜12およびSiGe膜13が形成されている。また、Si膜12の周囲およびSiGe膜13の周囲に第1のSiO膜14が形成され、第1のSiO膜14の周囲ならびにSi膜12およびSiGe膜13の上には、SiN膜15が形成されている。さらに、Si側の周囲のSiN膜15とSiGe側の周囲のSiN膜15との間には、第2のSiO膜16が形成されている。図1の(a)の構造のSiN膜15をエッチングして所望の半導体デバイスを形成するが、その際に、理想的には(b)に示すようにSiN膜15のみが除去された状態、すなわち、SiN膜15を、Si膜12、SiGe膜13、第1および第2のSiO膜14、16に対して高選択比でエッチングすることが求められる。
[Structural example to which the etching method of the first embodiment is applied]
FIG. 1 is a process cross-sectional view when an SiN film is etched with respect to an example of a structure to which the etching method of the first embodiment is applied. FIG. 1A is an example of a structure to which the etching method of this embodiment is applied. In the structure (a), a pole-like Si film 12 and a SiGe film 13 are formed on a silicon substrate 11. The first SiO 2 film 14 is formed around the periphery and SiGe film 13 of the Si film 12, on the first ambient and Si film 12 and the SiGe film 13 of SiO 2 film 14, SiN film 15 Is formed. Further, a second SiO 2 film 16 is formed between the SiN film 15 around the Si side and the SiN film 15 around the SiGe side. The SiN film 15 having the structure shown in FIG. 1A is etched to form a desired semiconductor device. In this case, ideally, only the SiN film 15 is removed as shown in FIG. That is, it is required to etch the SiN film 15 with a high selectivity with respect to the Si film 12, the SiGe film 13, and the first and second SiO 2 films 14 and 16.
 図2は、第1の実施形態のエッチング方法が適用される構造の他の例に対し、SiN膜のエッチングを行った際の工程断面図である。図2の(a)は、本実施形態のエッチング方法が適用される構造の他の例である。(a)の構造では、シリコン基板21上に、左側からポール状をなす第1のSi膜22a、第2のSi膜22b、第3のSi膜22cが設けられ、さらにその右にポール状をなすSiGe膜23が形成されている。これら第1~第3のSi膜22a~22cとSiGe膜23の上にはハードマスク24が残存している。第1のSi膜22aの周囲および第1のSi膜22a側の端部から第3のSi膜22cに達するまでのシリコン基板21上には、SiO膜25が形成されている。そして、SiO膜25の上および第2のSi膜22bの周囲にはSiN膜26が設けられている。図2の(a)の構造のSiN膜26をエッチングして所望の半導体デバイスを形成するが、その際に、理想的には(b)に示すようにSiN膜26のみが除去された状態、すなわち、SiN膜26を、第1~第3のSi膜22a~22c、SiGe膜23、SiO膜25に対して高選択比でエッチングすることが求められる。具体的には、SiOに対する選択比が5以上、Si、SiGeに対する選択比が50以上であることが求められる。 FIG. 2 is a process cross-sectional view when the SiN film is etched with respect to another example of the structure to which the etching method of the first embodiment is applied. FIG. 2A shows another example of a structure to which the etching method of this embodiment is applied. In the structure of (a), a first Si film 22a, a second Si film 22b, and a third Si film 22c having a pole shape from the left side are provided on the silicon substrate 21, and a pole shape is formed on the right side. A formed SiGe film 23 is formed. A hard mask 24 remains on the first to third Si films 22 a to 22 c and the SiGe film 23. An SiO 2 film 25 is formed on the silicon substrate 21 from the periphery of the first Si film 22a and the end on the first Si film 22a side to the third Si film 22c. A SiN film 26 is provided on the SiO 2 film 25 and around the second Si film 22b. The SiN film 26 having the structure shown in FIG. 2A is etched to form a desired semiconductor device. At this time, ideally, only the SiN film 26 is removed as shown in FIG. That is, it is required to etch the SiN film 26 with a high selectivity with respect to the first to third Si films 22a to 22c, the SiGe film 23, and the SiO 2 film 25. Specifically, the selection ratio to SiO 2 is required to be 5 or more, and the selection ratio to Si and SiGe is required to be 50 or more.
 Si膜12、第1~第3のSi膜22a~22c、およびSiGe膜13、23としては、例えばエピタキシャル成長により形成されたものや、CVDによる多結晶膜を用いることができる。また、第1および第2のSiO膜14および16、ならびにSiO膜25としては、化学蒸着法(CVD)により成膜されたものであっても、原子層堆積法(ALD)で成膜されたものであっても、熱酸化膜であってもよい。CVDによりSiO膜を成膜する際には、種々の手法があり、その手法により不純物として含まれる水素(H)、炭素(C)、窒素(N)等の量が異なり、低グレードのCVD-SiO膜では比較的多くの不純物が含まれる。ALD-SiO膜も同様にこれらの不純物が含まれる。一方、熱酸化膜の場合は、このような不純物は少ない。 As the Si film 12, the first to third Si films 22a to 22c, and the SiGe films 13 and 23, for example, those formed by epitaxial growth or polycrystalline films formed by CVD can be used. Further, even if the first and second SiO 2 films 14 and 16 and the SiO 2 film 25 are formed by chemical vapor deposition (CVD), they are formed by atomic layer deposition (ALD). Or may be a thermal oxide film. There are various methods for forming a SiO 2 film by CVD, and the amount of hydrogen (H), carbon (C), nitrogen (N), etc. contained as impurities differs depending on the method, and low grade CVD. The -SiO 2 film contains a relatively large amount of impurities. Similarly, the ALD-SiO 2 film contains these impurities. On the other hand, in the case of a thermal oxide film, there are few such impurities.
 エッチング対象となるSiN膜は、SiHガス、SiHCl、SiCl等のシラン系ガスと、NHガスやNガス等の窒素含有ガスを用いて、熱CVD、プラズマCVD、ALD等により成膜されたものである。 The SiN film to be etched is formed by thermal CVD, plasma CVD, silane-based gas such as SiH 4 gas, SiH 2 Cl 2 , Si 2 Cl 6 and nitrogen-containing gas such as NH 3 gas or N 2 gas. The film is formed by ALD or the like.
 [第1の実施形態のSiN膜エッチング]
 上記デバイス例で示す、SiN膜がSiO、SiおよびSiGeに隣接して形成されている場合に、SiN膜を高い選択比でエッチングする試みとしては、(1)HFガスや、HFガス+NHガスを用いてCOR装置でエッチングする方法、(2)このガス系にFを添加してエッチングする方法、(3)ラジカルSiNエッチングによる方法が行われてきた。
[SiN film etching of the first embodiment]
When the SiN film shown in the above device example is formed adjacent to SiO 2 , Si and SiGe, as an attempt to etch the SiN film with a high selectivity, (1) HF gas or HF gas + NH 3 A method of etching with a COR device using a gas, (2) a method of etching by adding F 2 to the gas system, and (3) a method by radical SiN etching have been performed.
 (1)のCOR処理の場合は、通常、4Torr(532Pa)以下と比較的低圧で行われるが、SiN/SiO選択比が2より小さい。また、(2)の場合は、SiN/SiO選択比は改善されるものの、Siに対する選択比がとれない。さらに、(3)のラジカルSiNエッチングの場合は、SiN/SiO選択比はとれるが、SiN/SiGe選択比がとれない。 In the case of the COR treatment of (1), it is usually carried out at a relatively low pressure of 4 Torr (532 Pa) or less, but the SiN / SiO 2 selection ratio is smaller than 2. In the case of (2), although the SiN / SiO 2 selection ratio is improved, the selection ratio for Si cannot be obtained. Furthermore, in the case of (3) radical SiN etching, the SiN / SiO 2 selectivity can be obtained, but the SiN / SiGe selectivity cannot be obtained.
 そこで、このようなSiO、SiおよびSiGeの全てに対して高選択比でSiN膜をエッチングできる方法を検討したところ、HFガスを用いて、圧力を1333Pa(10Torr)以上と高圧にすることが有効であることが見出された。このように高圧状態とすることにより高い選択比を得ることができる理由は、高圧にすることでHFガスの吸着効率が高まる効果が得られるからである。 Therefore, when a method capable of etching the SiN film with a high selection ratio with respect to all of SiO 2 , Si, and SiGe was examined, the pressure was increased to 1333 Pa (10 Torr) or higher using HF gas. It was found to be effective. The reason why a high selection ratio can be obtained by setting the high pressure state in this way is that an effect of increasing the adsorption efficiency of the HF gas can be obtained by setting the high pressure.
 以下詳細に説明する。
 本実施形態のSiNエッチングにおいては、例えば上述のような構造を有する半導体ウエハ(単にウエハとも記す)をチャンバー内に収容し、HFガスのみ、またはHFガスと不活性ガスの混合ガスをチャンバー内に導入することにより行われる。不活性ガスとしては、Nガスや、Ar、He等の希ガスを用いることができる。
This will be described in detail below.
In the SiN etching of the present embodiment, for example, a semiconductor wafer having the above-described structure (also simply referred to as a wafer) is accommodated in a chamber, and only HF gas or a mixed gas of HF gas and inert gas is contained in the chamber. It is done by introducing. As the inert gas, N 2 gas or a rare gas such as Ar or He can be used.
 この際のガス流量は、HFガス:200~3000sccm、不活性ガス:200~3000sccmであることが好ましい。 The gas flow rate at this time is preferably HF gas: 200 to 3000 sccm, and inert gas: 200 to 3000 sccm.
 この際のチャンバー内の圧力は、上述したように、1333Pa(10Torr)以上と高圧にする。好ましくは1333~11997Pa(10~90Torr)である。より好ましくは1333~5332Pa(10~40Torr)である。 The pressure in the chamber at this time is set to a high pressure of 1333 Pa (10 Torr) or more as described above. It is preferably 1333 to 11997 Pa (10 to 90 Torr). More preferably, it is 1333 to 5332 Pa (10 to 40 Torr).
 また、この際のウエハ温度は、10~120℃が好ましい。10℃未満および120℃超では、所望の選択比を得ることが困難となる場合がある。より好ましくは、30~80℃である。 In this case, the wafer temperature is preferably 10 to 120 ° C. Below 10 ° C. and above 120 ° C., it may be difficult to obtain a desired selection ratio. More preferably, it is 30 to 80 ° C.
 以上のようなSiN膜のエッチングが終了した後、必要に応じてエッチング残渣等の除去を行い、処理が終了する。 After the above etching of the SiN film is completed, etching residues and the like are removed as necessary, and the processing is completed.
 SiN膜のエッチングを、以上の条件でSiN膜の膜厚に応じて所定時間行うことにより、SiOに対して選択比5以上、SiおよびSiGeに対して選択比50以上の高い選択性でSiN膜をエッチングすることができる。SiOに対する選択比は15以上、SiおよびSiGeに対して選択比100以上が好ましい。 Etching of the SiN film is performed for a predetermined time according to the thickness of the SiN film under the above conditions, so that the SiN film has a high selectivity with a selectivity of 5 or more with respect to SiO 2 and a selectivity of 50 or more with respect to Si and SiGe. The film can be etched. The selection ratio to SiO 2 is preferably 15 or more and the selection ratio to Si and SiGe is preferably 100 or more.
  [第1の実施形態に用いる処理システムの一例]
 次に、第1の実施形態に用いる処理システムの一例について説明する。
 図3は、第1の実施形態に用いる処理システムの一例を示す概略構成図である。この処理システム100は、搬入出部102と、2つのロードロック室103と、2つの熱処理装置104と、2つのエッチング装置105と、制御部106とを備えている。搬入出部102は、上記構造例に示す構造を有するウエハWを搬入出するためのものである。2つのロードロック室103は、搬入出部102に隣接して設けられている。2つの熱処理装置104は、各ロードロック室103に隣接して設けられており、ウエハWに対して熱処理を行なうためのものである。2つのエッチング装置105は、各熱処理装置104に隣接して設けられており、ウエハWに対してエッチングを行うものである。
[An example of a processing system used in the first embodiment]
Next, an example of a processing system used in the first embodiment will be described.
FIG. 3 is a schematic configuration diagram illustrating an example of a processing system used in the first embodiment. The processing system 100 includes a carry-in / out unit 102, two load lock chambers 103, two heat treatment apparatuses 104, two etching apparatuses 105, and a control unit 106. The loading / unloading unit 102 is for loading / unloading the wafer W having the structure shown in the above structure example. The two load lock chambers 103 are provided adjacent to the carry-in / out section 102. The two heat treatment apparatuses 104 are provided adjacent to each load lock chamber 103, and are for performing heat treatment on the wafer W. The two etching apparatuses 105 are provided adjacent to the respective heat treatment apparatuses 104 and perform etching on the wafer W.
 搬入出部102は、ウエハWを搬送する第1ウエハ搬送機構111が内部に設けられた搬送室112を有している。第1ウエハ搬送機構111は、ウエハWを略水平に保持する2つの搬送アーム111a,111bを有している。搬送室112の長手方向の側部には、載置台113が設けられており、この載置台113には、FOUP等の複数枚のウエハWを収容するキャリアCが例えば3つ接続できるようになっている。また、搬送室112に隣接して、ウエハWのアライメントを行うアライメントチャンバ114が設けられている。 The loading / unloading unit 102 has a transfer chamber 112 in which a first wafer transfer mechanism 111 for transferring the wafer W is provided. The first wafer transfer mechanism 111 has two transfer arms 111a and 111b that hold the wafer W substantially horizontally. On the side of the transfer chamber 112 in the longitudinal direction, a mounting table 113 is provided. For example, three carriers C that accommodate a plurality of wafers W such as FOUP can be connected to the mounting table 113. ing. An alignment chamber 114 for aligning the wafer W is provided adjacent to the transfer chamber 112.
 搬入出部102において、ウエハWは、搬送アーム111a,111bによって保持され、第1ウエハ搬送機構111の駆動により略水平面内で直進移動、また昇降させられることにより、所望の位置に搬送させられる。そして、載置台113上のキャリアC、アライメントチャンバ114、ロードロック室103に対してそれぞれ搬送アーム111a,111bが進退することにより、搬入出させられるようになっている。 In the loading / unloading unit 102, the wafer W is held by the transfer arms 111 a and 111 b, and is moved to a desired position by moving straight and moving up and down substantially in a horizontal plane by driving the first wafer transfer mechanism 111. Then, the transfer arms 111 a and 111 b are moved forward and backward with respect to the carrier C, the alignment chamber 114, and the load lock chamber 103 on the mounting table 113, respectively, so that they can be carried in and out.
 2つのロードロック室103は、搬送室112との間にそれぞれゲートバルブ116が介在された状態で、搬送室112に連結されている。各ロードロック室103内には、ウエハWを搬送する第2ウエハ搬送機構117が設けられている。また、ロードロック室103は、所定の真空度まで真空引き可能に構成されている。 The two load lock chambers 103 are connected to the transfer chamber 112 with the gate valve 116 interposed between the two load lock chambers 103. In each load lock chamber 103, a second wafer transfer mechanism 117 for transferring the wafer W is provided. The load lock chamber 103 is configured to be evacuated to a predetermined degree of vacuum.
 第2ウエハ搬送機構117は、多関節アーム構造を有しており、ウエハWを略水平に保持するピックを有している。この第2ウエハ搬送機構117においては、多関節アームを縮めた状態でピックがロードロック室103内に位置し、多関節アームを伸ばすことにより、ピックが熱処理装置104に到達し、さらに伸ばすことによりエッチング装置105に到達することが可能となっており、ウエハWをロードロック室103、熱処理装置104、およびエッチング装置105間で搬送することが可能となっている。 The second wafer transfer mechanism 117 has an articulated arm structure and has a pick for holding the wafer W substantially horizontally. In the second wafer transfer mechanism 117, the pick is positioned in the load lock chamber 103 with the articulated arm contracted, and the pick reaches the heat treatment apparatus 104 by extending the articulated arm and further extends. It is possible to reach the etching apparatus 105, and the wafer W can be transferred between the load lock chamber 103, the heat treatment apparatus 104, and the etching apparatus 105.
 制御部106は、典型的にはコンピュータからなり、処理システム100の各構成部を制御するCPUを有する主制御部と、入力装置(キーボード、マウス等)、出力装置(プリンタ等)、表示装置(ディスプレイ等)、記憶装置(記憶媒体)を有している。制御部106の主制御部は、例えば、記憶装置に内蔵された記憶媒体、または記憶装置にセットされた記憶媒体に記憶された処理レシピに基づいて、処理システム100に、所定の動作を実行させる。 The control unit 106 is typically a computer, and includes a main control unit having a CPU that controls each component of the processing system 100, an input device (keyboard, mouse, etc.), an output device (printer, etc.), and a display device ( Display) and a storage device (storage medium). For example, the main control unit of the control unit 106 causes the processing system 100 to execute a predetermined operation based on a processing recipe stored in a storage medium built in the storage device or a storage medium set in the storage device. .
 このような処理システム100では、上記構造が形成されたウエハWを複数枚キャリアC内に収納して処理システム100に搬送する。処理システム100においては、大気側のゲートバルブ116を開いた状態で搬入出部102のキャリアCから第1ウエハ搬送機構111の搬送アーム111a、111bのいずれかによりウエハWを1枚ロードロック室103に搬送し、ロードロック室103内の第2ウエハ搬送機構117のピックに受け渡す。 In such a processing system 100, a plurality of wafers W on which the above structure is formed are stored in a carrier C and transferred to the processing system 100. In the processing system 100, a single wafer W is loaded from the carrier C of the loading / unloading unit 102 by the transfer arms 111 a and 111 b of the first wafer transfer mechanism 111 with the atmosphere-side gate valve 116 opened. To the pick of the second wafer transfer mechanism 117 in the load lock chamber 103.
 その後、大気側のゲートバルブ116を閉じてロードロック室103内を真空排気し、次いでゲートバルブ154を開いて、ピックをエッチング装置105まで伸ばしてウエハWをエッチング装置105へ搬送する。 Thereafter, the gate valve 116 on the atmosphere side is closed and the load lock chamber 103 is evacuated, then the gate valve 154 is opened, the pick is extended to the etching apparatus 105, and the wafer W is transferred to the etching apparatus 105.
 その後、ピックをロードロック室103に戻し、ゲートバルブ154を閉じ、エッチング装置105において上述したエッチング方法によりSiN膜のエッチング処理を行う。 Thereafter, the pick is returned to the load lock chamber 103, the gate valve 154 is closed, and the SiN film is etched in the etching apparatus 105 by the etching method described above.
 エッチング処理が終了した後、ゲートバルブ122、154を開き、第2ウエハ搬送機構117のピックによりエッチング処理後のウエハWを熱処理装置104に搬送し、エッチング残渣等を加熱除去する。 After the etching process is completed, the gate valves 122 and 154 are opened, the wafer W after the etching process is transferred to the heat treatment apparatus 104 by the pick of the second wafer transfer mechanism 117, and the etching residue and the like are removed by heating.
 熱処理装置104における熱処理が終了した後、第1ウエハ搬送機構111の搬送アーム111a、111bのいずれかによりキャリアCに戻す。これにより、一枚のウエハの処理が完了する。 After the heat treatment in the heat treatment apparatus 104 is completed, it is returned to the carrier C by one of the transfer arms 111a and 111b of the first wafer transfer mechanism 111. Thereby, processing of one wafer is completed.
 なお、エッチング残渣等を除去する必要がない場合には、熱処理装置104を設けなくともよく、その場合には、エッチング処理が終了した後のウエハWを第2ウエハ搬送機構117のピックによりロードロック室103に退避させ、第1ウエハ搬送機構111の搬送アーム111a、111bのいずれかによりキャリアCに戻せばよい。 If it is not necessary to remove etching residues and the like, it is not necessary to provide the heat treatment apparatus 104. In this case, the wafer W after the etching process is finished is load-locked by the pick of the second wafer transfer mechanism 117. It may be retracted to the chamber 103 and returned to the carrier C by one of the transfer arms 111a and 111b of the first wafer transfer mechanism 111.
  [エッチング装置]
 次に、本実施形態のエッチング方法を実施するためのエッチング装置105の一例について詳細に説明する。
 図4はエッチング装置105の一例を示す断面図である。図4に示すように、エッチング装置105は、密閉構造のチャンバー140を備えており、チャンバー140の内部には、ウエハWを略水平にした状態で載置させる載置台142が設けられている。また、エッチング装置105は、チャンバー140にエッチングガスを供給するガス供給機構143、チャンバー140内を排気する排気機構144を備えている。
[Etching device]
Next, an example of the etching apparatus 105 for performing the etching method of this embodiment will be described in detail.
FIG. 4 is a cross-sectional view showing an example of the etching apparatus 105. As shown in FIG. 4, the etching apparatus 105 includes a sealed chamber 140, and a mounting table 142 for mounting the wafer W in a substantially horizontal state is provided inside the chamber 140. The etching apparatus 105 also includes a gas supply mechanism 143 that supplies an etching gas to the chamber 140 and an exhaust mechanism 144 that exhausts the inside of the chamber 140.
 チャンバー140は、チャンバー本体151と蓋部152とによって構成されている。チャンバー本体151は、略円筒形状の側壁部151aと底部151bとを有し、上部は開口となっており、この開口が蓋部152で閉止される。側壁部151aと蓋部152とは、シール部材(図示せず)により密閉されて、チャンバー140内の気密性が確保される。 The chamber 140 includes a chamber main body 151 and a lid 152. The chamber main body 151 has a substantially cylindrical side wall portion 151 a and a bottom portion 151 b, and an upper portion is an opening, and the opening is closed by a lid portion 152. The side wall portion 151a and the lid portion 152 are sealed by a seal member (not shown), and airtightness in the chamber 140 is ensured.
 蓋部152は、外側を構成する蓋部材155と、蓋部材155の内側に嵌め込まれ、載置台142に臨むように設けられたシャワーヘッド156とを有している。シャワーヘッド156は円筒状をなす側壁157aと上部壁157bとを有する本体157と、本体157の底部に設けられたシャワープレート158とを有している。本体157とシャワープレート158との間には空間159が形成されている。 The lid portion 152 includes a lid member 155 that constitutes the outside, and a shower head 156 that is fitted inside the lid member 155 and faces the mounting table 142. The shower head 156 includes a main body 157 having a cylindrical side wall 157a and an upper wall 157b, and a shower plate 158 provided at the bottom of the main body 157. A space 159 is formed between the main body 157 and the shower plate 158.
 蓋部材155および本体157の上部壁157bには空間159まで貫通してガス導入路161が形成されており、このガス導入路161には後述するガス供給機構143のHFガス供給配管171が接続されている。 A gas introduction path 161 is formed through the cover member 155 and the upper wall 157b of the main body 157 to the space 159, and an HF gas supply pipe 171 of a gas supply mechanism 143, which will be described later, is connected to the gas introduction path 161. ing.
 シャワープレート158には複数のガス吐出孔162が形成されており、ガス供給配管171およびガス導入路161を経て空間159に導入されたガスがガス吐出孔162からチャンバー140内の空間に吐出される。 A plurality of gas discharge holes 162 are formed in the shower plate 158, and the gas introduced into the space 159 through the gas supply pipe 171 and the gas introduction path 161 is discharged from the gas discharge hole 162 into the space in the chamber 140. .
 側壁部151aには、熱処理装置104との間でウエハWを搬入出する搬入出口153が設けられており、この搬入出口153はゲートバルブ154により開閉可能となっている。 The side wall 151 a is provided with a loading / unloading port 153 for loading / unloading the wafer W to / from the heat treatment apparatus 104, and the loading / unloading port 153 can be opened and closed by a gate valve 154.
 載置台142は、平面視略円形をなしており、チャンバー140の底部151bに固定されている。載置台142の内部には、載置台142の温度を調節する温度調節器165が設けられている。温度調節器165は、例えば温度調節用媒体(例えば水など)が循環する管路を備えており、このような管路内を流れる温度調節用媒体と熱交換が行なわれることにより、載置台142の温度が調節され、載置台142上のウエハWの温度制御がなされる。 The mounting table 142 has a substantially circular shape in plan view, and is fixed to the bottom 151 b of the chamber 140. Inside the mounting table 142, a temperature controller 165 for adjusting the temperature of the mounting table 142 is provided. The temperature controller 165 includes, for example, a pipe line through which a temperature adjusting medium (for example, water) circulates, and heat exchange is performed with the temperature adjusting medium flowing in the pipe line, thereby the mounting table 142. The temperature of the wafer W on the mounting table 142 is controlled.
 ガス供給機構143は、HFガスを供給するHFガス供給源175および不活性ガスを供給する不活性ガス供給源176を有しており、これらにはそれぞれHFガス供給配管171および不活性ガス供給配管172の一端が接続されている。HFガス供給配管171および不活性ガス供給配管172には、流路の開閉動作および流量制御を行う流量制御器179が設けられている。流量制御器179は例えば開閉弁およびマスフローコントローラにより構成されている。HFガス供給配管171の他端は、上述したように、ガス導入路161に接続されている。また、不活性ガス供給配管172の他端はHFガス供給配管171に接続されている。 The gas supply mechanism 143 includes an HF gas supply source 175 that supplies HF gas and an inert gas supply source 176 that supplies inert gas. These include an HF gas supply pipe 171 and an inert gas supply pipe, respectively. One end of 172 is connected. The HF gas supply pipe 171 and the inert gas supply pipe 172 are provided with a flow rate controller 179 that performs opening / closing operation of the flow path and flow rate control. The flow rate controller 179 includes, for example, an on-off valve and a mass flow controller. The other end of the HF gas supply pipe 171 is connected to the gas introduction path 161 as described above. The other end of the inert gas supply pipe 172 is connected to the HF gas supply pipe 171.
 したがって、HFガスは、HFガス供給源175からHFガス供給配管171を経てシャワーヘッド156内に供給され、不活性ガスは、不活性ガス供給源176から不活性ガス供給配管172およびHFガス供給配管171を経てシャワーヘッド156に供給される。これらのガスは、シャワーヘッド156のガス吐出孔162からチャンバー140内のウエハWに向けて吐出される。 Accordingly, the HF gas is supplied from the HF gas supply source 175 through the HF gas supply pipe 171 into the shower head 156, and the inert gas is supplied from the inert gas supply source 176 to the inert gas supply pipe 172 and the HF gas supply pipe. 171 is supplied to the shower head 156. These gases are discharged from the gas discharge holes 162 of the shower head 156 toward the wafer W in the chamber 140.
 これらガスのうちHFガスが反応ガスであり、不活性ガスは希釈ガスおよびパージガスとして用いられる。HFガスを単独またはHFガスと不活性ガスを混合して供給することにより、所望のエッチング性能を得ることができる。 Of these gases, HF gas is a reactive gas, and an inert gas is used as a dilution gas and a purge gas. Desired etching performance can be obtained by supplying HF gas alone or by mixing HF gas and inert gas.
 排気機構144は、チャンバー140の底部151bに形成された排気口181に繋がる排気配管182を有している。排気機構144は、さらに、排気配管182に設けられた、チャンバー140内の圧力を制御するための自動圧力制御弁(APC)183およびチャンバー140内を排気するための真空ポンプ184を有している。 The exhaust mechanism 144 has an exhaust pipe 182 connected to an exhaust port 181 formed in the bottom portion 151 b of the chamber 140. The exhaust mechanism 144 further includes an automatic pressure control valve (APC) 183 provided on the exhaust pipe 182 for controlling the pressure in the chamber 140 and a vacuum pump 184 for exhausting the interior of the chamber 140. .
 チャンバー140の側壁には、チャンバー140内の圧力を計測するための圧力計として2つのキャパシタンスマノメータ186a,186bが、チャンバー140内に挿入されるように設けられている。キャパシタンスマノメータ186aは高圧力用、キャパシタンスマノメータ186bは低圧力用となっている。載置台142に載置されたウエハWの近傍には、ウエハWの温度を検出する温度センサ(図示せず)が設けられている。 On the side wall of the chamber 140, two capacitance manometers 186a and 186b are provided so as to be inserted into the chamber 140 as pressure gauges for measuring the pressure in the chamber 140. The capacitance manometer 186a is for high pressure, and the capacitance manometer 186b is for low pressure. A temperature sensor (not shown) for detecting the temperature of the wafer W is provided in the vicinity of the wafer W mounted on the mounting table 142.
 このようなエッチング装置105においては、上述した構造が形成されたウエハWをチャンバー140内に搬入し、載置台142に載置する。そして、載置台142の温度調節器165によりウエハWを好ましくは10~120℃、より好ましくは、30~80℃とする。また、チャンバー140内の圧力を、1333Pa(10Torr)以上、好ましくは1333~11997Pa(10~90Torr)、より好ましくは1333~5332Pa(10~40Torr)とする。そして、HFガスおよび不活性ガスを、好ましくはいずれも200~3000sccmの流量で供給し、SiN膜をエッチングする。 In such an etching apparatus 105, the wafer W having the above-described structure is loaded into the chamber 140 and placed on the mounting table 142. The temperature controller 165 of the mounting table 142 sets the wafer W to preferably 10 to 120 ° C., more preferably 30 to 80 ° C. The pressure in the chamber 140 is 1333 Pa (10 Torr) or more, preferably 1333 to 11997 Pa (10 to 90 Torr), more preferably 1333 to 5332 Pa (10 to 40 Torr). Then, HF gas and inert gas are preferably supplied at a flow rate of 200 to 3000 sccm to etch the SiN film.
 <第2の実施形態>
 次に、本発明の第2の実施形態について説明する。
 本実施形態は、第1の実施形態と同様、SiN膜をエッチング除去する工程を含むものである。本実施形態では、SiN膜に隣接するSiO膜中にNやH等の不純物が含まれていても、SiN膜をエッチングした際のSiO膜へのダメージが発生し難いエッチング方法について説明する。
<Second Embodiment>
Next, a second embodiment of the present invention will be described.
This embodiment includes a step of removing the SiN film by etching, as in the first embodiment. In this embodiment, also contain impurities such as N and H on SiO 2 film adjacent to the SiN film, damage to the SiO 2 film when etching the SiN film is described hardly etching method generated .
  [第2の実施形態のエッチング方法の第1の例]
 最初に、第2の実施形態の第1の例として、本実施形態の基本例について説明する。本例では、所定の不純物が含まれているSiO膜に隣接してSiN膜が形成されたウエハについて、SiN膜のエッチングを行う。
[First Example of Etching Method of Second Embodiment]
First, a basic example of the present embodiment will be described as a first example of the second embodiment. In this example, the SiN film is etched on the wafer on which the SiN film is formed adjacent to the SiO 2 film containing a predetermined impurity.
 SiO膜中にHやN等の不純物が含まれている場合、それに隣接するSiN膜をそのままHFガスによりエッチングすると、SiO膜中に含まれている不純物中のHやN等のガス成分が、SiN膜エッチングの際にHFと反応することが判明した。このようなガス成分がSiN膜エッチングの際にHFと反応すると、SiO膜が不均一にエッチングされ、ピッティング(孔)や表面荒れ等のダメージが発生するおそれがある。例えば、CVDやALDで成膜されたSiO膜の場合は、膜中に成膜原料ガス由来のH、N、C等が存在しており、SiN膜エッチング時のダメージが発生するおそれがある。特にCVDやALDで成膜されたSiO層間絶縁膜のアニール温度が低い場合は上記不純物が存在する他、密度が低く、SiN膜エッチング時のダメージを受けやすくなる。また、流動性化学蒸着法(F-CVD)により形成されたSiO膜も、上記のような不純物が多く存在し、密度も低いため、やはり、SiN膜エッチング時のダメージを受けやすくなる。 If it contains impurities such as H and N in the SiO 2 film, it is etched by SiN film directly HF gas adjacent thereto, the gas components such as H and N in the impurities contained in the SiO 2 film However, it was found to react with HF during the etching of the SiN film. If such a gas component reacts with HF during etching of the SiN film, the SiO 2 film is etched unevenly, and damage such as pitting (holes) or surface roughness may occur. For example, in the case of a SiO 2 film formed by CVD or ALD, H, N, C, etc. derived from the film forming source gas are present in the film, and there is a risk of damage during etching of the SiN film. . In particular, when the annealing temperature of the SiO 2 interlayer insulating film formed by CVD or ALD is low, in addition to the presence of the impurities, the density is low and the SiN film is susceptible to damage during etching. In addition, the SiO 2 film formed by fluid chemical vapor deposition (F-CVD) is also susceptible to damage during etching of the SiN film because it contains many impurities as described above and has a low density.
 また、SiN膜に隣接するSiO膜がエッチングされたものである場合、もともと含まれている不純物の他、エッチングのときに膜中に侵入する成分や、除去しきれずにウエハWに付着しているガス成分が存在する。そして、SiN膜エッチングの際に、HFと付着したガス成分とでSiO膜のエッチングによるダメージを受けやすくなる。特に、SiO膜をCORにより除去した際には、膜中に不純物であるH、N、C等の他、ガス成分中のNHやFが含まれており、さらにNHやHFといった反応性の高い副生成物がウエハWに付着している可能性がある。これらがSiN膜エッチングの際にHFと共存することにより、SiO膜がエッチングされやすくなる。上述したように、SiO膜がCVD膜やALD膜である場合は不純物が存在し、また成膜手法によっては、膜中の不純物が多く密度も低い傾向にある。このため、SiO膜エッチングの際に存在するガス成分や反応生成物と相俟って、SiN膜のエッチングによるSiO膜のダメージはより大きいものとなる。 In addition, when the SiO 2 film adjacent to the SiN film is etched, in addition to the impurities originally contained, the components that enter the film during etching and the wafers W adhere to the wafer W without being completely removed. Gas components are present. When the SiN film is etched, the HF and the attached gas component are easily damaged by the etching of the SiO 2 film. In particular, when the SiO 2 film is removed by COR, the film contains NH 3 and F in the gas component in addition to impurities such as H, N, and C, and further, NH 4 and HF 2 , etc. There is a possibility that a highly reactive by-product is attached to the wafer W. Since these coexist with HF during the etching of the SiN film, the SiO 2 film is easily etched. As described above, when the SiO 2 film is a CVD film or an ALD film, impurities are present, and depending on the film formation method, there are many impurities in the film and the density tends to be low. Therefore, gas components present during the SiO 2 film etching or reaction products coupled with damage of the SiO 2 film by etching the SiN film becomes more larger.
 一例を図5に示す。図5は、不純物を含むSiO膜と隣接したSiN膜をHFガスによりエッチングする際に、SiO膜にダメージが発生するメカニズムを説明するための図である。(a)に示すように、Si基板40上にFCVDで成膜され、CORによりエッチングされたSiO膜41は、膜の表層部分に不純物としてC、F、NH等が含まれている。この状態でエッチングガスとしてHFガスを用いて、SiN膜のエッチングを行うと、(b)に示すように、エッチングガスであるHFおよび膜中のNHが、SiO中のSiと反応してフルオロケイ酸アンモニウム((NHSiF;AFS)が生成される。その後の加熱処理により、(c)に示すように、ケイフッ化アンモニウムが揮発してSiO膜41にピッティング42が形成される。また、これにより、SiO膜41の表面に表面荒れが生じる。SiO膜41にNHやHF等の副生成物が付着している場合にも同様にピッティングや表面荒れが生じる。 An example is shown in FIG. FIG. 5 is a diagram for explaining a mechanism that causes damage to the SiO 2 film when the SiN film adjacent to the SiO 2 film containing impurities is etched with HF gas. (A), the deposited by FCVD on the Si substrate 40, SiO 2 film 41 is etched by the COR, C as an impurity into the surface layer portion of the film, F, it is included NH 3 or the like. When the SiN film is etched using HF gas as the etching gas in this state, as shown in (b), HF as the etching gas and NH 3 in the film react with Si in SiO 2. Ammonium fluorosilicate ((NH 4 ) 2 SiF 6 ; AFS) is produced. By subsequent heat treatment, as shown in (c), ammonium fluorosilicate is volatilized and a pitting 42 is formed in the SiO 2 film 41. This also causes surface roughness on the surface of the SiO 2 film 41. Similarly, when a by-product such as NH 4 or HF 2 adheres to the SiO 2 film 41, pitting or surface roughness occurs.
 そこで、本実施形態の第1の例では、図6のフローチャートに示すように、最初にウエハに対して表面改質処理を行い(ステップ1)、その後HFガスによるSiN膜のエッチングを行う(ステップ2)。 Therefore, in the first example of the present embodiment, as shown in the flowchart of FIG. 6, the wafer is first subjected to surface modification processing (step 1), and then the SiN film is etched with HF gas (step 1). 2).
 ステップ1の表面改質処理は、膜中のNH、F、C等の不純物やウエハWに付着しているNHやHF等の副生成物を除去するためのものである。表面改質処理によりこれらを除去することにより、その後のSiN膜エッチングによりSiO膜がエッチングされ難くなる。 The surface modification treatment in Step 1 is for removing impurities such as NH 3 , F, and C in the film and by-products such as NH 4 and HF 2 adhering to the wafer W. By removing these by the surface modification treatment, the SiO 2 film becomes difficult to be etched by the subsequent SiN film etching.
 表面改質処理としては、不活性雰囲気中で熱処理を行うドライ処理を挙げることができる。このときの温度は、150~400℃が好ましく、例えば250℃である。この処理により、膜中NH、F、C等の不純物やウエハWに付着しているNHやHF等の副生成物を熱分解または揮発させて、除去することができる。なお、ドライ処理としては、ラジカル処理等の他の処理を用いることもできる。 Examples of the surface modification treatment include dry treatment in which heat treatment is performed in an inert atmosphere. The temperature at this time is preferably 150 to 400 ° C., for example, 250 ° C. By this treatment, impurities such as NH 3 , F, and C in the film and by-products such as NH 4 and HF 2 adhering to the wafer W can be removed by thermal decomposition or volatilization. In addition, as a dry process, other processes, such as a radical process, can also be used.
 また、表面改質処理として、HOを用いた反応処理を行うものを挙げることができる。この処理により膜中の不純物やウエハWに付着している副生成物をHOと反応させて除去することができる。このときの温度は、20~100℃が好ましく、20~80℃がより好ましい。HOを用いた反応処理としては、HO蒸気を含有する雰囲気によるドライ処理で行ってもよいし、液体のHO(純水)に浸漬したり、液体のHO(純水)を供給したりするウエット処理により行ってもよい。 Further, as a surface modification treatment include those to perform the reaction process using H 2 O. By this treatment, impurities in the film and by-products attached to the wafer W can be removed by reacting with H 2 O. The temperature at this time is preferably 20 to 100 ° C., more preferably 20 to 80 ° C. The reaction process using of H 2 O, may be performed in a dry process by an atmosphere containing H 2 O vapor, or immersed in H 2 O (deionized water) of the liquid, the liquid H 2 O (deionized You may carry out by the wet process which supplies water.
 さらに、表面改質処理は、ウエハ表面に界面活性剤を吸着させる工程と、HO(純水)によるウエット洗浄工程とを有する処理により行うこともできる。 Further, the surface modification treatment can be performed by a treatment including a step of adsorbing a surfactant on the wafer surface and a wet cleaning step using H 2 O (pure water).
 SiO膜の表面に疎水性の部分が存在すると、単純なHOによるウエット処理では、疎水性の部分にはHOが到達できず、その部分でHO処理が不十分になって、膜中の不純物や膜に付着した反応生成物を十分に除去できない事態が生じることがある。これに対して、ウエハ表面に界面活性剤を吸着させることにより、ウエハ表面の全面を親水性とすることができる。そのため、その後のHO(純水)によるウエット洗浄の際の洗浄性が良好であり、SiO膜の膜中の不純物やSiO膜に付着した反応生成物をより効果的に除去することができる。 When surface hydrophobic portion of the SiO 2 film is present, the wet process by simple H 2 O, can not reach the H 2 O in the portion of the hydrophobic, it becomes insufficient H 2 O treated with the portion In some cases, impurities in the film and reaction products attached to the film cannot be sufficiently removed. On the other hand, the entire surface of the wafer surface can be made hydrophilic by adsorbing the surfactant on the wafer surface. Therefore, cleaning of the time of wet cleaning by subsequent H 2 O (pure water) is good, to more effectively remove the reaction product adhering to the impurities and the SiO 2 film in the film of the SiO 2 film Can do.
 図7は、表面改質処理に用いる界面活性剤の機能を説明するための図である。図7の(a)に示すように、界面活性剤は、1分子内に疎水基と親水基を有しており、疎水性の状態のものを、疎水基を介して水と親和させる機能を有している。そして、(b)に示すように、SiO膜表面の全面に、親水基が外側にして配列されるように吸着することができる。このため、(c)に示すように、HO(純水)がSiO膜表面の全面に供給されて良好な洗浄性でHO洗浄が行われ、SiO膜の膜中の不純物やSiO膜に付着した反応生成物を効果的に除去することができる。 FIG. 7 is a diagram for explaining the function of the surfactant used for the surface modification treatment. As shown in FIG. 7 (a), the surfactant has a hydrophobic group and a hydrophilic group in one molecule, and has a function of making a hydrophobic state compatible with water via the hydrophobic group. Have. Then, (b), the entire surface of the SiO 2 film surface can be hydrophilic group is adsorbed so as to be arranged in the outside. Therefore, as shown in (c), and H 2 O (deionized water) is supplied to the entire surface of the SiO 2 film surface is performed H 2 O washed with a good cleaning properties, impurities in the film of the SiO 2 film And the reaction product adhering to the SiO 2 film can be effectively removed.
 界面活性剤をウエハに吸着させる工程は、界面活性剤にウエハを浸漬させるか、または、界面活性剤を塗布することにより行うことができる。このとき、界面活性剤は原液であっても水溶液であってもよい。また、HO(純水)によるウエット洗浄工程は、純水にウエハを浸漬させるか、または、ウエハに純水を供給することにより行うことができる。 The step of adsorbing the surfactant onto the wafer can be performed by immersing the wafer in the surfactant or by applying the surfactant. At this time, the surfactant may be a stock solution or an aqueous solution. Further, the wet cleaning step using H 2 O (pure water) can be performed by immersing the wafer in pure water or supplying pure water to the wafer.
 ステップ2のSiN膜のエッチングは、第1の実施形態と同様、HFガスのみ、またはHFガスと不活性ガスの混合ガスをチャンバー内に導入し、圧力を1333Pa(10Torr)以上の高圧にして行われる。好ましくは1333~11997Pa(10~90Torr)である。より好ましくは1333~5332Pa(10~40Torr)である。不活性ガスとしては、Nガスや、Ar、He等の希ガスを用いることができる。 Etching of the SiN film in step 2 is performed by introducing only HF gas or a mixed gas of HF gas and inert gas into the chamber and setting the pressure to a high pressure of 1333 Pa (10 Torr) or more as in the first embodiment. Is called. It is preferably 1333 to 11997 Pa (10 to 90 Torr). More preferably, it is 1333 to 5332 Pa (10 to 40 Torr). As the inert gas, N 2 gas or a rare gas such as Ar or He can be used.
 第1の実施形態と同様、このときのガス流量は、HFガス:200~3000sccm、不活性ガス:200~3000sccmであることが好ましく、また、ウエハ温度は、10~120℃が好ましく、30~80℃がより好ましい。 As in the first embodiment, the gas flow rates at this time are preferably HF gas: 200 to 3000 sccm, inert gas: 200 to 3000 sccm, and the wafer temperature is preferably 10 to 120 ° C., 30 to 80 ° C. is more preferable.
 以上のようなSiN膜のエッチングが終了した後、必要に応じてエッチング残渣等の除去を行い、処理が終了する。 After the above etching of the SiN film is completed, etching residues and the like are removed as necessary, and the processing is completed.
 以上のような処理により、SiN膜をSiO膜に対し15以上の高選択比でエッチングすることができるとともに、SiN膜エッチング時のSiO膜のダメージ(ピッティングや表面荒れ等)を抑制することができる。 With the above processing, inhibit with an SiN film can be etched at a high selection ratio of 15 or more with respect to the SiO 2 film, a SiO 2 film during SiN film etching damage to (such as roughness pitting or surface) be able to.
 なお、SiN膜に隣接してSiやSiGeも存在している場合には、第1の実施形態と同様、これらに対して50以上の高い選択比でSiN膜をエッチングすることができる。 If Si or SiGe is also present adjacent to the SiN film, the SiN film can be etched with a high selection ratio of 50 or more as in the first embodiment.
  [第2の実施形態のエッチング方法の第2の例]
 次に、第2の例として本実施形態の応用例について説明する。
[Second Example of Etching Method of Second Embodiment]
Next, an application example of this embodiment will be described as a second example.
   (第2の例が適用される構造例)
 本実施形態の第2の例のエッチング方法が適用される構造の一例としては、図8に示すようなものを挙げることができる。図8の構造は、シリコン基板31上にポール状のSi膜32およびSiGe膜33が形成され、Si膜32の周囲およびSiGe膜33の周囲に薄いSiN膜34が形成されており、SiN膜34の周囲に全体を埋めるようにSiO膜35が形成されている。
(Structural example to which the second example is applied)
As an example of the structure to which the etching method of the second example of the present embodiment is applied, the structure shown in FIG. 8 can be cited. In the structure of FIG. 8, a pole-like Si film 32 and a SiGe film 33 are formed on a silicon substrate 31, and a thin SiN film 34 is formed around the Si film 32 and around the SiGe film 33. An SiO 2 film 35 is formed so as to fill the entire periphery of the substrate.
   (第2の例のエッチング方法)
 本実施形態の第2の例のエッチング方法は、図8の構造に対して、図9のフローチャートおよび図10の工程断面図に示すように行われる。
(Second Example Etching Method)
The etching method of the second example of this embodiment is performed on the structure of FIG. 8 as shown in the flowchart of FIG. 9 and the process cross-sectional view of FIG.
 最初に、図8のSiO膜35をエッチングする(ステップ11)。
 SiO膜35のエッチングは、図8のような構造を有するウエハをチャンバー内に収容し、HFガスとNHガスを用いたCORにより行うことができる。このとき、圧力:133~400Pa(1~3Torr)、処理温度:10~130℃、HFガス流量:20~1000sccm、NHガス流量:20~1000sccm、不活性ガス流量:20~1000sccmが好ましい。このCOR処理により、フルオロケイ酸アンモニウム((NHSiF;AFS)が生成されるので、加熱によりAFSを昇華させてエッチングが完了する。AFSの昇華は別個の加熱装置で行ってもよいし、CORチャンバー内でエッチングと加熱処理を繰り返し行って、その中でAFSの除去を行ってもよい。
First, the SiO 2 film 35 in FIG. 8 is etched (step 11).
The etching of the SiO 2 film 35 can be performed by COR with a wafer having a structure as shown in FIG. 8 in a chamber and using HF gas and NH 3 gas. At this time, the pressure is preferably 133 to 400 Pa (1 to 3 Torr), the processing temperature is 10 to 130 ° C., the HF gas flow rate is 20 to 1000 sccm, the NH 3 gas flow rate is 20 to 1000 sccm, and the inert gas flow rate is 20 to 1000 sccm. By this COR treatment, ammonium fluorosilicate ((NH 4 ) 2 SiF 6 ; AFS) is generated, so that the AFS is sublimated by heating to complete the etching. AFS sublimation may be performed with a separate heating apparatus, or etching and heat treatment may be repeatedly performed in the COR chamber, and AFS may be removed therein.
 また、SiO膜35のエッチングは、ラジカル処理により行ってもよい。このとき、ラジカルとしては、NFとNHの混合ガスを活性化させて形成されたFラジカル、Nラジカルを用いることができる。 Further, the etching of the SiO 2 film 35 may be performed by radical treatment. At this time, F radicals and N radicals formed by activating a mixed gas of NF 3 and NH 3 can be used as the radicals.
 ステップ11のエッチングにより、図10の(a)に示すように、SiO膜35が所定の高さ位置までエッチング除去され、SiN膜34は所定の高さ位置よりも高い位置まで残存する。このため、SiN膜34のフッティング領域を除去するためのエッチング(デフッティング(de-footing))が行われる。 By the etching in step 11, as shown in FIG. 10A, the SiO 2 film 35 is etched away to a predetermined height position, and the SiN film 34 remains up to a position higher than the predetermined height position. Therefore, etching (de-footing) for removing the footing region of the SiN film 34 is performed.
 このとき、SiO膜35のエッチング後のウエハWに対してそのままSiN膜をエッチングすると、SiN膜34以外の膜、主にSiO膜35をエッチングしてピッティングや表面荒れ等のダメージを発生させてしまうおそれがある。このダメージは、SiO膜35中に含まれている不純物や、SiO膜35のエッチングのときに膜中に侵入する成分や、除去しきれずにウエハWに付着しているガス成分が、SiN膜エッチングの際にHFと反応することにより生じる。特に、SiO膜35をCORにより除去した際には、膜中に不純物であるH、N、C等の他、ガス成分中のNHやFが含まれており、さらにNHやHFといった反応性の高い副生成物がウエハWに付着している可能性があり、これらがSiN膜エッチングの際にHFと共存することによりSiO膜35がエッチングされやすくなる。上述したように、SiO膜がCVDやALDで成膜された膜である場合、成膜方法によっては、膜中の不純物が多く密度も低い傾向にあるため、このような傾向が顕著である。 At this time, if the SiN film is etched as it is with respect to the wafer W after the etching of the SiO 2 film 35, a film other than the SiN film 34, mainly the SiO 2 film 35, is etched to cause damage such as pitting and surface roughness. There is a risk of letting you. This damage, and impurities contained in the SiO 2 film 35, components and entering in the film during the etching of the SiO 2 film 35, the gas components adhered to the wafer W without being completely removed, SiN It occurs by reacting with HF during film etching. In particular, when the SiO 2 film 35 is removed by COR, the film contains NH 3 and F in the gas component in addition to impurities such as H, N, and C, and further NH 4 and HF 2. There is a possibility that such a by-product with high reactivity adheres to the wafer W, and the SiO 2 film 35 is likely to be etched by coexistence with HF during the etching of the SiN film. As described above, when the SiO 2 film is a film formed by CVD or ALD, depending on the film forming method, there is a tendency that the impurity in the film is large and the density is low, and thus this tendency is remarkable. .
 そこで、本例においても、SiO膜35のエッチング後に、表面改質処理を行う(ステップ12)。 Therefore, also in this example, after the etching of the SiO 2 film 35, a surface modification process is performed (step 12).
 表面改質処理は、膜中の不純物やウエハWに付着しているNHやHF等の副生成物を除去するためのものである。これにより、その後のSiN膜34のエッチングの際にSiO膜35がエッチングされ難くなる。 The surface modification treatment is for removing impurities in the film and by-products such as NH 4 and HF 2 adhering to the wafer W. This makes it difficult for the SiO 2 film 35 to be etched during the subsequent etching of the SiN film 34.
 表面改質処理としては、第1の例と同様、不活性雰囲気中での熱処理、HOを用いた反応処理、およびウエハ表面に界面活性剤を吸着させる工程と、HO(純水)によるウエット洗浄工程とを有する処理を挙げることができる。また、表面改質処理として、ラジカル処理等の他の処理を用いることもできる。 As in the first example, the surface modification treatment includes heat treatment in an inert atmosphere, reaction treatment using H 2 O, a step of adsorbing a surfactant on the wafer surface, and H 2 O (pure water). And a wet cleaning step. Further, as the surface modification treatment, other treatment such as radical treatment can be used.
 このような表面改質処理を行った後、SiN膜34のフッティング領域のエッチング(de-footing)を行う(ステップ13)。 After performing such surface modification treatment, etching (de-footing) of the footing region of the SiN film 34 is performed (step 13).
 このエッチングは、図10の(a)に示す構造のウエハをチャンバー内に収容し、第1の実施形態と同様、HFガスのみ、またはHFガスと不活性ガスの混合ガスをチャンバー内に導入し、圧力を1333Pa(10Torr)以上の高圧にして行われる。好ましくは1333~11997Pa(10~90Torr)である。より好ましくは1333~5332Pa(10~40Torr)である。不活性ガスとしては、Nガスや、Ar、He等の希ガスを用いることができる。ただし、本実施形態では、表面改質処理が行われていることにより、特に、SiO膜35のエッチングがラジカル処理で行われている場合には、1333Pa(10Torr)より低くても選択比の高いSiN膜エッチングを行える可能性がある。 In this etching, a wafer having a structure shown in FIG. 10A is accommodated in the chamber, and, as in the first embodiment, only HF gas or a mixed gas of HF gas and inert gas is introduced into the chamber. The pressure is set at a high pressure of 1333 Pa (10 Torr) or more. It is preferably 1333 to 11997 Pa (10 to 90 Torr). More preferably, it is 1333 to 5332 Pa (10 to 40 Torr). As the inert gas, N 2 gas or a rare gas such as Ar or He can be used. However, in the present embodiment, since the surface modification process is performed, particularly when the etching of the SiO 2 film 35 is performed by a radical process, the selectivity ratio is low even if it is lower than 1333 Pa (10 Torr). There is a possibility that high SiN film etching can be performed.
 また、このエッチングにおいては、第1の実施形態と同様、ガス流量は、HFガス:200~3000sccm、不活性ガス:200~3000sccmであることが好ましく、また、ウエハ温度は、10~120℃が好ましく、30~80℃がより好ましい。 In this etching, as in the first embodiment, the gas flow rates are preferably HF gas: 200 to 3000 sccm, inert gas: 200 to 3000 sccm, and the wafer temperature is 10 to 120 ° C. Preferably, 30 to 80 ° C. is more preferable.
 これにより、図10の(b)に示すように、SiN膜34のフッティング領域をエッチング除去して所望の半導体デバイスを得ることができる。 Thereby, as shown in FIG. 10B, the footing region of the SiN film 34 can be removed by etching to obtain a desired semiconductor device.
 以上のようなSiN膜のエッチングが終了した後、必要に応じて熱処理等によりエッチング残渣等の除去を行い、処理が終了する。 After the etching of the SiN film as described above is completed, etching residues and the like are removed by heat treatment or the like as necessary, and the processing is completed.
 本例によれば、SiO膜35をエッチング除去した後、表面改質処理により、膜中の不純物やウエハWに付着しているNHやHF等の副生成物を除去する。これにより、その後のSiN膜34のエッチングにおいて、これらの影響によりSiO膜35がエッチングされてダメージ(ピッティングや表面荒れ)が発生することを防止した状態で、SiN膜34をSiO膜35、Si膜32、SiGe膜33に対して高選択比でエッチングすることができる。このときの選択比は、SiOに対して選択比5以上、好ましくは15以上、SiおよびSiGeに対して選択比50以上、好ましくは100以上である。このため、高精度で図10の(b)の構造を有する半導体素子を得ることができる。特に、SiO膜35として比較的不純物が多く密度が低い成膜方法のCVD(例えばFCVD)により形成されたものを用いた場合でも、SiO膜35のエッチングを抑制することができ、SiN膜34のSiO膜35に対する選択比を高くすることができる。 According to this example, after removing the SiO 2 film 35 by etching, impurities in the film and by-products such as NH 4 and HF 2 adhering to the wafer W are removed by a surface modification process. Thus, in the subsequent etching of the SiN film 34, by these effects in a state in which damage SiO 2 film 35 is etched (roughened pitting or surface) is prevented from occurring, SiO 2 film 35 SiN film 34 The Si film 32 and the SiGe film 33 can be etched with a high selectivity. The selection ratio at this time is 5 or more, preferably 15 or more with respect to SiO 2 , and 50 or more, preferably 100 or more, with respect to Si and SiGe. Therefore, a semiconductor element having the structure shown in FIG. 10B can be obtained with high accuracy. In particular, even when the SiO 2 film 35 is formed by CVD (for example, FCVD), which has a relatively large amount of impurities and a low density, etching of the SiO 2 film 35 can be suppressed, and the SiN film The selectivity ratio of 34 to the SiO 2 film 35 can be increased.
  [第2の実施形態の実施に用いる処理システムの一例]
 次に、第2の実施形態に用いる処理システムの一例について説明する。
 図11は、第2の実施形態の第2の例のエッチング方法に用いる処理システムの一例を示す概略構成図である。この処理システム200は、断面矩形状の真空搬送室201を有し、真空搬送室201の長辺の一方側にSiO膜をエッチングするための酸化膜エッチング装置202、表面改質処理装置203、およびSiN膜エッチング装置204がゲートバルブGを介して接続されている。また、真空搬送室201の長辺の他方側にも同様に酸化膜エッチング装置202、表面改質処理装置203、およびSiN膜エッチング装置204がゲートバルブGを介して接続されている。真空搬送室201内は、真空ポンプにより排気されて所定の真空度に保持される。
[An example of a processing system used to implement the second embodiment]
Next, an example of a processing system used in the second embodiment will be described.
FIG. 11 is a schematic configuration diagram illustrating an example of a processing system used in the etching method of the second example of the second embodiment. The processing system 200 includes a vacuum transfer chamber 201 having a rectangular cross section, and an oxide film etching device 202 for etching a SiO 2 film on one side of the long side of the vacuum transfer chamber 201, a surface modification processing device 203, And a SiN film etching apparatus 204 are connected via a gate valve G. Similarly, an oxide film etching device 202, a surface modification processing device 203, and a SiN film etching device 204 are connected to the other side of the long side of the vacuum transfer chamber 201 via a gate valve G. The inside of the vacuum transfer chamber 201 is evacuated by a vacuum pump and maintained at a predetermined degree of vacuum.
 酸化膜エッチング装置202は、CORによりSiO膜のエッチングを行うCOR装置として構成することができる。また、酸化膜エッチング装置202は、ラジカル処理装置であってもよい。 The oxide film etching apparatus 202 can be configured as a COR apparatus that performs etching of the SiO 2 film by COR. Further, the oxide film etching apparatus 202 may be a radical processing apparatus.
 また、表面改質処理装置203は、ウエハWを比較的高温で熱処理する熱処理装置として構成することができる。また、ウエハWをHOガス雰囲気で熱処理するHOガス処理装置であってもよい。さらに、表面改質処理装置203として、ラジカル処理装置等の他の処理装置を用いることもできる。 In addition, the surface modification processing apparatus 203 can be configured as a heat treatment apparatus that heat-treats the wafer W at a relatively high temperature. Further, the wafer W may be the H 2 O gas treatment apparatus for heat treatment with H 2 O gas atmosphere. Furthermore, as the surface modification treatment apparatus 203, another treatment apparatus such as a radical treatment apparatus can be used.
 SiN膜エッチング装置204は、第1の実施形態におけるエッチング装置105と同様に構成することができる。 The SiN film etching apparatus 204 can be configured in the same manner as the etching apparatus 105 in the first embodiment.
 また、真空搬送室201の短辺の一方側には2つのロードロック室205がゲートバルブG1を介して接続されている。ロードロック室205を挟んで真空搬送室201の反対側には大気搬送室206が設けられている。ロードロック室205は、ゲートバルブG2を介して大気搬送室206に接続されている。ロードロック室205は、大気搬送室206と真空搬送室201との間でウエハWを搬送する際に、大気圧と真空との間で圧力制御するものである。 Also, two load lock chambers 205 are connected to one side of the short side of the vacuum transfer chamber 201 via a gate valve G1. An atmospheric transfer chamber 206 is provided on the opposite side of the vacuum transfer chamber 201 across the load lock chamber 205. The load lock chamber 205 is connected to the atmospheric transfer chamber 206 via a gate valve G2. The load lock chamber 205 controls the pressure between the atmospheric pressure and the vacuum when the wafer W is transferred between the atmospheric transfer chamber 206 and the vacuum transfer chamber 201.
 大気搬送室206のロードロック室205取り付け壁部とは反対側の壁部には、FOUP等の複数枚のウエハWを収容するキャリアCを取り付ける3つのキャリア取り付けポート207を有している。また、大気搬送室206の側壁には、ウエハWのアライメントを行うアライメントチャンバ208が設けられている。大気搬送室206内には清浄空気のダウンフローが形成されるようになっている。 On the wall portion opposite to the load lock chamber 205 mounting wall portion of the atmospheric transfer chamber 206, there are three carrier mounting ports 207 for mounting a carrier C containing a plurality of wafers W such as FOUP. An alignment chamber 208 for aligning the wafer W is provided on the side wall of the atmospheric transfer chamber 206. A downflow of clean air is formed in the atmospheric transfer chamber 206.
 真空搬送室201内には、2のウエハ搬送機構210が設けられている。一方のウエハ搬送機構210は、真空搬送室201の長辺の一方側に接続された酸化膜エッチング装置202、表面改質処理装置203、およびSiN膜エッチング装置204、ならびに一方のロードロック室205に対してウエハWの搬入出を行えるようになっている。他方のウエハ搬送機構210は、真空搬送室201の長辺の他方側に接続された酸化膜エッチング装置202、表面改質処理装置203、およびSiN膜エッチング装置204、ならびに他方のロードロック室205に対してウエハWの搬入出を行えるようになっている。 In the vacuum transfer chamber 201, two wafer transfer mechanisms 210 are provided. One wafer transfer mechanism 210 includes an oxide film etching apparatus 202, a surface modification processing apparatus 203, a SiN film etching apparatus 204, and one load lock chamber 205 connected to one side of the long side of the vacuum transfer chamber 201. On the other hand, the wafer W can be loaded and unloaded. The other wafer transfer mechanism 210 is connected to the oxide film etching device 202, the surface modification processing device 203, the SiN film etching device 204, and the other load lock chamber 205 connected to the other side of the long side of the vacuum transfer chamber 201. On the other hand, the wafer W can be loaded and unloaded.
 大気搬送室206内には、ウエハ搬送機構211が設けられている。搬送機構211は、キャリアC、ロードロック室205、アライメントチャンバ208に対してウエハWを搬送するようになっている。 In the atmospheric transfer chamber 206, a wafer transfer mechanism 211 is provided. The transfer mechanism 211 transfers the wafer W to the carrier C, the load lock chamber 205, and the alignment chamber 208.
 処理システム200は、また、制御部212を有している。制御部212は、典型的にはコンピュータからなり、処理システム200の各構成部を制御するCPUを有する主制御部と、入力装置(キーボード、マウス等)、出力装置(プリンタ等)、表示装置(ディスプレイ等)、記憶装置(記憶媒体)を有している。制御部212の主制御部は、例えば、記憶装置に内蔵された記憶媒体、または記憶装置にセットされた記憶媒体に記憶された処理レシピに基づいて、処理システム200に、所定の動作を実行させる。 The processing system 200 also has a control unit 212. The control unit 212 is typically a computer, and includes a main control unit having a CPU that controls each component of the processing system 200, an input device (keyboard, mouse, etc.), an output device (printer, etc.), and a display device ( Display) and a storage device (storage medium). The main control unit of the control unit 212 causes the processing system 200 to execute a predetermined operation based on, for example, a processing medium stored in a storage device or a processing recipe stored in the storage medium set in the storage device. .
 このような処理システム200では、図8に示す構造が形成されたウエハを複数枚キャリアC内に収納して処理システム200に搬送する。処理システム200においては、ウエハ搬送機構211により大気搬送室206に接続されたキャリアCからウエハWを取り出し、いずれかのロードロック室205のゲートバルブG2を開けてウエハWをそのロードロック室205に搬入する。ゲートバルブG2を閉じた後、ロードロック室205内を真空排気する。 In such a processing system 200, a plurality of wafers having the structure shown in FIG. 8 are stored in the carrier C and transferred to the processing system 200. In the processing system 200, the wafer W is taken out from the carrier C connected to the atmospheric transfer chamber 206 by the wafer transfer mechanism 211, and the gate valve G2 of any one of the load lock chambers 205 is opened to transfer the wafer W to the load lock chamber 205. Carry in. After the gate valve G2 is closed, the load lock chamber 205 is evacuated.
 そのロードロック室205が、所定の真空度になった時点でゲートバルブG1を開けて、ウエハ搬送機構210によりロードロック室205からウエハWを取り出す。そして、酸化膜エッチング装置202のゲートバルブGを開けて、ウエハWを酸化膜エッチング装置202に搬入し、SiO膜のエッチングを行う。SiO膜のエッチングをCOR処理により行う場合は、上述したようにAFSが生成されるので、これを昇華させるために、表面改質処理装置203または別個に設けた熱処理装置で加熱処理を行う。または、酸化膜エッチング装置202内でエッチングと加熱処理を繰り返し行って、その中でAFSの除去を行ってもよい。 When the load lock chamber 205 reaches a predetermined degree of vacuum, the gate valve G1 is opened, and the wafer W is taken out of the load lock chamber 205 by the wafer transfer mechanism 210. Then, the gate valve G of the oxide film etching apparatus 202 is opened, the wafer W is loaded into the oxide film etching apparatus 202, and the SiO 2 film is etched. When the etching of the SiO 2 film is performed by the COR process, AFS is generated as described above. Therefore, in order to sublimate it, the heat treatment is performed by the surface modification apparatus 203 or a heat treatment apparatus provided separately. Alternatively, etching and heat treatment may be repeatedly performed in the oxide film etching apparatus 202, and AFS may be removed therein.
 SiO膜のエッチングが終了した後、ウエハ搬送機構210によりウエハWを取り出し、表面改質処理装置203のゲートバルブGを開けて、ウエハWを表面改質処理装置203に搬入し、表面改質処理を行う。 After the etching of the SiO 2 film is completed, the wafer W is taken out by the wafer transfer mechanism 210, the gate valve G of the surface modification processing apparatus 203 is opened, and the wafer W is carried into the surface modification processing apparatus 203, and the surface modification is performed. Process.
 ウエハWの表面改質処理が終了した後、ウエハ搬送機構210によりウエハを取り出し、SiN膜エッチング装置204のゲートバルブGを開けて、ウエハWをSiN膜エッチング装置204に搬入し、SiN膜のエッチングを行う。 After the surface modification processing of the wafer W is completed, the wafer is taken out by the wafer transfer mechanism 210, the gate valve G of the SiN film etching apparatus 204 is opened, the wafer W is carried into the SiN film etching apparatus 204, and the SiN film is etched. I do.
 SiN膜のエッチングの後、必要に応じて、表面改質処理装置203または別個に設けた熱処理装置等により、エッチング残渣の除去を行う。 After the etching of the SiN film, the etching residue is removed by the surface modification processing apparatus 203 or a heat treatment apparatus provided separately as necessary.
 その後、ロードロック室205のゲートバルブG1を開けて、ウエハ搬送機構210によりSiN膜エッチング後のウエハWをロードロック室205に搬入し、ゲートバルブG1を閉じてロードロック室205内を大気圧に戻す。その後、ゲートバルブG2を開けて、ウエハ搬送機構211にてロードロック室205内のウエハWをキャリアCに戻す。 Thereafter, the gate valve G1 of the load lock chamber 205 is opened, the wafer W after the SiN film etching is carried into the load lock chamber 205 by the wafer transfer mechanism 210, the gate valve G1 is closed, and the inside of the load lock chamber 205 is brought to atmospheric pressure. return. Thereafter, the gate valve G2 is opened, and the wafer W in the load lock chamber 205 is returned to the carrier C by the wafer transfer mechanism 211.
 以上のような処理を、複数のウエハWについて同時並行的に行って、所定枚数のウエハWの処理が完了する。 The above processing is performed simultaneously on a plurality of wafers W to complete the processing of a predetermined number of wafers W.
 次に、酸化膜エッチング装置202および表面改質処理装置203の一例について説明する。なお、SiN膜エッチング装置204は、第1の実施形態のエッチング装置105と同じ構成であるから説明を省略する。 Next, an example of the oxide film etching apparatus 202 and the surface modification processing apparatus 203 will be described. Since the SiN film etching apparatus 204 has the same configuration as the etching apparatus 105 of the first embodiment, description thereof is omitted.
  [酸化膜エッチング装置]
 最初に、酸化膜エッチング装置202の一例について説明する。
 図12は酸化膜エッチング装置202の一例を示す断面図である。
 本例では、COR処理によりSiO膜をエッチングするCOR処理装置を例にとって説明する。この場合、装置の基本構成は、第1の実施形態におけるエッチング装置105と同じであるから、図4と同じものには同じ符号を付して説明を省略する。
[Oxide film etching equipment]
First, an example of the oxide film etching apparatus 202 will be described.
FIG. 12 is a cross-sectional view showing an example of the oxide film etching apparatus 202.
In this example, a COR processing apparatus that etches a SiO 2 film by COR processing will be described as an example. In this case, since the basic configuration of the apparatus is the same as that of the etching apparatus 105 in the first embodiment, the same components as those in FIG.
 酸化膜エッチング装置202においては、蓋部材155および本体157の上部壁157bにはシャワーヘッド156の空間159まで貫通してガス導入路161の他、ガス導入路162も形成されている。ガス導入路161には後述するガス供給機構143′のHFガス供給配管171が接続されている。また、ガス導入路162にはNHガス供給配管191が接続されている。 In the oxide film etching apparatus 202, a gas introduction path 162 is formed in addition to the gas introduction path 161 through the lid member 155 and the upper wall 157 b of the main body 157 to the space 159 of the shower head 156. An HF gas supply pipe 171 of a gas supply mechanism 143 ′, which will be described later, is connected to the gas introduction path 161. An NH 3 gas supply pipe 191 is connected to the gas introduction path 162.
 ガス供給機構143′は、HFガスを供給するHFガス供給源175および不活性ガスを供給する不活性ガス供給源176を有しており、これらにはそれぞれHFガス供給配管171および不活性ガス供給配管172の一端が接続されている。HFガス供給配管171および不活性ガス供給配管172には、流量制御器179が設けられている。HFガス供給配管171の他端は、ガス導入路161に接続されている。また、不活性ガス供給配管172の他端はHFガス供給配管171に接続されている。 The gas supply mechanism 143 ′ includes an HF gas supply source 175 for supplying HF gas and an inert gas supply source 176 for supplying inert gas, which include an HF gas supply pipe 171 and an inert gas supply, respectively. One end of the pipe 172 is connected. A flow rate controller 179 is provided in the HF gas supply pipe 171 and the inert gas supply pipe 172. The other end of the HF gas supply pipe 171 is connected to the gas introduction path 161. The other end of the inert gas supply pipe 172 is connected to the HF gas supply pipe 171.
 ガス供給機構143′はまた、NHガスを供給するNHガス供給源195および不活性ガスを供給する不活性ガス供給源196を有しており、これらにはそれぞれNHガス供給配管191および不活性ガス供給配管192の一端が接続されている。NHガス供給配管191および不活性ガス供給配管192には、流量制御器179と同様に構成された流量制御器199が設けられている。NHガス供給配管191の他端は、ガス導入路162に接続されている。また、不活性ガス供給配管192の他端はNHガス供給配管191に接続されている。 The gas supply mechanism 143 ′ also has an NH 3 gas supply source 195 for supplying NH 3 gas and an inert gas supply source 196 for supplying inert gas, which include NH 3 gas supply pipe 191 and One end of the inert gas supply pipe 192 is connected. The NH 3 gas supply pipe 191 and the inert gas supply pipe 192 are provided with a flow rate controller 199 configured similarly to the flow rate controller 179. The other end of the NH 3 gas supply pipe 191 is connected to the gas introduction path 162. The other end of the inert gas supply pipe 192 is connected to the NH 3 gas supply pipe 191.
 したがって、HFガスは、HFガス供給源175からHFガス供給配管171を経てシャワーヘッド156内に供給され、NHガスは、NHガス供給源195からNHガス供給配管191を経てシャワーヘッド156内に供給される。また、不活性ガスは、不活性ガス供給源176および196から不活性ガス供給配管172および192を経て、それぞれHFガス供給配管171およびNHガス供給配管191に至り、シャワーヘッド156に供給される。そして、これらのガスは、シャワーヘッド156のガス吐出孔162からチャンバー140内のウエハWに向けて吐出される。 Therefore, HF gas, from the HF gas supply source 175 via a HF gas supply pipe 171 is supplied into the shower head 156, NH 3 gas, the shower head 156 through the NH 3 gas supply line 191 from the NH 3 gas supply source 195 Supplied in. Further, the inert gas is supplied from the inert gas supply sources 176 and 196 to the HF gas supply pipe 171 and the NH 3 gas supply pipe 191 through the inert gas supply pipes 172 and 192, respectively, and is supplied to the shower head 156. . These gases are discharged from the gas discharge hole 162 of the shower head 156 toward the wafer W in the chamber 140.
 HFガスおよびNHガスが反応ガスとして用いられ、不活性ガスは希釈ガスおよびパージガスとして用いられる。HFガスおよびNHガス、またはこれらを不活性ガスと混合して供給することにより、所望の反応を生じさせることができる。 HF gas and NH 3 gas are used as reaction gas, and inert gas is used as dilution gas and purge gas. A desired reaction can be caused by supplying HF gas and NH 3 gas, or a mixture thereof with an inert gas.
 このような酸化膜エッチング装置202においては、例えば図8に示す構造が形成されたウエハWをチャンバー140内に搬入し、載置台142に載置する。そして、チャンバー140内の圧力を、好ましくは133~400Pa(1~3Torr)、処理温度を好ましくは10~130℃とする。また、HFガス流量、NHガス流量、および不活性ガス流量を、好ましくは、いずれも20~1000sccmとしてこれらのガスを供給し、HFガスおよびNHガスとSiOを反応させて、AFSを生成させる。そして、ウエハWを適宜の装置内で加熱することによりSiO膜を除去する。 In such an oxide film etching apparatus 202, for example, the wafer W having the structure shown in FIG. 8 is loaded into the chamber 140 and mounted on the mounting table 142. The pressure in the chamber 140 is preferably 133 to 400 Pa (1 to 3 Torr), and the processing temperature is preferably 10 to 130 ° C. The HF gas flow rate, NH 3 gas flow rate, and inert gas flow rate are preferably set to 20 to 1000 sccm, and these gases are supplied to react the HF gas, NH 3 gas, and SiO 2 to react with AFS. Generate. Then, the SiO 2 film is removed by heating the wafer W in an appropriate apparatus.
  [表面改質処理装置]
 次に、表面改質処理装置203の一例について説明する。
 図13は表面改質処理装置203の一例を示す断面図である。
 本例では、表面改質処理装置203として熱処理により膜中不純物や副生成物を除去する熱処理装置を例にとって説明する。
[Surface modification equipment]
Next, an example of the surface modification processing apparatus 203 will be described.
FIG. 13 is a cross-sectional view showing an example of the surface modification treatment apparatus 203.
In this example, a heat treatment apparatus that removes impurities and by-products in the film by heat treatment will be described as an example of the surface modification treatment apparatus 203.
 表面改質処理装置203は、図13に示すように、真空引き可能なチャンバー220と、その中でウエハWを載置する載置台223を有する。載置台223にはヒーター224が埋設されており、このヒーター224によりSiO膜のエッチング処理が施された後のウエハWを加熱して膜中に存在する不純物やウエハW表面に付着する副生成物を熱分解または揮発させて除去する。チャンバー220の側面には、真空搬送室201との間でウエハを搬送する搬入出口234が設けられており、この搬入出口234はゲートバルブGによって開閉可能となっている。チャンバー220の側壁上部にはガス供給路225が接続され、ガス供給路225は不活性ガス供給源230に接続されている。また、チャンバー220の底壁には排気路227が接続され、排気路227は真空ポンプ233に接続されている。ガス供給路225には流量調節弁231が設けられており、排気路227には圧力調整弁232が設けられていて、これら弁を調整することにより、チャンバー220内を所定圧力のNガス雰囲気にして熱処理が行われる。不活性ガスとしてはNガスやArガス等の希ガスを用いることができる。 As shown in FIG. 13, the surface modification processing apparatus 203 has a chamber 220 that can be evacuated and a mounting table 223 on which the wafer W is mounted. A heater 224 is embedded in the mounting table 223, and the wafer W after the etching process of the SiO 2 film is heated by the heater 224 to heat impurities existing in the film and by-products attached to the surface of the wafer W. Objects are removed by thermal decomposition or volatilization. A loading / unloading port 234 for transferring a wafer to / from the vacuum transfer chamber 201 is provided on the side surface of the chamber 220, and the loading / unloading port 234 can be opened and closed by a gate valve G. A gas supply path 225 is connected to the upper portion of the side wall of the chamber 220, and the gas supply path 225 is connected to an inert gas supply source 230. An exhaust path 227 is connected to the bottom wall of the chamber 220, and the exhaust path 227 is connected to the vacuum pump 233. The gas supply path 225 is provided with a flow rate adjusting valve 231, and the exhaust path 227 is provided with a pressure adjusting valve 232. By adjusting these valves, the inside of the chamber 220 is filled with an N 2 gas atmosphere at a predetermined pressure. Then, heat treatment is performed. As the inert gas, a rare gas such as N 2 gas or Ar gas can be used.
 このような表面改質処理装置203においては、SiO膜エッチングにより、例えば図10の(a)の構造となったウエハWをチャンバー220内に搬入し、載置台223に載置する。そして、チャンバー220内にNガス等の不活性ガスを導入して所定の減圧雰囲気にしつつ、ヒーター224によりウエハWを150~400℃、例えば250℃に加熱する。これにより、膜中の不純物やウエハWに付着しているNHやHF等の副生成物を熱分解または揮発させることができる。 In such a surface modification processing apparatus 203, for example, the wafer W having the structure of FIG. 10A is carried into the chamber 220 by the SiO 2 film etching and placed on the mounting table 223. Then, the wafer W is heated to 150 to 400 ° C., for example, 250 ° C. by the heater 224 while introducing an inert gas such as N 2 gas into the chamber 220 to make a predetermined reduced pressure atmosphere. Thereby, impurities in the film and by-products such as NH 4 and HF 2 adhering to the wafer W can be thermally decomposed or volatilized.
 なお、チャンバー220内にHO蒸気を導入して、好ましくは20~100℃、より好ましくは20~80℃で反応処理することにより、膜中の不純物やウエハWに付着している副生成物をHOガスと反応させて除去するようにしてもよい。 It should be noted that by introducing H 2 O vapor into the chamber 220 and performing a reaction treatment preferably at 20 to 100 ° C., more preferably at 20 to 80 ° C., impurities in the film and by-products attached to the wafer W can be obtained. The substance may be removed by reacting with H 2 O gas.
 なお、本例では、処理システム200として、クラスタータイプのものを用いて、SiO膜のエッチング、表面改質処理、およびSiN膜のエッチングをin-situで行う例を示したが、これら装置を単独で用いてex-situで行ってもよい。 In this example, a cluster type system is used as the processing system 200, and the SiO 2 film etching, the surface modification process, and the SiN film etching are performed in-situ. It may be used alone and performed ex-situ.
 また、上述したように、表面改質処理をウエット処理で行う場合は、表面改質処理装置の一例として、図14に示すものを用いることができる。この図に示すように、表面改質処理装置250は、液体Lを貯留して処理を行う液処理槽251を有している。液処理槽251に貯留された液体Lに、ウエハ保持部材252に保持された複数のウエハWが浸漬されるようになっている。ウエハ保持部材252は、複数のウエハ保持棒252aを有しており、これらウエハ保持棒252aにより複数のウエハWが保持される。ウエハ保持部材252は、搬送装置(図示せず)により上下動および水平動され、保持した複数のウエハWが搬送されるようになっている。 Further, as described above, when the surface modification treatment is performed by wet treatment, an example of the surface modification treatment apparatus shown in FIG. 14 can be used. As shown in this figure, the surface modification processing apparatus 250 has a liquid processing tank 251 for storing and processing the liquid L. A plurality of wafers W held by the wafer holding member 252 are immersed in the liquid L stored in the liquid processing tank 251. The wafer holding member 252 has a plurality of wafer holding bars 252a, and a plurality of wafers W are held by these wafer holding bars 252a. The wafer holding member 252 is moved up and down and horizontally by a transfer device (not shown) so that a plurality of held wafers W are transferred.
 液処理槽251内にはノズル253が設けられており、ノズル253には液供給配管254が接続されている。液供給配管254には液体供給機構255から所定の液体が供給可能となっている。 A nozzle 253 is provided in the liquid treatment tank 251, and a liquid supply pipe 254 is connected to the nozzle 253. A predetermined liquid can be supplied from the liquid supply mechanism 255 to the liquid supply pipe 254.
 液処理槽251の底部には排液配管256が接続されており、排液機構257により排液配管256を介して液処理槽251内の液体を排液するようになっている。 A drainage pipe 256 is connected to the bottom of the liquid treatment tank 251, and the liquid in the liquid treatment tank 251 is drained via the drainage pipe 256 by the drainage mechanism 257.
 表面改質処理として、液体のHO(純水)による処理を行う場合には、液体供給機構255から供給する液体として純水を用いる。また、表面改質処理として、ウエハ表面に界面活性剤を吸着させる工程と、HO(純水)によるウエット洗浄工程とを有する処理を行う場合には、液体供給機構255から供給する液体として純水および界面活性剤を用いる。そして、これらを選択的に供給できるようにするか、または、液処理層251を純水用と界面活性剤用の2種類準備する。 In the case where a treatment with liquid H 2 O (pure water) is performed as the surface modification treatment, pure water is used as the liquid supplied from the liquid supply mechanism 255. Further, as a surface modification process, when a process including a step of adsorbing a surfactant on the wafer surface and a wet cleaning process using H 2 O (pure water) is performed, the liquid supplied from the liquid supply mechanism 255 is used. Use pure water and surfactant. Then, these can be selectively supplied, or two types of liquid treatment layers 251 for pure water and a surfactant are prepared.
 このように構成される表面改質処理装置250においては、表面改質処理が液体のHO(純水)による処理の場合は、液処理槽251内に純水を供給し、貯留した状態で複数枚のウエハWを純水に浸漬することにより行われる。また、表面改質処理が、ウエハ表面に界面活性剤を吸着させる工程と、HO(純水)によるウエット洗浄工程とを有する処理の場合には、以下のように行われる。すなわち、最初に、液処理槽251内に界面活性剤を供給し、貯留した状態で、複数枚のウエハWを界面活性剤に浸漬し、その後、液処理槽251内に供給する液体を純水に切り替えて純水を貯留した状態で、複数枚のウエハWを純水に浸漬する。または、別の液処理槽251内に純水を供給し、貯留した状態で、複数枚のウエハWを純水に浸漬する。 In the surface modification treatment apparatus 250 configured as described above, when the surface modification treatment is a treatment with liquid H 2 O (pure water), pure water is supplied into the liquid treatment tank 251 and stored. This is performed by immersing a plurality of wafers W in pure water. In the case where the surface modification process is a process including a step of adsorbing a surfactant on the wafer surface and a wet cleaning step using H 2 O (pure water), the surface modification treatment is performed as follows. That is, first, a surfactant is supplied into the liquid processing tank 251 and stored, so that a plurality of wafers W are immersed in the surfactant, and then the liquid supplied into the liquid processing tank 251 is purified water. A plurality of wafers W are immersed in pure water in a state where the pure water is stored by switching to the above. Alternatively, a plurality of wafers W are immersed in pure water in a state where pure water is supplied and stored in another liquid processing tank 251.
 表面改質処理をウエット処理で行う場合の表面改質処理装置の他の例として、図15に示すものを用いることができる。この図に示すように、表面改質処理装置260は、チャンバー261と、スピンチャック262と、モータ263と、ノズル264と、液体供給機構265とを有している。スピンチャック262は、チャンバー261内でウエハWを回転可能に保持する、モータ263は、スピンチャック262を回転させる。ノズル264は、スピンチャック262に保持されたウエハWに液体を吐出する。液体供給機構265は、ノズル264に液体を供給する。液体供給機構265からノズル264へは、液供給配管266により液体が供給されるようになっている。液体供給機構265からは、所定の液体が供給可能となっている。 As another example of the surface modification treatment apparatus when the surface modification treatment is performed by wet treatment, the one shown in FIG. 15 can be used. As shown in this figure, the surface modification processing device 260 includes a chamber 261, a spin chuck 262, a motor 263, a nozzle 264, and a liquid supply mechanism 265. The spin chuck 262 rotatably holds the wafer W in the chamber 261. The motor 263 rotates the spin chuck 262. The nozzle 264 discharges liquid onto the wafer W held by the spin chuck 262. The liquid supply mechanism 265 supplies a liquid to the nozzle 264. Liquid is supplied from the liquid supply mechanism 265 to the nozzle 264 through a liquid supply pipe 266. A predetermined liquid can be supplied from the liquid supply mechanism 265.
 表面改質処理として、液体のHO(純水)による処理を行う場合には、液体供給機構265から供給する液体として純水を用いる。また、表面改質処理として、ウエハ表面に界面活性剤を吸着させる工程と、HO(純水)によるウエット洗浄工程とを有する処理を行う場合には、液体供給機構265から供給する液体として純水および界面活性剤を用い、これらを選択的に供給できるようにする。 As the surface modification treatment, when performing the processing by H 2 O (deionized water) of the liquid, pure water is used as the liquid supplied from the liquid supply mechanism 265. In addition, as a surface modification process, when a process including a step of adsorbing a surfactant on the wafer surface and a wet cleaning step using H 2 O (pure water) is performed, the liquid supplied from the liquid supply mechanism 265 is used. Using pure water and a surfactant, these can be selectively supplied.
 チャンバー261内には、スピンチャック262に保持されたウエハWを覆うためのカップ267が設けられている。カップ267の底部には、排気および排液のための排気・排液管268が、チャンバー261の下方へ延びるように設けられている。チャンバー261の側壁には、ウエハWを搬入出するための搬入出口269が設けられている。 A cup 267 for covering the wafer W held by the spin chuck 262 is provided in the chamber 261. An exhaust / drain pipe 268 for exhaust and drainage is provided at the bottom of the cup 267 so as to extend below the chamber 261. On the side wall of the chamber 261, a loading / unloading port 269 for loading and unloading the wafer W is provided.
 このように構成される表面改質処理装置260においては、一枚のウエハWを搬送装置(図示せず)によりチャンバー261内に搬入し、スピンチャック262に装着する。この状態で、モータ263によりスピンチャック262とともにウエハを回転させながら、液体供給機構265から液供給配管266を介してノズル264から液体を吐出させ、液体をウエハWの表面全面に供給する。 In the surface modification processing apparatus 260 configured as described above, a single wafer W is loaded into the chamber 261 by a transfer apparatus (not shown) and mounted on the spin chuck 262. In this state, while the wafer is rotated together with the spin chuck 262 by the motor 263, the liquid is discharged from the nozzle 264 from the liquid supply mechanism 265 through the liquid supply pipe 266 to supply the liquid to the entire surface of the wafer W.
 表面改質処理として、液体のHO(純水)による処理を行う場合には、液体供給機構265から液供給配管266およびノズル264を介して回転しているウエハW上に純水を供給し、ウエハWの全面に純水を広げることにより行う。 When the surface modification process is performed using liquid H 2 O (pure water), pure water is supplied from the liquid supply mechanism 265 to the rotating wafer W via the liquid supply pipe 266 and the nozzle 264. Then, pure water is spread over the entire surface of the wafer W.
 表面改質処理として、ウエハ表面に界面活性剤を吸着させる工程と、HO(純水)によるウエット洗浄工程とを有する処理を行う場合には、以下のように行われる。すなわち、最初に、液体供給機構265から液供給配管266およびノズル264を介して回転しているウエハW上に界面活性剤を供給し、ウエハWの全面に界面活性剤を広げて吸着させる。次いで、液体供給機構265から供給する液体を純水に切り替えて、ウエハ上に純水を供給してウエット洗浄を行う。 When the surface modification treatment includes a step of adsorbing a surfactant on the wafer surface and a wet cleaning step using H 2 O (pure water), the surface modification treatment is performed as follows. That is, first, a surfactant is supplied from the liquid supply mechanism 265 to the rotating wafer W via the liquid supply pipe 266 and the nozzle 264, and the surfactant is spread and adsorbed on the entire surface of the wafer W. Next, the liquid supplied from the liquid supply mechanism 265 is switched to pure water, and pure water is supplied onto the wafer to perform wet cleaning.
 <実験例>
 次に、本発明の実験例について説明する。
<Experimental example>
Next, experimental examples of the present invention will be described.
  (実験例1)
 ここでは、SiN膜としてジクロロシラン(SiCl)ガスおよびNHガスを用いたCVDにより成膜したSiN膜、および熱酸化膜(SiO膜)、ポリシリコン膜について、エッチングを行った。エッチングは、エッチングガスとしてHFガスを用い、温度および圧力を変化させて行った。エッチングの際の条件は、HFガスの流量:1500sccm、圧力:30Torr(4000Pa)および50Torr(6665Pa)、温度:50~150℃とした。
(Experimental example 1)
Here, the SiN film, the thermal oxide film (SiO 2 film), and the polysilicon film formed by CVD using dichlorosilane (Si 2 H 2 Cl 2 ) gas and NH 3 gas as the SiN film are etched. It was. Etching was performed using HF gas as an etching gas and changing the temperature and pressure. The etching conditions were as follows: HF gas flow rate: 1500 sccm, pressure: 30 Torr (4000 Pa) and 50 Torr (6665 Pa), temperature: 50 to 150 ° C.
 図16は、温度70℃のときの、圧力と、各膜のエッチング量(nm)ならびにSiN膜の熱酸化膜に対する選択比およびSiN膜のポリシリコン膜に対する選択比との関係を示す図である。また、図17は、圧力50Torrのときの、温度と、各膜のエッチング量(nm)ならびにSiN膜の熱酸化膜およびポリシリコン膜に対する選択比との関係を示す図である。 FIG. 16 is a diagram showing the relationship between the pressure, the etching amount (nm) of each film, the selection ratio of the SiN film to the thermal oxide film, and the selection ratio of the SiN film to the polysilicon film at a temperature of 70 ° C. . FIG. 17 is a diagram showing the relationship between the temperature, the etching amount (nm) of each film, and the selectivity of the SiN film to the thermal oxide film and the polysilicon film when the pressure is 50 Torr.
 図16に示すように、圧力が高いほうがSiN膜のエッチング量が増加し、SiN膜の熱酸化膜に対する選択比およびSiN膜のポリシリコン膜に対する選択比が高くなることがわかる。また、図17に示すように、温度が50~120℃の範囲が選択比の許容範囲であり、特に70℃においてSiN膜のエッチング量が多くなり、SiN膜の熱酸化膜に対する選択比およびSiN膜のポリシリコン膜に対する選択比が高くなることがわかる。圧力50Torr、温度70℃において、SiN膜の熱酸化膜に対する選択比が15以上、SiN膜のポリシリコン膜に対する選択比が100以上と高い値が得られた。 As shown in FIG. 16, it can be seen that the higher the pressure, the higher the etching amount of the SiN film, and the higher the selectivity ratio of the SiN film to the thermal oxide film and the selectivity of the SiN film to the polysilicon film. In addition, as shown in FIG. 17, the temperature range of 50 to 120 ° C. is an allowable range of the selection ratio. In particular, the etching amount of the SiN film increases at 70 ° C., and the selection ratio of the SiN film to the thermal oxide film and the SiN film It can be seen that the selectivity of the film to the polysilicon film is high. At a pressure of 50 Torr and a temperature of 70 ° C., the SiN film has a high selectivity ratio of 15 or more and the SiN film has a selectivity ratio of 100 or more.
 なお、図16および図17には示していないが、SiGe膜についてはポリシリコン膜と同様の傾向を示し、圧力50Torr、温度70℃において、SiN膜のSiGe膜の選択比についても100以上の高い値が得られた。 Although not shown in FIGS. 16 and 17, the SiGe film shows the same tendency as the polysilicon film, and the selectivity of the SiGe film to the SiN film is 100 or more at a pressure of 50 Torr and a temperature of 70 ° C. A value was obtained.
  (実験例2)
 ここでは、CVDによるSiO膜を形成したウエハについて、最初にHFガスおよびNHガスを用いて、圧力:333Pa(2.5Torr)、温度:100℃の条件でSiO膜のCOR処理を行った。次いで、250℃の加熱処理によりAFSを除去してSiO膜エッチングを行った。その後、このウエハについて、そのままSiN膜エッチング条件の処理(HFガス処理+加熱処理)を行ったサンプル(サンプル1)を作成した。また、純水処理を行った後、SiN膜エッチング条件の処理を行ったサンプル(サンプル2)、界面活性剤を吸着させる工程と、HO(純水)によるウエット洗浄工程とを行った後、SiN膜エッチング条件の処理を行ったサンプル(サンプル3)も作成した。これらサンプルについて、SiO膜の表面状態を調査した。
(Experimental example 2)
Here, the wafer with the SiO 2 film formed by CVD is first subjected to COR treatment of the SiO 2 film using HF gas and NH 3 gas under the conditions of pressure: 333 Pa (2.5 Torr) and temperature: 100 ° C. It was. Next, AFS was removed by heat treatment at 250 ° C., and SiO 2 film etching was performed. Thereafter, a sample (sample 1) was prepared by performing the SiN film etching condition treatment (HF gas treatment + heat treatment) on the wafer as it was. In addition, after performing pure water treatment, after performing a SiN film etching condition treatment (sample 2), a step of adsorbing a surfactant, and a wet cleaning step using H 2 O (pure water) A sample (sample 3) subjected to SiN film etching conditions was also prepared. For these samples, the surface state of the SiO 2 film was investigated.
 なお、SiN膜エッチング条件の処理は、HFガス流量:2000sccm、圧力:1333~1995Pa(10~15Torr)、温度:50~75℃の条件でガス処理した後、250℃の熱処理を行うものとした。 The SiN film etching conditions are as follows: gas treatment is performed under the conditions of HF gas flow rate: 2000 sccm, pressure: 1333 to 1995 Pa (10 to 15 Torr), temperature: 50 to 75 ° C., and then heat treatment at 250 ° C. .
 その結果サンプル1では、SiO膜表面にピッティングが多く発生し、表面ラフネスも悪かったが、サンプル2では、SiO膜表面のピッティングの数が20%程度減少し、表面ラフネスの改善もみられた。またサンプル3ではSiO膜表面のピッティングが見られず、表面ラフネスもさらに改善された。 As a result, in sample 1, a lot of pitting occurred on the SiO 2 film surface and the surface roughness was poor, but in sample 2, the number of pitting on the SiO 2 film surface decreased by about 20%, and the surface roughness was also improved. It was. In sample 3, no pitting was observed on the SiO 2 film surface, and the surface roughness was further improved.
 <他の適用>
 以上、実施形態について説明したが、今回開示された実施形態は、全ての点で例示であって制限的なものではないと考えられるべきである。上記の実施形態は、添付の特許請求の範囲およびその主旨を逸脱することなく、様々な形態で省略、置換、変更されてもよい。また、上記種々の実施形態は、適宜組み合わせて実施してもよい。
<Other applications>
Although the embodiment has been described above, the embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The above embodiments may be omitted, replaced, and modified in various forms without departing from the scope and spirit of the appended claims. The various embodiments described above may be implemented in combination as appropriate.
 例えば、上記実施形態の構造例はあくまで例示であり、SiN膜が、SiO、Si、SiGeと共存している構造であれば適用可能である。また、上記処理システムや個別的な装置の構造についても例示に過ぎず、種々の構成のシステムや装置により本開示のエッチング方法を実施することができる。 For example, the structural example of the above embodiment is merely an example, and any structure can be applied as long as the SiN film coexists with SiO 2 , Si, and SiGe. In addition, the structure of the processing system and the individual apparatuses are merely examples, and the etching method of the present disclosure can be performed by systems and apparatuses having various configurations.
 11,21,31;シリコン基板、12,22a,22b,22c,32;Si膜、13,23,33;SiGe膜、14,16,25,35;SiO膜、15,26,34;SiN膜、100,200;処理システム、105;エッチング装置、202;酸化膜エッチング装置、203,250,260;表面改質処理装置、204;SiN膜エッチング装置、W;ウエハ 11, 21, 31; silicon substrate, 12, 22a, 22b, 22c, 32; Si film, 13, 23, 33; SiGe film, 14, 16, 25, 35; SiO 2 film, 15, 26, 34; SiN Film, 100, 200; processing system, 105; etching apparatus, 202; oxide film etching apparatus, 203, 250, 260; surface modification processing apparatus, 204; SiN film etching apparatus, W; wafer

Claims (22)

  1.  窒化シリコン膜、酸化シリコン膜、シリコンおよびシリコンゲルマニウムを有する被処理基板をチャンバー内に配置する工程と、
     前記チャンバー内の圧力を1333Pa以上にする工程と、
     前記チャンバー内にフッ化水素ガスを供給し、前記窒化シリコン膜を、前記酸化シリコン膜、シリコンおよびシリコンゲルマニウムに対して選択的にエッチングする工程と、
    を有する、エッチング方法。
    Placing a substrate to be processed having a silicon nitride film, a silicon oxide film, silicon and silicon germanium in the chamber;
    Setting the pressure in the chamber to 1333 Pa or higher;
    Supplying hydrogen fluoride gas into the chamber, and selectively etching the silicon nitride film with respect to the silicon oxide film, silicon, and silicon germanium;
    An etching method comprising:
  2.  前記チャンバー内の圧力を1333~11997Paの範囲にする、請求項1に記載のエッチング方法。 The etching method according to claim 1, wherein the pressure in the chamber is in the range of 1333 to 11997 Pa.
  3.  前記チャンバー内の圧力を1333~5332Paの範囲にする、請求項2に記載のエッチング方法。 The etching method according to claim 2, wherein the pressure in the chamber is in the range of 1333 to 5332 Pa.
  4.  前記被処理基板の温度を10~120℃とする、請求項1に記載のエッチング方法。 The etching method according to claim 1, wherein the temperature of the substrate to be processed is 10 to 120 ° C.
  5.  前記被処理基板の温度を30~80℃とする、請求項4に記載のエッチング方法。 The etching method according to claim 4, wherein the temperature of the substrate to be processed is 30 to 80 ° C.
  6.  前記窒化シリコン膜の前記酸化シリコン膜に対する選択比が5以上である、請求項1に記載のエッチング方法。 The etching method according to claim 1, wherein a selectivity ratio of the silicon nitride film to the silicon oxide film is 5 or more.
  7.  前記窒化シリコン膜の前記酸化シリコン膜に対する選択比が15以上である、請求項6に記載のエッチング方法。 The etching method according to claim 6, wherein a selection ratio of the silicon nitride film to the silicon oxide film is 15 or more.
  8.  前記窒化シリコン膜の前記シリコンおよびシリコンゲルマニウムに対する選択比が50以上である、請求項1に記載のエッチング方法。 The etching method according to claim 1, wherein a selection ratio of the silicon nitride film to the silicon and silicon germanium is 50 or more.
  9.  前記窒化シリコン膜の前記シリコンおよびシリコンゲルマニウムに対する選択比が100以上である、請求項8に記載のエッチング方法。 The etching method according to claim 8, wherein a selection ratio of the silicon nitride film to the silicon and silicon germanium is 100 or more.
  10.  窒化シリコン膜および酸化シリコン膜を有する被処理基板について、前記窒化シリコン膜を選択的にエッチングするエッチング方法であって、
     前記被処理基板に対し、膜中の不純物を除去する表面改質処理を行う工程と、
     次いで、表面改質処理後の被処理基板を1333Pa以上の圧力下に保持し、前記被処理基板にHFガスを供給して前記窒化シリコン膜を選択的にエッチングする工程と、
    を有する、エッチング方法。
    An etching method for selectively etching the silicon nitride film for a substrate to be processed having a silicon nitride film and a silicon oxide film,
    Performing a surface modification process to remove impurities in the film on the substrate to be processed;
    Next, holding the substrate to be processed after the surface modification treatment under a pressure of 1333 Pa or more, supplying HF gas to the substrate to be processed, and selectively etching the silicon nitride film;
    An etching method comprising:
  11.  前記表面改質処理に先立って、前記酸化シリコン膜をエッチングする、請求項10に記載のエッチング方法。 The etching method according to claim 10, wherein the silicon oxide film is etched prior to the surface modification treatment.
  12.  前記被処理基板は、さらに、シリコンおよびシリコンゲルマニウムを有し、前記窒化シリコン膜を、前記シリコンおよび前記シリコンゲルマニウムに対して選択的にエッチングする、請求項10に記載のエッチング方法。 11. The etching method according to claim 10, wherein the substrate to be processed further includes silicon and silicon germanium, and the silicon nitride film is selectively etched with respect to the silicon and the silicon germanium.
  13.  前記窒化シリコン膜のエッチングの際の圧力を1333~11997Paの範囲とする、請求項10に記載のエッチング方法。 The etching method according to claim 10, wherein the pressure at the time of etching the silicon nitride film is in the range of 1333 to 11997 Pa.
  14.  前記窒化シリコン膜のエッチングの際の圧力を1333~5332Paの範囲とする、請求項13に記載のエッチング方法。 The etching method according to claim 13, wherein the pressure at the time of etching the silicon nitride film is in the range of 1333 to 5332 Pa.
  15.  前記窒化シリコン膜のエッチングの際の被処理基板の温度を10~120℃とする、請求項10に記載のエッチング方法。 The etching method according to claim 10, wherein the temperature of the substrate to be processed at the time of etching the silicon nitride film is set to 10 to 120 ° C.
  16.  前記窒化シリコン膜のエッチングの際の被処理基板の温度を30~80℃とする、請求項15に記載のエッチング方法。 The etching method according to claim 15, wherein the temperature of the substrate to be processed at the time of etching the silicon nitride film is set to 30 to 80 ° C.
  17.  前記表面改質処理は、不活性雰囲気で150~400℃の範囲の熱処理により行われる、請求項10に記載のエッチング方法。 The etching method according to claim 10, wherein the surface modification treatment is performed by a heat treatment in a range of 150 to 400 ° C in an inert atmosphere.
  18.  前記表面改質処理は、HOを用いた20~100℃の範囲の反応処理により行われる、請求項10に記載のエッチング方法。 The etching method according to claim 10, wherein the surface modification treatment is performed by a reaction treatment in a range of 20 to 100 ° C using H 2 O.
  19.  前記表面改質処理は、被処理基板の表面に界面活性剤を吸着させる工程と、HOによるウエット洗浄工程とを有する、請求項10に記載のエッチング方法。 The etching method according to claim 10, wherein the surface modification treatment includes a step of adsorbing a surfactant on the surface of a substrate to be processed and a wet cleaning step using H 2 O.
  20.  窒化シリコン膜、酸化シリコン膜、シリコンおよびシリコンゲルマニウムを有する被処理基板のエッチング方法であって、
     最初に、酸化シリコン膜をエッチングする工程と、
     次いで、膜中の不純物および被処理基板表面の副生成物を除去する表面改質処理を行う工程と、
     次いで、表面改質処理後の被処理基板を1333Pa以上の圧力下に保持し、前記被処理基板にHFガスを供給して前記窒化シリコン膜を選択的にエッチングする工程と、
    を有する、エッチング方法。
    A method for etching a substrate to be processed having a silicon nitride film, a silicon oxide film, silicon and silicon germanium,
    First, etching the silicon oxide film,
    Next, a step of performing surface modification treatment to remove impurities in the film and by-products on the surface of the substrate to be processed;
    Next, holding the substrate to be processed after the surface modification treatment under a pressure of 1333 Pa or more, supplying HF gas to the substrate to be processed, and selectively etching the silicon nitride film;
    An etching method comprising:
  21.  前記酸化シリコン膜のエッチングは、HFガスおよびNHガスを用いて行われる、請求項20に記載のエッチング方法。 21. The etching method according to claim 20, wherein the etching of the silicon oxide film is performed using HF gas and NH 3 gas.
  22.  前記酸化シリコン膜のエッチングは、ラジカル処理により行われる、請求項20に記載のエッチング方法。 21. The etching method according to claim 20, wherein the etching of the silicon oxide film is performed by radical treatment.
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