WO2018214470A1 - 电流均衡电路、阵列电路及多相变换器 - Google Patents

电流均衡电路、阵列电路及多相变换器 Download PDF

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Publication number
WO2018214470A1
WO2018214470A1 PCT/CN2017/115337 CN2017115337W WO2018214470A1 WO 2018214470 A1 WO2018214470 A1 WO 2018214470A1 CN 2017115337 W CN2017115337 W CN 2017115337W WO 2018214470 A1 WO2018214470 A1 WO 2018214470A1
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circuit
sub
input end
input
output end
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PCT/CN2017/115337
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English (en)
French (fr)
Inventor
黄冬其
董少青
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华为技术有限公司
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Priority to EP17911385.7A priority Critical patent/EP3641119A4/en
Publication of WO2018214470A1 publication Critical patent/WO2018214470A1/zh
Priority to US16/692,381 priority patent/US11095224B2/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter

Definitions

  • the present application relates to the field of electronic technologies, and in particular, to a current balancing circuit, an array circuit, and a multi-phase converter. .
  • DC-DC converters With the rapid development of electronic technology, Direct Current-Direct Current (DC-DC) converters have been widely used in electronic equipment power supply systems, and the saturation current of chip inductors in DC-DC converters The size determines the rated load capacity of the DC-DC converter.
  • the multi-photo inductor is arranged in parallel to increase the rated load capacity of the DC-DC converter.
  • the multi-photo inductor has a current imbalance between the phases. problem.
  • the input current of each phase inductor is adjusted according to the sampling current of each phase inductor and the average sampling current of each phase inductor, thereby achieving current equalization of each phase inductor.
  • the 4-phase inductors are A, B, C, and D, respectively.
  • the sampling current of A is a
  • the sampling current of B is b
  • the sampling current of C is c
  • the sampling current of D is d, 4.
  • the average sampling current of the phase inductor is (a+b+c+d)/4.
  • the input current of each phase inductor is adjusted to realize the current of each phase inductor. balanced.
  • the present application provides a current balancing circuit, an array circuit, and a multi-phase converter to solve the technical problem of high circuit complexity in the prior art.
  • the present application provides a current balancing circuit, which may include:
  • a first inductor a first resistor, an output end of the first inductor is connected to an input end of the first resistor, an output end of the first resistor is grounded, and an input end of the first resistor is connected to the first input end of the error detecting sub-circuit;
  • the output ends of the second inductor, the second resistor and the second inductor are respectively connected to the output end of the first inductor and the input end of the second resistor, the output end of the second resistor is grounded, the input end of the second resistor and the error detecting sub-circuit
  • the second input is connected;
  • the error detecting sub-circuit is configured to amplify a difference between a voltage of the first input end of the error detecting sub-circuit and a voltage of the second input end;
  • the first error adjustment sub-circuit includes two input ends, and the two input ends are respectively configured to receive a preset input signal and a voltage signal input by the first output end of the error detecting sub-circuit, and the first error adjusting sub-circuit is configured according to the preset The input signal and the voltage signal input by the first input end of the error detecting sub-circuit adjust the input current of the first inductor;
  • the second error adjustment sub-circuit includes two input ends, the two input ends respectively for receiving the preset input signal and the voltage signal input by the second output end of the error detecting sub-circuit, and the second error adjusting sub-circuit is configured according to the preset The input signal and the voltage signal input from the second input of the error detection sub-circuit adjust the input current of the second inductor.
  • the current equalization circuit provided by the present application directly connects the input end of the first resistor corresponding to the first inductor to be equalized and the input end of the second resistor corresponding to the second inductor to the input end of the error detecting sub-circuit, thus detecting the error
  • the sub-circuit can directly detect the difference between the voltage of the first input end of the error detecting sub-circuit and the voltage of the second input end, thereby adjusting the input current of the first inductor through the first error adjusting sub-circuit, and adjusting by the second error adjusting sub-circuit
  • the input current of the second inductor is used to balance the current of the first inductor and the current of the second inductor, thereby reducing the complexity of the circuit.
  • the error detection sub-circuit may include: a transimpedance operational amplifier, a third resistor, and a fourth resistor.
  • the first input end of the transimpedance operational amplifier is connected to the input end of the first resistor
  • the second input end of the transimpedance operational amplifier is connected to the input end of the second resistor
  • the first output end of the transimpedance operational amplifier and the third The output ends of the resistors are connected to the first input end of the first error adjustment sub-circuit;
  • the second output end of the transimpedance operational amplifier and the output end of the fourth resistor are both connected to the first input end of the second error adjustment sub-circuit,
  • a preset voltage signal is input to both the input end of the third resistor and the input end of the fourth resistor.
  • the first error adjustment sub-circuit may include: a first pulse width modulation PWM comparator, a first complex position bit RS flip-flop, and a first power level adjustment sub-circuit.
  • the first input end of the first PWM comparator is connected to the first output end of the error detecting sub-circuit, and the second input end of the first PWM comparator inputs a preset input signal, and the output end of the first PWM comparator a first input end of the RS flip-flop is connected, and a second input end of the first RS flip-flop inputs a preset square wave signal, the first output end of the first RS flip-flop and the first input of the first power stage adjustment sub-circuit
  • the second output end of the first RS flip-flop is connected to the second input end of the first power stage adjusting sub-circuit, and the output end of the first power level adjusting sub-circuit is connected to the input end of the first inductor;
  • the first power stage adjustment sub-circuit is configured to adjust an input current of the first inductor according to the first output end signal of the first RS flip-flop and the second output end signal of the first RS flip-flop.
  • the second error adjustment sub-circuit may include: a second PWM comparator, a second RS flip-flop, and a second power stage adjustment sub-circuit.
  • the first input end of the second PWM comparator is connected to the first output end of the error detecting sub-circuit, the second input end of the second PWM comparator inputs a preset input signal, and the output end of the second PWM comparator is The first input end of the second RS flip-flop is connected, the second input end of the second RS flip-flop inputs a preset square wave signal, and the first output end of the second RS flip-flop and the first input of the second power stage adjustment sub-circuit.
  • the second output end of the first RS flip-flop is connected to the second input end of the second power stage adjusting sub-circuit, and the output end of the second power stage adjusting sub-circuit is connected to the input end of the second inductor;
  • the second power stage adjustment sub-circuit is configured to adjust an input current of the second inductor according to the first output signal of the second RS flip-flop and the second output signal of the second RS flip-flop.
  • the first power stage adjustment sub-circuit may include: a first driving sub-circuit, a second driving sub-circuit, a first MOS transistor, and a second MOS transistor;
  • the input end of the first driving sub-circuit is connected to the first output end of the first RS flip-flop, the output end of the first driving sub-circuit is connected to the gate of the first MOS tube, and the input end of the second driving sub-circuit is a second output end of the first RS flip-flop is connected, an output end of the second driving sub-circuit is connected to a gate of the second MOS transistor, a drain of the first MOS transistor and a source of the second MOS transistor are both connected to the first inductor
  • the input terminal is connected, the source of the first MOS transistor is grounded, and the drain of the second MOS transistor is connected to the first power source.
  • the second power stage adjustment sub-circuit may include: a third driving sub-circuit, a fourth driving sub-circuit, a third MOS tube, and a fourth MOS tube.
  • the input end of the third driving sub-circuit is connected to the first output end of the second RS flip-flop, the output end of the third driving sub-circuit is connected to the gate of the third MOS tube, and the input end of the fourth driving sub-circuit is The second output end of the second RS flip-flop is connected, the output end of the fourth driving sub-circuit is connected to the gate of the fourth MOS transistor, the drain of the third MOS transistor and the source of the fourth MOS transistor are both connected to the second inductor The input terminal is connected, the source of the third MOS transistor is grounded, and the drain of the fourth MOS transistor is connected to the second power source.
  • the current balancing circuit may further include: a first current detecting sub-circuit and a second current detecting sub-circuit;
  • the input end of the first current detecting sub-circuit is connected to the output end of the first inductor, and the output end of the first current detecting sub-circuit is connected to the input end of the first resistor; the first current detecting sub-circuit is configured to detect the first inductor Sampling current and scaling the sampling current of the first inductor;
  • An input end of the second current detecting sub-circuit is connected to an output end of the second inductor, and an output end of the second current detecting sub-circuit is respectively connected to an output end of the first current detecting sub-circuit and an input end of the second resistor; the second current The detecting sub-circuit is configured to detect a sampling current of the second inductor and perform scaling processing on the sampling current of the second inductor.
  • the error detection sub-circuit may further include: a voltage adjustment sub-circuit and an output voltage feedback sub-circuit.
  • the output end of the voltage adjusting sub-circuit is respectively connected to the input end of the third resistor and the input end of the fourth resistor, and the first input end of the voltage adjusting sub-circuit is connected with the first output end of the output voltage feedback sub-circuit, and the voltage is adjusted.
  • the second input end of the sub-circuit inputs a reference voltage signal, the second output end of the output voltage feedback sub-circuit is grounded, the third output end of the output voltage feedback sub-circuit is grounded, and the input end of the output voltage feedback sub-circuit is respectively associated with the first current detection
  • the output of the sub-circuit is connected to the output of the second current detecting sub-circuit;
  • the input end of the voltage feedback sub-circuit is configured to receive a current signal of the first inductor and a current signal of the second inductor, and the voltage feedback sub-circuit is configured to convert the current signal of the first inductor and the current signal of the second inductor into a voltage signal, and Performing a voltage division process on the converted voltage signal;
  • the input end of the voltage adjustment sub-circuit is configured to receive the voltage signal after the voltage feedback sub-circuit is divided, and adjust the voltage signal after the voltage feedback sub-circuit is divided according to the reference voltage signal, so that the output end of the voltage adjustment sub-circuit
  • the input end of the third resistor and the input end of the fourth resistor input a preset voltage signal.
  • the voltage adjustment sub-circuit may include: an error amplifier, a first impedance network, and a second impedance network.
  • the first input end of the error amplifier is respectively connected to the output end of the first impedance network and the input end of the second impedance network, and the second input end of the error amplifier inputs the reference voltage signal, the output of the error amplifier and the second impedance network. Both are connected to the input end of the third resistor and the input end of the fourth resistor, and the input end of the first impedance network is connected to the first output end of the output voltage feedback sub-circuit.
  • the output voltage feedback sub-circuit may include: a fifth resistor, a sixth resistor, and a capacitor.
  • the input end of the fifth resistor and the input end of the capacitor are both connected to the output end of the first current detecting sub-circuit, and the input end of the fifth resistor and the input end of the capacitor are both connected to the output end of the second current detecting sub-circuit
  • the output end of the fifth resistor is respectively connected to the input end of the sixth resistor and the input end of the voltage adjusting sub-circuit, the output end of the sixth resistor is grounded, and the output end of the capacitor is grounded.
  • the present application provides a current balanced array circuit, which may include at least two current equalization circuit units, and the first current equalization circuit unit and the second current equalization circuit unit are at least two current equalization circuits. Any two adjacent current equalization circuit units in the circuit unit, wherein the first output end of the error detecting sub-circuit in the first current equalization electronic unit and the second one of the error detecting sub-circuit in the second current equalization electronic unit The two output terminals are connected, wherein any current equalization circuit unit comprises:
  • a first inductor a first resistor, an output end of the first inductor is connected to an input end of the first resistor, an output end of the first resistor is grounded, and an input end of the first resistor is connected to the first input end of the error detecting sub-circuit;
  • the output ends of the second inductor, the second resistor and the second inductor are respectively connected to the output end of the first inductor and the input end of the second resistor, the output end of the second resistor is grounded, the input end of the second resistor and the error detecting sub-circuit
  • the second input is connected;
  • the error detecting sub-circuit is configured to amplify a difference between a voltage of the first input end of the error detecting sub-circuit and a voltage of the second input end;
  • the first error adjustment sub-circuit includes two input ends, and the two input ends are respectively configured to receive a preset input signal and a voltage signal input by the first output end of the error detecting sub-circuit, and the first error adjusting sub-circuit is configured according to the preset The input signal and the voltage signal input by the first input end of the error detecting sub-circuit adjust the input current of the first inductor;
  • the second error adjustment sub-circuit includes two input ends, the two input ends respectively for receiving the preset input signal and the voltage signal input by the second output end of the error detecting sub-circuit, and the second error adjusting sub-circuit is configured according to the preset The input signal and the voltage signal input from the second input of the error detection sub-circuit adjust the input current of the second inductor.
  • the current-balanced array circuit provided by the present application may include at least two current equalization circuit units by inputting a first resistance corresponding to the first inductance to be equalized in any current equalization circuit unit
  • the input end of the second resistor corresponding to the second inductor is directly connected to the input end of the error detecting sub-circuit, so that the error detecting sub-circuit can directly detect the difference between the voltage of the first input end of the error detecting sub-circuit and the voltage of the second input end Therefore, the input current of the first inductor is adjusted by the first error adjustment sub-circuit, and the input current of the second inductor is adjusted by the second error adjustment sub-circuit to achieve equalization of the current of the first inductor and the current of the second inductor, thereby Reduced circuit complexity.
  • the error detection sub-circuit may include:
  • transimpedance operational amplifier a transimpedance operational amplifier, a third resistor, and a fourth resistor
  • the first input end of the transimpedance operational amplifier is connected to the input end of the first resistor
  • the second input end of the transimpedance operational amplifier is connected to the input end of the second resistor
  • the first output end of the transimpedance operational amplifier and the third The output ends of the resistors are connected to the first input end of the first error adjustment sub-circuit;
  • the second output end of the transimpedance operational amplifier and the output end of the fourth resistor are both connected to the first input end of the second error adjustment sub-circuit,
  • a preset voltage signal is input to both the input end of the third resistor and the input end of the fourth resistor.
  • the first error adjustment sub-circuit may include:
  • the first input end of the first PWM comparator is connected to the first output end of the error detecting sub-circuit, and the second input end of the first PWM comparator inputs a preset input signal, and the output end of the first PWM comparator a first input end of the RS flip-flop is connected, and a second input end of the first RS flip-flop inputs a preset square wave signal, the first output end of the first RS flip-flop and the first input of the first power stage adjustment sub-circuit
  • the second output end of the first RS flip-flop is connected to the second input end of the first power stage adjusting sub-circuit, and the output end of the first power level adjusting sub-circuit is connected to the input end of the first inductor;
  • the first power stage adjustment sub-circuit is configured to adjust an input current of the first inductor according to the first output end signal of the first RS flip-flop and the second output end signal of the first RS flip-flop.
  • the second error adjustment sub-circuit may include:
  • the first input end of the second PWM comparator is connected to the first output end of the error detecting sub-circuit, the second input end of the second PWM comparator inputs a preset input signal, and the output end of the second PWM comparator is The first input end of the second RS flip-flop is connected, the second input end of the second RS flip-flop inputs a preset square wave signal, and the first output end of the second RS flip-flop and the first input of the second power stage adjustment sub-circuit.
  • the second output end of the first RS flip-flop is connected to the second input end of the second power stage adjusting sub-circuit, and the output end of the second power stage adjusting sub-circuit is connected to the input end of the second inductor;
  • the second power stage adjustment sub-circuit is configured to adjust an input current of the second inductor according to the first output signal of the second RS flip-flop and the second output signal of the second RS flip-flop.
  • the first power level adjustment sub-circuit may include:
  • a first driving sub-circuit a second driving sub-circuit, a first MOS transistor and a second MOS transistor;
  • the input end of the first driving sub-circuit is connected to the first output end of the first RS flip-flop, the output end of the first driving sub-circuit is connected to the gate of the first MOS tube, and the input end of the second driving sub-circuit is a second output end of the first RS flip-flop is connected, an output end of the second driving sub-circuit is connected to a gate of the second MOS transistor, a drain of the first MOS transistor and a source of the second MOS transistor are both connected to the first inductor
  • the input terminal is connected, the source of the first MOS transistor is grounded, and the drain of the second MOS transistor is connected to the first power source.
  • the second power stage adjustment sub-circuit may include:
  • the input end of the third driving sub-circuit is connected to the first output end of the second RS flip-flop, the output end of the third driving sub-circuit is connected to the gate of the third MOS tube, and the input end of the fourth driving sub-circuit is The second output end of the second RS flip-flop is connected, the output end of the fourth driving sub-circuit is connected to the gate of the fourth MOS transistor, the drain of the third MOS transistor and the source of the fourth MOS transistor are both connected to the second inductor The input terminal is connected, the source of the third MOS transistor is grounded, and the drain of the fourth MOS transistor is connected to the second power source.
  • the circuit equalization array circuit may further include:
  • the input end of the first current detecting sub-circuit is connected to the output end of the first inductor, and the output end of the first current detecting sub-circuit is connected to the input end of the first resistor; the first current detecting sub-circuit is configured to detect the first inductor Sampling current and scaling the sampling current of the first inductor;
  • An input end of the second current detecting sub-circuit is connected to an output end of the second inductor, and an output end of the second current detecting sub-circuit is respectively connected to an output end of the first current detecting sub-circuit and an input end of the second resistor; the second current The detecting sub-circuit is configured to detect a sampling current of the second inductor and perform scaling processing on the sampling current of the second inductor.
  • the error detection sub-circuit may further include:
  • the output end of the voltage adjusting sub-circuit is respectively connected to the input end of the third resistor and the input end of the fourth resistor, and the first input end of the voltage adjusting sub-circuit is connected with the first output end of the output voltage feedback sub-circuit, and the voltage is adjusted.
  • the second input end of the sub-circuit inputs a reference voltage signal, the second output end of the output voltage feedback sub-circuit is grounded, the third output end of the output voltage feedback sub-circuit is grounded, and the input end of the output voltage feedback sub-circuit is respectively associated with the first current detection
  • the output of the sub-circuit is connected to the output of the second current detecting sub-circuit;
  • the input end of the voltage feedback sub-circuit is configured to receive a current signal of the first inductor and a current signal of the second inductor, and the voltage feedback sub-circuit is configured to convert the current signal of the first inductor and the current signal of the second inductor into a voltage signal, and Performing a voltage division process on the converted voltage signal;
  • the input end of the voltage adjustment sub-circuit is configured to receive the voltage signal after the voltage feedback sub-circuit is divided, and adjust the voltage signal after the voltage feedback sub-circuit is divided according to the reference voltage signal, so that the output end of the voltage adjustment sub-circuit
  • the input end of the third resistor and the input end of the fourth resistor input a preset voltage signal.
  • the voltage adjustment sub-circuit may include:
  • the first input end of the error amplifier is respectively connected to the output end of the first impedance network and the input end of the second impedance network, and the second input end of the error amplifier inputs the reference voltage signal, the output of the error amplifier and the second impedance network. Both are connected to the input end of the third resistor and the input end of the fourth resistor, and the input end of the first impedance network is connected to the first output end of the output voltage feedback sub-circuit.
  • the output voltage feedback sub-circuit may include:
  • the input end of the fifth resistor and the input end of the capacitor are both connected to the output end of the first current detecting sub-circuit, and the input end of the fifth resistor and the input end of the capacitor are both connected to the output end of the second current detecting sub-circuit
  • the output end of the fifth resistor is respectively connected to the input end of the sixth resistor and the input end of the voltage adjusting sub-circuit, the output end of the sixth resistor is grounded, and the output end of the capacitor is grounded.
  • the present application provides a multiphase converter that can include the current balanced array circuit shown in any of the possible implementations of the second aspect above.
  • the current equalization circuit, the array circuit and the multi-phase converter provided by the present application comprise: a first inductor, a first resistor, an output end of the first inductor is connected to an input end of the first resistor, and an output of the first resistor The terminal is grounded, the input end of the first resistor is connected to the first input end of the error detecting sub-circuit; the second inductor, the second resistor, the output end of the second inductor are respectively connected with the output end of the first inductor and the input end of the second resistor Connecting, the output end of the second resistor is grounded, the input end of the second resistor is connected to the second input end of the error detecting sub-circuit; the error detecting sub-circuit, the first output end of the error detecting sub-circuit and the first error adjusting sub-circuit The first input end is connected, the second output end of the error detecting sub-circuit is connected to the first input end of the second error adjusting sub-circuit, and the error detecting sub-circuit
  • the current balancing circuit provided by the embodiment of the present application directly connects the input end of the first resistor corresponding to the first inductor to be equalized and the input end of the second resistor corresponding to the second inductor to the error detecting sub-circuit.
  • the input terminals are connected, so that the error detecting sub-circuit can directly detect the difference between the voltage of the first input end of the error detecting sub-circuit and the voltage of the second input end, thereby adjusting the input current of the first inductor through the first error adjusting sub-circuit, and
  • the input current of the second inductor is adjusted by the second error adjustment sub-circuit to achieve equalization of the current of the first inductor and the current of the second inductor, thereby reducing the complexity of the circuit.
  • FIG. 1 is a schematic structural diagram of a current balancing circuit according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another current balancing circuit according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of a current balanced array circuit according to an embodiment of the present application.
  • multiple photo inductors can be arranged in parallel, and the input current of each phase inductor can be adjusted according to the sampling current of each phase inductor and the average sampling current of each phase inductor, thereby realizing each phase.
  • the current of the inductor is equalized.
  • the average sampling current of each phase inductor needs to be calculated in advance, so that the complexity of the circuit is high.
  • the current equalization circuit and the multi-phase converter provided by the embodiments of the present application do not need to calculate the average sampling current of each inductor in advance, and achieve the circuit equalization of the inductance of each phase while reducing the complexity of the circuit.
  • FIG. 1 is a schematic structural diagram of a current balancing circuit 10 according to an embodiment of the present disclosure.
  • the current balancing circuit 10 may include:
  • the first inductor 101, the first resistor 102, the output end of the first inductor 101 is connected to the input end of the first resistor 102, the output end of the first resistor 102 is grounded, the input end of the first resistor 102 and the error detecting sub-circuit 103 The first input is connected.
  • the output ends of the second inductor 104, the second resistor 105, and the second inductor 104 are respectively connected to the output end of the first inductor 101 and the input end of the second resistor 105, and the output end of the second resistor 105 is grounded, and the second resistor 105 is The input is coupled to the second input of the error detection sub-circuit 103.
  • the error detecting sub-circuit 103, the first output end of the error detecting sub-circuit 103 is connected to the first input end of the first error adjusting sub-circuit 106, the second output end of the error detecting sub-circuit 103 and the second error adjusting sub-circuit 107
  • the first input terminal is connected, and the error detecting sub-circuit 103 is for amplifying the difference between the voltage of the first input terminal of the error detecting sub-circuit 103 and the voltage of the second input terminal.
  • the first error adjustment sub-circuit 106 includes two input ends for respectively receiving a preset input signal and a voltage signal input by the first output end of the error detecting sub-circuit 103, and the first error adjusting sub-circuit 106 is used for The input current of the first inductor 101 is adjusted according to the preset input signal and the voltage signal input by the first input terminal of the error detecting sub-circuit 103.
  • the second error adjustment sub-circuit 107 includes two input terminals for respectively receiving a preset input signal and a voltage signal input by the second output end of the error detecting sub-circuit 103, and the second error adjusting sub-circuit 107 is used for The input current of the second inductor 104 is adjusted according to the preset input signal and the voltage signal input from the second input terminal of the error detecting sub-circuit 103.
  • the preset input signal may be a sawtooth wave signal or a triangular wave signal.
  • the type of the preset input signal is not specifically limited in this application.
  • the preset input signal is a triangular wave signal as an example for description. It should be noted that when the preset input signal is a triangular wave signal, in the process of adjusting the current of the first inductor, it needs to be performed. The clock is reset. When the preset input signal is a sawtooth signal, no clock reset is required during the process of adjusting the current of the first inductor.
  • the sampling current of the first inductor 101 can be converted into a voltage by the first resistor 102.
  • the sampling current of the second inductor 104 can be converted into a voltage by the second resistor 105.
  • the input end of the first resistor 102 is connected to the first input end of the error detecting sub-circuit 103, and the input end of the second resistor 105 is connected to the second input end of the error detecting sub-circuit 103, so that the error detecting sub-circuit 103
  • the difference between the voltage of the first input end of the error detecting sub-circuit 103 and the voltage of the second input end can be directly detected, and the difference is amplified to generate a first voltage difference signal and a second voltage difference signal;
  • a voltage difference signal is input to the first error adjustment sub-circuit 106, and the second voltage difference signal is input to the second error adjustment sub-circuit 107, so that the first error adjustment sub-circuit 106 can be based on the first voltage difference signal and the triangular wave.
  • the signal adjusts the input current of the first inductor 101
  • the second error adjustment sub-circuit 107 can adjust the input current of the second inductor 104 according to the second voltage difference signal and the triangular wave signal; thereby causing the current of the first inductor 101 and the second inductor 104.
  • the current is balanced. It can be seen that the current balancing circuit 10 provided in the embodiment of the present application does not need to obtain the average value of the sampling current of the first inductor 101 and the sampling current of the second inductor 104 in advance, thereby reducing the complexity of the circuit.
  • the first input end of the error detecting sub-circuit 103 receives the first of the first inductor 101.
  • the adjustment sub-circuit 107 outputs a second pulse signal according to the second voltage difference signal and the triangular wave signal, and the duty ratio of the second pulse signal
  • the increase is such that the input current of the second inductor 104 is increased, thereby achieving
  • the sampling current of the first inductor 101 and the sampling current of the second inductor 104 are determined. Will be equal.
  • the current equalization circuit 10 includes: a first inductor 101 and a first resistor 102.
  • the output end of the first inductor 101 is connected to the input end of the first resistor 102, and the output end of the first resistor 102 is grounded, and the first resistor
  • An input of 102 is coupled to a first input of error detection sub-circuit 103.
  • the output ends of the second inductor 104, the second resistor 105, and the second inductor 104 are respectively connected to the output end of the first inductor 101 and the input end of the second resistor 105, and the output end of the second resistor 105 is grounded, and the second resistor 105 is The input is coupled to the second input of the error detection sub-circuit 103.
  • the error detecting sub-circuit 103, the first output end of the error detecting sub-circuit 103 is connected to the first input end of the first error adjusting sub-circuit 106, the second output end of the error detecting sub-circuit 103 and the second error adjusting sub-circuit 107
  • the first input terminal is connected, and the error detecting sub-circuit 103 is for amplifying the difference between the voltage of the first input terminal of the error detecting sub-circuit 103 and the voltage of the second input terminal.
  • the first error adjustment sub-circuit 106 includes two input ends for respectively receiving a preset input signal and a voltage signal input by the first output end of the error detecting sub-circuit 103, and the first error adjusting sub-circuit 106 is used for The input current of the first inductor 101 is adjusted according to the preset input signal and the voltage signal input by the first input terminal of the error detecting sub-circuit 103.
  • the second error adjustment sub-circuit 107 includes two input terminals for respectively receiving a preset input signal and a voltage signal input by the second output end of the error detecting sub-circuit 103, and the second error adjusting sub-circuit 107 is used for
  • the input current of the second inductor 104 is adjusted according to the preset input signal and the voltage signal input from the second input terminal of the error detecting sub-circuit 103. It can be seen that the current balancing circuit 10 provided by the embodiment of the present application directly compares the input end of the first resistor 103 corresponding to the first inductor 101 to be equalized with the input end of the second resistor 105 corresponding to the second inductor 104.
  • the two input terminals of the detecting sub-circuit 103 are connected, so that the error detecting sub-circuit 103 can directly detect the difference between the voltage of the first input terminal of the error detecting sub-circuit 103 and the voltage of the second input terminal, thereby passing through the first error adjusting sub-circuit 106.
  • the input current of the first inductor 101 is adjusted, and the input current of the second inductor 104 is adjusted by the second error adjustment sub-circuit 107 to achieve equalization of the current of the first inductor 101 and the current of the second inductor 104, thereby reducing the circuit. the complexity.
  • FIG. 2 is a schematic structural diagram of another current balancing circuit 10 according to an embodiment of the present application, and an error detector of the current balancing circuit 10 Circuitry 103 can include:
  • a transimpedance operational amplifier a third resistor, and a fourth resistor.
  • the first input of the transimpedance operational amplifier is coupled to the input of the first resistor 102, and the second input of the transimpedance operational amplifier is coupled to the input of the second resistor 105, the first output of the transimpedance operational amplifier and The output end of the third resistor is connected to the first input end of the first error adjustment sub-circuit 106; the output end of the second output end of the transimpedance operational amplifier and the fourth resistor are both the first of the second error adjustment sub-circuit 107
  • the input terminal is connected, and the input end of the third resistor and the input end of the fourth resistor are input with a preset voltage signal.
  • the input end of the first resistor 102 is connected to the first input end of the transimpedance operational amplifier in the error detecting sub-circuit 103, and the input end of the second resistor 105 and the error detecting sub-circuit 103 are crossed.
  • the second input terminal of the operational amplifier is connected, so that the transimpedance operational amplifier can directly detect the difference between the voltage of the first input terminal of the transimpedance operational amplifier and the voltage of the second input terminal, and amplify the difference to generate a current difference.
  • the current difference signal is superimposed on the preset voltage signal input at the input end of the third resistor through the first output end to generate a first voltage difference signal; so that the first error adjustment sub-circuit 106 can be based on the first The voltage difference signal and the triangular wave signal adjust the input current of the first inductor 101.
  • the transimpedance operational amplifier superimposes the current difference signal on the preset voltage signal input at the input end of the fourth resistor through the second output terminal to generate the first a second voltage difference signal; so that the second error adjustment sub-circuit 107 can adjust the second inductor 104 according to the second voltage difference signal and the triangular wave signal The electric current, so that the second inductor 104 current and the current first inductor 101 to achieve equilibrium.
  • the first error adjustment sub-circuit 106 may include: a first pulse width modulation (PWM) comparator, a first reset-set (RS) trigger, and a first power level. Adjust the subcircuit.
  • PWM pulse width modulation
  • RS reset-set
  • the first input end of the first PWM comparator is connected to the first output end of the error detecting sub-circuit 103, and the second input end of the first PWM comparator inputs a preset input signal, and the output end of the first PWM comparator is a first input end of the first RS flip-flop is connected, and a second input end of the first RS flip-flop inputs a preset square wave signal, the first output end of the first RS flip-flop and the first of the first power-level adjustment sub-circuit
  • the input end is connected, and the second output end of the first RS flip-flop is connected to the second input end of the first power stage adjusting sub-circuit, and the output end of the first power stage adjusting sub-circuit is connected to the input end of the first inductor 101.
  • the first power stage adjustment sub-circuit is configured to adjust an input current of the first inductor 101 according to the first output end signal of the first RS flip-flop and the second output end signal of the first RS flip-flop.
  • the first input end of the first PWM comparator may output the first pulse signal by comparing the first voltage difference signal and the triangular wave signal, and The first pulse signal is input to the first RS comparator, so that the first RS comparator can control the on and off of the first power stage adjustment sub-circuit according to the first pulse signal and the preset square wave signal, thereby achieving the first The adjustment of the input current of the inductor 101.
  • the first power stage adjustment sub-circuit may include: a first driving sub-circuit, a second driving sub-circuit, a first MOS transistor, and a second MOS transistor.
  • the input end of the first driving sub-circuit is connected to the first output end of the first RS flip-flop, the output end of the first driving sub-circuit is connected to the gate of the first MOS tube, and the input end of the second driving sub-circuit is a second output end of the first RS flip-flop is connected, an output end of the second driving sub-circuit is connected to a gate of the second MOS transistor, a drain of the first MOS transistor and a source of the second MOS transistor are both connected to the first inductor
  • the input terminal of 101 is connected, the source of the first MOS transistor is grounded, and the drain of the second MOS transistor is connected to the first power source.
  • the sampling current of the first inductor 101 is adjusted by the first driving sub-circuit, the second driving sub-circuit, the first MOS transistor and the second MOS transistor, the first driving sub-circuit and the second driving sub-circuit
  • the output is non-overlapping, so that the first MOS transistor and the second MOS transistor can be alternately turned on, when the opening time of the second MOS transistor connected to the first power source is increased, and the first MOS transistor connected to the ground is As the turn-on time decreases, the sampling current of the first inductor 101 increases, and conversely, the sampling current of the first inductor 101 decreases.
  • the second error adjustment sub-circuit 107 includes: a second PWM comparator, a second RS flip-flop, and a second power stage adjustment sub-circuit.
  • the first input end of the second PWM comparator is connected to the first output end of the error detecting sub-circuit 103, the second input end of the second PWM comparator inputs a preset input signal, and the output end of the second PWM comparator is a first input end of the second RS flip-flop is connected, a second input end of the second RS flip-flop inputting a preset square wave signal, and the first output end of the second RS flip-flop and the first end of the second power-level adjustment sub-circuit
  • the input end is connected, the second output end of the first RS flip-flop is connected to the second input end of the second power stage adjusting sub-circuit, and the output end of the second power stage adjusting sub-circuit is connected to the input end of the second inductor 105.
  • the second power stage adjustment sub-circuit is configured to adjust an input current of the second inductor 104 according to the first output signal of the second RS flip-flop and the second output signal of the second RS flip-flop.
  • the first input end of the second PWM comparator may output the second pulse signal by comparing the second voltage difference signal with the triangular wave signal. And inputting the second pulse signal to the second RS comparator, so that the first RS comparator can control the on and off of the second power stage adjustment sub-circuit according to the first pulse signal and the preset square wave signal, thereby realizing Adjustment of the input current to the second inductor 104.
  • the second power stage adjustment sub-circuit includes: a third driving sub-circuit, a fourth driving sub-circuit, a third MOS tube, and a fourth MOS tube.
  • the input end of the third driving sub-circuit is connected to the first output end of the second RS flip-flop, the output end of the third driving sub-circuit is connected to the gate of the third MOS tube, and the input end of the fourth driving sub-circuit is The second output end of the second RS flip-flop is connected, the output end of the fourth driving sub-circuit is connected to the gate of the fourth MOS transistor, the drain of the third MOS transistor and the source of the fourth MOS transistor are both connected to the second inductor
  • the input terminal of 104 is connected, the source of the third MOS transistor is grounded, and the drain of the fourth MOS transistor is connected to the second power source.
  • the sampling current of the second inductor 104 is adjusted by the third driving sub-circuit, the fourth driving sub-circuit, the third MOS transistor and the fourth MOS transistor, the third driving sub-circuit and the fourth driving sub-circuit
  • the output is non-overlapping, so that the third MOS transistor and the fourth MOS transistor can be alternately turned on, when the turn-on time of the fourth MOS transistor connected to the second power source is increased, and the third MOS transistor connected to the ground is
  • the turn-on time decreases, the sampling current of the second inductor 105 increases, and conversely, the sample current of the second inductor 104 decreases.
  • the circuit equalization circuit 10 further includes:
  • the first current detecting sub-circuit 108 and the second current detecting sub-circuit 109 The input end of the first current detecting sub-circuit 108 is connected to the output end of the first inductor 101, and the output end of the first current detecting sub-circuit 108 is connected to the input end of the first resistor 102.
  • the first current detecting sub-circuit 108 is used.
  • the sampling current of the first inductor 101 is detected, and the sampling current of the first inductor 101 is scaled.
  • An input end of the second current detecting sub-circuit 109 is connected to an output end of the second inductor 104, and an output end of the second current detecting sub-circuit 109 is respectively connected to an output end of the first current detecting sub-circuit 108 and an input end of the second resistor 105.
  • the second current detecting sub-circuit 109 is configured to detect the sampling current of the second inductor 104 and perform scaling processing on the sampling current of the second inductor 104.
  • the configuration of the first current detecting sub-circuit 108 and the second current detecting sub-circuit 109 is not specifically limited in the embodiment of the present application, as long as the sampling current of the collecting inductor and the sampling current are scaled.
  • the configurations of the first current detecting sub-circuit 108 and the second current detecting sub-circuit 109 are not described in detail in the embodiments of the present application.
  • the sampling current of the first inductor 101 is collected by the first current detecting sub-circuit 108, and the first inductor 101 is The sampling current is reduced by a certain ratio, and then the processed voltage signal is input to the first input end of the error detecting sub-circuit 103 through the first resistor 102.
  • the second current detecting sub-circuit 109 is collected by the second current detecting sub-circuit 109.
  • the sampling current of the second inductor 104 is reduced by a certain ratio of the sampling current of the second inductor 104, and then the processed voltage signal is input to the second input end of the error detecting sub-circuit 103 through the second resistor 105. Therefore, it is possible to prevent the sampling current of the first inductor 101 and the second inductor 104 from being excessively large, thereby causing damage to components in the circuit and improving the safety of the circuit.
  • the error detecting sub-circuit 103 further includes: a voltage adjusting sub-circuit and an output voltage feedback sub-circuit.
  • the output end of the voltage adjusting sub-circuit is respectively connected to the input end of the third resistor and the input end of the fourth resistor, and the first input end of the voltage adjusting sub-circuit is connected with the first output end of the output voltage feedback sub-circuit, and the voltage is adjusted.
  • the second input end of the sub-circuit inputs a reference voltage signal, the second output end of the output voltage feedback sub-circuit is grounded, the third output end of the output voltage feedback sub-circuit is grounded, and the input end of the output voltage feedback sub-circuit is respectively coupled to the first inductor 101
  • the output is connected to the output of the second inductor 104.
  • the input end of the voltage feedback sub-circuit is configured to receive the current signal of the first inductor 101 and the current signal of the second inductor 104, and the voltage feedback sub-circuit is configured to convert the current signal of the first inductor 101 and the current signal of the second inductor 104 into The voltage signal is subjected to voltage division processing on the converted voltage signal.
  • the input end of the voltage adjustment sub-circuit is configured to receive the voltage signal after the voltage feedback sub-circuit is divided, and adjust the voltage signal after the voltage feedback sub-circuit is divided according to the reference voltage signal, so that the output end of the voltage adjustment sub-circuit
  • the input end of the third resistor and the input end of the fourth resistor input a preset voltage signal.
  • the preset voltage of the third resistance input and the preset voltage of the fourth resistance input may be implemented by a voltage adjustment sub-circuit and an output voltage feedback sub-circuit.
  • the output voltage feedback sub-circuit receives the first voltage signal of the first inductor 101 and the second voltage signal of the second inductor 105
  • the current signal of the first inductor 101 and the current signal of the second inductor 104 are converted into a voltage.
  • the signal is subjected to voltage division processing on the converted voltage signal to obtain a third voltage signal.
  • the third voltage signal may be input to the first In the voltage adjustment sub-circuit, the voltage adjustment sub-circuit adjusts the voltage value of the third voltage signal according to the reference voltage signal, thereby inputting a stable preset voltage to the input end of the third resistor and the input end of the fourth resistor signal.
  • the voltage adjustment sub-circuit may include: an error amplifier, a first impedance network, and a second impedance network.
  • the first input end of the error amplifier is respectively connected to the output end of the first impedance network and the input end of the second impedance network, and the second input end of the error amplifier inputs the reference voltage signal, the output of the error amplifier and the second impedance network. Both are connected to the input end of the third resistor and the input end of the fourth resistor, and the input end of the first impedance network is connected to the first output end of the output voltage feedback sub-circuit.
  • the third voltage signal may be received through the first input end of the error amplifier in the voltage adjustment sub-circuit, and the third voltage signal is The voltage value is compared with the reference voltage signal to adjust the voltage value of the third voltage signal, and a preset voltage signal is input to the input terminal of the third resistor and the input terminal of the fourth resistor.
  • the first impedance network and the second impedance network are used for frequency compensation of the adjustment process to ensure stability of the voltage adjustment sub-circuit during the adjustment process.
  • the output voltage feedback sub-circuit may include: a fifth resistor, a sixth resistor, and a capacitor.
  • the input end of the fifth resistor and the input end of the capacitor are both connected to the output end of the first current detecting sub-circuit 108, and the input end of the fifth resistor and the input end of the capacitor are both connected to the output of the second current detecting sub-circuit 109.
  • the end connection, the output end of the fifth resistor is respectively connected to the input end of the sixth resistor and the input end of the voltage adjusting sub-circuit, the output end of the sixth resistor is grounded, and the output end of the capacitor is grounded.
  • the fifth resistor and the sixth resistor form a voltage dividing circuit, and the function is to reduce the output voltage by a certain ratio, and then input to the input end of the error amplifier, and the function of the capacitor is to stabilize the output voltage.
  • the two input terminals of the transimpedance operational amplifier are respectively connected to the input end of the first resistor 102 and the input end of the second resistor 105.
  • the connected, transimpedance operational amplifier can directly detect the difference between the voltage of the first input terminal of the transimpedance operational amplifier and the voltage of the second input terminal, and amplify the difference to generate a current difference signal; and pass the current difference signal through An output terminal is superimposed on the preset voltage signal input at the input end of the third resistor to generate a first voltage difference signal; likewise, the transimpedance operational amplifier also superimposes the current difference signal on the fourth resistor through the second output terminal a second voltage difference signal is generated on the preset voltage signal input by the input terminal (the preset voltage is a preset voltage signal output by the error amplifier); wherein, the voltage of the first voltage difference signal is smaller than the voltage of the second voltage difference signal, And inputting the first voltage signal to the first PWM comparator, the first PWM comparator comparing the first voltage difference signal and the triangular wave signal, and outputting a pulse signal, the duty ratio of the first pulse signal is reduced, and the first pulse signal is input to the first RS comparator, and the first
  • the second voltage signal is input to the second PWM comparator, and the second PWM comparator compares the second voltage difference signal with the triangular wave signal, and outputs a second pulse signal, and the duty ratio of the second pulse signal increases.
  • the second RS comparator can control the third driving sub-circuit and the first according to the second pulse signal (large duty ratio) and the preset square wave signal.
  • the fourth driving sub-circuit controls the opening time of the third MOS transistor to be reduced by the third driving sub-circuit, and the opening time of the fourth MOS transistor is controlled by the fourth driving sub-circuit to increase the current of the second inductor 104
  • the equalization of the current of the first inductor 101 and the current of the second inductor 104 is achieved. It can be seen that the current balancing circuit 10 provided in the embodiment of the present application does not need to obtain the average value of the voltage of the first inductor 101 and the voltage of the second inductor 104 in
  • the current-balanced array circuit includes at least two current balancing circuit units, and the first current balancing circuit unit and the second current balancing circuit unit are at least Any two adjacent current equalization circuit units of the two current equalization circuit units, wherein the first output end of the error detecting sub-circuit in the first current equalization electronic unit and the error detector in the second current equalization electronic unit A second output terminal in the circuit is connected, wherein any current equalization circuit unit comprises:
  • the first inductor, the first resistor, the output end of the first inductor is connected to the input end of the first resistor, the output end of the first resistor is grounded, and the input end of the first resistor is connected to the first input end of the error detecting sub-circuit.
  • the output ends of the second inductor, the second resistor and the second inductor are respectively connected to the output end of the first inductor and the input end of the second resistor, the output end of the second resistor is grounded, the input end of the second resistor and the error detecting sub-circuit The second input is connected.
  • the error detecting sub-circuit is configured to amplify the difference between the voltage of the first input end of the error detecting sub-circuit and the voltage of the second input end.
  • the first error adjustment sub-circuit includes two input ends, and the two input ends are respectively configured to receive a preset input signal and a voltage signal input by the first output end of the error detecting sub-circuit, and the first error adjusting sub-circuit is configured according to the preset The input signal and the voltage signal input at the first input of the error detecting sub-circuit adjust the input current of the first inductor.
  • the second error adjustment sub-circuit includes two input ends, the two input ends respectively for receiving the preset input signal and the voltage signal input by the second output end of the error detecting sub-circuit, and the second error adjusting sub-circuit is configured according to the preset The input signal and the voltage signal input from the second input of the error detection sub-circuit adjust the input current of the second inductor.
  • the error detection sub-circuit includes: a transimpedance operational amplifier, a third resistor, and a fourth resistor.
  • the first input end of the transimpedance operational amplifier is connected to the input end of the first resistor
  • the second input end of the transimpedance operational amplifier is connected to the input end of the second resistor
  • the first output end of the transimpedance operational amplifier and the third The output ends of the resistors are connected to the first input end of the first error adjustment sub-circuit;
  • the second output end of the transimpedance operational amplifier and the output end of the fourth resistor are both connected to the first input end of the second error adjustment sub-circuit,
  • a preset voltage signal is input to both the input end of the third resistor and the input end of the fourth resistor.
  • the first error adjustment sub-circuit includes: a first pulse width modulation PWM comparator, a first complex position bit RS flip-flop, and a first power level adjustment sub-circuit.
  • the first input end of the first PWM comparator is connected to the first output end of the error detecting sub-circuit, and the second input end of the first PWM comparator inputs a preset input signal, and the output end of the first PWM comparator a first input end of the RS flip-flop is connected, and a second input end of the first RS flip-flop inputs a preset square wave signal, the first output end of the first RS flip-flop and the first input of the first power stage adjustment sub-circuit
  • the second output end of the first RS flip-flop is connected to the second input end of the first power stage adjusting sub-circuit, and the output end of the first power stage adjusting sub-circuit is connected to the input end of the first inductor.
  • the first power stage adjustment sub-circuit is configured to adjust an input current of the first inductor according to the first output end signal of the first RS flip-flop and the second output end signal of the first RS flip-flop.
  • the second error adjustment sub-circuit includes: a second PWM comparator, a second RS flip-flop, and a second power stage adjustment sub-circuit.
  • the first input end of the second PWM comparator is connected to the first output end of the error detecting sub-circuit, the second input end of the second PWM comparator inputs a preset input signal, and the output end of the second PWM comparator is The first input end of the second RS flip-flop is connected, the second input end of the second RS flip-flop inputs a preset square wave signal, and the first output end of the second RS flip-flop and the first input of the second power stage adjustment sub-circuit.
  • the second output end of the first RS flip-flop is connected to the second input end of the second power stage adjusting sub-circuit, and the output end of the second power stage adjusting sub-circuit is connected to the input end of the second inductor.
  • the second power stage adjustment sub-circuit is configured to adjust an input current of the second inductor according to the first output signal of the second RS flip-flop and the second output signal of the second RS flip-flop.
  • the first power stage adjustment sub-circuit includes: a first driving sub-circuit, a second driving sub-circuit, a first MOS transistor, and a second MOS transistor.
  • the input end of the first driving sub-circuit is connected to the first output end of the first RS flip-flop, the output end of the first driving sub-circuit is connected to the gate of the first MOS tube, and the input end of the second driving sub-circuit is a second output end of the first RS flip-flop is connected, an output end of the second driving sub-circuit is connected to a gate of the second MOS transistor, a drain of the first MOS transistor and a source of the second MOS transistor are both connected to the first inductor
  • the input terminal is connected, the source of the first MOS transistor is grounded, and the drain of the second MOS transistor is connected to the first power source.
  • the second power stage adjustment sub-circuit includes: a third driving sub-circuit, a fourth driving sub-circuit, a third MOS tube, and a fourth MOS tube.
  • the input end of the third driving sub-circuit is connected to the first output end of the second RS flip-flop, the output end of the third driving sub-circuit is connected to the gate of the third MOS tube, and the input end of the fourth driving sub-circuit is The second output end of the second RS flip-flop is connected, the output end of the fourth driving sub-circuit is connected to the gate of the fourth MOS transistor, the drain of the third MOS transistor and the source of the fourth MOS transistor are both connected to the second inductor The input terminal is connected, the source of the third MOS transistor is grounded, and the drain of the fourth MOS transistor is connected to the second power source.
  • the current balancing array circuit further includes:
  • the first current detecting sub-circuit is configured to detect a sampling current of the first inductor and perform scaling processing on the sampling current of the first inductor.
  • An input end of the second current detecting sub-circuit is connected to an output end of the second inductor, and an output end of the second current detecting sub-circuit is respectively connected to an output end of the first current detecting sub-circuit and an input end of the second resistor; the second current The detecting sub-circuit is configured to detect a sampling current of the second inductor and perform scaling processing on the sampling current of the second inductor.
  • the error detection sub-circuit further includes: a voltage adjustment sub-circuit and an output voltage feedback sub-circuit.
  • the output end of the voltage adjusting sub-circuit is respectively connected to the input end of the third resistor and the input end of the fourth resistor, and the first input end of the voltage adjusting sub-circuit is connected with the first output end of the output voltage feedback sub-circuit, and the voltage is adjusted.
  • the second input end of the sub-circuit inputs a reference voltage signal, the second output end of the output voltage feedback sub-circuit is grounded, the third output end of the output voltage feedback sub-circuit is grounded, and the input end of the output voltage feedback sub-circuit is respectively associated with the first current detection
  • the output of the sub-circuit is connected to the output of the second current detecting sub-circuit.
  • the input end of the voltage feedback sub-circuit is configured to receive a current signal of the first inductor and a current signal of the second inductor, and the voltage feedback sub-circuit is configured to convert the current signal of the first inductor and the current signal of the second inductor into a voltage signal, and The voltage signal after the conversion is subjected to voltage division processing.
  • the input end of the voltage adjustment sub-circuit is configured to receive the voltage signal after the voltage feedback sub-circuit is divided, and adjust the voltage signal after the voltage feedback sub-circuit is divided according to the reference voltage signal, so that the output end of the voltage adjustment sub-circuit
  • the input end of the third resistor and the input end of the fourth resistor input a preset voltage signal.
  • the voltage adjustment sub-circuit comprises: an error amplifier, a first impedance network, and a second impedance network.
  • the first input end of the error amplifier is respectively connected to the output end of the first impedance network and the input end of the second impedance network, and the second input end of the error amplifier inputs the reference voltage signal, the output of the error amplifier and the second impedance network. Both are connected to the input end of the third resistor and the input end of the fourth resistor, and the input end of the first impedance network is connected to the first output end of the output voltage feedback sub-circuit.
  • the output voltage feedback sub-circuit includes: a fifth resistor, a sixth resistor, and a capacitor.
  • the input end of the fifth resistor and the input end of the capacitor are both connected to the output end of the first current detecting sub-circuit, and the input end of the fifth resistor and the input end of the capacitor are both connected to the output end of the second current detecting sub-circuit
  • the output end of the fifth resistor is respectively connected to the input end of the sixth resistor and the input end of the voltage adjusting sub-circuit, the output end of the sixth resistor is grounded, and the output end of the capacitor is grounded.
  • the present application also provides a multi-phase converter, which may include the current-balanced array circuit shown in the embodiment corresponding to FIG. 3 above.
  • the multi-phase converter provided by the present application can perform the technical solution shown in the embodiment of the current-balanced array circuit, and the implementation principle and the beneficial effects are similar, and details are not described herein.

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Abstract

一种电流均衡电路（10）、阵列电路及多相变换器，包括：第一电感（101）的输出端与第一电阻（102）的输入端连接，第二电感（104）的输出端分别与第一电感（101）的输出端和第二电阻（105）的输入端连接，第一电阻（102）的输入端和第二电阻（105）的输入端分别与误差检测子电路（103）的第一输入端和第二输入端连接；误差检测子电路（103）的第一输出端与第一误差调整子电路（106）的第一输入端连接，其第二输出端与第二误差调整子电路（107）的第一输入端连接，第一误差调整子电路（106）根据预设输入信号和误差检测子电路（103）第一输入端输入的电压信号调整第一电感（101）的输入电流，第二误差调整子电路（107）根据预设输入信号和误差检测子电路第二输入端输入的电压信号调整第二电感（104）的输入电流，在实现电流均衡的同时，降低了电路的复杂度。

Description

电流均衡电路、阵列电路及多相变换器
本申请要求于2017年05月24日提交中国专利局、申请号为201710374931.1、申请名称为“电流均衡电路、阵列电路及多相变换器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子技术领域，尤其涉及一种电流均衡电路、阵列电路及多相变换器。.
背景技术
随着电子技术的飞速发展，直流电源-直流电源(Direct Current-Direct Current简称DC-DC)变换器在电子设备供电系统中得到了广泛应用，DC-DC变换器中的片式电感的饱和电流大小决定了DC-DC变换器的额定带载能力，通常通过并联设置多相片式电感以提升DC-DC变换器的额定带载能力，然而，多相片式电感存在各相之间电流不均衡的问题。
现有技术中，根据各相电感的采样电流以及各相电感的平均采样电流，调整各相电感的输入电流，从而实现各相电感的电流均衡。以4相电感并联为例，4相电感分别为A、B、C和D，A的采样电流为a，B的采样电流为b，C的采样电流为c，D的采样电流为d，4相电感的平均采样电流为(a+b+c+d)/4，根据各相电感的采样电流以及各相电感的平均采样电流，调整各相电感的输入电流，从而实现各相电感的电流均衡。
然而，采用现有技术的方案，电路复杂度高。
发明内容
本申请提供一种电流均衡电路、阵列电路及多相变换器，用以解决现有技术中电路复杂度较高的技术问题。
第一方面，本申请提供一种电流均衡电路，可以包括：
第一电感、第一电阻，第一电感的输出端与第一电阻的输入端连接，第一电阻的输出端接地，第一电阻的输入端与误差检测子电路的第一输入端连接；
第二电感，第二电阻，第二电感的输出端分别与第一电感的输出端和第二电阻的输入端连接，第二电阻的输出端接地，第二电阻的输入端与误差检测子电路的第二输入端连接；
误差检测子电路，误差检测子电路的第一输出端与第一误差调整子电路的第一输入端连接，误差检测子电路的第二输出端与第二误差调整子电路的第一输入端连接，误差检测子电路用于对误差检测子电路的第一输入端的电压与第二输入端的电压的差 值进行放大处理；
第一误差调整子电路，包括两个输入端，两个输入端分别用于接收预设输入信号和误差检测子电路第一输出端输入的电压信号，第一误差调整子电路用于根据预设输入信号和误差检测子电路第一输入端输入的电压信号调整第一电感的输入电流；
第二误差调整子电路，包括两个输入端，两个输入端分别用于接收预设输入信号和误差检测子电路第二输出端输入的电压信号，第二误差调整子电路用于根据预设输入信号和误差检测子电路第二输入端输入的电压信号调整第二电感的输入电流。
本申请提供的电流均衡电路，通过将待均衡的第一电感对应的第一电阻的输入端和第二电感对应的第二电阻的输入端直接与误差检测子电路的输入端连接，这样误差检测子电路可以直接检测误差检测子电路的第一输入端的电压与第二输入端的电压的差值，从而通过第一误差调整子电路调节第一电感的输入电流，并通过第二误差调整子电路调节第二电感的输入电流，以实现第一电感的电流和第二电感的电流的均衡，从而降低了电路的复杂度。
在一种可能的实现方式中，误差检测子电路可以包括：跨阻运算放大器、第三电阻和第四电阻。
其中，跨阻运算放大器的第一输入端与第一电阻的输入端连接，跨阻运算放大器的第二输入端与第二电阻的输入端连接，跨阻运算放大器的第一输出端和第三电阻的输出端均与第一误差调整子电路的第一输入端连接；跨阻运算放大器的第二输出端和第四电阻的输出端均与第二误差调整子电路的第一输入端连接，第三电阻的输入端和第四电阻的输入端均输入预设电压信号。
在一种可能的实现方式中，第一误差调整子电路可以包括：第一脉冲宽度调制PWM比较器、第一复位置位RS触发器及第一功率级调整子电路。
其中，第一PWM比较器的第一输入端与误差检测子电路的第一输出端连接，第一PWM比较器的第二输入端输入预设输入信号，第一PWM比较器的输出端与第一RS触发器的第一输入端连接，第一RS触发器的第二输入端输入预设方波信号，第一RS触发器的第一输出端与第一功率级调整子电路的第一输入端连接，第一RS触发器的第二输出端与第一功率级调整子电路的第二输入端连接，第一功率级调整子电路的输出端与第一电感的输入端连接；
第一功率级调整子电路用于根据第一RS触发器的第一输出端信号和第一RS触发器的第二输出端信号调整第一电感的输入电流。
在一种可能的实现方式中，第二误差调整子电路可以包括：第二PWM比较器、第二RS触发器及第二功率级调整子电路。
其中，第二PWM比较器的第一输入端与误差检测子电路的第一输出端连接，第二PWM比较器的第二输入端输入预设输入信号，第二PWM比较器的输出端与第二RS触发器的第一输入端连接，第二RS触发器的第二输入端输入预设方波信号，第二RS触发器的第一输出端与第二功率级调整子电路的第一输入端连接，第一RS触发器的第二输出端与第二功率级调整子电路的第二输入端连接，第二功率级调整子电路的输出端与第二电感的输入端连接；
第二功率级调整子电路用于根据第二RS触发器的第一输出端信号和第二RS触发 器的第二输出端信号调整第二电感的输入电流。
在一种可能的实现方式中，第一功率级调整子电路可以包括：第一驱动子电路、第二驱动子电路、第一MOS管及第二MOS管；
其中，第一驱动子电路的输入端与第一RS触发器的第一输出端连接，第一驱动子电路的输出端与第一MOS管的栅极连接，第二驱动子电路的输入端与第一RS触发器的第二输出端连接，第二驱动子电路的输出端与第二MOS管的栅极连接，第一MOS管的漏极和第二MOS管的源极均与第一电感的输入端连接，第一MOS管的源极接地，第二MOS管的漏极与第一电源连接。
在一种可能的实现方式中，第二功率级调整子电路可以包括：第三驱动子电路、第四驱动子电路、第三MOS管及第四MOS管。
其中，第三驱动子电路的输入端与第二RS触发器的第一输出端连接，第三驱动子电路的输出端与第三MOS管的栅极连接，第四驱动子电路的输入端与第二RS触发器的第二输出端连接，第四驱动子电路的输出端与第四MOS管的栅极连接，第三MOS管的漏极和第四MOS管的源极均与第二电感的输入端连接，第三MOS管的源极接地，第四MOS管的漏极与第二电源连接。
在一种可能的实现方式中，电流均衡电路还可以包括：第一电流检测子电路和第二电流检测子电路；
其中，第一电流检测子电路的输入端与第一电感的输出端连接，第一电流检测子电路的输出端与第一电阻的输入端连接；第一电流检测子电路用于检测第一电感的采样电流，并对第一电感的采样电流进行缩放处理；
第二电流检测子电路的输入端与第二电感的输出端连接，第二电流检测子电路的输出端分别与第一电流检测子电路的输出端和第二电阻的输入端连接；第二电流检测子电路用于检测第二电感的采样电流，并对第二电感的采样电流进行缩放处理。
在一种可能的实现方式中，误差检测子电路还可以包括：电压调整子电路和输出电压反馈子电路。
其中，电压调整子电路的输出端分别与第三电阻的输入端和第四电阻的输入端连接，电压调整子电路的第一输入端与输出电压反馈子电路的第一输出端连接，电压调整子电路的第二输入端输入基准电压信号，输出电压反馈子电路的第二输出端接地，输出电压反馈子电路的第三输出端接地，输出电压反馈子电路的输入端分别与第一电流检测子电路的输出端和第二电流检测子电路的输出端连接；
电压反馈子电路的输入端用于接收第一电感的电流信号和第二电感的电流信号，电压反馈子电路用于将第一电感的电流信号和第二电感的电流信号转换为电压信号，并对转换后的电压信号进行分压处理；
电压调整子电路的输入端用于接收电压反馈子电路分压处理后的电压信号，并根据基准电压信号调整电压反馈子电路分压处理后的电压信号，以使电压调整子电路的输出端向第三电阻的输入端和第四电阻的输入端输入预设电压信号。
在一种可能的实现方式中，电压调整子电路可以包括：误差放大器、第一阻抗网络、第二阻抗网络。
误差放大器、第一阻抗网络、第二阻抗网络；
其中，误差放大器的第一输入端分别与第一阻抗网络的输出端和第二阻抗网络的输入端连接，误差放大器的第二输入端输入基准电压信号，误差放大器和第二阻抗网络的输出端均与第三电阻的输入端和第四电阻的输入端连接，第一阻抗网络的输入端与输出电压反馈子电路的第一输出端连接。
在一种可能的实现方式中，输出电压反馈子电路可以包括：第五电阻、第六电阻及电容。
第五电阻、第六电阻及电容；
其中，第五电阻的输入端和电容的输入端均与第一电流检测子电路的输出端连接，且第五电阻的输入端和电容的输入端均与第二电流检测子电路的输出端连接，第五电阻的输出端分别与第六电阻的输入端和电压调整子电路的输入端连接，第六电阻的输出端接地，电容的输出端接地。
第二方面，本申请提供一种电流均衡的阵列电路，该电流均衡的阵列电路可以包括至少两个电流均衡电路单元，第一电流均衡电路单元和第二电流均衡电路单元为至少两个电流均衡电路单元中任意两个相邻的电流均衡电路单元，其中，第一电流均衡电子单元中的误差检测子电路中的第一输出端与第二电流均衡电子单元中的误差检测子电路中的第二输出端连接，其中，任一电流均衡电路单元包括：
第一电感、第一电阻，第一电感的输出端与第一电阻的输入端连接，第一电阻的输出端接地，第一电阻的输入端与误差检测子电路的第一输入端连接；
第二电感，第二电阻，第二电感的输出端分别与第一电感的输出端和第二电阻的输入端连接，第二电阻的输出端接地，第二电阻的输入端与误差检测子电路的第二输入端连接；
误差检测子电路，误差检测子电路的第一输出端与第一误差调整子电路的第一输入端连接，误差检测子电路的第二输出端与第二误差调整子电路的第一输入端连接，误差检测子电路用于对误差检测子电路的第一输入端的电压与第二输入端的电压的差值进行放大处理；
第一误差调整子电路，包括两个输入端，两个输入端分别用于接收预设输入信号和误差检测子电路第一输出端输入的电压信号，第一误差调整子电路用于根据预设输入信号和误差检测子电路第一输入端输入的电压信号调整第一电感的输入电流；
第二误差调整子电路，包括两个输入端，两个输入端分别用于接收预设输入信号和误差检测子电路第二输出端输入的电压信号，第二误差调整子电路用于根据预设输入信号和误差检测子电路第二输入端输入的电压信号调整第二电感的输入电流。
本申请提供的电流均衡的阵列电路，该电流均衡的阵列电路可以包括至少两个电流均衡电路单元，通过将任一电流均衡电路单元中的待均衡的第一电感对应的第一电阻的输入端和第二电感对应的第二电阻的输入端直接与误差检测子电路的输入端连接，这样误差检测子电路可以直接检测误差检测子电路的第一输入端的电压与第二输入端的电压的差值，从而通过第一误差调整子电路调节第一电感的输入电流，并通过第二误差调整子电路调节第二电感的输入电流，以实现第一电感的电流和第二电感的电流的均衡，从而降低了电路的复杂度。
在一种可能的实现方式中，误差检测子电路可以包括：
跨阻运算放大器、第三电阻和第四电阻；
其中，跨阻运算放大器的第一输入端与第一电阻的输入端连接，跨阻运算放大器的第二输入端与第二电阻的输入端连接，跨阻运算放大器的第一输出端和第三电阻的输出端均与第一误差调整子电路的第一输入端连接；跨阻运算放大器的第二输出端和第四电阻的输出端均与第二误差调整子电路的第一输入端连接，第三电阻的输入端和第四电阻的输入端均输入预设电压信号。
在一种可能的实现方式中，第一误差调整子电路可以包括：
第一脉冲宽度调制PWM比较器、第一复位置位RS触发器及第一功率级调整子电路；
其中，第一PWM比较器的第一输入端与误差检测子电路的第一输出端连接，第一PWM比较器的第二输入端输入预设输入信号，第一PWM比较器的输出端与第一RS触发器的第一输入端连接，第一RS触发器的第二输入端输入预设方波信号，第一RS触发器的第一输出端与第一功率级调整子电路的第一输入端连接，第一RS触发器的第二输出端与第一功率级调整子电路的第二输入端连接，第一功率级调整子电路的输出端与第一电感的输入端连接；
第一功率级调整子电路用于根据第一RS触发器的第一输出端信号和第一RS触发器的第二输出端信号调整第一电感的输入电流。
在一种可能的实现方式中，第二误差调整子电路可以包括：
第二PWM比较器、第二RS触发器及第二功率级调整子电路；
其中，第二PWM比较器的第一输入端与误差检测子电路的第一输出端连接，第二PWM比较器的第二输入端输入预设输入信号，第二PWM比较器的输出端与第二RS触发器的第一输入端连接，第二RS触发器的第二输入端输入预设方波信号，第二RS触发器的第一输出端与第二功率级调整子电路的第一输入端连接，第一RS触发器的第二输出端与第二功率级调整子电路的第二输入端连接，第二功率级调整子电路的输出端与第二电感的输入端连接；
第二功率级调整子电路用于根据第二RS触发器的第一输出端信号和第二RS触发器的第二输出端信号调整第二电感的输入电流。
在一种可能的实现方式中，第一功率级调整子电路可以包括：
第一驱动子电路、第二驱动子电路、第一MOS管及第二MOS管；
其中，第一驱动子电路的输入端与第一RS触发器的第一输出端连接，第一驱动子电路的输出端与第一MOS管的栅极连接，第二驱动子电路的输入端与第一RS触发器的第二输出端连接，第二驱动子电路的输出端与第二MOS管的栅极连接，第一MOS管的漏极和第二MOS管的源极均与第一电感的输入端连接，第一MOS管的源极接地，第二MOS管的漏极与第一电源连接。
在一种可能的实现方式中，第二功率级调整子电路可以包括：
第三驱动子电路、第四驱动子电路、第三MOS管及第四MOS管；
其中，第三驱动子电路的输入端与第二RS触发器的第一输出端连接，第三驱动子电路的输出端与第三MOS管的栅极连接，第四驱动子电路的输入端与第二RS触发器的第二输出端连接，第四驱动子电路的输出端与第四MOS管的栅极连接，第三MOS管的漏极和第四MOS管的源极均与第二电感的输入端连接，第三MOS管的源极接地，第四 MOS管的漏极与第二电源连接。
在一种可能的实现方式中，该电路均衡阵列电路还可以包括：
第一电流检测子电路和第二电流检测子电路；
其中，第一电流检测子电路的输入端与第一电感的输出端连接，第一电流检测子电路的输出端与第一电阻的输入端连接；第一电流检测子电路用于检测第一电感的采样电流，并对第一电感的采样电流进行缩放处理；
第二电流检测子电路的输入端与第二电感的输出端连接，第二电流检测子电路的输出端分别与第一电流检测子电路的输出端和第二电阻的输入端连接；第二电流检测子电路用于检测第二电感的采样电流，并对第二电感的采样电流进行缩放处理。
在一种可能的实现方式中，误差检测子电路还可以包括：
电压调整子电路和输出电压反馈子电路；
其中，电压调整子电路的输出端分别与第三电阻的输入端和第四电阻的输入端连接，电压调整子电路的第一输入端与输出电压反馈子电路的第一输出端连接，电压调整子电路的第二输入端输入基准电压信号，输出电压反馈子电路的第二输出端接地，输出电压反馈子电路的第三输出端接地，输出电压反馈子电路的输入端分别与第一电流检测子电路的输出端和第二电流检测子电路的输出端连接；
电压反馈子电路的输入端用于接收第一电感的电流信号和第二电感的电流信号，电压反馈子电路用于将第一电感的电流信号和第二电感的电流信号转换为电压信号，并对转换后的电压信号进行分压处理；
电压调整子电路的输入端用于接收电压反馈子电路分压处理后的电压信号，并根据基准电压信号调整电压反馈子电路分压处理后的电压信号，以使电压调整子电路的输出端向第三电阻的输入端和第四电阻的输入端输入预设电压信号。
在一种可能的实现方式中，电压调整子电路可以包括：
误差放大器、第一阻抗网络、第二阻抗网络；
其中，误差放大器的第一输入端分别与第一阻抗网络的输出端和第二阻抗网络的输入端连接，误差放大器的第二输入端输入基准电压信号，误差放大器和第二阻抗网络的输出端均与第三电阻的输入端和第四电阻的输入端连接，第一阻抗网络的输入端与输出电压反馈子电路的第一输出端连接。
在一种可能的实现方式中，输出电压反馈子电路可以包括：
第五电阻、第六电阻及电容；
其中，第五电阻的输入端和电容的输入端均与第一电流检测子电路的输出端连接，且第五电阻的输入端和电容的输入端均与第二电流检测子电路的输出端连接，第五电阻的输出端分别与第六电阻的输入端和电压调整子电路的输入端连接，第六电阻的输出端接地，电容的输出端接地。
第三方面，本申请提供一种多相变换器，可以包括上述第二方面任一种可能的实现方式中所示的电流均衡的阵列电路。
本申请提供的电流均衡电路、阵列电路及多相变换器，该电流均衡电路包括：第一电感、第一电阻，第一电感的输出端与第一电阻的输入端连接，第一电阻的输出端接地，第一电阻的输入端与误差检测子电路的第一输入端连接；第二电感，第二电阻， 第二电感的输出端分别与第一电感的输出端和第二电阻的输入端连接，第二电阻的输出端接地，第二电阻的输入端与误差检测子电路的第二输入端连接；误差检测子电路，误差检测子电路的第一输出端与第一误差调整子电路的第一输入端连接，误差检测子电路的第二输出端与第二误差调整子电路的第一输入端连接，误差检测子电路用于对误差检测子电路的第一输入端的电压与第二输入端的电压的差值进行放大处理；第一误差调整子电路，包括两个输入端，两个输入端分别用于接收预设输入信号和误差检测子电路第一输出端输入的电压信号，第一误差调整子电路用于根据预设输入信号和误差检测子电路第一输入端输入的电压信号调整第一电感的输入电流；第二误差调整子电路，包括两个输入端，两个输入端分别用于接收预设输入信号和误差检测子电路第二输出端输入的电压信号，第二误差调整子电路用于根据预设输入信号和误差检测子电路第二输入端输入的电压信号调整第二电感的输入电流。由此可见，本申请实施例提供的电流均衡电路，通过将待均衡的第一电感对应的第一电阻的输入端和第二电感对应的第二电阻的输入端直接与误差检测子电路的两个输入端连接，这样误差检测子电路可以直接检测误差检测子电路的第一输入端的电压与第二输入端的电压的差值，从而通过第一误差调整子电路调节第一电感的输入电流，并通过第二误差调整子电路调节第二电感的输入电流，以实现第一电感的电流和第二电感的电流的均衡，从而降低了电路的复杂度。
附图说明
图1为本申请实施例提供的一种电流均衡电路的结构示意图；
图2为本申请实施例提供的另一种电流均衡电路的结构示意图；
图3为本申请实施例提供的一种电流均衡的阵列电路的结构示意图。
具体实施方式
为了提升DC-DC变换器的额定带载能力，可以通过并联设置多相片式电感，根据各相电感的采样电流以及各相电感的平均采样电流，调整各相电感的输入电流，从而实现各相电感的电流均衡。但是采用该方式，需要预先计算各相电感的平均采样电流，使得电路的复杂度较高。本申请实施例提供的电流均衡电路及多相变换器，无需预先计算各项电感的平均采样电流，在实现各相电感的电流均衡的同时，降低了电路的复杂度。
下面以具体地实施例对本申请的技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
图1为本申请实施例提供的一种电流均衡电路10的结构示意图，请参见图1所示，该电流均衡电路10可以包括：
第一电感101、第一电阻102，第一电感101的输出端与第一电阻102的输入端连接，第一电阻102的输出端接地，第一电阻102的输入端与误差检测子电路103的第一输入端连接。
第二电感104、第二电阻105，第二电感104的输出端分别与第一电感101的输出 端和第二电阻105的输入端连接，第二电阻105的输出端接地，第二电阻105的输入端与误差检测子电路103的第二输入端连接。
误差检测子电路103，误差检测子电路103的第一输出端与第一误差调整子电路106的第一输入端连接，误差检测子电路103的第二输出端与第二误差调整子电路107的第一输入端连接，误差检测子电路103用于对误差检测子电路103的第一输入端的电压与第二输入端的电压的差值进行放大处理。
第一误差调整子电路106，包括两个输入端，两个输入端分别用于接收预设输入信号和误差检测子电路103第一输出端输入的电压信号，第一误差调整子电路106用于根据预设输入信号和误差检测子电路103第一输入端输入的电压信号调整第一电感101的输入电流。
第二误差调整子电路107，包括两个输入端，两个输入端分别用于接收预设输入信号和误差检测子电路103第二输出端输入的电压信号，第二误差调整子电路107用于根据预设输入信号和误差检测子电路103第二输入端输入的电压信号调整第二电感104的输入电流。
其中，预设输入信号可以为锯齿波信号或三角波信号，在此，对于预设输入信号的类型，本申请不做具体限制。示例的，在本申请实施例中，以预设输入信号为三角波信号为例进行说明，需要注意的是，当预设输入信号为三角波信号时，在调节第一电感的电流过程中，需要进行时钟复位，当预设输入信号为锯齿波信号时，在调节第一电感的电流的过程中，不需要进行时钟复位。
在实现电流均衡的过程中，通过将第一电感101的输出端与第一电阻102的输入端连接，使得可以通过第一电阻102将第一电感101的采样电流转换为电压。同理，通过将第二电感104的输出端与第二电阻105的输入端连接，使得可以通过该第二电阻105将第二电感104的采样电流转换为电压。之后，再将第一电阻102的输入端与误差检测子电路103的第一输入端连接，第二电阻105的输入端与误差检测子电路103的第二输入端连接，这样误差检测子电路103可以直接检测误差检测子电路103的第一输入端的电压与第二输入端的电压的差值，并对该差值进行放大处理，生成第一电压差信号和第二电压差信号；再将该第一电压差信号输入至第一误差调整子电路106，将该第二电压差信号输入至第二误差调整子电路107，以使第一误差调整子电路106可以根据该第一电压差信号和三角波信号调整第一电感101的输入电流，第二误差调整子电路107可以根据该第二电压差信号和三角波信号调整第二电感104的输入电流；从而使得第一电感101的电流和第二电感104的电流实现均衡。由此可见，本申请实施例提供的电流均衡电路10，无需预先获取第一电感101的采样电流和第二电感104的采样电流的平均值，从而降低了电路的复杂度。
示例的，在本申请中，以第一电感101的第一采样电流大于第二电感104的第二采样电流为例，误差检测子电路103的第一输入端接收到第一电感101的第一电压信号，且误差检测子电路103的第二输入端接收到第二电感104的第二电压信号之后，直接检测第一电压信号的电压和第二电压信号的电压的差值，并对该差值进行放大处理，生成第一电压差信号和第二电压差信号，其中，第一电压差信号的电压小于第二电压差信号的电压，第一误差调整子电路106接收到第一电压差信号之后，根据该第 一电压差信号和三角波信号比较，输出第一脉冲信号，该第一脉冲信号的占空比减小，从而使得第一电感101的输入电流减小；同理，第二误差调整子电路107接收到第二电压差信号之后，根据该第二电压差信号和三角波信号比较，输出第二脉冲信号，该第二脉冲信号的占空比增大，从而使得第二电感104的输入电流增大，进而实现第一电感101的电流和第二电感104的电流的均衡。
需要说明的是，若误差检测子电路103的输入失调电压等非理想因素可以忽略，则通过该电流均衡电路10进行电流均衡之后，第一电感101的采样电流和第二电感104的采样电流定会相等。
本申请提供的电流均衡电路10，包括：第一电感101、第一电阻102，第一电感101的输出端与第一电阻102的输入端连接，第一电阻102的输出端接地，第一电阻102的输入端与误差检测子电路103的第一输入端连接。第二电感104、第二电阻105，第二电感104的输出端分别与第一电感101的输出端和第二电阻105的输入端连接，第二电阻105的输出端接地，第二电阻105的输入端与误差检测子电路103的第二输入端连接。误差检测子电路103，误差检测子电路103的第一输出端与第一误差调整子电路106的第一输入端连接，误差检测子电路103的第二输出端与第二误差调整子电路107的第一输入端连接，误差检测子电路103用于对误差检测子电路103的第一输入端的电压与第二输入端的电压的差值进行放大处理。第一误差调整子电路106，包括两个输入端，两个输入端分别用于接收预设输入信号和误差检测子电路103第一输出端输入的电压信号，第一误差调整子电路106用于根据预设输入信号和误差检测子电路103第一输入端输入的电压信号调整第一电感101的输入电流。第二误差调整子电路107，包括两个输入端，两个输入端分别用于接收预设输入信号和误差检测子电路103第二输出端输入的电压信号，第二误差调整子电路107用于根据预设输入信号和误差检测子电路103第二输入端输入的电压信号调整第二电感104的输入电流。由此可见，本申请实施例提供的电流均衡电路10，通过将待均衡的第一电感101对应的第一电阻103的输入端和第二电感104对应的第二电阻105的输入端直接与误差检测子电路103的两个输入端连接，这样误差检测子电路103可以直接检测误差检测子电路103的第一输入端的电压与第二输入端的电压的差值，从而通过第一误差调整子电路106调节第一电感101的输入电流，并通过第二误差调整子电路107调节第二电感104的输入电流，以实现第一电感101的电流和第二电感104的电流的均衡，从而降低了电路的复杂度。
在图1对应的实施例的基础上，进一步地，请参见图2所示，图2为本申请实施例提供的另一种电流均衡电路10的结构示意图，该电流均衡电路10的误差检测子电路103可以包括：
跨阻运算放大器、第三电阻和第四电阻。
其中，跨阻运算放大器的第一输入端与第一电阻102的输入端连接，跨阻运算放大器的第二输入端与第二电阻105的输入端连接，跨阻运算放大器的第一输出端和第三电阻的输出端均与第一误差调整子电路106的第一输入端连接；跨阻运算放大器的第二输出端和第四电阻的输出端均与第二误差调整子电路107的第一输入端连接，第三电阻的输入端和第四电阻的输入端均输入预设电压信号。
在实现电流均衡的过程中，通过将第一电阻102的输入端与误差检测子电路103中跨阻运算放大器的第一输入端连接，第二电阻105的输入端与误差检测子电路103中跨阻运算放大器的第二输入端连接，这样跨阻运算放大器可以直接检测跨阻运算放大器的第一输入端的电压与第二输入端的电压的差值，并对该差值进行放大处理，生成电流差信号，并将该电流差信号通过第一输出端叠加在第三电阻的输入端输入的预设电压信号上，生成第一电压差信号；以使第一误差调整子电路106可以根据该第一电压差信号和三角波信号调整第一电感101的输入电流，同理，跨阻运算放大器将该电流差信号通过第二输出端叠加在第四电阻的输入端输入的预设电压信号上，生成第二电压差信号；以使第二误差调整子电路107可以根据该第二电压差信号和三角波信号调整第二电感104的输入电流，从而使得第一电感101的电流和第二电感104的电流实现均衡。
可选的，第一误差调整子电路106可以包括：第一脉冲宽度调制(Pulse Width Modulation，简称PWM)比较器、第一复位置位(Reset-Set，简称RS)触发器及第一功率级调整子电路。
其中，第一PWM比较器的第一输入端与误差检测子电路103的第一输出端连接，第一PWM比较器的第二输入端输入预设输入信号，第一PWM比较器的输出端与第一RS触发器的第一输入端连接，第一RS触发器的第二输入端输入预设方波信号，第一RS触发器的第一输出端与第一功率级调整子电路的第一输入端连接，第一RS触发器的第二输出端与第一功率级调整子电路的第二输入端连接，第一功率级调整子电路的输出端与第一电感101的输入端连接。
第一功率级调整子电路用于根据第一RS触发器的第一输出端信号和第一RS触发器的第二输出端信号调整第一电感101的输入电流。
在本申请实施例中，第一PWM比较器的第一输入端接收到第一电压差信号之后，可以通过将该第一电压差信号和三角波信号进行比较，输出第一脉冲信号，并将该第一脉冲信号输入至第一RS比较器，以使该第一RS比较器可以根据该第一脉冲信号和预设方波信号控制第一功率级调整子电路的通断，从而实现对第一电感101的输入电流的调整。
进一步地，第一功率级调整子电路可以包括：第一驱动子电路、第二驱动子电路、第一MOS管及第二MOS管。
其中，第一驱动子电路的输入端与第一RS触发器的第一输出端连接，第一驱动子电路的输出端与第一MOS管的栅极连接，第二驱动子电路的输入端与第一RS触发器的第二输出端连接，第二驱动子电路的输出端与第二MOS管的栅极连接，第一MOS管的漏极和第二MOS管的源极均与第一电感101的输入端连接，第一MOS管的源极接地，第二MOS管的漏极与第一电源连接。
在实际应用过程中，通过第一驱动子电路、第二驱动子电路、第一MOS管及第二MOS管调整第一电感101的采样电流时，由于第一驱动子电路和第二驱动子电路的输出是非交叠的，这样就可以控制第一MOS管和第二MOS管交替开启，当与第一电源连接的第二MOS管的开启时间增大，而与地连接的第一MOS管的开启时间减小，第一电感101的采样电流就会增大，反之，第一电感101的采样电流就会减小。
可选的，第二误差调整子电路107包括：第二PWM比较器、第二RS触发器及第二功率级调整子电路。
其中，第二PWM比较器的第一输入端与误差检测子电路103的第一输出端连接，第二PWM比较器的第二输入端输入预设输入信号，第二PWM比较器的输出端与第二RS触发器的第一输入端连接，第二RS触发器的第二输入端输入预设方波信号，第二RS触发器的第一输出端与第二功率级调整子电路的第一输入端连接，第一RS触发器的第二输出端与第二功率级调整子电路的第二输入端连接，第二功率级调整子电路的输出端与第二电感105的输入端连接。
第二功率级调整子电路用于根据第二RS触发器的第一输出端信号和第二RS触发器的第二输出端信号调整第二电感104的输入电流。
类似的，在本申请实施例中，第二PWM比较器的第一输入端接收到第二电压差信号之后，可以通过将该第二电压差信号和三角波信号进行比较，输出第二脉冲信号，并将该第二脉冲信号输入至第二RS比较器，以使该第一RS比较器可以根据该第一脉冲信号和预设方波信号控制第二功率级调整子电路的通断，从而实现对第二电感104的输入电流的调整。
进一步地，第二功率级调整子电路包括：第三驱动子电路、第四驱动子电路、第三MOS管及第四MOS管。
其中，第三驱动子电路的输入端与第二RS触发器的第一输出端连接，第三驱动子电路的输出端与第三MOS管的栅极连接，第四驱动子电路的输入端与第二RS触发器的第二输出端连接，第四驱动子电路的输出端与第四MOS管的栅极连接，第三MOS管的漏极和第四MOS管的源极均与第二电感104的输入端连接，第三MOS管的源极接地，第四MOS管的漏极与第二电源连接。
在实际应用过程中，通过第三驱动子电路、第四驱动子电路、第三MOS管及第四MOS管调整第二电感104的采样电流时，由于第三驱动子电路和第四驱动子电路的输出是非交叠的，这样就可以控制第三MOS管和第四MOS管交替开启，当与第二电源连接的第四MOS管的开启时间增大，而与地连接的第三MOS管的开启时间减小，第二电感105的采样电流就会增大，反之，第二电感104的采样电流就会减小。
可选的，在本申请实施例中，电路均衡电路10还包括：
第一电流检测子电路108和第二电流检测子电路109。其中，第一电流检测子电路108的输入端与第一电感101的输出端连接，第一电流检测子电路108的输出端与第一电阻102的输入端连接；第一电流检测子电路108用于检测第一电感101的采样电流，并对第一电感101的采样电流进行缩放处理。
第二电流检测子电路109的输入端与第二电感104的输出端连接，第二电流检测子电路109的输出端分别与第一电流检测子电路108的输出端和第二电阻105的输入端连接；第二电流检测子电路109用于检测第二电感104的采样电流，并对第二电感104的采样电流进行缩放处理。
其中，对于第一电流检测子电路108和第二电流检测子电路109的结构本申请实施例不做具体限制，只要能是实现采集电感的采样电流和对采样电流进行缩放处理即可，在此，关于第一电流检测子电路108和第二电流检测子电路109的结构，本申请 实施例不再进行赘述。
在实际应用过程中，通过设置第一电流检测子电路108和第二电流检测子电路109，使得通过该第一电流检测子电路108采集第一电感101的采样电流，并将第一电感101的采样电流按一定比例进行缩小处理，之后，再将处理后的电压信号通过第一电阻102输入至误差检测子电路103的第一输入端，同理，通过该第二电流检测子电路109采集第二电感104的采样电流，并将第二电感104的采样电流按一定比例进行缩小处理，之后，再将处理后的电压信号通过第二电阻105输入至误差检测子电路103的第二输入端，从而可以避免因第一电感101和第二电感104的采样电流过大，而导致电路中部件损害，提高了电路的安全性。
可选的，在本申请实施例中，误差检测子电路103还包括：电压调整子电路和输出电压反馈子电路。
其中，电压调整子电路的输出端分别与第三电阻的输入端和第四电阻的输入端连接，电压调整子电路的第一输入端与输出电压反馈子电路的第一输出端连接，电压调整子电路的第二输入端输入基准电压信号，输出电压反馈子电路的第二输出端接地，输出电压反馈子电路的第三输出端接地，输出电压反馈子电路的输入端分别与第一电感101的输出端和第二电感104的输出端连接。
电压反馈子电路的输入端用于接收第一电感101的电流信号和第二电感104的电流信号，电压反馈子电路用于将第一电感101的电流信号和第二电感104的电流信号转换为电压信号，并对转换后的电压信号进行分压处理。电压调整子电路的输入端用于接收电压反馈子电路分压处理后的电压信号，并根据基准电压信号调整电压反馈子电路分压处理后的电压信号，以使电压调整子电路的输出端向第三电阻的输入端和第四电阻的输入端输入预设电压信号。
示例的，在本申请实施例中，第三电阻输入的预设电压和第四电阻输入的预设电压可以通过电压调整子电路和输出电压反馈子电路实现。输出电压反馈子电路的输入端接收到第一电感101的第一电压信号和第二电感105的第二电压信号之后，将第一电感101的电流信号和第二电感104的电流信号转换为电压信号，并对转换后的电压信号进行分压处理，得到第三电压信号，为了使得该输出电压反馈子电路在每一次调整过程中输出的电压值相等，可以先将该第三电压信号输入至电压调整子电路中，以使该电压调整子电路根据基准电压信号对该第三电压信号的电压值进行调整，从而向第三电阻的输入端和第四电阻的输入端输入稳定的预设电压信号。
进一步地，电压调整子电路可以包括：误差放大器、第一阻抗网络、第二阻抗网络。
其中，误差放大器的第一输入端分别与第一阻抗网络的输出端和第二阻抗网络的输入端连接，误差放大器的第二输入端输入基准电压信号，误差放大器和第二阻抗网络的输出端均与第三电阻的输入端和第四电阻的输入端连接，第一阻抗网络的输入端与输出电压反馈子电路的第一输出端连接。
示例的，在通过电压调整子电路对第三电压信号的电压值进行调整时，可以通过电压调整子电路中的误差放大器的第一输入端接收第三电压信号，并将该第三电压信号的电压值和基准电压信号进行比较，从而调整第三电压信号的电压值，并向第三电 阻的输入端和第四电阻的输入端输入预设电压信号。其中，第一阻抗网络和第二阻抗网络用于对该调整过程进行频率补偿，以确保调整过程中，电压调整子电路的稳定性。
可选的，输出电压反馈子电路可以包括：第五电阻、第六电阻及电容。
其中，第五电阻的输入端和电容的输入端均与第一电流检测子电路108的输出端连接，且第五电阻的输入端和电容的输入端均与第二电流检测子电路109的输出端连接，第五电阻的输出端分别与第六电阻的输入端和电压调整子电路的输入端连接，第六电阻的输出端接地，电容的输出端接地。
在本申请实施例中，第五电阻和第六电阻组成分压电路，作用是将输出电压缩小一定比例之后，再输入至误差放大器的输入端，电容的作用是稳定输出电压。
在实际应用过程中，若第一电感101的采样电流大于第二电感104的采样电流，由于跨阻运算放大器的两个输入端分别与第一电阻102的输入端和第二电阻105的输入端连接，跨阻运算放大器可以直接检测跨阻运算放大器的第一输入端的电压与第二输入端的电压的差值，对该差值进行放大处理，生成电流差信号；并将该电流差信号通过第一输出端叠加在第三电阻的输入端输入的预设电压信号上，生成第一电压差信号；同样的，跨阻运算放大器也将该电流差信号通过第二输出端叠加在第四电阻的输入端输入的预设电压信号(该预设电压为误差放大器输出的预设电压信号)上，生成第二电压差信号；其中，第一电压差信号的电压小于第二电压差信号的电压，并将该第一电压信号输入至第一PWM比较器，第一PWM比较器将该第一电压差信号和三角波信号进行比较，输出第一脉冲信号，该第一脉冲信号的占空比减小，并将该第一脉冲信号输入至第一RS比较器，该第一RS比较器可以根据该第一脉冲信号(占空比小)和预设方波信号控制第一驱动子电路和第二驱动子电路，以通过第一驱动子电路控制第一MOS管的开启时间增大，通过第二驱动子电路控制第二MOS管的开启时间减小，从而使得第一电感101的电流减小。同时，将该第二电压信号输入至第二PWM比较器，第二PWM比较器将该第二电压差信号和三角波信号进行比较，输出第二脉冲信号，该第二脉冲信号的占空比增大，并将该第二脉冲信号输入至第二RS比较器，该第二RS比较器可以根据该第二脉冲信号(占空比大)和预设方波信号控制第三驱动子电路和第四驱动子电路，以通过第三驱动子电路控制第三MOS管的开启时间减小，通过第四驱动子电路控制第四MOS管的开启时间增大，从而使得第二电感104的电流增大，从而实现第一电感101的电流与第二电感104的电流的均衡。由此可见，本申请实施例提供的电流均衡电路10，无需预先获取第一电感101的电压和第二电感104的电压的平均值，从而降低了电路的复杂度。
图3为本申请实施例提供的一种电流均衡的阵列电路的结构示意图，该电流均衡的阵列电路包括至少两个电流均衡电路单元，第一电流均衡电路单元和第二电流均衡电路单元为至少两个电流均衡电路单元中任意两个相邻的电流均衡电路单元，其中，第一电流均衡电子单元中的误差检测子电路中的第一输出端与第二电流均衡电子单元中的误差检测子电路中的第二输出端连接，其中，任一电流均衡电路单元包括：
第一电感、第一电阻，第一电感的输出端与第一电阻的输入端连接，第一电阻的输出端接地，第一电阻的输入端与误差检测子电路的第一输入端连接。
第二电感，第二电阻，第二电感的输出端分别与第一电感的输出端和第二电阻的 输入端连接，第二电阻的输出端接地，第二电阻的输入端与误差检测子电路的第二输入端连接。
误差检测子电路，误差检测子电路的第一输出端与第一误差调整子电路的第一输入端连接，误差检测子电路的第二输出端与第二误差调整子电路的第一输入端连接，误差检测子电路用于对误差检测子电路的第一输入端的电压与第二输入端的电压的差值进行放大处理。
第一误差调整子电路，包括两个输入端，两个输入端分别用于接收预设输入信号和误差检测子电路第一输出端输入的电压信号，第一误差调整子电路用于根据预设输入信号和误差检测子电路第一输入端输入的电压信号调整第一电感的输入电流。
第二误差调整子电路，包括两个输入端，两个输入端分别用于接收预设输入信号和误差检测子电路第二输出端输入的电压信号，第二误差调整子电路用于根据预设输入信号和误差检测子电路第二输入端输入的电压信号调整第二电感的输入电流。
可选的，误差检测子电路包括：跨阻运算放大器、第三电阻和第四电阻。
其中，跨阻运算放大器的第一输入端与第一电阻的输入端连接，跨阻运算放大器的第二输入端与第二电阻的输入端连接，跨阻运算放大器的第一输出端和第三电阻的输出端均与第一误差调整子电路的第一输入端连接；跨阻运算放大器的第二输出端和第四电阻的输出端均与第二误差调整子电路的第一输入端连接，第三电阻的输入端和第四电阻的输入端均输入预设电压信号。
可选的，第一误差调整子电路包括：第一脉冲宽度调制PWM比较器、第一复位置位RS触发器及第一功率级调整子电路。
其中，第一PWM比较器的第一输入端与误差检测子电路的第一输出端连接，第一PWM比较器的第二输入端输入预设输入信号，第一PWM比较器的输出端与第一RS触发器的第一输入端连接，第一RS触发器的第二输入端输入预设方波信号，第一RS触发器的第一输出端与第一功率级调整子电路的第一输入端连接，第一RS触发器的第二输出端与第一功率级调整子电路的第二输入端连接，第一功率级调整子电路的输出端与第一电感的输入端连接。
第一功率级调整子电路用于根据第一RS触发器的第一输出端信号和第一RS触发器的第二输出端信号调整第一电感的输入电流。
可选的，第二误差调整子电路包括：第二PWM比较器、第二RS触发器及第二功率级调整子电路。
其中，第二PWM比较器的第一输入端与误差检测子电路的第一输出端连接，第二PWM比较器的第二输入端输入预设输入信号，第二PWM比较器的输出端与第二RS触发器的第一输入端连接，第二RS触发器的第二输入端输入预设方波信号，第二RS触发器的第一输出端与第二功率级调整子电路的第一输入端连接，第一RS触发器的第二输出端与第二功率级调整子电路的第二输入端连接，第二功率级调整子电路的输出端与第二电感的输入端连接。
第二功率级调整子电路用于根据第二RS触发器的第一输出端信号和第二RS触发器的第二输出端信号调整第二电感的输入电流。
可选的，第一功率级调整子电路包括：第一驱动子电路、第二驱动子电路、第一 MOS管及第二MOS管。
其中，第一驱动子电路的输入端与第一RS触发器的第一输出端连接，第一驱动子电路的输出端与第一MOS管的栅极连接，第二驱动子电路的输入端与第一RS触发器的第二输出端连接，第二驱动子电路的输出端与第二MOS管的栅极连接，第一MOS管的漏极和第二MOS管的源极均与第一电感的输入端连接，第一MOS管的源极接地，第二MOS管的漏极与第一电源连接。
可选的，第二功率级调整子电路包括：第三驱动子电路、第四驱动子电路、第三MOS管及第四MOS管。
其中，第三驱动子电路的输入端与第二RS触发器的第一输出端连接，第三驱动子电路的输出端与第三MOS管的栅极连接，第四驱动子电路的输入端与第二RS触发器的第二输出端连接，第四驱动子电路的输出端与第四MOS管的栅极连接，第三MOS管的漏极和第四MOS管的源极均与第二电感的输入端连接，第三MOS管的源极接地，第四MOS管的漏极与第二电源连接。
可选的，电流均衡阵列电路还包括：
第一电流检测子电路和第二电流检测子电路；其中，第一电流检测子电路的输入端与第一电感的输出端连接，第一电流检测子电路的输出端与第一电阻的输入端连接；第一电流检测子电路用于检测第一电感的采样电流，并对第一电感的采样电流进行缩放处理。
第二电流检测子电路的输入端与第二电感的输出端连接，第二电流检测子电路的输出端分别与第一电流检测子电路的输出端和第二电阻的输入端连接；第二电流检测子电路用于检测第二电感的采样电流，并对第二电感的采样电流进行缩放处理。
可选的，误差检测子电路还包括：电压调整子电路和输出电压反馈子电路。
其中，电压调整子电路的输出端分别与第三电阻的输入端和第四电阻的输入端连接，电压调整子电路的第一输入端与输出电压反馈子电路的第一输出端连接，电压调整子电路的第二输入端输入基准电压信号，输出电压反馈子电路的第二输出端接地，输出电压反馈子电路的第三输出端接地，输出电压反馈子电路的输入端分别与第一电流检测子电路的输出端和第二电流检测子电路的输出端连接。
电压反馈子电路的输入端用于接收第一电感的电流信号和第二电感的电流信号，电压反馈子电路用于将第一电感的电流信号和第二电感的电流信号转换为电压信号，并对转换后的电压信号进行分压处理。
电压调整子电路的输入端用于接收电压反馈子电路分压处理后的电压信号，并根据基准电压信号调整电压反馈子电路分压处理后的电压信号，以使电压调整子电路的输出端向第三电阻的输入端和第四电阻的输入端输入预设电压信号。
可选的，电压调整子电路包括：误差放大器、第一阻抗网络、第二阻抗网络。
其中，误差放大器的第一输入端分别与第一阻抗网络的输出端和第二阻抗网络的输入端连接，误差放大器的第二输入端输入基准电压信号，误差放大器和第二阻抗网络的输出端均与第三电阻的输入端和第四电阻的输入端连接，第一阻抗网络的输入端与输出电压反馈子电路的第一输出端连接。
可选的，输出电压反馈子电路包括：第五电阻、第六电阻及电容。
其中，第五电阻的输入端和电容的输入端均与第一电流检测子电路的输出端连接，且第五电阻的输入端和电容的输入端均与第二电流检测子电路的输出端连接，第五电阻的输出端分别与第六电阻的输入端和电压调整子电路的输入端连接，第六电阻的输出端接地，电容的输出端接地。
本申请还提供的一种多相变换器，该多相变换器可以包括：上述图3对应的实施例所示的电流均衡的阵列电路。
本申请提供的多相变换器，可以执行上述电流均衡的阵列电路实施例所示的技术方案，其实现原理以及有益效果类似，此处不再进行赘述。

Claims (21)

  1. 一种电流均衡电路，其特征在于，包括：
    第一电感、第一电阻，所述第一电感的输出端与所述第一电阻的输入端连接，所述第一电阻的输出端接地，所述第一电阻的输入端与误差检测子电路的第一输入端连接；
    第二电感，第二电阻，所述第二电感的输出端分别与所述第一电感的输出端和所述第二电阻的输入端连接，所述第二电阻的输出端接地，所述第二电阻的输入端与所述误差检测子电路的第二输入端连接；
    所述误差检测子电路，所述误差检测子电路的第一输出端与第一误差调整子电路的第一输入端连接，所述误差检测子电路的第二输出端与所述第二误差调整子电路的第一输入端连接，所述误差检测子电路用于对所述误差检测子电路的第一输入端的电压与第二输入端的电压的差值进行放大处理；
    所述第一误差调整子电路，包括两个输入端，所述两个输入端分别用于接收预设输入信号和所述误差检测子电路第一输出端输入的电压信号，所述第一误差调整子电路用于根据所述预设输入信号和所述误差检测子电路第一输入端输入的电压信号调整所述第一电感的输入电流；
    所述第二误差调整子电路，包括两个输入端，所述两个输入端分别用于接收所述预设输入信号和所述误差检测子电路第二输出端输入的电压信号，所述第二误差调整子电路用于根据所述预设输入信号和所述误差检测子电路第二输入端输入的电压信号调整所述第二电感的输入电流。
  2. 根据权利要求1所述的电路，其特征在于，所述误差检测子电路包括：
    跨阻运算放大器、第三电阻和第四电阻；
    其中，所述跨阻运算放大器的第一输入端与所述第一电阻的输入端连接，所述跨阻运算放大器的第二输入端与所述第二电阻的输入端连接，所述跨阻运算放大器的第一输出端和所述第三电阻的输出端均与所述第一误差调整子电路的第一输入端连接；所述跨阻运算放大器的第二输出端和所述第四电阻的输出端均与所述第二误差调整子电路的第一输入端连接，所述第三电阻的输入端和所述第四电阻的输入端均输入预设电压信号。
  3. 根据权利要求1所述的电路，其特征在于，所述第一误差调整子电路包括：
    第一脉冲宽度调制PWM比较器、第一复位置位RS触发器及第一功率级调整子电路；
    其中，所述第一PWM比较器的第一输入端与所述误差检测子电路的第一输出端连接，所述第一PWM比较器的第二输入端输入预设输入信号，所述第一PWM比较器的输出端与所述第一RS触发器的第一输入端连接，所述第一RS触发器的第二输入端输入预设方波信号，所述第一RS触发器的第一输出端与所述第一功率级调整子电路的第一输入端连接，所述第一RS触发器的第二输出端与所述第一功率级调整子电路的第二输入端连接，所述第一功率级调整子电路的输出端与所述第一电感的输入端连接；
    所述第一功率级调整子电路用于根据所述第一RS触发器的第一输出端信号和所述第一RS触发器的第二输出端信号调整所述第一电感的输入电流。
  4. 根据权利要求1所述的电路，其特征在于，所述第二误差调整子电路包括：
    第二PWM比较器、第二RS触发器及第二功率级调整子电路；
    其中，所述第二PWM比较器的第一输入端与所述误差检测子电路的第一输出端连接，所述第二PWM比较器的第二输入端输入预设输入信号，所述第二PWM比较器的输出端与所述第二RS触发器的第一输入端连接，所述第二RS触发器的第二输入端输入预设方波信号，所述第二RS触发器的第一输出端与所述第二功率级调整子电路的第一输入端连接，所述第一RS触发器的第二输出端与所述第二功率级调整子电路的第二输入端连接，所述第二功率级调整子电路的输出端与所述第二电感的输入端连接；
    所述第二功率级调整子电路用于根据所述第二RS触发器的第一输出端信号和所述第二RS触发器的第二输出端信号调整所述第二电感的输入电流。
  5. 根据权利要求3所述的电路，其特征在于，所述第一功率级调整子电路包括：
    第一驱动子电路、第二驱动子电路、第一MOS管及第二MOS管；
    其中，所述第一驱动子电路的输入端与所述第一RS触发器的第一输出端连接，所述第一驱动子电路的输出端与所述第一MOS管的栅极连接，所述第二驱动子电路的输入端与所述第一RS触发器的第二输出端连接，所述第二驱动子电路的输出端与所述第二MOS管的栅极连接，所述第一MOS管的漏极和所述第二MOS管的源极均与所述第一电感的输入端连接，所述第一MOS管的源极接地，所述第二MOS管的漏极与第一电源连接。
  6. 根据权利要求4所述的电路，其特征在于，所述第二功率级调整子电路包括：
    第三驱动子电路、第四驱动子电路、第三MOS管及第四MOS管；
    其中，所述第三驱动子电路的输入端与所述第二RS触发器的第一输出端连接，所述第三驱动子电路的输出端与所述第三MOS管的栅极连接，所述第四驱动子电路的输入端与所述第二RS触发器的第二输出端连接，所述第四驱动子电路的输出端与所述第四MOS管的栅极连接，所述第三MOS管的漏极和所述第四MOS管的源极均与所述第二电感的输入端连接，所述第三MOS管的源极接地，所述第四MOS管的漏极与第二电源连接。
  7. 根据权利要求2所述的电路，其特征在于，还包括：
    第一电流检测子电路和第二电流检测子电路；
    其中，所述第一电流检测子电路的输入端与所述第一电感的输出端连接，所述第一电流检测子电路的输出端与所述第一电阻的输入端连接；所述第一电流检测子电路用于检测所述第一电感的采样电流，并对所述第一电感的采样电流进行缩放处理；
    所述第二电流检测子电路的输入端与所述第二电感的输出端连接，所述第二电流检测子电路的输出端分别与所述第一电流检测子电路的输出端和所述第二电阻的输入端连接；所述第二电流检测子电路用于检测所述第二电感的采样电流，并对所述第二电感的采样电流进行缩放处理。
  8. 根据权利要求7所述的电路，其特征在于，所述误差检测子电路还包括：
    电压调整子电路和输出电压反馈子电路；
    其中，所述电压调整子电路的输出端分别与所述第三电阻的输入端和所述第四电阻的输入端连接，所述电压调整子电路的第一输入端与所述输出电压反馈子电路的第 一输出端连接，所述电压调整子电路的第二输入端输入基准电压信号，所述输出电压反馈子电路的第二输出端接地，所述输出电压反馈子电路的第三输出端接地，所述输出电压反馈子电路的输入端分别与所述第一电流检测子电路的输出端和所述第二电流检测子电路的输出端连接；
    所述电压反馈子电路的输入端用于接收所述第一电感的电流信号和所述第二电感的电流信号，所述电压反馈子电路用于将所述第一电感的电流信号和所述第二电感的电流信号转换为电压信号，并对所述转换后的电压信号进行分压处理；
    所述电压调整子电路的输入端用于接收所述电压反馈子电路分压处理后的电压信号，并根据所述基准电压信号调整所述电压反馈子电路分压处理后的电压信号，以使所述电压调整子电路的输出端向所述第三电阻的输入端和第四电阻的输入端输入预设电压信号。
  9. 根据权利要求8所述的电路，其特征在于，所述电压调整子电路包括：
    误差放大器、第一阻抗网络、第二阻抗网络；
    其中，所述误差放大器的第一输入端分别与所述第一阻抗网络的输出端和所述第二阻抗网络的输入端连接，所述误差放大器的第二输入端输入基准电压信号，所述误差放大器和所述第二阻抗网络的输出端均与所述第三电阻的输入端和所述第四电阻的输入端连接，所述第一阻抗网络的输入端与所述输出电压反馈子电路的第一输出端连接。
  10. 根据权利要求8所述的电路，其特征在于，所述输出电压反馈子电路包括：
    第五电阻、第六电阻及电容；
    其中，所述第五电阻的输入端和所述电容的输入端均与所述第一电流检测子电路的输出端连接，且所述第五电阻的输入端和所述电容的输入端均与所述第二电流检测子电路的输出端连接，所述第五电阻的输出端分别与所述第六电阻的输入端和所述电压调整子电路的输入端连接，所述第六电阻的输出端接地，所述电容的输出端接地。
  11. 一种电流均衡的阵列电路，其特征在于，包括至少两个电流均衡电路单元，所述第一电流均衡电路单元和所述第二电流均衡电路单元为所述至少两个电流均衡电路单元中任意两个相邻的电流均衡电路单元，其中，所述第一电流均衡电子单元中的误差检测子电路中的第一输出端与所述第二电流均衡电子单元中的误差检测子电路中的第二输出端连接，其中，所述任一电流均衡电路单元包括：
    第一电感、第一电阻，所述第一电感的输出端与所述第一电阻的输入端连接，所述第一电阻的输出端接地，所述第一电阻的输入端与误差检测子电路的第一输入端连接；
    第二电感，第二电阻，所述第二电感的输出端分别与所述第一电感的输出端和所述第二电阻的输入端连接，所述第二电阻的输出端接地，所述第二电阻的输入端与所述误差检测子电路的第二输入端连接；
    所述误差检测子电路，所述误差检测子电路的第一输出端与第一误差调整子电路的第一输入端连接，所述误差检测子电路的第二输出端与所述第二误差调整子电路的第一输入端连接，所述误差检测子电路用于对所述误差检测子电路的第一输入端的电压与第二输入端的电压的差值进行放大处理；
    所述第一误差调整子电路，包括两个输入端，所述两个输入端分别用于接收预设输入信号和所述误差检测子电路第一输出端输入的电压信号，所述第一误差调整子电路用于根据所述预设输入信号和所述误差检测子电路第一输入端输入的电压信号调整所述第一电感的输入电流；
    所述第二误差调整子电路，包括两个输入端，所述两个输入端分别用于接收所述预设输入信号和所述误差检测子电路第二输出端输入的电压信号，所述第二误差调整子电路用于根据所述预设输入信号和所述误差检测子电路第二输入端输入的电压信号调整所述第二电感的输入电流。
  12. 根据权利要求11所述的阵列电路，其特征在于，所述误差检测子电路包括：
    跨阻运算放大器、第三电阻和第四电阻；
    其中，所述跨阻运算放大器的第一输入端与所述第一电阻的输入端连接，所述跨阻运算放大器的第二输入端与所述第二电阻的输入端连接，所述跨阻运算放大器的第一输出端和所述第三电阻的输出端均与所述第一误差调整子电路的第一输入端连接；所述跨阻运算放大器的第二输出端和所述第四电阻的输出端均与所述第二误差调整子电路的第一输入端连接，所述第三电阻的输入端和所述第四电阻的输入端均输入预设电压信号。
  13. 根据权利要求11所述的阵列电路，其特征在于，所述第一误差调整子电路包括：
    第一脉冲宽度调制PWM比较器、第一复位置位RS触发器及第一功率级调整子电路；
    其中，所述第一PWM比较器的第一输入端与所述误差检测子电路的第一输出端连接，所述第一PWM比较器的第二输入端输入预设输入信号，所述第一PWM比较器的输出端与所述第一RS触发器的第一输入端连接，所述第一RS触发器的第二输入端输入预设方波信号，所述第一RS触发器的第一输出端与所述第一功率级调整子电路的第一输入端连接，所述第一RS触发器的第二输出端与所述第一功率级调整子电路的第二输入端连接，所述第一功率级调整子电路的输出端与所述第一电感的输入端连接；
    所述第一功率级调整子电路用于根据所述第一RS触发器的第一输出端信号和所述第一RS触发器的第二输出端信号调整所述第一电感的输入电流。
  14. 根据权利要求11所述的阵列电路，其特征在于，所述第二误差调整子电路包括：
    第二PWM比较器、第二RS触发器及第二功率级调整子电路；
    其中，所述第二PWM比较器的第一输入端与所述误差检测子电路的第一输出端连接，所述第二PWM比较器的第二输入端输入预设输入信号，所述第二PWM比较器的输出端与所述第二RS触发器的第一输入端连接，所述第二RS触发器的第二输入端输入预设方波信号，所述第二RS触发器的第一输出端与所述第二功率级调整子电路的第一输入端连接，所述第一RS触发器的第二输出端与所述第二功率级调整子电路的第二输入端连接，所述第二功率级调整子电路的输出端与所述第二电感的输入端连接；
    所述第二功率级调整子电路用于根据所述第二RS触发器的第一输出端信号和所述第二RS触发器的第二输出端信号调整所述第二电感的输入电流。
  15. 根据权利要求13所述的阵列电路，其特征在于，所述第一功率级调整子电路 包括：
    第一驱动子电路、第二驱动子电路、第一MOS管及第二MOS管；
    其中，所述第一驱动子电路的输入端与所述第一RS触发器的第一输出端连接，所述第一驱动子电路的输出端与所述第一MOS管的栅极连接，所述第二驱动子电路的输入端与所述第一RS触发器的第二输出端连接，所述第二驱动子电路的输出端与所述第二MOS管的栅极连接，所述第一MOS管的漏极和所述第二MOS管的源极均与所述第一电感的输入端连接，所述第一MOS管的源极接地，所述第二MOS管的漏极与第一电源连接。
  16. 根据权利要求14所述的阵列电路，其特征在于，所述第二功率级调整子电路包括：
    第三驱动子电路、第四驱动子电路、第三MOS管及第四MOS管；
    其中，所述第三驱动子电路的输入端与所述第二RS触发器的第一输出端连接，所述第三驱动子电路的输出端与所述第三MOS管的栅极连接，所述第四驱动子电路的输入端与所述第二RS触发器的第二输出端连接，所述第四驱动子电路的输出端与所述第四MOS管的栅极连接，所述第三MOS管的漏极和所述第四MOS管的源极均与所述第二电感的输入端连接，所述第三MOS管的源极接地，所述第四MOS管的漏极与第二电源连接。
  17. 根据权利要求12所述的阵列电路，其特征在于，还包括：
    第一电流检测子电路和第二电流检测子电路；
    其中，所述第一电流检测子电路的输入端与所述第一电感的输出端连接，所述第一电流检测子电路的输出端与所述第一电阻的输入端连接；所述第一电流检测子电路用于检测所述第一电感的采样电流，并对所述第一电感的采样电流进行缩放处理；
    所述第二电流检测子电路的输入端与所述第二电感的输出端连接，所述第二电流检测子电路的输出端分别与所述第一电流检测子电路的输出端和所述第二电阻的输入端连接；所述第二电流检测子电路用于检测所述第二电感的采样电流，并对所述第二电感的采样电流进行缩放处理。
  18. 根据权利要求17所述的阵列电路，其特征在于，所述误差检测子电路还包括：
    电压调整子电路和输出电压反馈子电路；
    其中，所述电压调整子电路的输出端分别与所述第三电阻的输入端和所述第四电阻的输入端连接，所述电压调整子电路的第一输入端与所述输出电压反馈子电路的第一输出端连接，所述电压调整子电路的第二输入端输入基准电压信号，所述输出电压反馈子电路的第二输出端接地，所述输出电压反馈子电路的第三输出端接地，所述输出电压反馈子电路的输入端分别与所述第一电流检测子电路的输出端和所述第二电流检测子电路的输出端连接；
    所述电压反馈子电路的输入端用于接收所述第一电感的电流信号和所述第二电感的电流信号，所述电压反馈子电路用于将所述第一电感的电流信号和所述第二电感的电流信号转换为电压信号，并对所述转换后的电压信号进行分压处理；
    所述电压调整子电路的输入端用于接收所述电压反馈子电路分压处理后的电压信号，并根据所述基准电压信号调整所述电压反馈子电路分压处理后的电压信号，以使 所述电压调整子电路的输出端向所述第三电阻的输入端和第四电阻的输入端输入预设电压信号。
  19. 根据权利要求18所述的阵列电路，其特征在于，所述电压调整子电路包括：
    误差放大器、第一阻抗网络、第二阻抗网络；
    其中，所述误差放大器的第一输入端分别与所述第一阻抗网络的输出端和所述第二阻抗网络的输入端连接，所述误差放大器的第二输入端输入基准电压信号，所述误差放大器和所述第二阻抗网络的输出端均与所述第三电阻的输入端和所述第四电阻的输入端连接，所述第一阻抗网络的输入端与所述输出电压反馈子电路的第一输出端连接。
  20. 根据权利要求18所述的阵列电路，其特征在于，所述输出电压反馈子电路包括：
    第五电阻、第六电阻及电容；
    其中，所述第五电阻的输入端和所述电容的输入端均与所述第一电流检测子电路的输出端连接，且所述第五电阻的输入端和所述电容的输入端均与所述第二电流检测子电路的输出端连接，所述第五电阻的输出端分别与所述第六电阻的输入端和所述电压调整子电路的输入端连接，所述第六电阻的输出端接地，所述电容的输出端接地。
  21. 一种多相变换器，其特征在于，包括：
    上述权利要求11-20任一项所述的电流均衡的阵列电路。
PCT/CN2017/115337 2017-05-24 2017-12-08 电流均衡电路、阵列电路及多相变换器 WO2018214470A1 (zh)

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