WO2018211398A1 - Semiconductor device and electronic apparatus - Google Patents

Abstract

This semiconductor device (10) is provided with: a first layer (20); and a second layer (30) above the first layer, wherein the first layer has a control circuit (21), and the second layer has a storage circuit (MEM). The control circuit has a function of controlling the operation of the storage circuit, and the storage circuit has a plurality of memory cells (32), wherein the memory cells each has a first transistor (Tr1), a second transistor (Tr2), and a capacitive element (C1). Either a source or a drain of the first transistor is electrically connected to a gate of the second transistor and to the capacitive element, and the control circuit has a transistor formed on a semiconductor substrate. The first transistor and the second transistor have a metal oxide in a channel forming region, and the polarity of the first transistor and the polarity of the second transistor are the same.

Description

Semiconductor device and electronic equipment

One embodiment of the present invention relates to a semiconductor device and an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. Technical fields of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, and an input / output Devices, their driving methods, or their manufacturing methods can be cited as examples.

In this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A transistor, a semiconductor circuit, an arithmetic device, a memory device, or the like is one embodiment of a semiconductor device. In addition, a display device, an imaging device, an electro-optical device, a power generation device (including a thin film solar cell and an organic thin film solar cell), and an electronic device may include a semiconductor device.

Patent Document 1 describes a memory device including a transistor using an oxide semiconductor and a transistor using single crystal silicon. Further, it is described that a transistor including an oxide semiconductor has extremely small off-state current.

JP 2012-256400 A

An object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with a high degree of freedom in layout.

Note that one embodiment of the present invention does not necessarily have to solve all of the problems described above, and may be any that can solve at least one problem. Further, the description of the above problem does not disturb the existence of other problems. Issues other than these will be apparent from the description of the specification, claims, drawings, etc., and other issues will be extracted from the description of the specification, claims, drawings, etc. Is possible.

A semiconductor device according to one embodiment of the present invention includes a first layer and a second layer above the first layer, the first layer includes a control circuit, and the second layer Includes a memory circuit, the control circuit has a function of controlling the operation of the memory circuit, the memory circuit includes a plurality of memory cells and a driver circuit, and the memory cell includes a first transistor, A second transistor; and a capacitor, wherein one of a source and a drain of the first transistor is electrically connected to a gate and the capacitor of the second transistor, and the control circuit is formed over the semiconductor substrate The first transistor and the second transistor are semiconductor devices each including a metal oxide in a channel formation region.

In the semiconductor device according to one embodiment of the present invention, the driver circuit includes a first driver circuit and a second driver circuit, and the first driver circuit has a function of selecting a memory cell. The second driver circuit has a function of writing data to the memory cell and a function of reading data stored in the memory cell. The first driver circuit and the second driver circuit include a control circuit and The first driver circuit and the second driver circuit which are electrically connected may each include a transistor including a metal oxide in a channel formation region.

In the semiconductor device according to one embodiment of the present invention, the control circuit may include a clock generation circuit and a timing controller.

In the semiconductor device of one embodiment of the present invention, the first layer includes a processor, a peripheral circuit, and a power supply circuit, and the processor, the peripheral circuit, and the power supply circuit are formed over the semiconductor substrate. A transistor may be included.

Further, an electronic device according to one embodiment of the present invention is an electronic device including the above semiconductor device.

According to one embodiment of the present invention, a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with a high degree of freedom in layout can be provided.

Note that the description of these effects does not disturb the existence of other effects. Further, one embodiment of the present invention does not necessarily have all of these effects. Effects other than these will be apparent from the description of the specification, claims and drawings, and other effects will be extracted from the description of the specification, claims and drawings. Is possible.

FIG. 9 illustrates a configuration example of a semiconductor device. The figure which shows the structural example of a memory cell. FIG. 9 illustrates a configuration example of a semiconductor device. FIG. 9 illustrates a configuration example of a semiconductor device. FIG. 9 illustrates a configuration example of a semiconductor device. FIG. 9 illustrates a configuration example of a semiconductor device. FIG. 10 is a cross-sectional view illustrating a structure example of a semiconductor device. FIG. 10 is a cross-sectional view illustrating a structure example of a semiconductor device. 8A and 8B are a top view and a cross-sectional view illustrating a structure example of a semiconductor device. FIG. 10 is a cross-sectional view illustrating a structure example of a semiconductor device. FIG. 10 is a cross-sectional view illustrating a structure example of a semiconductor device. FIG. 10 is a cross-sectional view illustrating a structure example of a semiconductor device. 8A and 8B are a top view and a cross-sectional view illustrating a structure example of a semiconductor device. FIG. 10 is a cross-sectional view illustrating a structure example of a semiconductor device. FIG. 10 is a cross-sectional view illustrating a structure example of a semiconductor device. 8A and 8B are a top view and a cross-sectional view illustrating a structure example of a semiconductor device. FIG. 10 is a cross-sectional view illustrating a structure example of a semiconductor device. 8A and 8B are a top view and a cross-sectional view illustrating a structure example of a semiconductor device. FIG. 10 is a cross-sectional view illustrating a structure example of a semiconductor device. FIG. 9 illustrates a configuration example of an electronic device. FIG. 9 illustrates a configuration example of an electronic device. FIG. 9 illustrates a configuration example of an electronic device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the description in the following embodiments, and those skilled in the art can easily understand that the forms and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

In addition, in this specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, in the case where a metal oxide is used for a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide has at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor, or OS for short. Hereinafter, a transistor including a metal oxide in a channel formation region is also referred to as an OS transistor.

In addition, in this specification and the like, metal oxides having nitrogen may be collectively referred to as metal oxides. In addition, a metal oxide containing nitrogen may be referred to as a metal oxynitride. Details of the metal oxide will be described later.

In addition, in this specification and the like, when it is explicitly described that X and Y are connected, X and Y are electrically connected, and X and Y function. And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and things other than the connection relation shown in the figure or text are also described in the figure or text. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are directly connected, an element that enables electrical connection between X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.) Element, light emitting element, load, etc.) are not connected between X and Y, and elements (for example, switches, transistors, capacitive elements, inductors) that enable electrical connection between X and Y X and Y are not connected via a resistor element, a diode, a display element, a light emitting element, a load, or the like.

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in an on state or an off state, and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a current flow path. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

In addition, when it is explicitly described that X and Y are electrically connected, a case where X and Y are electrically connected (that is, there is a separate connection between X and Y). And X and Y are functionally connected (that is, they are functionally connected with another circuit between X and Y). And the case where X and Y are directly connected (that is, the case where another element or another circuit is not connected between X and Y). It shall be disclosed in the document. In other words, when it is explicitly described that it is electrically connected, the same contents as when it is explicitly described only that it is connected are disclosed in this specification and the like. It is assumed that

In addition, even in the case where independent components are illustrated as being electrically connected to each other in the drawing, one component may have the functions of a plurality of components. is there. For example, in the case where a part of the wiring also functions as an electrode, one conductive film has both the functions of the constituent elements of the wiring function and the electrode function. Therefore, the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.

In the drawings, the size, the layer thickness, or the region is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale. The drawings schematically show an ideal example, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, a layer or a resist mask may be lost unintentionally by a process such as etching, but may be omitted for easy understanding. In the drawings, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. In addition, in the case where the same function is indicated, the hatch pattern is the same, and there is a case where no reference numeral is given.

In particular, in a top view (also referred to as a “plan view”), a perspective view, and the like, some components may be omitted in order to facilitate understanding of the invention. Moreover, description of some hidden lines may be omitted.

In the present specification and the like, the ordinal numbers attached as the first, second, etc. are used for convenience and do not indicate the process order or the stacking order. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

Further, in this specification, terms indicating arrangement such as “above” and “below” are used for convenience in order to describe the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.

Note that the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in FIG. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as “effective channel width”) and the channel width (hereinafter “apparently” shown in the top view of the transistor). Sometimes referred to as “channel width”). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence may not be negligible. For example, in a fine transistor whose gate electrode covers a side surface of a semiconductor, the ratio of a channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width.

Note that in this specification and the like, a silicon oxynitride film has a higher oxygen content than nitrogen as its composition. For example, preferably oxygen is 55 atomic% to 65 atomic%, nitrogen is 1 atomic% to 20 atomic%, silicon is 25 atomic% to 35 atomic%, and hydrogen is 0.1 atomic% to 10 atomic%. It is included in the concentration range. The silicon nitride oxide film has a nitrogen content higher than that of oxygen. For example, preferably, nitrogen is 55 atomic% to 65 atomic%, oxygen is 1 atomic% to 20 atomic%, silicon is 25 atomic% to 35 atomic%, and hydrogen is 0.1 atomic% to 10 atomic%. It is included in the concentration range.

In addition, in this specification and the like, the terms “film” and “layer” can be interchanged. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

Further, in this specification and the like, the term “insulator” can be referred to as an insulating film or an insulating layer. In addition, the term “conductor” can be restated as a conductive film or a conductive layer. In addition, the term “semiconductor” can be restated as a semiconductor film or a semiconductor layer.

(Embodiment 1)
In this embodiment, a semiconductor device according to one embodiment of the present invention will be described. A semiconductor device according to one embodiment of the present invention has a structure in which a layer including a transistor formed over a semiconductor substrate and a layer including an OS transistor are stacked.

<Configuration Example 1 of Semiconductor Device>
FIG. 1 shows a configuration example of the semiconductor device 10. The semiconductor device 10 includes a layer 20 and a layer 30 stacked above the layer 20. The layer 20 has a control circuit 21 and the layer 30 has a memory circuit MEM. Note that an interlayer insulating layer can be provided between the layer 20 and the layer 30.

The control circuit 21 has a function of controlling the operation of the memory circuit MEM. Specifically, the control circuit 21 receives data to be written in the memory circuit MEM, an address signal that specifies an address of the memory circuit MEM that reads and writes data, and various control signals for controlling the operation of the memory circuit MEM. It has a function to supply.

The control signal output from the control circuit 21 includes a clock signal and a timing signal. The control circuit 21 includes a clock generation circuit having a function of generating a clock signal and a timing controller having a function of generating a timing signal.

The control circuit 21 is configured using transistors formed on the semiconductor substrate SUB. The semiconductor substrate SUB is not particularly limited as long as a channel formation region of a transistor can be formed in the vicinity of the surface of the substrate. For example, a single crystal silicon substrate, a single crystal germanium substrate, a compound semiconductor substrate (SiC substrate, GaN substrate, or the like), an SOI (Silicon On Insulator) substrate, or the like can be used. Further, the SOI substrate was formed by injecting oxygen ions into a mirror-polished wafer and then heating it at a high temperature to form an oxide layer at a certain depth from the surface and eliminate defects generated in the surface layer. Using a SIMOX (Separation by IMplanted OXygen) substrate, a smart cut method that cleaves a semiconductor substrate using heat treatment of microvoids formed by hydrogen ion implantation, an ELTRAN method (Epitaxial Layer Transfer: registered trademark), etc. A formed SOI substrate may be used. A transistor formed using a single crystal substrate includes a single crystal semiconductor in a channel formation region.

Hereinafter, as an example, a case where a single crystal silicon substrate is used as the semiconductor substrate SUB will be described. Hereinafter, a transistor formed over a single crystal silicon substrate is also referred to as a Si transistor.

The control circuit 21 is connected to the memory circuit MEM via the wiring CL that connects the layer 20 and the layer 30. The wiring CL is formed by a conductor formed in a contact hole between the layer 20 and the layer 30. The input / output of signals between the control circuit 21 and the memory circuit MEM is performed via the wiring CL.

The memory circuit MEM provided in the layer 30 includes a cell array 31, a drive circuit 33, and a drive circuit 34. The cell array 31 is composed of a plurality of memory cells 32 arranged in a matrix.

The memory cell 32 has a function of storing data. The memory cell 32 may have a function of storing binary (high level and low level) data, or may have a function of storing multilevel data of four or more values. The memory cell 32 may have a function of storing analog data.

The drive circuit 33 has a function of selecting the memory cell 32. Specifically, the drive circuit 33 has a function of supplying a signal for selecting a memory cell 32 from which data is written or read (hereinafter also referred to as a selection signal) to a wiring connected to the memory cell 32. .

The drive circuit 34 has a function of writing data to the memory cell 32 and a function of reading data stored in the memory cell 32. Specifically, the drive circuit 34 has a function of supplying a potential corresponding to data stored in the memory cell 32 (hereinafter also referred to as a write potential) to a wiring connected to the memory cell 32 in which data is written. Have. In addition, the drive circuit 34 has a function of reading a potential (hereinafter also referred to as a read potential) corresponding to data stored in the memory cell 32 and outputting the potential to the control circuit MEM via the wiring CL.

An address signal, a clock signal, a timing signal, and the like are input to the drive circuit 33 from the control circuit 21 provided in the layer 20 through the wiring CL. Then, the drive circuit 33 generates a selection signal using these signals. Note that the timing at which the selection signal is output from the drive circuit 33 is controlled by the timing signal input from the control circuit 21.

In addition, an address signal, a clock signal, a timing signal, data to be written in the memory cell 32, and the like are supplied from the control circuit 21 provided in the layer 20 to the drive circuit 34 through the wiring CL. Then, the drive circuit 34 generates a write potential using these signals. Note that the timing at which the write potential is output from the drive circuit 34 is controlled by the timing signal input from the control circuit 21.

In FIG. 1, one wiring CL connected to the drive circuit 33 and one wiring CL connected to the drive circuit 34 are illustrated, but each of these wirings CL is configured by a plurality of wirings. It may be.

The memory cell 32, the drive circuit 33, and the drive circuit 34 are configured by OS transistors. Since the band gap of an oxide semiconductor is 3.0 eV or more, the OS transistor has a small leakage current due to thermal excitation and an extremely small off-state current. Note that off-state current refers to current that flows between a source and a drain when a transistor is off. The oxide semiconductor used for the channel formation region of the transistor is preferably an oxide semiconductor containing at least one of indium (In) and zinc (Zn). As such an oxide semiconductor, an In-M-Zn oxide (the element M is typically Al, Ga, Y, or Sn) is typical. By reducing impurities such as moisture and hydrogen which are electron donors (donors) and reducing oxygen vacancies, the oxide semiconductor can be i-type (intrinsic) or substantially i-type. Such an oxide semiconductor can be referred to as a highly purified oxide semiconductor. Note that details of the OS transistor will be described in Embodiment 2.

The OS transistor is suitable as a transistor used for the memory cell 32 because the off-state current is extremely small. For example, the off-current per channel width of the OS transistor can be 100 zA / μm or less, 10 zA / μm or less, 1 zA / μm or less, or 10 yA / μm or less. By using the OS transistor for the memory cell 32, data stored in the memory cell 32 can be held for an extremely long time.

FIG. 2 shows a configuration example of the memory cell 32 using the OS transistor. A memory cell 32 illustrated in FIG. 2A includes a transistor Tr1, a transistor Tr2, and a capacitor C1. In the figure, the symbol “OS” indicates an OS transistor.

The gate of the transistor Tr1 is connected to the node a1, one of the source or the drain is connected to the gate of the transistor Tr2 and one electrode of the capacitor C1, and the other of the source or the drain is connected to the node a3. One of the source and the drain of the transistor Tr2 is connected to the node a4, and the other of the source and the drain is connected to the node a5. The other electrode of the capacitive element C1 is connected to the node a2. The nodes a1 and a2 are connected to the drive circuit 33 in FIG. 1, and the nodes a3 and a4 are connected to the drive circuit 34 in FIG. Note that a node connected to one of the source and the drain of the transistor Tr1, the gate of the transistor Tr2, and one electrode of the capacitor C1 is referred to as a node N1.

When writing data to the memory cell 32, a write potential is supplied to the node a3. In addition, by supplying a selection signal (high-level potential) to the node a1, the transistor Tr1 is turned on. As a result, the write potential is supplied to the node N1. After that, by supplying a low-level potential to the node a1, the transistor Tr1 is turned off. As a result, the node N1 enters a floating state, and the write potential is held.

When reading the data stored in the memory cell 32, the potential of the node a4 becomes the read potential. For example, the potential of the node a5 is fixed, and the node a4 is precharged and then brought into a floating state. At this time, a current according to the potential of the node N1 flows through the transistor Tr2. Therefore, the potential of the node a4 is determined according to the potential of the node N1. In this way, data stored in the memory cell 32 is read. Note that by supplying a predetermined potential to the node a2, the potential of the node N1 can be controlled and the memory cell 32 from which data is read can be selected.

Here, the transistor Tr1 is an OS transistor and has an extremely small off-state current. Therefore, the potential of the node N1 can be held for a very long period even during a period in which power is not supplied to the memory cell 32. That is, the memory cell 32 has a non-volatile characteristic. In this specification and the like, a memory circuit MEM in which a memory cell 32 is configured by a gain cell configured using an OS transistor as illustrated in FIG.

NOSRAM rewrites data by charging / discharging capacitive elements, so that in principle there is no restriction on the number of rewrites, and data can be written and read with low energy. Further, since the circuit configuration of the memory cell is simple, the capacity can be easily increased. Therefore, NOSRAM is a memory having a large capacity, low power consumption, and high rewrite resistance.

The transistor Tr2 is also composed of an OS transistor. That is, the memory cell 32 does not include a Si transistor and is configured by an n-channel OS transistor. In this way, a circuit constituted by transistors having the same polarity is hereinafter also referred to as a unipolar circuit.

Further, as shown in FIG. 2B, the memory cell 32 may include a transistor Tr3 that selects reading of data. In FIG. 2B, reading is performed when a high-level potential is supplied to the node a6 and the transistor Tr3 is turned on.

Some nodes of the memory cell 32 may be shared with other memory cells 32. For example, as shown in FIG. 2C, the node a3 can be shared between adjacent memory cells 32. In this case, the write potential of the adjacent memory cell 32 is supplied from a common wiring connected to the node a3.

Alternatively, the structure shown in FIG. 2D can be used as the memory cell 32. A memory cell 32 illustrated in FIG. 2D includes a transistor Tr4 and a capacitor C2.

The gate of the transistor Tr4 is connected to the node a7, one of the source and the drain is connected to one electrode of the capacitor C2, and the other of the source and the drain is connected to the node a8. The other electrode of the capacitive element C2 is connected to a node a9 to which a constant potential (for example, a low power supply potential) is supplied. Further, the node a7 is connected to the driving circuit 33 in FIG. 1, and the node a8 is connected to the driving circuit 34 in FIG. Note that a node connected to one of the source and the drain of the transistor Tr4 and the one electrode of the capacitor C2 is a node N2.

When writing data to the memory cell 32, a write potential is supplied to the node a8. Then, by supplying a selection signal (high-level potential) to the node a7, the transistor Tr4 is turned on. Thereby, the write potential is written to the node N2. After that, by supplying a low-level potential to the node a7, the transistor Tr4 is turned off. As a result, the node N2 enters a floating state, and the write potential is held.

When reading the data stored in the memory cell 32, the potential of the node a8 becomes the read potential. By supplying a selection signal (high level potential) to the node a7, the transistor Tr4 is turned on. Thereby, the potential of the node a8 is determined according to the potential of the node N2. In this way, data stored in the memory cell 32 is read.

Since an OS transistor is used as the transistor Tr4, the potential of the node N2 is held for an extremely long time. As a result, the frequency of data refresh can be extremely reduced, and the power consumption can be reduced. In this specification and the like, the memory circuit MEM in which the memory cell 32 includes the circuit illustrated in FIG. 2D is referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).

The drive circuit 33 and the drive circuit 34 shown in FIG. 1 are also configured by a unipolar circuit using an OS transistor, like the memory cell 32 described above. That is, the layer 30 includes the memory circuit MEM configured by a unipolar circuit using an OS transistor.

Here, for example, when the memory circuit MEM is configured using a p-channel Si transistor formed in the layer 20 and an n-channel OS transistor formed in the layer 30, these transistors are connected. For this purpose, a large number of connecting portions (contact holes and wirings) are required. In particular, when the plurality of memory cells 32 are configured using Si transistors and OS transistors, the connection between the layer 20 and the layer 30 is required in each memory cell 32, and the increase in the number of connection portions becomes more remarkable. This increase in the number of connecting portions causes a reduction in the degree of freedom in circuit layout.

Further, mixing of impurities (such as hydrogen) into the oxide semiconductor included in the OS transistor causes deterioration of the OS transistor. Here, the connection portion serves as an impurity path, and the impurity can enter the layer 30 through the connection portion. Therefore, when the connection portion between the layer 20 and the layer 30 is increased, impurities mixed in the oxide semiconductor are increased, and the OS transistor formed in the layer 30 is deteriorated.

In one embodiment of the present invention, the memory circuit MEM is configured by a unipolar circuit using an OS transistor. Therefore, the connection between the layer 20 and the layer 30 inside the memory circuit MEM is unnecessary. Specifically, predetermined information necessary for the operation of the entire memory circuit MEM, such as address signals, data, and various control signals, is supplied from the layer 20, but signals generated inside the memory circuit MEM are: Except for data that is finally output from the drive circuit 34 (read data of the memory circuit MEM), output to the layer 20 becomes unnecessary. As a result, the number of connection portions can be reduced, and the degree of freedom in circuit layout and the reliability of the OS transistor can be improved.

In particular, since a large number of memory cells 32 are provided, the number of connection portions can be greatly reduced by configuring the memory cells 32 with a unipolar circuit. Further, by providing the drive circuit 33 and the drive circuit 34 in the same layer as the cell array 31, a large number of wirings connecting the drive circuit 33 and the cell array 31 and the drive circuit 34 and the cell array 31 are provided in the layer 20 and the layer 30. Can be avoided, and the number of connecting portions can be further reduced.

Note that the control circuit 21 for controlling the memory circuit MEM is provided in the layer 20 and can be constituted by a CMOS circuit using a Si transistor or the like. Thereby, the high-speed and high-performance control circuit 21 can be configured, and the memory circuit MEM can be operated using the control circuit 21. For example, a clock generation circuit and a timing controller that can be used for the memory circuit MEM can be configured using Si transistors.

Further, a circuit other than the control circuit 21 can be provided in the layer 20. For example, as shown in FIG. 1, the layer 20 may include a processor 22, a peripheral circuit 23, and a power supply circuit 24. In this case, the processor 22, the peripheral circuit 23, and the power supply circuit 24 are configured using Si transistors.

As the processor 22, a CPU (Central Processor Unit), an MPU (Micro Processor Unit), a GPU (Graphics Processing Unit), or the like can be used. As the peripheral circuit 23, a memory circuit, an input / output circuit, a power management unit, a timer, a counter, a conversion circuit (an AD conversion circuit, a DA conversion circuit, or the like) can be used. A plurality of peripheral circuits 23 may be provided.

When a memory is used as a peripheral circuit, the memory may be a volatile memory such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), or a flash memory, a magnetic storage device (hard disk drive, magnetic memory, etc.) A non-volatile memory such as ROM (Read Only Memory) can be used. Moreover, it can also comprise using both a volatile memory and a non-volatile memory.

The control circuit 21, the processor 22, and the peripheral circuit 23 are connected to the bus BUS. Thereby, transmission / reception of data or signals among the control circuit 21, the processor 22, and the peripheral circuit 23 can be performed via the bus BUS. For example, data output from the memory circuit MEM to the control circuit 21 can be used for processing by the processor 22 or stored in a memory provided as the peripheral circuit 23.

The power supply circuit 24 has a function of supplying power to various circuits included in the layer 20. In addition, the power supply circuit 24 may have a function of supplying power to various circuits included in the layer 30 through a wiring provided between the layer 20 and the layer 30.

Although FIG. 1 shows a configuration in which the processor 22 and the peripheral circuit 23 are provided in the layer 20, these circuits can also be provided in the layer 30. In this case, the processor 22 and the peripheral circuit 23 are configured by a unipolar circuit using OS transistors.

As described above, in one embodiment of the present invention, the memory circuit MEM is formed using a unipolar circuit including an OS transistor, whereby the number of connection portions between the layers 20 and 30 can be reduced. . Note that the semiconductor device 10 can be used as a storage device, an arithmetic device, or the like.

Note that the structure in which the OS transistor is used for the circuit provided in the layer 30 is described above; however, a transistor in which a channel formation region is formed in a film containing a semiconductor material other than an oxide semiconductor can also be used. Examples of such a transistor include an amorphous silicon film, a microcrystalline silicon film, a polycrystalline silicon film, a single crystal silicon film, an amorphous germanium film, a microcrystalline germanium film, a polycrystalline germanium film, or a single crystal germanium. A transistor using a film as a semiconductor layer can be given.

<Configuration Example 2 of Semiconductor Device>
Although FIG. 1 shows a configuration example in which one layer 30 having the memory circuit MEM is provided on the layer 20, two or more layers 30 can be stacked on the layer 20. FIG. 3 shows a structure in which N layers (N is an integer of 2 or more) layers 30 (layers 30_1 to 30_N) are stacked on the layer 20. The layers 30_1 to 30_N include memory circuits MEM_1 to MEM_N, respectively. Note that the structures and functions of the memory circuits MEM_1 to MEM_N are similar to those of the memory circuit MEM in FIG.

Further, each of the memory circuits MEM_1 to MEM_N is connected to the control circuit 21 via the wiring CE. The wiring CE is a selection line of the memory circuit MEM, and the control circuit 21 supplies a selection signal to the wiring CE, thereby selecting the memory circuit MEM that supplies a control signal or the like from the memory circuits MEM_1 to MEM_N. Then, a control signal or the like is supplied to the selected memory circuit MEM via the wiring CL.

Thus, the amount of data stored in the semiconductor device 10 can be increased by stacking the memory circuits MEM.

1 shows a configuration example in which the layer 30 is provided above the layer 20 (circuit formation surface side), but the layer 30 is provided below the layer 20 (opposite side of the circuit formation surface). May be. FIG. 4 illustrates a structure in which a layer 30_1 is provided above the layer 20 and a layer 30_2 is provided below the layer 20. Note that one layer or two or more layers 30 may be further provided above the layer 30_1 and / or below the layer 30_2.

<Configuration Example 3 of Semiconductor Device>
Although FIG. 1 illustrates a configuration example in which the memory circuit MEM is provided in the layer 30, the circuit provided in the layer 30 is not limited to the memory circuit MEM. The layer 30 may be provided with a plurality of circuits having different functions. FIG. 5 illustrates a configuration example in which the layer 30 includes NOSRAM, DOSRAM, FPGA, and an analog arithmetic circuit. The layer 20 includes a control circuit 25, a control circuit 26, a control circuit 27, and a control circuit 28. The control circuit 25, the control circuit 26, the control circuit 27, and the control circuit 28 are connected to the bus BUS.

The control circuit 25 is connected to NOSRAM, and the control circuit 26 is connected to DOSRAM. The configurations and functions of the control circuit 25 and the control circuit 26 are the same as those of the control circuit 21 in FIG.

FPGA is a device that allows the user to arbitrarily change the circuit configuration. The change in the circuit configuration of the FPGA is performed by changing data (configuration data) stored in the configuration memory provided in the logic element of the FPGA and the switch between wirings.

The above configuration memory can be composed of a unipolar circuit using OS transistors. For example, the circuit configuration shown in FIGS. 2A and 2B can be used for the configuration memory.

The control circuit 27 is connected to the FPGA. Various control signals and data (configuration data, calculation input data, etc.) are output from the control circuit 27 to the FPGA, and the result of the calculation by the FPGA is output from the FPGA to the control circuit 27.

Analog operation circuit has a function to perform operations using analog data. This analog data is stored in an analog memory provided in the analog arithmetic circuit. The analog arithmetic circuit can be used for arithmetic operation of AI (Artificial Intelligence), for example. Specifically, the product-sum operation of the neural network can be performed by an analog operation circuit provided in the layer 30. By performing the product-sum operation using an analog operation circuit, the circuit scale can be reduced and the power consumption can be improved.

The analog memory provided in the analog arithmetic circuit can be composed of a unipolar circuit using an OS transistor. For example, the circuit configuration shown in FIGS. 2A and 2B can be used for the analog memory.

The control circuit 28 is connected to an analog arithmetic circuit. Various control signals and data (calculation input data and the like) are output from the control circuit 28 to the analog arithmetic circuit, and the arithmetic result is output from the analog arithmetic circuit to the control circuit 28.

5 shows a configuration example in which NOSRAM, DOSRAM, FPGA, and an analog arithmetic circuit are provided in the same layer 30, but these circuits may be provided in different layers 30, respectively.

<Configuration Example 4 of Semiconductor Device>
The semiconductor device 10 may have a function as an imaging device. FIG. 6 illustrates a configuration example of the semiconductor device 10 having a function as an imaging device. The semiconductor device 10 illustrated in FIG. 6 has a structure in which a layer 40 is further stacked above the layer 30 (see FIG. 1) including the memory circuit MEM.

The layer 40 has a light receiving part 41 constituted by a plurality of light receiving elements. The light receiving unit 41 has a function of converting the irradiated light into an electrical signal and outputting it as imaging data.

As the light receiving element, for example, a pn junction photodiode using a selenium-based material as a photoelectric conversion layer can be used. A photoelectric conversion element using a selenium-based material has high external quantum efficiency with respect to visible light, and can realize a highly sensitive photosensor.

Selenium-based material can be used as a p-type semiconductor. Examples of the selenium-based material include crystalline selenium such as single crystal selenium and polycrystalline selenium, amorphous selenium, copper, indium, selenium compound (CIS), or copper, indium, gallium, selenium compound (CIGS), etc. Can be used.

The n-type semiconductor of the pn junction photodiode is preferably formed of a material having a wide band gap and a light-transmitting property with respect to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or an oxide in which they are mixed can be used.

Further, as the light receiving element of the layer 40, a pn junction type photodiode composed of a p-type silicon semiconductor and an n-type silicon semiconductor may be used. Further, it may be a pin junction photodiode in which an i-type silicon semiconductor layer is provided between a p-type silicon semiconductor and an n-type silicon semiconductor.

The photodiode using silicon can be formed using single crystal silicon, amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like.

The layer 20 has a control circuit 29 connected to the light receiving unit 41. The imaging data acquired by the light receiving unit 41 is output to the control circuit 29.

The semiconductor device 10 shown in FIG. 6 can be used as a sensor built in a camera or the like.

This embodiment mode can be combined with any of the other embodiment modes as appropriate.

(Embodiment 2)
In this embodiment, a specific structural example of the semiconductor device described in the above embodiment will be described with reference to FIGS.

<Configuration example of semiconductor device>
7 to 11 are a top view and a cross-sectional view of a memory device including a transistor 300 (a transistor 300a, a transistor 300b, and a transistor 300c), a transistor 700, and a memory cell 600 according to one embodiment of the present invention. Here, the memory cell 600 includes the transistor 200, the transistor 500, and the capacitor 100.

FIG. 7 is a cross-sectional view of the memory device according to one embodiment of the present invention. The lower layer in which the transistor 300 (the transistor 300a, the transistor 300b, and the transistor 300c) is provided is the layer described in Embodiment 1. The upper layer in which the transistor 700 and the memory cell 600 are arranged corresponds to the layer 30 described in Embodiment 1. FIG. 8A is a cross-sectional view in the channel width direction of the transistor 700, which is a cross-sectional view in the channel length direction in FIG. 7. FIG. 8B is a cross-sectional view in the channel width direction of the transistor 300a, which is a cross-sectional view in the channel length direction in FIG. FIG. 9A is a top view of the memory cell 600. 9B, 10A, 10B, 11A, and 11B are cross-sectional views of the memory cell 600. FIG. Here, FIG. 9B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 9A and is a cross-sectional view in the channel length direction of the transistor 200 and in the channel width direction of the transistor 500. . 10A is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 9A and is a cross-sectional view in the channel width direction of the transistor 200. FIG. FIG. 10B is a cross-sectional view taken along dashed-dotted line A5-A6 in FIG. 9A and is a cross-sectional view in the channel length direction of the transistor 500. FIG. 11A is a cross-sectional view taken along the dashed-dotted line A7-A8 in FIG. 9A, and is also a cross-sectional view of one of the source region and the drain region of the transistor 200. FIG. 11B is a cross-sectional view taken along the dashed-dotted line A9-A10 in FIG. 9A and is the other cross-sectional view of the source region or the drain region of the transistor 200. Note that in the top view of FIG. 9A, some elements are omitted for clarity.

Here, the transistor 300 corresponds to the transistor provided in the layer 20, and in particular, the transistor 300 a corresponds to the transistor provided in the control circuit 21. The transistor 700 corresponds to a transistor provided in the drive circuit 33 or the drive circuit 34. The memory cell 600 corresponds to the memory cell 32, the transistor 200 corresponds to the transistor Tr1, the transistor 500 corresponds to the transistor Tr2, and the capacitor 100 corresponds to the capacitor C1.

First, a lower layer (a layer corresponding to the layer 20) of the semiconductor device described in this embodiment will be described. The transistor 300 includes a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 311, a low resistance region 314a which functions as a source region or a drain region, and a low resistance region 314b. Have. Each transistor 300 is electrically isolated by an insulator 321 functioning as an element isolation insulating layer. As the insulator 321, an insulator similar to the insulator 326 described later can be used.

In the transistor 300, as illustrated in FIG. 8B, the upper surface of the semiconductor region 313 and the side surface in the channel width direction are covered with a conductor 316 with an insulator 315 interposed therebetween. In this manner, when the transistor 300 is of the Fin type, an effective channel width is increased, so that the on-state characteristics of the transistor 300 can be improved. In addition, since the contribution of the electric field of the gate electrode can be increased, off characteristics of the transistor 300 can be improved.

The transistor 300 may be either a p-channel type or an n-channel type.

The region in which the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the low resistance region 314a that serves as the source region or the drain region, the low resistance region 314b, and the like preferably include a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

The low-resistance region 314a and the low-resistance region 314b provide an n-type conductivity element such as arsenic or phosphorus, or a p-type conductivity property such as boron, in addition to the semiconductor material used for the semiconductor region 313. Containing elements.

The conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron. A conductive material such as a material or a metal oxide material can be used.

Since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable from the viewpoint of heat resistance.

Note that the transistor 300 illustrated in FIGS. 7A and 7B is an example, and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

The insulator 320, the insulator 322, the insulator 324, and the insulator 326 are stacked in this order so as to cover the transistor 300.

As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. That's fine.

The insulator 322 may have a function as a planarization film that planarizes a step generated by the transistor 300 or the like provided thereunder. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.

The insulator 324 is preferably formed using a film having a barrier property such that hydrogen and impurities do not diffuse from the substrate 311 or the transistor 300 into a region where the transistor 200 is provided.

As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

The amount of desorption of hydrogen can be analyzed using, for example, a temperature programmed desorption gas analysis method (TDS). For example, the amount of hydrogen desorbed from the insulator 324 is calculated by converting the amount of desorption converted to hydrogen atoms per area of the insulator 324 in the range of the surface temperature of the film from 50 ° C. to 500 ° C. in TDS analysis. 10 × 10 ¹⁵ atoms / cm ² or less, preferably 5 × 10 ¹⁵ atoms / cm ² or less.

Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 326 is preferably equal to or less than 0.7 times, more preferably equal to or less than 0.6 times that of the insulator 324. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

The insulator 320, the insulator 322, the insulator 324, and the insulator 326 each have a function as a gate, a source, or a drain of the transistor 300 or a conductor 328 that functions as the wiring CL connected to the transistor 700. , And the conductor 330 and the like are embedded. Note that the conductor 328 and the conductor 330 function as plugs or wirings. In addition, a conductor having a function as a plug or a wiring may be given the same reference numeral by collecting a plurality of structures. In this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

As a material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or a stacked layer. Can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low-resistance conductive material.

A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 7, the insulator 350, the insulator 352, and the insulator 354 are sequentially stacked. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.

Note that as the insulator 350, an insulator having a barrier property against hydrogen is preferably used as in the case of the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 350 having a barrier property against hydrogen. With this structure, the layer including the transistor 300 and the layer including the transistor 700 can be separated by a barrier layer, so that diffusion of hydrogen from the layer including the transistor 300 to the layer including the transistor 700 can be suppressed.

For example, tantalum nitride may be used as the conductor having a barrier property against hydrogen. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

Further, a wiring layer having a similar structure may be provided over the insulator 354 and the conductor 356. The wiring layer similar to the wiring layer including the conductor 356 may be two or less, or the wiring layer similar to the wiring layer including the conductor 356 may be three or more.

An insulator 210, an insulator 212, an insulator 214, and an insulator 216 are sequentially stacked over the insulator 354. Any of the insulator 210, the insulator 212, the insulator 214, and the insulator 216 is preferably formed using a substance having a barrier property against oxygen or hydrogen. Note that details of the insulator 210, the insulator 212, the insulator 214, and the insulator 216 will be described later.

For example, the insulator 210 and the insulator 214 are preferably formed using a film having a barrier property so that hydrogen and impurities do not diffuse from a region where the substrate 311 or the transistor 300 is provided to a region where the transistor 200 is provided. . Therefore, a material similar to that of the insulator 324 can be used.

As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the layer including the transistor 700 and the layer including the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

Further, as the film having a barrier property against hydrogen, for example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 210 and the insulator 214.

In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200.

For example, the insulator 212 and the insulator 216 can be formed using the same material as the insulator 320. In addition, by using a material having a relatively low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 212 and the insulator 216, a silicon oxide film, a silicon oxynitride film, or the like can be used.

The insulator 210, the insulator 212, the insulator 214, and the insulator 216 include the conductor 218 and the conductors included in the transistor 200, the transistor 500, the transistor 700, and the like (eg, the conductor 703 and the conductor 705). Etc.) are embedded.

The insulator 220 and the insulator 222 are provided over the insulator 216, and layers such as the transistor 200, the transistor 500, and the transistor 700 are formed. An insulator 273, an insulator 274, and an insulator 280 are provided so as to cover the transistor 200, the transistor 500, the transistor 700, and the like. Here, detailed structures of the transistor 200, the transistor 500, the transistor 700, the insulator 220, the insulator 222, the insulator 273, the insulator 274, and the insulator 280 will be described later.

A conductor 745 is provided in an opening provided in the insulator 210, the insulator 212, the insulator 214, the insulator 216, the insulator 220, and the insulator 222. Note that the conductor 745 functions as a plug or a wiring for electrically connecting the transistor 700 and the transistor 300. The conductor 745 can be provided using a material similar to that of the conductor 328 and the conductor 330.

In particular, the insulator 210 and the conductor 745 in a region in contact with the insulator 214 are preferably conductors having a barrier property against oxygen, hydrogen, and water. With this structure, the layer including the transistor 300 and the layer including the transistor 700 are barrier layers against oxygen, hydrogen, and water and can be separated from the layer including the transistor 300 to the layer including the transistor 700. Diffusion of hydrogen can be suppressed.

A conductor 740a, a conductor 740b, a conductor 740c, and the like are provided in openings provided in the insulator 273, the insulator 274, and the insulator 280. The conductors 740a and 740c function as plugs or wirings that electrically connect the transistor 700 and the transistor 300. Detailed configurations of the conductor 740a, the conductor 740b, and the conductor 740c will be described later.

Note that an insulator having a barrier property against oxygen and hydrogen, which is the same as that of the insulator 214, is preferably provided over the insulator 280. For example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used as the insulator. Accordingly, impurities such as hydrogen and water can be prevented from diffusing from an upper layer than the insulator 280 to the transistor 200 side. By forming such a metal oxide by a sputtering method or the like, oxygen can be added to the insulator 280 and oxygen can be supplied to the oxide semiconductors in the transistor 200 and the transistor 700. In the case where an insulator having such a barrier property is provided over the insulator 280, either one or both of the insulator 273 and the insulator 274 may be omitted.

Alternatively, the insulator 150 may be provided over the insulator 280. The insulator 150 can be provided using a material similar to that of the insulator 280. Further, the insulator 150 may function as a planarization film that covers the concave and convex shapes below the insulator 150.

Further, it is preferable to provide the conductor 112 in the opening formed in the insulator 150. The conductor 112 functions as a wiring of the transistor 200, the transistor 500, the transistor 700, the capacitor 100, and the like. In addition, it is preferable to electrically connect the conductors 740a and 740c using the conductor 112.

The conductor 112 includes a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above-described elements (a tantalum nitride film, A titanium nitride film, a molybdenum nitride film, a tungsten nitride film, or the like can be used. Or indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide.

As shown in FIG. 7, the conductor 112 may have a laminated structure of two or more layers. For example, a conductor having a high barrier property and a conductor having a high barrier property may be formed between a conductor having a barrier property and a conductor having a high conductivity. Note that the conductor 112 is not limited to this, and may have a single-layer structure, for example.

Here, one of a source and a drain of the transistor 300a includes the source of the transistor 700 through the conductor 328, the conductor 330, the conductor 356, the conductor 745, the conductor 740c, the conductor 112, the conductor 740a, and the like. It is electrically connected to one of the drains. This series of wirings corresponds to the wiring CL described in the above embodiment.

As shown in FIG. 7, in the semiconductor device described in this embodiment, the layer corresponding to the layer 20 and the layer corresponding to the layer 30 are connected by only a part of wiring. Thereby, the number of connection portions between the layer corresponding to the layer 20 and the layer corresponding to the layer 30 can be greatly reduced. Thus, diffusion of impurities such as hydrogen into the transistor 200, the transistor 500, the transistor 700, and the like can be suppressed through the connection portion.

With the above structure, in a semiconductor device including a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved.

The layers corresponding to the layer 30 of the semiconductor device described in this embodiment are the transistor 200, the transistor 500, the transistor 700, the capacitor 100, the insulator 210 functioning as an interlayer film, the insulator 212, and the insulator 273. , An insulator 274, and an insulator 280. In addition, the semiconductor device 200 includes a conductor 203 which is electrically connected to the transistor 200 and functions as a wiring, and a conductor 240a which functions as a plug. In addition, a conductor 503 which is electrically connected to the transistor 500 and functions as a wiring, and a conductor 540a and a conductor 540b which function as plugs are included. In addition, a conductor 703 which is electrically connected to the transistor 700 and functions as a wiring, and a conductor 740a, a conductor 740b, and a conductor 740c which function as plugs are included. In addition, the conductor 240b is electrically connected to the capacitor 100 and functions as a plug. Hereinafter, the conductor 240a and the conductor 240b may be collectively referred to as the conductor 240. Note that the conductor 540a and the conductor 540b may be collectively referred to as the conductor 540 below. Note that the conductor 740a, the conductor 740b, and the conductor 740c may be collectively referred to as the conductor 740 below. Here, the conductor 503 and the conductor 703 are formed in the same layer as the conductor 203, and the conductor 540 and the conductor 740 are formed in the same layer as the conductor 240, and have the same structure. Therefore, the description of the conductor 203 can be referred to for the conductor 503 and the conductor 703, and the conductor 240 can be referred to for the conductor 540 and the conductor 740.

Note that the conductor 203 is in contact with the inner wall of the opening of the insulator 212, the first conductor of the conductor 203 is formed, and the second conductor of the conductor 203 is further formed inside. Here, the height of the upper surface of the conductor 203 and the height of the upper surface of the insulator 212 can be approximately the same. Note that although a structure in which the first conductor of the conductor 203 and the second conductor of the conductor 203 are stacked is described in this embodiment, the present invention is not limited to this. For example, the conductor 203 may be provided as a single layer or a stacked structure including three or more layers. Moreover, when a structure has a laminated structure, an ordinal number may be given in the order of formation to be distinguished. Note that the conductor 503 and the conductor 703 also have a structure similar to that of the conductor 203.

The insulator 273 is disposed over the transistor 200, the transistor 500, the transistor 700, and the capacitor 100. The insulator 274 is disposed on the insulator 273. Insulator 280 is disposed on insulator 274.

Further, the conductor 240 is formed in contact with the inner walls of the openings of the insulator 273, the insulator 274, and the insulator 280. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 280 can be approximately the same. Note that although a structure in which the conductor 240 has a two-layer structure is shown in this embodiment mode, the present invention is not limited to this. For example, the conductor 240 may be a single layer or a stacked structure of three or more layers. Note that the conductor 540 and the conductor 740 have a structure similar to that of the conductor 240.

As illustrated in FIGS. 9 and 10A, the transistor 200 is embedded in the insulator 214 and the insulator 216 which are disposed over the substrate (not illustrated), and the insulator 214 and the insulator 216. , The insulator 216, the insulator 220 disposed on the conductor 205, the insulator 222 disposed on the insulator 220, and the insulator 222. Insulator 224, oxide 230 (oxide 230a, oxide 230b, and oxide 230c) disposed over insulator 224, insulator 250 disposed over oxide 230, and insulator 250 Metal oxide 252 disposed on top, conductor 260 (conductor 260a and conductor 260b) disposed on metal oxide 252, and insulator 270 disposed on conductor 260 Formed over the oxide 230, the insulator 271 disposed over the insulator 270, the insulator 275 disposed in contact with at least the oxide 230c, the insulator 250, the metal oxide 252, and the side surfaces of the conductor 260 Layer 242. In addition, the conductor 240a is disposed in contact with one of the layers 242.

In the transistor 200, one of the layers 242 functions as one of a source and a drain, the other of the layers 242 functions as the other of a source and a drain, the conductor 260 functions as a front gate, and the conductor 205 functions as a back gate. To do.

9 and 10B, the transistor 500 is embedded in the insulator 214 and the insulator 216 which are provided over a substrate (not shown), and the insulator 214 and the insulator 216. A conductor 505 disposed on the insulator 216, an insulator 220 disposed on the conductor 505, an insulator 222 disposed on the insulator 220, and disposed on the insulator 222. Insulator 524, oxide 530 (oxide 530a, oxide 530b, and oxide 530c) disposed over insulator 524, insulator 550 disposed over oxide 530, and insulation Metal oxide 552 disposed on body 550, conductor 560 (conductor 560a and conductor 560b) disposed on metal oxide 552, and insulator 5 disposed on conductor 560 0, an insulator 571 disposed over the insulator 570, an insulator 575 disposed in contact with side surfaces of at least the oxide 530c, the insulator 550, the metal oxide 552, and the conductor 560, and the oxide 530 A layer 542 formed thereon. In addition, the conductor 540a is disposed in contact with one of the layers 542, and the conductor 540b is disposed in contact with the other of the layers 542.

In the transistor 500, one of the layers 542 functions as one of a source and a drain, the other of the layers 542 functions as the other of a source and a drain, the conductor 560 functions as a front gate, and the conductor 505 functions as a back gate. To do.

Here, the transistor 500 is formed in the same layer as the transistor 200 and has the same configuration. Therefore, the oxide 530 has a structure similar to that of the oxide 230, and the description of the oxide 230 can be referred to. The conductor 505 has a structure similar to that of the conductor 205, and the description of the conductor 205 can be referred to. The insulator 524 has a structure similar to that of the insulator 224, and the description of the insulator 224 can be referred to. The insulator 550 has a structure similar to that of the insulator 250, and the description of the insulator 250 can be referred to. The metal oxide 552 has a structure similar to that of the metal oxide 252, and the description of the metal oxide 252 can be referred to. The conductor 560 has a structure similar to that of the conductor 260, and the description of the conductor 260 can be referred to. The insulator 570 has a structure similar to that of the insulator 270, and the description of the insulator 270 can be referred to. The insulator 571 has a structure similar to that of the insulator 271, and the description of the insulator 271 can be referred to. The insulator 575 has a structure similar to that of the insulator 275, and the description of the insulator 275 can be referred to. In the following description, the description of the structure of the transistor 200 can be referred to for the structure of the transistor 500 as described above unless otherwise specified.

As illustrated in FIGS. 7 and 8A, the transistor 700 is embedded in the insulator 214 and the insulator 216 which are provided over a substrate (not illustrated), and the insulator 214 and the insulator 216. A conductor 705 disposed on the insulator 216, an insulator 220 disposed on the conductor 705, an insulator 222 disposed on the insulator 220, and disposed on the insulator 222. Insulator 724, oxide 730 disposed on insulator 724 (oxide 730a, oxide 730b, and oxide 730c), insulator 750 disposed on oxide 730, and insulation Metal oxide 752 disposed over body 750, conductor 760 (conductor 760 a and conductor 760 b) disposed over metal oxide 752, and insulator 77 disposed over conductor 760. An insulator 771 disposed over the insulator 770, at least the oxide 730c, the insulator 750, the metal oxide 752, and the insulator 775 disposed in contact with the side surfaces of the conductor 760; And a layer 742 formed on the substrate. In addition, the conductor 740a is disposed in contact with one of the layers 742, and the conductor 740b is disposed in contact with the other of the layers 742.

In the transistor 700, one of the layers 742 functions as one of a source and a drain, the other of the layer 742 functions as the other of the source and the drain, the conductor 760 functions as a front gate, and the conductor 705 functions as a back gate. To do.

Here, the transistor 700 is formed in the same layer as the transistor 200 and has a similar structure. Therefore, the oxide 730 has a structure similar to that of the oxide 230, and the description of the oxide 230 can be referred to. The conductor 705 has a structure similar to that of the conductor 205, and the description of the conductor 205 can be referred to. The insulator 724 has a structure similar to that of the insulator 224, and the description of the insulator 224 can be referred to. The insulator 750 has a structure similar to that of the insulator 250, and the description of the insulator 250 can be referred to. The metal oxide 752 has a structure similar to that of the metal oxide 252, and the description of the metal oxide 252 can be referred to. The conductor 760 has a structure similar to that of the conductor 260, and the description of the conductor 260 can be referred to. The insulator 770 has a structure similar to that of the insulator 270, and the description of the insulator 270 can be referred to. The insulator 771 has a structure similar to that of the insulator 271, and the description of the insulator 271 can be referred to. The insulator 775 has a structure similar to that of the insulator 275, and the description of the insulator 275 can be referred to. In the following description, the description of the structure of the transistor 200 can be referred to for the structure of the transistor 700 as described above unless otherwise specified.

Note that although the transistor 200 has a structure in which three layers of the oxide 230a, the oxide 230b, and the oxide 230c are stacked, the present invention is not limited to this. For example, a structure in which a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers may be employed. The same applies to the oxide 530 of the transistor 500 and the oxide 730 of the transistor 700. In the transistor 200, the structure in which the conductors 260a and 260b are stacked is described; however, the present invention is not limited to this. The same applies to the conductor 560 of the transistor 500 and the conductor 760 of the transistor 700.

The capacitor element 100 includes a conductor 110, an insulator 130 on the conductor 110, and a conductor 120 on the insulator 130. The conductor 120 is preferably disposed so that at least a part thereof overlaps the conductor 110 with the insulator 130 interposed therebetween. In addition, a conductor 240b is disposed on and in contact with the conductor 120. The conductor 110 is in contact with the layer 242 functioning as one of the source and the drain of the transistor 200 and in contact with the conductor 560 through the openings of the insulator 570 and the insulator 571.

In the capacitor element 100, the conductor 110 functions as one of the electrodes, and the conductor 120 functions as the other of the electrodes. Further, the insulator 130 functions as a dielectric of the capacitor 100. Here, the conductor 110 is connected to one of the source and the drain of the transistor 200 and the gate of the transistor 500, and functions as the node N1.

As shown in FIG. 9A, a part of the capacitor 100 is formed so as to overlap with the transistor 200 or the transistor 500. Thus, the total projected area of the transistor 200, the transistor 500, and the capacitor 100 can be reduced, and the occupied area of the memory cell 600 can be reduced. Therefore, miniaturization and high integration of the semiconductor device are facilitated. Further, since the transistor 200 and the transistor 500 can be formed in the same process, the process can be shortened and productivity can be improved.

Note that in the memory cell 600, the transistor 200, the transistor 500, and the capacitor 100 are provided so that the channel length direction of the transistor 200 and the channel length direction of the transistor 500 are orthogonal to each other; however, the semiconductor device described in this embodiment It is not limited to this. A memory cell 600 illustrated in FIGS. 1A and 1B is an example of a structure of a semiconductor device, and a transistor having an appropriate structure may be provided as appropriate depending on a circuit structure or a driving method.

Next, details of the oxide 230 used for the transistor 200 will be described. In the following description, the oxide 230 is referred to for the oxide 530 of the transistor 500 and the oxide 730 of the transistor 700 unless otherwise specified. The transistor 200 includes a metal oxide that functions as an oxide semiconductor in an oxide 230 (an oxide 230a, an oxide 230b, and an oxide 230c) including a region where a channel is formed (hereinafter also referred to as a channel formation region). (Hereinafter also referred to as an oxide semiconductor) is preferably used.

Since the transistor 200 using an oxide semiconductor in a channel formation region has extremely small leakage current in a non-conduction state, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for the transistor 200 included in a highly integrated semiconductor device.

For example, the oxide 230 includes an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium) It is preferable to use a metal oxide such as one or a plurality selected from hafnium, tantalum, tungsten, or magnesium. Further, as the oxide 230, an In—Ga oxide or an In—Zn oxide may be used.

Here, an oxide semiconductor forms a metal compound by adding a metal element such as aluminum, ruthenium, titanium, tantalum, chromium, or tungsten in addition to the elements included in the oxide semiconductor, and has low resistance. Turn into. Note that aluminum, titanium, tantalum, tungsten, or the like is preferably used.

In order to add a metal element to an oxide semiconductor, for example, a metal film containing the metal element, a nitride film containing the metal element, or an oxide film containing the metal element is preferably provided over the oxide semiconductor. In addition, by providing the film, part of oxygen in the oxide semiconductor located at or near the interface between the film and the oxide semiconductor is absorbed by the film, and oxygen vacancies are formed. The vicinity of the interface may be reduced in resistance.

Further, after a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is provided over the oxide semiconductor, heat treatment may be performed in an atmosphere containing nitrogen. By heat treatment in an atmosphere containing nitrogen, a metal element which is a component of the film is converted into an oxide semiconductor or a component of an oxide semiconductor from a metal film, a nitride film containing a metal element, or an oxide film containing a metal element. A certain metal element diffuses into the film, and the oxide semiconductor and the film form a metal compound, so that resistance can be reduced. The metal element added to the oxide semiconductor is in a relatively stable state by forming a metal compound with the oxide semiconductor, the metal element, and thus a highly reliable semiconductor device can be provided.

Further, a compound layer (hereinafter also referred to as a different layer) may be formed at the interface between the metal film, the nitride film containing a metal element, or the oxide film containing a metal element and the oxide semiconductor. Note that a compound layer (different layer) is a layer having a metal compound including a metal film, a nitride film containing a metal element, or a component of an oxide film containing a metal element and a component of an oxide semiconductor. For example, a layer in which a metal element of an oxide semiconductor and an added metal element are alloyed may be formed as the compound layer. The alloyed layer is in a relatively stable state, and a highly reliable semiconductor device can be provided.

In addition, hydrogen existing in the oxide semiconductor diffuses into a region where the resistance of the oxide semiconductor is reduced, and becomes relatively stable when it enters oxygen vacancies existing in the region where the resistance is reduced. In addition, hydrogen in oxygen vacancies present in the oxide semiconductor escapes from the oxygen vacancies by heat treatment at 250 ° C. or higher, diffuses into the low-resistance region of the oxide semiconductor, and exists in the low-resistance regions. Has been found to be relatively stable. Accordingly, a region where the resistance of the oxide semiconductor is reduced by heat treatment, or a region where the metal compound is formed is further reduced in resistance, and an oxide semiconductor which is not reduced in resistance is highly purified (impurities such as water or hydrogen). There is a tendency to increase resistance.

In addition, in an oxide semiconductor, the carrier density increases when an impurity element such as hydrogen or nitrogen is present. In some cases, hydrogen in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, thereby forming oxygen vacancies. When hydrogen enters the oxygen vacancy, the carrier density increases. In addition, part of hydrogen may combine with oxygen bonded to a metal atom to generate an electron that is a carrier. That is, the resistance of an oxide semiconductor containing nitrogen or hydrogen is reduced.

Therefore, by selectively adding a metal element and an impurity element such as hydrogen and nitrogen to an oxide semiconductor, a high-resistance region and a low-resistance region can be provided in the oxide semiconductor. That is, by selectively reducing the resistance of the oxide 230, the oxide 230 processed into an island shape has a low resistance that functions as a region having a low carrier density and functioning as a source region or a drain region. A region can be provided.

Here, an enlarged view of a region 239 surrounded by a broken line in FIG. 9B is shown in FIG. As shown in FIG. 12, the region 239 includes an oxide 230 b that is selectively reduced in resistance.

As illustrated in FIG. 12, the oxide 230 includes a region 234 that functions as a channel formation region of a transistor, a region 231 (a region 231 a and a region 231 b) that functions as a source region or a drain region, a region 234, and a region 231. And a region 232 (region 232a and region 232b) provided between the two.

The region 231 functioning as a source region or a drain region is a region having a low oxygen concentration and a low resistance. The region 234 functioning as a channel formation region is a high-resistance region having a higher oxygen concentration and a lower carrier density than the region 231 functioning as a source region or a drain region. The region 232 has a higher oxygen concentration and a lower carrier density than the region 231 functioning as a source region or a drain region, and a lower oxygen concentration and a carrier density than the region 234 functioning as a channel formation region. It is a high area.

Note that the region 231 preferably has a higher concentration of at least one of the metal element and impurity elements such as hydrogen and nitrogen than the region 232 and the region 234.

For example, the region 231 may include any one or more metal elements selected from metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium in addition to the metal element included in the oxide 230. preferable.

In order to form the region 231, for example, a film containing a metal element may be provided in contact with the region 231 of the oxide 230. The film containing the metal element is patterned into an island shape after the region 231 is formed, so that the conductor 110 is formed. Note that as the film containing the metal element, a metal film, an oxide film containing a metal element, or a nitride film containing a metal element can be used. At that time, a layer 242 may be formed at the interface between the metal element-containing film and the oxide 230. For example, the layer 242 may be formed on the top and side surfaces of the oxide 230. Note that the layer 242 is a layer including a metal compound including a component of the film including the metal element and a component of the oxide 230 and can also be referred to as a compound layer. For example, as the layer 242, a layer in which the metal element in the oxide 230 and the added metal element are alloyed may be formed.

By adding a metal element to the oxide 230, a metal compound is formed in the oxide 230, and the resistance of the region 231 can be reduced. Note that the metal compound is not necessarily formed in the oxide 230. For example, a metal compound may be formed on the film containing the metal element (conductor 110). Further, for example, the layer 242 may be provided on the surface of the oxide 230, the surface of the conductor 110, or the interface between the conductor 110 and the oxide 230.

Therefore, the region 231 may also include the low resistance region of the layer 242. Thus, at least part of the layer 242 may function as the source region or the drain region of the transistor 200 in some cases.

The region 232 has a region overlapping with the insulator 275. The region 232 preferably has a higher concentration of at least one of a metal element such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium and an impurity element such as hydrogen and nitrogen than the region 234. For example, when the film containing the metal element is provided in contact with the region 231 of the oxide 230, the component in the film containing the metal element and the component of the oxide semiconductor may form a metal compound. . The metal compound may attract hydrogen contained in the oxide 230 in some cases. Therefore, the concentration of hydrogen in the region 232 in the vicinity of the region 231 may increase.

Note that one or both of the region 232 a and the region 232 b may have a region overlapping with the conductor 260.

In FIG. 12, the region 234, the region 231, and the region 232 are formed in the oxide 230b, but the present invention is not limited to this. For example, these regions may also be formed in the layer 242, the oxide 230a, and the oxide 230c. In FIG. 12, the boundaries of the regions are displayed substantially perpendicular to the upper surface of the oxide 230, but this embodiment is not limited to this. For example, the region 232 may protrude toward the conductor 260 near the surface of the oxide 230b and recede toward the conductor 240a or the conductor 240b near the lower surface of the oxide 230b.

In addition, in the oxide 230, it may be difficult to clearly detect the boundary of each region. The concentration of the metal element detected in each region and the impurity elements such as hydrogen and nitrogen is not limited to a stepwise change for each region, but continuously changes (also referred to as gradation) in each region. May be. That is, the closer to the channel formation region, the lower the concentration of the metal element and impurity elements such as hydrogen and nitrogen.

In order to selectively reduce the resistance of the oxide 230, for example, at least one of a metal element that increases conductivity, such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium, and an impurity is added to a desired region. That's fine. Note that as the impurity, an element that forms oxygen vacancies, an element that is captured by oxygen vacancies, or the like may be used. Examples of the element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and a rare gas element. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon.

The region 231 can have high carrier density and low resistance by increasing the content of the above-described metal element that increases conductivity, an element that forms oxygen vacancies, or an element that is trapped by oxygen vacancies. it can.

In order to reduce the resistance of the region 231, for example, a film containing the above metal element may be formed in contact with the region 231 of the oxide 230. As the film including the metal element, a metal film, an oxide film including a metal element, a nitride film including a metal element, or the like can be used. The film containing the metal element is preferably provided over the oxide 230 with the insulator 250, the metal oxide 252, the conductor 260, the insulator 270, the insulator 271, and the insulator 275 interposed therebetween. Note that the film containing the metal element may have a thickness greater than or equal to 10 nm and less than or equal to 200 nm. The film containing a metal element is a film containing a metal element such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium. Note that the film containing the metal element can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

When the oxide 230 and the film containing the metal element are in contact with each other, the component of the film containing the metal element and the component of the oxide 230 form a metal compound, which becomes a region 231 and lowers resistance. In addition, part of oxygen in the oxide 230 located near or in the vicinity of the interface between the oxide 230 and the film containing the metal element is absorbed by the layer 242, and oxygen vacancies are formed in the oxide 230. The region 231 may be formed by resistance.

Further, heat treatment may be performed in an atmosphere containing nitrogen in a state where the oxide 230 is in contact with the film containing the metal element. By the heat treatment, the metal element which is a component of the film having the metal element is changed from the film having the metal element to the oxide 230, or the metal element which is a component of the oxide 230 is changed to the film having the metal element. When diffused, the oxide 230 and the film containing the metal element form a metal compound, which reduces resistance. In this manner, the layer 242 is formed between the oxide 230 and the film containing the metal element. At that time, the metal element of the oxide 230 and the metal element of the film containing the metal element may be alloyed. Thus, layer 242 may include an alloy. The alloy is in a relatively stable state and can provide a highly reliable semiconductor device.

The heat treatment may be performed at, for example, 250 ° C. or more and 650 ° C. or less, preferably 300 ° C. or more and 500 ° C. or less, more preferably 320 ° C. or more and 450 ° C. or less. Note that the heat treatment is performed in a nitrogen or inert gas atmosphere. Further, the heat treatment may be performed in a reduced pressure state. Further, after heat treatment in a nitrogen or inert gas atmosphere, heat treatment may be performed in an atmosphere containing an oxidizing gas.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters into oxygen vacancies existing in the region 231, a relatively stable state is obtained. Further, hydrogen in the oxygen vacancy existing in the region 234 escapes from the oxygen vacancy by heat treatment at 250 ° C. or higher, diffuses into the region 231, enters the oxygen vacancy existing in the region 231, and is in a relatively stable state. Become. Therefore, by the heat treatment, the region 231 has a lower resistance, and the region 234 has a higher purity (reduction of impurities such as water or hydrogen) and has a higher resistance.

On the other hand, part of the oxide 230 (the region 234 and the region 232) overlaps with the conductor 260 and the insulator 275, so that the addition of a metal element is suppressed. Further, in the region 234 and the region 232 of the oxide 230, oxygen in the oxide 230 is suppressed from being absorbed into the above-described film containing the metal element.

In addition, oxygen vacancies may be generated in the region 231 and the region 232 due to absorption of oxygen in the region 231 of the oxide 230 and the region 232 adjacent to the region 231 in the film containing the metal element. As hydrogen in the oxide 230 enters the oxygen vacancies, the carrier density in the region 231 and the region 232 increases. Accordingly, the resistance of the region 231 and the region 232 of the oxide 230 is reduced.

Here, when the film containing the metal element has a characteristic of absorbing hydrogen, hydrogen in the oxide 230 is absorbed into the film. Therefore, hydrogen which is an impurity in the oxide 230 can be reduced. Since the film containing the metal element is later patterned into the conductor 110, most of the hydrogen absorbed from the oxide 230 is removed.

After forming the layer 242, a part of the film containing the metal element is removed to form the island-shaped conductor 110. When the thickness of the film containing the metal element is sufficiently large, for example, about 10 nm to 200 nm, sufficient conductivity can be given to the conductor 110. Therefore, similarly to the film containing the metal element, the conductor 110 preferably has a thickness of 10 nm to 200 nm, and preferably includes a metal element such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium. The conductor 110 may be an oxide film containing a metal element or a nitride film containing a metal element.

A layer 242 is formed between the conductor 110 and the oxide 230. In the layer 242, the metal element of the film containing the metal element and the metal element of the oxide 230 may be alloyed in some cases, and the resistance between the conductor 110 and the region 231b may be reduced.

As shown in FIG. 9B, the conductor 110 is in contact with the conductor 560 functioning as the gate of the transistor 500 through the openings of the insulator 570 and the insulator 571. By using the conductor 110 having sufficient conductivity in this manner, conductivity between the transistor 200 and the transistor 500 can be improved, and a charge corresponding to data can be accurately held in the node N1. Further, since the transistor 200 and the transistor 500 can be formed in the same layer and connected by the conductor 110 in this way, an extra plug is formed, so that the transistor 200 and the transistor 500 formed in the upper layer or the lower layer can be formed. It is not necessary to connect. Accordingly, the number of plugs formed in the layer where the transistor 200 and the transistor 500 are formed can be reduced, so that diffusion of impurities such as hydrogen to the transistor 200 and the transistor 500 through the plug can be suppressed.

In the above, as a method for forming the region 231 and the region 232, a method in which the layer 242 is formed by providing a film containing a metal element in contact with the region 231 of the oxide 230 has been described. It is not limited. For example, the layer 242 may be formed by adding an element capable of increasing the carrier density of the oxide 230 and reducing the resistance as a dopant.

As the dopant, an element that forms oxygen vacancies or an element that combines with oxygen vacancies may be used. As such an element, typically, boron or phosphorus can be given. Further, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas, or the like may be used. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. Also, metals such as aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc. Any one or more metal elements selected from the elements may be added. Among the above-described dopants, boron and phosphorus are preferable as the dopant. When boron or phosphorus is used as a dopant, equipment for an amorphous silicon or low-temperature polysilicon production line can be used, so that capital investment can be suppressed. The concentration of the element may be measured by using secondary ion mass spectrometry (SIMS) or the like.

In particular, as an element to be added to the layer 242, an element that easily forms an oxide is preferably used. Typical examples of such elements include boron, phosphorus, aluminum, and magnesium. The element added to the layer 242 can take oxygen in the oxide 230 to form an oxide. As a result, the layer 242 has many oxygen vacancies. The oxygen deficiency and hydrogen in the oxide 230 are combined with each other, so that carriers are generated and an extremely low resistance region is obtained. Further, since the element added to the layer 242 exists in the layer 242 in a stable oxide state, it is difficult to be detached from the layer 242 even if a process requiring a high temperature is performed in a subsequent process. In other words, by using an element that easily forms an oxide as an element to be added to the layer 242, a region in the oxide 230 that is difficult to increase in resistance even after a high-temperature process can be formed.

In the case where the layer 242 is formed by adding a dopant, for example, the dopant is added using the insulator 271, the insulator 270, the conductor 260, the metal oxide 252, the insulator 250, the oxide 230 c, and the insulator 275 as a mask. Good. Accordingly, the layer 242 containing the above element can be formed in a region where the mask of the oxide 230 is not overlapped. Instead of using the insulator 271, the insulator 270, the conductor 260, the metal oxide 252, the insulator 250, the oxide 230 c, and the insulator 275 as a mask, a dummy gate may be formed and used as a mask. In this case, the insulator 271, the insulator 270, the conductor 260, the metal oxide 252, the insulator 250, the oxide 230c, and the insulator 275 may be formed after the dopant is added.

As a method for adding a dopant, an ion implantation method in which ionized source gas is added by mass separation, an ion doping method in which ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like is used. Can do. When mass separation is performed, the ionic species to be added and the concentration thereof can be strictly controlled. On the other hand, when mass separation is not performed, high-concentration ions can be added in a short time. Alternatively, an ion doping method in which atomic or molecular clusters are generated and ionized may be used. Note that the dopant may be referred to as an ion, a donor, an acceptor, an impurity, an element, or the like.

In addition, by adding an element that forms oxygen vacancies to the layer 242 and performing heat treatment, hydrogen contained in the region 234 functioning as a channel formation region can be trapped by the oxygen vacancies contained in the layer 242 in some cases. Thus, stable electrical characteristics can be given to the transistor 200, and reliability can be improved.

Here, in a transistor including an oxide semiconductor, if an impurity and an oxygen vacancy exist in a region where a channel is formed in the oxide semiconductor, electric characteristics may be easily changed and reliability may be deteriorated. In addition, when an oxygen vacancy is included in a region where a channel is formed in an oxide semiconductor, the transistor is likely to be normally on. Therefore, oxygen vacancies in the region 234 where a channel is formed are preferably reduced as much as possible.

Therefore, as shown in FIG. 12, the insulating layer 250, the region 230 of the oxide 230b, and the oxide 230c are in contact with each other and contain more oxygen (also referred to as excess oxygen) than oxygen that satisfies the stoichiometric composition. An insulator 275 is preferably provided. That is, excess oxygen in the insulator 275 is diffused into the region 234 of the oxide 230, whereby oxygen vacancies in the region 234 of the oxide 230 can be reduced.

In order to provide an excess oxygen region in the insulator 275, an oxide film may be formed as the insulator 273 in contact with the insulator 275 by a sputtering method. By using a sputtering method for forming an oxide, an insulator with few impurities such as water or hydrogen can be formed. In the case of using a sputtering method, for example, it is preferable to form a film using a facing target type sputtering apparatus. Since the facing target type sputtering apparatus can form a film without exposing the film formation surface to a high electric field region between the facing targets, the film formation surface can be formed without being easily damaged by plasma. It is preferable because film formation damage to the oxide 230 can be reduced when an insulator to be the insulator 273 is formed. A film forming method using a facing target type sputtering apparatus can be referred to as VDSP (Vapor Deposition SP) (registered trademark).

During film formation by sputtering, ions and sputtered particles exist between the target and the substrate. For example, the target is connected to a power source and is supplied with the potential E0. The substrate is given a potential E1 such as a ground potential. However, the substrate may be electrically floating. In addition, there is a region having the potential E2 between the target and the substrate. The magnitude relationship between the potentials is E2> E1> E0.

The ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target, so that the sputtered particles are ejected from the target. The sputtered particles adhere to and deposit on the film formation surface to form a film. Some ions recoil by the target, pass through a film formed as recoil ions, and may be taken into the insulator 275 in contact with the deposition surface. Further, ions in the plasma are accelerated by the potential difference E2-E1, and impact the film formation surface. At this time, some ions reach the inside of the insulator 275. When the ions are taken into the insulator 275, a region into which the ions are taken is formed in the insulator 275. That is, when the ions are oxygen-containing ions, an excess oxygen region is formed in the insulator 275.

By introducing excess oxygen into the insulator 275, an excess oxygen region can be formed in the insulator 275. Excess oxygen in the insulator 275 can be supplied to the region 234 of the oxide 230 to compensate for oxygen vacancies in the oxide 230.

Note that the insulator 275 is preferably formed using silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having holes. Materials such as silicon oxynitride tend to form excess oxygen regions. On the other hand, compared to the above-described materials such as silicon oxynitride, the oxide 230 tends to hardly form an excess oxygen region even if an oxide film formed by a sputtering method is formed over the oxide 230. Therefore, by providing the insulator 275 having an excess oxygen region around the region 234 of the oxide 230, the excess oxygen of the insulator 275 can be effectively supplied to the region 234 of the oxide 230.

The insulator 273 is preferably made of aluminum oxide. Aluminum oxide may extract hydrogen in the oxide 230 by performing heat treatment in the state of being close to the oxide 230. Note that in the case where the layer 242 is provided between the oxide 230 and aluminum oxide, the hydrogen in the layer 242 is absorbed by the aluminum oxide, and the layer 242 in which hydrogen is reduced reduces the hydrogen in the oxide 230. May absorb. Therefore, the hydrogen concentration in the oxide 230 can be reduced. In addition, oxygen may be supplied from the insulator 273 to the oxide 230, the insulator 224, or the insulator 222 by performing heat treatment in a state where the insulator 273 and the oxide 230 are in proximity to each other.

The oxide 230 can be selectively reduced in resistance by combining the above structure or the above steps.

That is, when a low resistance region is formed in the oxide 230, the resistance of the oxide 230 is reduced in a self-aligning manner by using the conductor 260 functioning as a gate electrode and the insulator 275 as a mask. Therefore, when the plurality of transistors 200 are formed at the same time, variation in electrical characteristics between the transistors can be reduced. Further, the channel length of the transistor 200 is determined by the width of the conductor 260 or the film thickness of the insulator 275, and the transistor 200 can be miniaturized by setting the width of the conductor 260 to the minimum processing dimension. Become.

As described above, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics that meet the requirements according to the circuit design.

Further, since an oxide semiconductor can be formed by a sputtering method or the like, it can be used for a transistor included in a highly integrated semiconductor device. In addition, since a transistor using an oxide semiconductor in a channel formation region has extremely small leakage current (off-state current) in a non-conduction state, a semiconductor device with low power consumption can be provided. In addition, since the off-state current of the transistor 200 is small, stored data can be held for a long time by using the transistor 200 for a semiconductor device. In other words, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the semiconductor device can be sufficiently reduced.

As described above, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.

Hereinafter, a detailed configuration of a layer corresponding to the layer 30 of the semiconductor device described in this embodiment will be described. In the following description, the description of the detailed structure of the transistor 200 is also referred to for the detailed structures of the transistor 500 and the transistor 700 unless otherwise specified.

The conductor 203 is extended in the channel width direction as shown in FIGS. 9A and 10A and functions as a wiring for applying a potential to the conductor 205. Note that the conductor 203 is preferably provided so as to be embedded in the insulator 212.

The conductor 205 is disposed so as to overlap with the oxide 230 and the conductor 260. The conductor 205 is preferably provided in contact with the conductor 203. The conductor 205 is preferably provided so as to be embedded in the insulator 214 and the insulator 216.

Here, the conductor 260 may function as a first gate (also referred to as a front gate) electrode. The conductor 205 may function as a second gate (also referred to as a back gate) electrode. In that case, the threshold voltage of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without being linked. In particular, by applying a negative potential to the conductor 205, the threshold voltage of the transistor 200 can be made higher than 0 V and the off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be made smaller than when a negative potential is not applied.

Further, by providing the conductor 205 over the conductor 203, the distance between the conductor 203 having the function of the first gate electrode and the wiring and the conductor 203 can be appropriately designed. That is, by providing the insulator 214, the insulator 216, and the like between the conductor 203 and the conductor 260, parasitic capacitance between the conductor 203 and the conductor 260 can be reduced, and the conductor 203 and the conductor 260 can be reduced. The insulation breakdown voltage can be increased.

Further, by reducing the parasitic capacitance between the conductor 203 and the conductor 260, the switching speed of the transistor 200 can be improved and a transistor having high frequency characteristics can be obtained. Further, by increasing the withstand voltage between the conductor 203 and the conductor 260, the reliability of the transistor 200 can be improved. Therefore, it is preferable to increase the thickness of the insulator 214 and the insulator 216. Note that the extending direction of the conductor 203 is not limited thereto, and the conductor 203 may be extended in the channel length direction of the transistor 200, for example.

Note that the conductor 205 is provided so as to overlap with the oxide 230 and the conductor 260 as illustrated in FIG. The conductor 205 is preferably provided larger than the region 234 in the oxide 230. In particular, as illustrated in FIG. 10A, the conductor 205 preferably extends to a region outside the end portion in the channel width direction of the region 234 of the oxide 230. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other through the insulator on the side surface of the oxide 230 in the channel width direction.

With the above structure, when a potential is applied to the conductor 260 and the conductor 205, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected to form a channel formed in the oxide 230. The area can be covered.

That is, the channel formation region in the region 234 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. . In this specification, a transistor structure that electrically surrounds a channel formation region by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.

Further, the conductor 205 is formed with a first conductor in contact with the inner walls of the openings of the insulator 214 and the insulator 216, and further a second conductor is formed inside. Here, the height of the top surfaces of the first conductor and the second conductor and the height of the top surface of the insulator 216 can be approximately the same. Note that although the transistor 200 has a structure in which the first conductor of the conductor 205 and the second conductor of the conductor 205 are stacked, the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer or a stacked structure including three or more layers.

Here, the first conductor of the conductor 205 or the conductor 203 includes a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N ₂ O, NO, NO _2, etc.), copper It is preferable to use a conductive material having a function of suppressing diffusion of impurities such as atoms (the impurities are difficult to permeate). Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the oxygen hardly transmits). Note that in this specification, the function of suppressing diffusion of impurities or oxygen is a function of suppressing diffusion of any one or all of the impurities and oxygen.

Since the conductor 205 or the first conductor of the conductor 203 has a function of suppressing diffusion of oxygen, the conductor 205 or the second conductor of the conductor 203 is oxidized to reduce conductivity. This can be suppressed. As a conductive material having a function of suppressing oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. Therefore, the conductive material may be a single layer or a stacked layer as the first conductor of the conductor 205 or the conductor 203. Accordingly, diffusion of impurities such as hydrogen and water to the transistor 200 side through the conductor 203 and the conductor 205 can be suppressed.

In addition, the second conductor of the conductor 205 is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. Note that the second conductor of the conductor 205 is illustrated as a single layer, but may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.

Further, since the second conductor of the conductor 203 functions as a wiring, a conductor having higher conductivity than the second conductor of the conductor 205 is preferably used. For example, a conductive material mainly containing copper or aluminum can be used. Further, the second conductor of the conductor 203 may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.

In particular, it is preferable to use copper for the conductor 203. Since copper has low resistance, it is preferably used for wiring and the like. On the other hand, since copper easily diffuses, the electrical characteristics of the transistor 200 may be deteriorated by diffusing into the oxide 230. Thus, for example, the insulator 214 can be made of copper diffusion by using a material such as aluminum oxide or hafnium oxide having low copper permeability.

Note that the conductor 205, the insulator 214, and the insulator 216 are not necessarily provided. In that case, part of the conductor 203 can function as the second gate electrode.

The insulator 210 and the insulator 214 preferably function as barrier insulating films that prevent impurities such as water or hydrogen from entering the transistor 200 from the substrate side. Therefore, the insulator 210 and the insulator 214 can diffuse impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N ₂ O, NO, NO _{2, and the} like) and a copper atom. It is preferable to use an insulating material having a function of suppressing (the above impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule) (the oxygen hardly transmits). Further, an insulator that functions as a barrier insulating film similar to the insulator 210 or the insulator 214 may be provided over the insulator 280. Accordingly, impurities such as water or hydrogen can be prevented from entering the transistor 200 from above the insulator 280.

For example, it is preferable to use aluminum oxide or the like as the insulator 210 and silicon nitride or the like as the insulator 214. Thus, impurities such as hydrogen and water can be prevented from diffusing from the substrate side to the transistor 200 side with respect to the insulator 210 and the insulator 214. Alternatively, diffusion of oxygen contained in the insulator 224 and the like to the substrate side with respect to the insulator 210 and the insulator 214 can be suppressed.

In addition, by providing a structure in which the conductor 205 is provided over the conductor 203, the insulator 214 can be provided between the conductor 203 and the conductor 205. Here, even when a metal that easily diffuses, such as copper, is used for the second conductor of the conductor 203, by providing silicon nitride or the like as the insulator 214, the metal diffuses into a layer above the insulator 214. Can be suppressed.

Further, the insulator 212, the insulator 216, and the insulator 280 that function as interlayer films preferably have a lower dielectric constant than the insulator 210 or the insulator 214. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

For example, as the insulator 212, the insulator 216, and the insulator 280, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), titanate An insulator such as strontium (SrTiO ₃ ) or (Ba, Sr) TiO ₃ (BST) can be used as a single layer or a stacked layer. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

The insulator 220, the insulator 222, and the insulator 224 have a function as a gate insulator. In addition, the insulator 524 provided in the transistor 500 and the insulator 724 provided in the transistor 700 also function as gate insulators similarly to the insulator 224. Note that although the insulator 224 is separated from the insulator 524 and the insulator 724 in this embodiment, the insulator 224 may be connected to the insulator 524 and the insulator 724.

Here, the insulator 224 in contact with the oxide 230 is preferably an insulator containing more oxygen than oxygen that satisfies the stoichiometric composition. That is, it is preferable that an excess oxygen region be formed in the insulator 224. By providing such an insulator containing excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region. The oxide that desorbs oxygen by heating means that the amount of desorbed oxygen in terms of oxygen molecules is 1.0 × 10 ¹⁸ molecules / cm ³ or more, preferably 1 in TDS (Thermal Desorption Spectroscopy) analysis. The oxide film has a thickness of 0.0 × 10 ¹⁹ molecules / cm ³ or more, more preferably 2.0 × 10 ¹⁹ molecules / cm ³ or more, or 3.0 × 10 ²⁰ molecules / cm ³ or more. The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 400 ° C.

In the case where the insulator 224 has an excess oxygen region, the insulator 222 has a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule) (the oxygen is difficult to transmit). It is preferable.

Since the insulator 222 has a function of suppressing oxygen diffusion, oxygen in the excess oxygen region included in the insulator 224 can be efficiently supplied to the oxide 230 without diffusing to the insulator 220 side. . In addition, the conductor 205 can be prevented from reacting with oxygen in the excess oxygen region of the insulator 224.

The insulator 222 is, for example, so-called high such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba, Sr) TiO ₃ (BST). It is preferable to use an insulator including a -k material in a single layer or a stacked layer. As transistor miniaturization and higher integration progress, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material for the insulator functioning as a gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical film thickness.

In particular, an insulator including one or both of oxides of aluminum and hafnium, which is an insulating material having a function of suppressing diffusion of impurities and oxygen (the oxygen is difficult to permeate) may be used. As the insulator containing one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. In the case where the insulator 222 is formed using such a material, the insulator 222 suppresses release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the peripheral portion of the transistor 200 into the oxide 230. Acts as a layer.

Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

In addition, the insulator 220 is preferably thermally stable. For example, since silicon oxide and silicon oxynitride are thermally stable, a stacked structure having a high thermal stability and a high relative dielectric constant can be obtained by combining an insulator of a high-k material and the insulator 220. Can do.

Note that the insulator 220, the insulator 222, and the insulator 224 may have a stacked structure of two or more layers. In that case, it is not limited to the laminated structure which consists of the same material, The laminated structure which consists of a different material may be sufficient.

The oxide 230 includes an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. By including the oxide 230a under the oxide 230b, diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed. Further, by including the oxide 230c over the oxide 230b, diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b can be suppressed.

Note that the oxide 230 preferably has a stacked structure of oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent element is larger than the atomic ratio of the element M in the constituent element in the metal oxide used for the oxide 230b. It is preferable. In the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. As the oxide 230c, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.

Further, it is preferable that the energy at the lower end of the conduction band of the oxide 230a and the oxide 230c is higher than the energy at the lower end of the conduction band of the oxide 230b. In other words, the electron affinity of the oxide 230a and the oxide 230c is preferably smaller than the electron affinity of the oxide 230b.

Here, at the junction of the oxide 230a, the oxide 230b, and the oxide 230c, the conduction band lower end gently changes. In other words, it can be said that the lower end of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c is continuously changed or continuously joined. In order to achieve this, the defect state density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c is preferably low.

Specifically, the oxide 230a and the oxide 230b, and the oxide 230b and the oxide 230c have a common element (main component) in addition to oxygen, so that a mixed layer with a low density of defect states is formed. can do. For example, in the case where the oxide 230b is an In—Ga—Zn oxide, an In—Ga—Zn oxide, a Ga—Zn oxide, a gallium oxide, or the like may be used as the oxide 230a and the oxide 230c.

At this time, the main path of the carrier is the oxide 230b. When the oxide 230a and the oxide 230c have the above structure, the density of defect states at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c can be reduced. Therefore, the influence on the carrier conduction due to the interface scattering is reduced, and the transistor 200 can obtain a high on-state current.

In addition, the oxide 230 includes a region 231, a region 232, and a region 234. Note that at least part of the region 231 has a region in proximity to the insulator 273. The region 232 has at least a region overlapping with the insulator 275.

Note that when the transistor 200 is turned on, the region 231a or the region 231b functions as a source region or a drain region. On the other hand, at least part of the region 234 functions as a channel formation region. By including the region 232 between the region 231 and the region 234, the transistor 200 can have a large on-state current and a small non-conducting leakage current (off-state current).

In the transistor 200, since the region 232 is provided, a high-resistance region is not formed between the region 231 functioning as a source region and a drain region and the region 234 where a channel is formed; thus, on-state current and mobility of the transistor Can be increased. In addition, since the region 232 includes the source region, the drain region, and the first gate electrode (conductor 260) in the channel length direction, unnecessary capacitance is formed between the two. Can be suppressed. In addition, by including the region 232, leakage current at the time of non-conduction can be reduced.

That is, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics that meet the requirements according to the circuit design. For example, the transistor 200 can be configured to have low off-state current, and the transistor 500 can be configured to increase on-state current.

As the oxide 230, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used. For example, as the metal oxide used for the region 234, a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more is preferably used. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a large band gap.

Since a transistor including an oxide semiconductor has extremely small leakage current in a non-conduction state, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.

The insulator 250 functions as a gate insulator. The insulator 250 is preferably provided in contact with the upper surface of the oxide 230c. The insulator 250 is preferably formed using an insulator from which oxygen is released by heating. For example, in the temperature-programmed desorption gas spectroscopy analysis (TDS analysis), the amount of desorbed oxygen in terms of oxygen molecules is 1.0 × 10 ¹⁸ molecules / cm ³ or more, preferably 1.0 × 10 ^19. It is an insulating film having a molecular weight / cm ³ or higher, more preferably 2.0 × 10 ¹⁹ molecules / cm ³ or higher, or 3.0 × 10 ²⁰ molecules / cm ³ or higher. The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or more and 700 ° C. or less.

Specifically, as the insulator 250, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added Alternatively, silicon oxide having pores can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

By providing an insulator from which oxygen is released by heating in contact with the upper surface of the oxide 230c, the insulator 250 can effectively supply oxygen from the insulator 250 to the region 234 of the oxide 230b. . Similarly to the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

Further, a metal oxide 252 may be provided in order to efficiently supply excess oxygen included in the insulator 250 to the oxide 230. Therefore, the metal oxide 252 preferably suppresses oxygen diffusion from the insulator 250. By providing the metal oxide 252 that suppresses oxygen diffusion, diffusion of excess oxygen from the insulator 250 to the conductor 260 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to excess oxygen can be suppressed.

Note that the metal oxide 252 may have a function as a part of the first gate. For example, an oxide semiconductor that can be used as the oxide 230 can be used as the metal oxide 252. In that case, by forming the conductor 260 by a sputtering method, the electric resistance value of the metal oxide 252 can be reduced, whereby the conductor can be obtained. This can be called an OC (Oxide Conductor) electrode.

Further, the metal oxide 252 may function as a part of the gate insulator. Therefore, in the case where silicon oxide, silicon oxynitride, or the like is used for the insulator 250, the metal oxide 252 is preferably a metal oxide that is a high-k material with a high relative dielectric constant. By setting it as the said laminated structure, it can be set as the laminated structure stable with respect to a heat | fever, and a high dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of an insulator that functions as a gate insulator.

In the transistor 200, the metal oxide 252 is illustrated as a single layer; however, a stacked structure including two or more layers may be used. For example, a metal oxide that functions as part of the gate electrode and a metal oxide that functions as part of the gate insulator may be stacked.

When the metal oxide 252 serves as the gate electrode, the on-state current of the transistor 200 can be improved without weakening the influence of the electric field from the conductor 260. Alternatively, in the case of functioning as a gate insulator, the distance between the conductor 260 and the oxide 230 is maintained by the physical thickness of the insulator 250 and the metal oxide 252, so that the conductor 260 Leakage current between the oxide 230 can be suppressed. Therefore, by providing a stacked structure of the insulator 250 and the metal oxide 252, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 are It can be easily adjusted as appropriate.

Specifically, an oxide semiconductor that can be used for the oxide 230 can be used as the metal oxide 252 by reducing resistance. Alternatively, a metal oxide containing one kind or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used.

In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in a heat history in a later process. Note that the metal oxide 252 is not an essential component. What is necessary is just to design suitably according to the transistor characteristic to request | require.

The conductor 260 functioning as the first gate electrode includes a conductor 260a and a conductor 260b over the conductor 260a. Like the first conductor of the conductor 205, the conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N ₂ O, NO, NO _2, etc.), a copper atom It is preferable to use a conductive material having a function of suppressing diffusion of impurities such as. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

When the conductor 260a has a function of suppressing oxygen diffusion, it is possible to suppress the conductivity from being lowered due to oxidation of the conductor 260b due to excess oxygen included in the insulator 250 and the metal oxide 252. . As a conductive material having a function of suppressing oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.

Further, since the conductor 260 functions as a wiring, it is preferable to use a conductor having high conductivity. For example, as the conductor 260b, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 260b may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.

In addition, as illustrated in FIG. 10A, when the conductor 205 extends to a region outside the end portion of the oxide 230 in the channel width direction, the conductor 260 includes an insulator in the region. It is preferable to overlap with the conductor 205 through 250. That is, it is preferable that the conductor 205, the insulator 250, and the conductor 260 form a stacked structure outside the side surface of the oxide 230.

With the above structure, when a potential is applied to the conductor 260 and the conductor 205, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected to form a channel formed in the oxide 230. The area can be covered.

That is, the channel formation region in the region 234 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. .

Further, an insulator 270 that functions as a barrier film may be provided over the conductor 260b. As the insulator 270, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is preferably used. For example, aluminum oxide or hafnium oxide is preferably used. Thus, the conductor 260 can be prevented from being oxidized by oxygen diffusing from above the insulator 270. Further, impurities such as water or hydrogen diffusing from above the insulator 270 can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250.

Further, it is preferable to dispose an insulator 271 functioning as a hard mask over the insulator 270. By providing the insulator 271, when processing the conductor 260, the side surface of the conductor 260 is substantially vertical, specifically, the angle between the side surface of the conductor 260 and the substrate surface is 75 degrees or more and 100 degrees or less, Preferably, it can be set to 80 degrees or more and 95 degrees or less. By processing the conductor 260 into such a shape, the insulator 275 to be formed next can be formed into a desired shape.

Note that the insulator 271 may also function as a barrier film by using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. In that case, the insulator 270 is not necessarily provided.

The insulator 275 functioning as a buffer layer is provided in contact with the side surface of the oxide 230 c, the side surface of the insulator 250, the side surface of the metal oxide 252, the side surface of the conductor 260, and the side surface of the insulator 270.

For example, as the insulator 275, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having a hole Or it is preferable to have resin etc. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having holes are preferable because an excess oxygen region can be easily formed in a later step.

The insulator 275 preferably has an excess oxygen region. By providing an insulator from which oxygen is released by heating as the insulator 275 in contact with the oxide 230c and the insulator 250, oxygen is effectively supplied from the insulator 250 to the region 234 of the oxide 230b. be able to. In addition, the concentration of impurities such as water or hydrogen in the insulator 275 is preferably reduced.

The insulator 130 is preferably an insulator having a large relative dielectric constant, and an insulator that can be used for the insulator 222 or the like may be used. For example, an insulator including one or both of aluminum and hafnium can be used. As the insulator containing one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. The insulator 130 may have a single-layer structure or a stacked structure. As the insulator 130, for example, two or more layers of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and the like are stacked. Also good. For example, it is preferable that hafnium oxide, aluminum oxide, and hafnium oxide are sequentially formed by an ALD method to form a stacked structure. The film thicknesses of hafnium oxide and aluminum oxide are 0.5 nm to 5 nm, respectively. By setting it as such a laminated structure, it can be set as the capacitive element 100 with a large capacitance value and a small league current.

As shown in FIGS. 9A and 9B, the side surface of the insulator 130 coincides with the side surfaces of the conductor 110 and the conductor 120 in a top view, but the present invention is not limited to this. For example, the insulator 130 may cover the transistor 200 and the transistor 500 without patterning the insulator 130.

The conductor 120 is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Although not shown, the conductor 120 may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.

Further, as shown in FIG. 11B, the conductor 110, the insulator 130, and the conductor 120 are preferably provided so as to cover the side surface of the oxide 230. With such a structure, the capacitor 100 can be formed also in the side surface direction of the oxide 230, so that the capacitance per unit area of the capacitor 100 can be increased.

The insulator 273 is provided over at least the layer 242, the insulator 275, the layer 542, the insulator 575, the layer 742, the insulator 775, and the conductor 120. By depositing the insulator 273 by a sputtering method, an excess oxygen region can be provided in the insulator 275, the insulator 575, and the insulator 775. Accordingly, oxygen can be supplied into the oxide 230, the oxide 530, and the oxide 730 from the excess oxygen region. Further, by providing the insulator 273 over the oxide layer 230, the oxide 530 layer 542, and the oxide 730 layer 742, hydrogen in the oxide 230, the oxide 530, and the oxide 730 can be reduced. It can be pulled out to the insulator 273.

For example, as the insulator 273, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like is used. be able to.

In particular, aluminum oxide has a high barrier property and can suppress diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm.

In addition, an insulator 274 is provided over the insulator 273. The insulator 274 is preferably formed using a film having barrier properties and a reduced hydrogen concentration. For example, as the insulator 274, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, or the like may be used. By providing the insulator 273 having a barrier property and the insulator 274 having a barrier property, diffusion of impurities from other structures such as an interlayer film to the transistor 200 can be suppressed.

Further, an insulator 280 that functions as an interlayer film is preferably provided over the insulator 274. As in the case of the insulator 224, the insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the film. Note that an insulator similar to the insulator 210 may be provided over the insulator 280. By forming the insulator by a sputtering method, impurities in the insulator 280 can be reduced.

Further, the conductor 240a, the conductor 240b, the conductor 540a, the conductor 540b, the conductor 740a, the conductor 740b, and the conductor 740c are inserted into openings formed in the insulator 280, the insulator 274, and the insulator 273. Deploy. The conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. The conductors 540a and 540b are provided to face each other with the conductor 560 interposed therebetween. The conductors 740a and 740b are provided to face each other with the conductor 760 interposed therebetween. Note that the top surfaces of the conductor 240a, the conductor 240b, the conductor 540a, the conductor 540b, the conductor 740a, the conductor 740b, and the conductor 740c may be flush with the top surface of the insulator 280.

Note that a conductor 240a is formed in contact with the inner walls of the openings of the insulator 280, the insulator 274, and the insulator 273. A region 231a of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240a is in contact with the region 231a. The same applies to the conductor 540a, the conductor 540b, the conductor 740a, and the conductor 740b.

Here, as illustrated in FIG. 11A, the conductor 240a preferably overlaps with a side surface of the oxide 230. In particular, the conductor 240a preferably overlaps with both or one of the side surface on the A7 side and the side surface on the A8 side on the side surface intersecting with the channel width direction of the oxide 230. Alternatively, the conductor 240a may overlap with the side surface on the A1 side (A2 side) on the side surface intersecting the channel length direction of the oxide 230. In this manner, the conductor 240a overlaps with the region 231 serving as the source region or the drain region and the side surface of the oxide 230 without increasing the projected area of the contact portion between the conductor 240a and the transistor 200. The contact area of the contact portion can be increased, and the contact resistance between the conductor 240a and the transistor 200 can be reduced. Thus, the on-current can be increased while miniaturizing the source electrode and the drain electrode of the transistor. In addition, the conductor 110 in contact with the region 231 to be the source region or the drain region of the oxide 230 is preferably in contact with the oxide 230 and the layer 242 as well. The same applies to the conductor 540a, the conductor 540b, the conductor 740a, and the conductor 740b.

The conductor 240a, the conductor 240b, the conductor 540a, the conductor 540b, the conductor 740a, the conductor 740b, and the conductor 740c are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240a, the conductor 240b, the conductor 540a, the conductor 540b, the conductor 740a, the conductor 740b, and the conductor 740c may have a stacked structure.

Here, for example, when the openings are formed in the insulator 280, the insulator 274, and the insulator 273, the oxide 230 has a reduced resistance region of the region 231 and is not reduced in resistance. May be exposed. In that case, a metal film, a nitride film containing a metal element, or a metal element is used as a conductor used for a conductor in contact with the oxide 230 of the conductor 240 (hereinafter also referred to as a first conductor of the conductor 240). It is preferable to use an oxide film having the same. That is, when the oxide 230 whose resistance has not been reduced is in contact with the first conductor of the conductor 240, oxygen vacancies are formed in the metal compound or the oxide 230, and the region 231 of the oxide 230 has low resistance. Turn into. Therefore, by reducing the resistance of the oxide 230 in contact with the first conductor of the conductor 240, the contact resistance between the oxide 230 and the conductor 240 can be reduced. Therefore, the first conductor of the conductor 240 preferably includes a metal element such as aluminum, ruthenium, titanium, tantalum, or tungsten. The conductors 540 and 740 may have a similar structure.

In the case where the conductor 240, the conductor 540, and the conductor 740 have a stacked structure, the insulator 280, the insulator 274, and the conductor in contact with the insulator 273 include the first conductor of the conductor 205, and the like. Similarly to the above, it is preferable to use a conductive material having a function of suppressing permeation of impurities such as water or hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. Further, the conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using the conductive material, impurities such as hydrogen and water from an upper layer than the insulator 280 are prevented from being mixed into the oxide 230 and the oxide 530 through the conductor 240, the conductor 540, and the conductor 740. be able to.

Note that an opening in which the conductor 240, the conductor 540, and the conductor 740 are provided may be configured such that an inner wall of the opening is covered with an insulator having a barrier property against oxygen or hydrogen. Here, as the insulator having a barrier property against oxygen and hydrogen, an insulator similar to the insulator 214 may be used, and for example, aluminum oxide or the like is preferably used. Accordingly, impurities such as hydrogen and water from the insulator 280 and the like are prevented from being mixed into the oxide 230, the oxide 530, and the oxide 730 through the conductor 240, the conductor 540, and the conductor 740. it can. Further, the insulator can be formed with good coverage by forming the insulator using, for example, an ALD method or a CVD method.

Although not shown, a conductor 240, a conductor 540, and a conductor that functions as a wiring may be disposed in contact with the top surfaces of the conductor 740. As the conductor functioning as the wiring, a conductive material containing tungsten, copper, or aluminum as a main component is preferably used. The conductor may have a stacked structure, for example, a stack of titanium, titanium nitride, and the conductive material. Note that like the conductor 203 and the like, the conductor may be formed so as to be embedded in an opening provided in the insulator.

<Constituent materials for semiconductor devices>
Hereinafter, constituent materials that can be used for the semiconductor device will be described. In the following, a material that can be used for the transistor 200 can be used for the transistor 500 and the transistor 700 unless otherwise specified.

The constituent materials shown below are formed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and pulsed laser deposition (PLD). Alternatively, it can be performed by using an atomic layer deposition (ALD) method or the like.

In addition, the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. . Furthermore, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method depending on the source gas used.

The plasma CVD method can obtain a high-quality film at a relatively low temperature. Further, the thermal CVD method is a film formation method that can suppress plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma. At this time, a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge. On the other hand, in the case of a thermal CVD method without using plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. In addition, in the thermal CVD method, plasma damage during film formation does not occur, so that a film with few defects can be obtained.

The ALD method is also a film forming method that can suppress plasma damage to the object to be processed. Therefore, a film with few defects can be obtained. Note that some precursors used in the ALD method include impurities such as carbon. Therefore, a film provided by the ALD method may contain a larger amount of impurities such as carbon than a film provided by another film formation method. The quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).

The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, compared to film formation using multiple film formation chambers, the time required for film formation is shortened by the time required for transport and pressure adjustment. can do. Therefore, the productivity of the semiconductor device may be increased.

Further, the processing of the constituent material may be performed using a lithography method. For the processing, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing.

In the lithography method, first, a resist is exposed through a mask. Next, a resist mask is formed by removing or leaving the exposed region using a developer. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultra violet) light, or the like. Further, an immersion technique may be used in which exposure is performed by filling a liquid (for example, water) between the substrate and the projection lens. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that when an electron beam or an ion beam is used, writing is performed directly on the resist, so that the resist exposure mask described above becomes unnecessary. Note that the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process. .

Further, a hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film to be a hard mask material is formed on the constituent material, a resist mask is formed thereon, and a hard mask having a desired shape is formed by etching the hard mask material. can do. Etching of the constituent material may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the constituent material is etched. On the other hand, when the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.

As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes. Alternatively, a configuration in which a plurality of different high-frequency power sources are applied to one electrode of the parallel plate electrode may be employed. Or the structure which applies the high frequency power supply of the same frequency to each parallel plate type | mold electrode may be sufficient. Or the structure which applies the high frequency power source from which a frequency differs to each parallel plate type | mold electrode may be sufficient. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used.

<< Insulator >>
Examples of the insulator include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.

For example, when the transistor is miniaturized and highly integrated, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material for the insulator functioning as a gate insulator, the voltage during transistor operation can be reduced while maintaining the physical film thickness. On the other hand, a parasitic capacitance generated between wirings can be reduced by using a material having a low relative dielectric constant for the insulator functioning as an interlayer film. Therefore, the material may be selected according to the function of the insulator.

Insulators having a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, silicon and hafnium. There are oxynitrides having silicon and nitrides having silicon and hafnium.

Insulators having a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, Examples include silicon oxide or resin having holes.

In particular, silicon oxide and silicon oxynitride are thermally stable. Therefore, for example, by combining with a resin, a laminated structure having a thermally stable and low relative dielectric constant can be obtained. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. Further, for example, silicon oxide and silicon oxynitride can be combined with an insulator having a high relative dielectric constant to provide a thermally stable and high stacked dielectric structure.

In addition, a transistor including an oxide semiconductor can be stabilized in electrical characteristics of the transistor by being surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen.

Examples of the insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or A metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.

For example, as the insulator 273, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like is used. be able to.

In particular, aluminum oxide has a high barrier property and can suppress diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. Hafnium oxide has a lower barrier property than aluminum oxide, but the barrier property can be increased by increasing the film thickness. Therefore, by adjusting the film thickness of hafnium oxide, appropriate addition amounts of hydrogen and nitrogen can be adjusted.

For example, the insulator 224 and the insulator 250 that function as part of the gate insulator are preferably insulators having an excess oxygen region. For example, by using a structure in which silicon oxide or silicon oxynitride having an excess oxygen region is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.

For example, in the insulator 222 that functions as part of the gate insulator, an insulator including one or more oxides of aluminum, hafnium, and gallium can be used. In particular, as the insulator including one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.

For example, for the insulator 220, it is preferable to use silicon oxide or silicon oxynitride which is stable against heat. The gate insulator has a laminated structure of a heat stable film and a film having a high relative dielectric constant, so that a thin film having an equivalent oxide thickness (EOT) of the gate insulator is maintained while maintaining a physical film thickness. Can be realized.

With the above laminated structure, the on-current can be improved without weakening the influence of the electric field from the gate electrode. In addition, the leakage current between the gate electrode and the channel formation region can be suppressed by maintaining the distance between the gate electrode and the region where the channel is formed depending on the physical thickness of the gate insulator. .

It is preferable that the insulator 212, the insulator 216, the insulator 271, the insulator 275, and the insulator 280 include an insulator with a low relative dielectric constant. For example, the insulator includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having a hole Or it is preferable to have resin etc. Alternatively, the insulator includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having a hole And a laminated structure of resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.

As the insulator 210, the insulator 214, the insulator 270, and the insulator 273, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen can be used. Examples of the insulator 210, the insulator 214, the insulator 270, and the insulator 273 include aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide. Metal oxide, silicon nitride oxide, silicon nitride, or the like may be used.

<< Conductor >>
As the conductor, a metal selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. A material containing one or more elements can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

Further, a plurality of conductive layers formed of the above materials may be stacked. For example, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen may be combined. Alternatively, a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed. Alternatively, a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.

Note that in the case where an oxide is used for a channel formation region of the transistor, the conductor functioning as the gate electrode has a stacked structure in which the above-described material containing a metal element and the conductive material containing oxygen are combined. Is preferred. In this case, a conductive material containing oxygen is preferably provided on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material can be easily supplied to the channel formation region.

In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed as a conductor functioning as a gate electrode. Alternatively, the above-described conductive material containing a metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in a metal oxide in which a channel is formed can be captured in some cases. Alternatively, hydrogen mixed from an external insulator or the like may be captured.

As the conductor 260, the conductor 203, the conductor 205, and the conductor 240, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium A material containing one or more metal elements selected from zirconium, beryllium, indium, ruthenium, and the like can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

<< Metal oxide >>
As the oxide 230, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used. Below, the metal oxide applicable to the oxide 230 which concerns on this invention is demonstrated.

The metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. One or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.

Here, consider a case where the metal oxide is an In-M-Zn oxide containing indium, the element M, and zinc. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.

Note that in this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. In addition, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

[Composition of metal oxide]
A structure of a CAC (Cloud-Aligned Composite) -OS that can be used for the transistor disclosed in one embodiment of the present invention is described below.

In addition, in this specification etc., it may describe as CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material structure.

CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and the whole material has a function as a semiconductor. Note that in the case where CAC-OS or CAC-metal oxide is used for an active layer of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is a carrier. This function prevents electrons from flowing. A function of switching (a function of turning on / off) can be imparted to CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

Further, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, respectively. There is.

Also, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.

That is, CAC-OS or CAC-metal oxide can also be called a matrix composite material (metal matrix composite) or a metal matrix composite material (metal matrix composite).

[Structure of metal oxide]
An oxide semiconductor (metal oxide) is classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), and a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor). OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductor.

The CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and has a strain. Note that the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.

Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons. In addition, there may be a lattice arrangement such as a pentagon and a heptagon in the distortion. Note that in the CAAC-OS, it is difficult to check a clear crystal grain boundary (also referred to as a grain boundary) even in the vicinity of strain. That is, it can be seen that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Because.

In addition, the CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. There is a tendency to have a structure (also called a layered structure). Note that indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.

CAAC-OS is a highly crystalline metal oxide. On the other hand, since it is difficult to confirm a clear crystal grain boundary in the CAAC-OS, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs. In addition, since the crystallinity of the metal oxide may be reduced due to entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the metal oxide including a CAAC-OS are stable. Therefore, a metal oxide including a CAAC-OS is resistant to heat and has high reliability.

Nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

A-like OS is a metal oxide having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.

Oxide semiconductors (metal oxides) have various structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[Transistor with metal oxide]
Next, the case where the metal oxide is used for a channel formation region of a transistor will be described.

Note that a transistor with high field-effect mobility can be realized by using the metal oxide for a channel formation region of the transistor. In addition, a highly reliable transistor can be realized.

For the transistor, a metal oxide with low carrier density is preferably used. In the case where the carrier density of the metal oxide film is lowered, the impurity concentration in the metal oxide film may be lowered and the defect level density may be lowered. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic. For example, the metal oxide has a carrier density of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / What is necessary is just to be cm ³ or more.

Further, since the metal oxide film having high purity intrinsic or substantially high purity intrinsic has a low defect level density, the trap level density may also be low.

Further, the charge trapped in the trap level of the metal oxide takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor including a metal oxide with a high trap state density in a channel formation region may have unstable electrical characteristics.

Therefore, to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide. In order to reduce the impurity concentration in the metal oxide, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.

[impurities]
Here, the influence of each impurity in the metal oxide will be described.

In the metal oxide, when silicon or carbon, which is one of Group 14 elements, is included, a defect level is formed in the metal oxide. Therefore, the concentration of silicon or carbon in the metal oxide and the concentration of silicon or carbon in the vicinity of the interface with the metal oxide (concentration obtained by SIMS) are 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

In addition, when the metal oxide contains an alkali metal or an alkaline earth metal, a defect level is formed and carriers may be generated. Therefore, a transistor in which a metal oxide containing an alkali metal or an alkaline earth metal is used for a channel formation region is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

Further, when nitrogen is contained in the metal oxide, electrons as carriers are generated, the carrier density is increased, and the n-type is easily obtained. As a result, a transistor in which a metal oxide containing nitrogen is used for a channel formation region is likely to be normally on. Therefore, in the metal oxide, nitrogen in the channel formation region is preferably reduced as much as possible. For example, the nitrogen concentration in the metal oxide is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less in SIMS, Preferably, it is 5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, so that oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor in which a metal oxide containing hydrogen is used for a channel formation region is likely to be normally on. For this reason, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm 3. Less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

Stable electrical characteristics can be imparted by using a metal oxide in which impurities are sufficiently reduced for a channel formation region of a transistor.

<Modification of semiconductor device>
An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS.

13, 14, and 15 are different from the semiconductor device illustrated in FIGS. 9 to 12 in that the transistor 200 is provided with an insulator 272 instead of the insulator 275. Note that the description of the semiconductor device illustrated in FIGS. 9 to 12 can be referred to for description of other structures. Similarly, the transistor 500 is provided with an insulator 572 instead of the insulator 575. Although not illustrated, the transistor 700 is similarly provided with an insulator equivalent to the insulator 572 instead of the insulator 775. Hereinafter, the description of the insulator 272 can be referred to for the insulator 572 and the insulator corresponding to the insulator 572.

FIG. 13A is a top view of a semiconductor device having a memory cell 600. FIG. FIGS. 13B, 14A, and 14B are cross-sectional views of the semiconductor device. Here, FIG. 13B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 13A and is a cross-sectional view in the channel length direction of the transistor 200 and in the channel width direction of the transistor 500. . FIG. 14A is a cross-sectional view taken along the dashed-dotted line A3-A4 in FIG. 13A and is a cross-sectional view in the channel width direction of the transistor 200. FIG. 14B is a cross-sectional view taken along the dashed-dotted line A5-A6 in FIG. 13A and also a cross-sectional view in the channel length direction of the transistor 500. Note that in the top view of FIG. 13A, some elements are omitted for clarity. Further, the cross section of the portion indicated by the dashed-dotted line A7-A8 in FIG. 13A is the same as the structure illustrated in FIG. Further, the cross section of the portion indicated by the single-dot chain line in FIG. 13A is the same as the structure shown in FIG. FIG. 15 shows an enlarged view of a region 239 surrounded by a broken line in FIG.

The insulator 272 is provided in contact with the side surface of the oxide 230 c, the side surface of the insulator 250, the side surface of the metal oxide 252, the side surface of the conductor 260, and the side surface of the insulator 270. Here, the insulator 272 functions as a buffer layer. Note that the insulator 272 may be formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. In that case, the insulator 272 also has a function as a barrier layer.

For example, the insulator 272 is preferably formed using an ALD method. By using the ALD method, a dense thin film can be formed. For the insulator 272, for example, aluminum oxide, hafnium oxide, or the like is preferably used. In the case where aluminum oxide is provided using the ALD method as the insulator 272, the thickness of the insulator 272 is preferably greater than or equal to 0.5 nm and less than or equal to 3.0 nm.

By providing the insulator 272, side surfaces of the insulator 250, the metal oxide 252, and the conductor 260 can be covered with an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. Therefore, entry of impurities such as hydrogen and water into the oxide 230 from the insulator 250, the end portions of the metal oxide 252, and the like can be suppressed. Therefore, formation of oxygen vacancies at the interface between the oxide 230 and the insulator 250 is suppressed, and the reliability of the transistor 200 can be improved. That is, the insulator 272 functions as a side barrier that protects the side surfaces of the gate electrode and the gate insulator.

16 and FIG. 17 includes an insulator 135 provided over the transistor 200 and the transistor 500, and the transistor 200 and the transistor 500 are connected to each other by a conductor 120a. Different from the semiconductor device shown in FIG. Note that the description of the semiconductor device illustrated in FIGS. 9 to 12 can be referred to for description of other structures.

FIG. 16A is a top view of a semiconductor device having a memory cell 600. FIG. FIGS. 16B and 17 are cross-sectional views of the semiconductor device. Here, FIG. 16B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 16A and is a cross-sectional view in the channel length direction of the transistor 200 and in the channel width direction of the transistor 500. . FIG. 17 is a cross-sectional view taken along the dashed-dotted line A9-A10 in FIG. Note that in the top view of FIG. 16A, some elements are omitted for clarity. 16A is substantially the same as the structure shown in FIGS. 10 and 11A because the cross-section of the portion indicated by the alternate long and short dashed lines in A3-A4, A5-A6, and A7-A8 in FIG.

A film containing a metal element which is formed in contact with the oxide 230 to reduce the resistance of the oxide 230 is oxidized by oxygen absorbed from the oxide 230 to be an insulator, which may increase resistance. is there. By leaving the film containing the metal element as an insulator, the film can function as an interlayer film. The insulator is referred to as an insulator 135. That is, the insulator 135 includes the same metal element as the film including the metal element.

In the case where the insulator 135 is formed, the film containing the metal element is provided with a thickness that can be insulated in a later step. For example, the film containing the metal element is provided with a thickness of 0.5 nm to 5 nm, preferably 1 nm to 2 nm.

In the case of forming the insulator 135, it is preferable that the heat treatment is performed in an oxidizing atmosphere after the heat treatment is performed once in an atmosphere containing nitrogen. By performing heat treatment once in an atmosphere containing nitrogen, oxygen in the oxide 230 is easily diffused into the film containing the metal element.

When the insulator 135 is formed, as illustrated in FIGS. 16 and 17, in the transistor 200, the insulator 135 includes at least the insulator 250, the metal oxide 252, the conductor 260, the insulator 270, the insulator 271, And the insulator 275 through the insulator 275. A layer 242 may be formed between the insulator 135 and the oxide 230. The same applies to the transistor 500 and the transistor 700.

In the memory cell 600 shown in FIGS. 16 and 17, unlike the memory cell 600 shown in FIGS. 9 to 12, the contact portions of the transistors 200 and 500 and the capacitor element 100 do not overlap.

The contact portions of the transistor 200 and the transistor 500 include openings formed in the insulator 135 and the insulator 130a over the region 231b of the oxide 230, the insulator 135 over the conductor 560, the insulator 130a, the insulator 570, and Through the opening formed in the insulator 571, the conductor 120a electrically connects one of the source and the drain of the transistor 200 to the gate of the transistor 500. Here, the conductor 120 a has the same structure as the conductor 120, and the insulator 130 a has the same structure as the insulator 130.

The capacitor 100 includes the layer 242 (the region 231b of the oxide 230), the insulator 135 over the layer 242, the insulator 130b over the insulator 135, and the conductor 120b over the insulator 130b. Furthermore, it is preferable that the conductor 120b be disposed over the insulator 130b so that at least a part thereof overlaps with the region 231b of the oxide 230. In addition, the conductor 240c is preferably disposed in contact with the conductor 120b. Here, the conductor 120b has the same structure as the conductor 120, the insulator 130b has the same structure as the insulator 130, and the conductor 240c has the same structure as the conductor 240b.

The region 231 b of the oxide 230 functions as one of the electrodes of the capacitor 100, and the conductor 120 b functions as the other of the electrodes of the capacitor 100. The insulator 130b and the insulator 135 function as a dielectric of the capacitor 100. The region 231b of the oxide 230 has a reduced resistance and is a conductive oxide. Therefore, it can function as one of the electrodes of the capacitor 100.

In the above embodiment, when two memory cells are arranged adjacent to each other as shown in FIG. 2C, two memory cells 600 (memory cell 600a and memory cell 600b) are arranged as shown in FIG. May be arranged. The memory cell 600a includes a transistor 200a, a transistor 500a, and a capacitor 100a. The memory cell 600b includes a transistor 200b, a transistor 500b, and a capacitor 100b.

Here, the conductor 260_a and the conductor 260_b included in the memory cell 600a and the memory cell 600b illustrated in FIG. 18 correspond to the conductor 260, the insulator 275_a and the insulator 275_b correspond to the insulator 275, and the conductor 203_a and the conductor 203_b correspond to the conductor 203, the conductor 110_a and the conductor 110_b correspond to the conductor 110, the conductor 120_a and the conductor 120_b correspond to the conductor 120, and the conductor 540a_a and the conductor 540a_b. Corresponds to the conductor 540a, and the conductor 540b_a and the conductor 540b_b correspond to the conductor 540b.

One of the source and drain of the transistor 200a and one of the source and drain of the transistor 200b are both electrically connected to the conductor 240. Further, the conductor 112 provided on the conductor 240 is connected to the conductor 240. As described above, by sharing the wiring electrically connected to one of the source and the drain, the area occupied by the memory cell array can be further reduced. Note that a conductor that extends in parallel with the conductor 112 may be provided over any one or more of the conductors 540a_a, 540a_b, 540b_a, and 540b_b.

As shown in FIG. 18, an insulator 275_a is provided on the side surface of the gate of the transistor 200a and an insulator 275_b is provided on the side surface of the gate of the transistor 200b, whereby the common conductor 240 is replaced with the transistor 200a and the transistor 200b. It can be formed in a self-aligned manner without being short-circuited with the gate. Here, the conductor 240 preferably has a region in contact with one or both of the side surfaces of the insulator 275_a and the insulator 275_b.

In order to form an opening for embedding the conductor 240, the opening condition of the insulator 280, the insulator 274, and the insulator 273 is such that the etching rate of the insulator 275 is significantly lower than the etching rate of the insulator 273. It is preferable to do. When the etching rate of the insulator 275 is 1, the etching rate of the insulator 273 is preferably 5 or more, more preferably 10 or more. Here, the insulating material used as the insulator 275 is preferably selected as appropriate in accordance with the etching conditions and the insulating material used as the insulator 273 so as to satisfy the above etching rate. For example, as the insulating material used as the insulator 275, an insulating material that can be used for the insulator 270 as well as the above insulating material may be used.

By forming the opening for embedding the conductor 240 in this manner, the insulator 275_a and the insulator 275_b function as an etching stopper when the opening is formed, and thus the opening is prevented from reaching the conductor 260_a and the conductor 260_b. be able to. Therefore, the conductor 240 and the opening in which the conductor 240 is embedded can be formed in a self-aligning manner. For example, even when the opening for forming the conductor 240 is formed to be shifted to the A1 side or the A2 side, the conductor 240 and the conductor 260_a or the conductor 260_b do not contact each other. In addition, the width of the opening in which the conductor 240 is formed in the channel length direction of the transistor 200 is larger than the distance between the insulator 275_a and the insulator 275_b, so that the conductor 240 is formed even when the opening is displaced. Good contact can be made with layer 242.

Therefore, the alignment margin between the contact portions of the transistors 200a and 200b, the gate of the transistor 200a, and the gate of the transistor 200b can be widened, and the interval between these components can be designed to be small. As described above, miniaturization and high integration of the semiconductor device can be achieved.

As shown in FIG. 18, a conductor corresponding to the conductor 240b of the transistor 200a and the transistor 200b is not necessarily provided. For example, as illustrated in FIG. 18, when the conductors 120_a and 120_b are extended to function as wirings, the conductors 240b of the transistors 200a and 200b are not necessarily provided. Similarly to the conductor 120_a and the conductor 120_b, the conductor 260_a, the conductor 260_b, the conductor 203_a, and the conductor 203_b may function as wirings, and in that case, in the channel width direction of the transistor 200a or the transistor 200b You may provide by extending | stretching. Note that in FIG. 18, the conductor 120_a, the conductor 120_b, the conductor 203_a, and the conductor 203_b that function as wirings are extended in the same direction as the conductor 260_a and the conductor 260_b; The semiconductor device is not limited to this, and may be appropriately arranged in accordance with the circuit arrangement of the memory cell array and the driving method.

The memory cell 600a and the memory cell 600b illustrated in FIG. 18 can have a structure in which the conductor 260_a and the conductor 260_b functioning as wirings and the conductor 112 functioning as a wiring are orthogonal to each other.

In the above embodiment, when a plurality of layers including the memory cell 600 are stacked as illustrated in FIG. 3, as illustrated in FIG. 19, the layer 310 including the transistors 300 a to 300 c is formed on the layer 310. A layer 610 including the transistor 700 and the memory cell 600 may be stacked. In FIG. 19, the layer 610 is laminated | stacked from the 1st layer to the Nth layer. Here, one of the source and the drain of the transistor 300a is preferably electrically connected to one of the source and the drain of the transistor 700 in each layer 610 through a conductor functioning as the wiring CL. As shown in FIG. 19, by stacking a plurality of cell arrays, the cells can be integrated and arranged without increasing the exclusive area of the cell array. That is, a 3D cell array can be configured.

According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a highly productive semiconductor device can be provided.

This embodiment mode can be combined with any of the other embodiment modes as appropriate.

(Embodiment 3)
In this embodiment, examples of electronic devices each including the semiconductor device described in any of the above embodiments will be described.

20A includes a computing device 2110, an illuminance sensor 2101, a microphone 2102, an upper camera 2103, a speaker 2104, a display 2105, a lower camera 2106, an obstacle sensor 2107, and a moving mechanism 2108.

In the robot 2100, the semiconductor device can be used for the arithmetic device 2110, the illuminance sensor 2101, the upper camera 2103, the lower camera 2106, the obstacle sensor 2107, and the like.

The microphone 2102 has a function of detecting a user's speaking voice and environmental sound. The speaker 2104 has a function of emitting sound. The robot 2100 can communicate with the user using the microphone 2102 and the speaker 2104.

The display 2105 has a function of displaying various information. The robot 2100 can display information desired by the user on the display 2105. The display 2105 may be equipped with a touch panel.

The upper camera 2103 and the lower camera 2106 have a function of imaging the surroundings of the robot 2100. The obstacle sensor 2107 can detect the presence or absence of an obstacle in the traveling direction when the robot 2100 moves forward using the moving mechanism 2108. The robot 2100 can recognize the surrounding environment using the upper camera 2103, the lower camera 2106, and the obstacle sensor 2107, and can move safely.

A flying object 2120 shown in FIG. 20B includes a calculation device 2121, a propeller 2123, and a camera 2122, and has a function of flying independently.

In the flying object 2120, the semiconductor device can be used for the arithmetic device 2121 and the camera 2122.

FIG. 20C is an external view showing an example of an automobile. The automobile 2980 has a camera 2981 and the like. The automobile 2980 includes various sensors such as an infrared radar, a millimeter wave radar, and a laser radar. The automobile 2980 can analyze an image taken by the camera 2981, determine surrounding traffic conditions such as the presence or absence of a pedestrian, and perform automatic driving.

In the automobile 2980, the above semiconductor device can be used for the camera 2981.

FIG. 20D shows a situation in which the portable electronic device 2130 performs simultaneous interpretation in communication between a plurality of people who speak in different languages.

The portable electronic device 2130 includes a microphone, a speaker, and the like, and has a function of recognizing a user's speaking voice and translating it into a language spoken by the other party. The semiconductor device can be used for the arithmetic device of the portable electronic device 2130.

In FIG. 20D, the user has a portable microphone 2131. The portable microphone 2131 has a wireless communication function and a function of transmitting detected sound to the portable electronic device 2130.

FIG. 21 (A) is a schematic cross-sectional view showing an example of a pacemaker.

The pacemaker body 5300 includes at least batteries 5301a and 5301b, a regulator, a control circuit, an antenna 5304, a wire 5302 to the right atrium, and a wire 5303 to the right ventricle.

The semiconductor device can be used for the pacemaker body 5300.

The pacemaker body 5300 is placed in the body by surgery, and two wires pass through the human subclavian vein 5305 and superior vena cava 5306, one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium. To be.

Further, power can be received by the antenna 5304, and the power is charged in a plurality of batteries 5301a and 5301b, so that the pacemaker replacement frequency can be reduced. Since the pacemaker body 5300 has a plurality of batteries, it is highly safe, and even if one of the pacemakers breaks down, the other can function, and thus functions as an auxiliary power source.

In addition to an antenna 5304 that can receive power, an antenna that can transmit physiological signals may be provided. For example, physiological signals such as a pulse, a respiratory rate, a heart rate, and a body temperature can be confirmed by an external monitor device. A system for monitoring cardiac activity may be configured.

21B is attached to the human body using an adhesive pad or the like. The sensor 5900 gives a signal to the electrode 5931 or the like attached to the human body via the wiring 5932 and acquires biological information such as a heart rate and an electrocardiogram. The acquired information is transmitted as a wireless signal to a terminal such as a reader.

The above semiconductor device can be used for the sensor 5900.

FIG. 22 is a schematic diagram showing an example of a cleaning robot.

The cleaning robot 5100 includes a display 5101 disposed on the top surface, a plurality of cameras 5102 disposed on the side surface, brushes 5103, and operation buttons 5104. Although not shown, the lower surface of the cleaning robot 5100 is provided with a tire, a suction port, and the like. In addition, the cleaning robot 5100 includes various sensors such as an infrared sensor, an ultrasonic sensor, an acceleration sensor, a piezo sensor, an optical sensor, and a gyro sensor. Moreover, the cleaning robot 5100 includes a wireless communication unit.

The above semiconductor device can be used for the camera 5102.

The cleaning robot 5100 is self-propelled, can detect the dust 5120, and can suck the dust from the suction port provided on the lower surface.

In addition, the cleaning robot 5100 can analyze the image taken by the camera 5102 and determine whether there is an obstacle such as a wall, furniture, or a step. In addition, when an object that is likely to be entangled with the brush 5103 such as wiring is detected by image analysis, the rotation of the brush 5103 can be stopped.

The display 5101 can display the remaining amount of the battery, the amount of dust sucked, and the like. Further, the route traveled by the cleaning robot 5100 may be displayed on the display 5101. Alternatively, the display 5101 may be a touch panel, and the operation buttons 5104 may be provided on the display 5101.

The cleaning robot 5100 can communicate with a portable electronic device 5140 such as a smartphone. An image captured by the camera 5102 can be displayed on the portable electronic device 5140. Therefore, the owner of the cleaning robot 5100 can know the state of the room even when away from home.

This embodiment mode can be combined with any of the other embodiment modes as appropriate.

10: Semiconductor device, 20: Layer, 21: Control circuit, 22: Processor, 23: Peripheral circuit, 24: Power supply circuit, 25: Control circuit, 26: Control circuit, 27: Control circuit, 28: Control circuit, 29: Control circuit, 30: layer, 31: cell array, 32: memory cell, 33: drive circuit, 34: drive circuit, 40: layer, 41: light receiving unit, 100: capacitive element, 100a: capacitive element, 100b: capacitive element, 110: conductor, 112: conductor, 120: conductor, 120a: conductor, 120b: conductor, 130: insulator, 130a: insulator, 130b: insulator, 135: insulator, 150: insulator, 200: transistor, 200a: transistor, 200b: transistor, 203: conductor, 205: conductor, 210: insulator, 212: insulator, 214: insulator, 216: insulator 218: conductor, 220: insulator, 222: insulator, 224: insulator, 230: oxide, 230a: oxide, 230b: oxide, 230c: oxide, 231: region, 231a: region, 231b: Region, 232: region, 232a: region, 232b: region, 234: region, 239: region, 240: conductor, 240a: conductor, 240b: conductor, 240c: conductor, 242: layer, 250: insulator 252: metal oxide, 260: conductor, 260a: conductor, 260b: conductor, 270: insulator, 271: insulator, 272: insulator, 273: insulator, 274: insulator, 275: insulation 280: insulator, 300: transistor, 300a: transistor, 300b: transistor, 300c: transistor, 310: layer, 311: substrate, 313: Conductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 321: insulator, 322: insulator, 324: insulator, 326: insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 500: Transistor, 500a: Transistor, 500b: Transistor, 503: Conductor, 505: Conductive Body, 524: insulator, 530: oxide, 530a: oxide, 530b: oxide, 530c: oxide, 540: conductor, 540a: conductor, 540b: conductor, 542: layer, 550: insulator 552: metal oxide, 560: conductor, 560a: conductor, 560b: conductor, 570: insulator, 571: insulator, 572: insulator, 575: insulator, 600: memory cell, 600a: memory cell, 600b: memory cell, 610: layer, 700: transistor, 703: conductor, 705: conductor, 724: insulator, 730: oxide, 730a: oxide, 730b: Oxide, 730c: oxide, 740: conductor, 740a: conductor, 740b: conductor, 740c: conductor, 742: layer, 745: conductor, 750: insulator, 752: metal oxide, 760: Conductor, 760a: Conductor, 760b: Conductor, 770: Insulator, 771: Insulator, 775: Insulator, 2100: Robot, 2101: Illuminance sensor, 2102: Microphone, 2103: Upper camera, 2104: Speaker, 2105: Display, 2106: Lower camera, 2107: Obstacle sensor, 2108: Moving mechanism, 2110: Computing device 2120: Aircraft, 2121: Computing device, 2122: Camera, 2123: Propeller, 2130: Portable electronic device, 2131: Portable microphone, 2980: Car, 2981: Camera, 5100: Cleaning robot, 5101: Display, 5102: Camera 5103: Brush 5104: Operation button 5120: Garbage 5140: Portable electronic device 5300: Pacemaker body 5301a: Battery 5301b: Battery 5302: Wire 5303: Wire 5304: Antenna 5305: Under clavicle Vein, 5306: superior vena cava, 5900: sensor, 5931: electrode, 5932: wiring

Claims (9)

1. A first layer and a second layer above the first layer;
   The first layer has a control circuit;
   The second layer has a memory circuit;
   The control circuit has a function of controlling the operation of the memory circuit,
   The memory circuit includes a plurality of memory cells and a drive circuit,
   The memory cell includes a first transistor, a second transistor, and a capacitor,
   One of the source and the drain of the first transistor is electrically connected to the gate of the second transistor and the capacitor.
   The control circuit has a transistor formed on a semiconductor substrate,
   The first transistor and the second transistor each have a metal oxide in a channel formation region.
2. In claim 1,
   The drive circuit includes a first drive circuit and a second drive circuit,
   The first drive circuit has a function of selecting the memory cell,
   The second drive circuit has a function of writing data to the memory cell and a function of reading data stored in the memory cell,
   The first drive circuit and the second drive circuit are electrically connected to the control circuit,
   The first driver circuit and the second driver circuit each include a transistor including a metal oxide in a channel formation region.
3. In claim 1 or 2,
   A semiconductor device in which the first transistor and the second transistor have the same polarity.
4. In claim 1 or 2,
   The semiconductor device, wherein the first transistor and the second transistor are formed on the same insulating layer.
5. In claim 1 or 2,
   The control circuit is a semiconductor device having a clock generation circuit and a timing controller.
6. In claim 1 or 2,
   The first layer has a processor, a peripheral circuit, and a power supply circuit,
   The processor, the peripheral circuit, and the power supply circuit each include a transistor formed on the semiconductor substrate.
7. An electronic device having the semiconductor device according to claim 1.
8. The third layer according to claim 1 or 2, further comprising a third layer above the second layer,
   The third layer is a semiconductor device having a light receiving portion.
9. The first layer further comprises a second control circuit;
   The second control circuit is a semiconductor device electrically connected to the light receiving unit.

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