WO2018205542A1 - 一种1pps+tod信息单总线传送同步系统及方法 - Google Patents

一种1pps+tod信息单总线传送同步系统及方法 Download PDF

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Publication number
WO2018205542A1
WO2018205542A1 PCT/CN2017/111567 CN2017111567W WO2018205542A1 WO 2018205542 A1 WO2018205542 A1 WO 2018205542A1 CN 2017111567 W CN2017111567 W CN 2017111567W WO 2018205542 A1 WO2018205542 A1 WO 2018205542A1
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Prior art keywords
tod
frame
module
information
clock
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PCT/CN2017/111567
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English (en)
French (fr)
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李正辉
刘福
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烽火通信科技股份有限公司
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Publication of WO2018205542A1 publication Critical patent/WO2018205542A1/zh
Priority to PH12019500991A priority Critical patent/PH12019500991A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node

Definitions

  • the present invention relates to the field of clock synchronization, and in particular to a 1PPS+TOD information single bus transmission synchronization system and method.
  • time synchronization is a high-precision time synchronization protocol.
  • the implementation process is to transfer the 1PPS (second pulse) and TOD (day time) of the clock source provided by the source node to each slave node in the form of message interaction.
  • the slave node synchronizes with the time of the source node.
  • the real-time time between the service board and the main control board also needs to be synchronized.
  • the 1588 synchronization core unit is located on the main control board.
  • the main control board needs to transmit the local real-time time to the service disk card, so that the service board can accurately update the 1588 time stamp.
  • Communication between the main control board and the service board is performed through the backplane bus.
  • a clock, a PPS port, and a serial TOD port are required, occupying at least three backplane buses.
  • the backplane bus is used to realize signal interconnection between the boards, and is an important element constituting the device.
  • backplane bus speed, bandwidth, and integration continue to increase, but backplane bus resources are limited, and the number of backplane bus ports is larger, and the stability of communication is more difference.
  • multi-backplane bus communication there are mutual interference between multiple backplane buses.
  • the lengths of the backplane buses are required to be the same. If the lengths are different, a certain amount of synchronous transmission will occur. influences.
  • the object of the present invention is to provide a 1PPS+TOD information single bus transmission synchronization system and method, which can transmit 1PPS+TOD information through a single bus, thereby saving backplane bus resources and improving communication stability. Does not affect synchronous transmission.
  • the present invention adopts a 1PPS+TOD information single bus transmission synchronization system, including a transmitting end and a receiving end, and the transmitting end and the receiving end are connected through a backplane bus;
  • the sending end includes:
  • a first sampling module configured to set a sampling frequency of the local TOD information and sample
  • a framing module configured to encapsulate the TOD information in the storage module into a TOD frame to be sent;
  • the TOD frame includes a frame header, a frame sequence number, a type, a length, a TOD data payload, a check field, and a gap for filling the two TOD frames.
  • a verification module configured to calculate a check field of the TOD frame to be sent
  • a code sending module configured to send a TOD frame code, the encoded TOD frame carries a clock rising edge information of the transmitting end, and is further configured to send the encoded TOD frame to the receiving end;
  • phase locked loop frequency multiplication module configured to recover clock information from the received TOD frame encoded data stream
  • a second sampling module configured to find an intermediate moment of a symbol of the TOD encoded bit stream and sample in the recovered clock domain
  • a decoding module configured to decode the received TOD serial bit information into a TOD frame
  • a deframing module configured to decompose the decoded TOD frame into respective fields and transmit the same to the verification module
  • a verification module configured to verify the TOD frame by means of a checksum, and transmit the verification result to the TOD maintenance module
  • the TOD maintenance module is used to update the local TOD of the receiving end by using the current receiving TOD when the TOD frame is not lost and the calibration is correct.
  • the local TOD adds a TOD maintenance clock cycle ⁇ X to complete the TOD real-time and the transmitting end of the receiving end.
  • the first sampling module samples the local TOD information at a frequency of 10000 times per second with a clock of 125M, and the sampling module of the second sampling module is the same as the sampling period of the first sampling module.
  • the code sending module modulates the falling edge phase of the transmitting clock by using the bit information stream of the TOD frame to be transmitted, and the rising edge phase remains unchanged, and the modulated serial TOD information is 25 Mbits/s encoding.
  • the rate of the chip, the effective information rate of the modulated bearer is 6.25 Mbits/s.
  • the local TOD information of the transmitting end is a 125M clock domain, and includes 80-bit information, a 48-bit second value, and a 32-bit nanosecond value.
  • the position of the PPS pulse is 125M.
  • the clock is used as both the sampling clock for receiving the TOD and the TOD maintenance clock. That is, one TOD maintenance clock period ⁇ X is equal to the TOD sampling reception clock period, which is 8 ns.
  • the invention also provides a 1PPS+TOD information single bus transmission synchronization method, comprising: The sending end sets the sampling times of the local TOD information every second through the first sampling module, and samples and stores the data into the storage module, and the framing module uses the check field calculated by the check module to perform framing for each acquired TOD information. Then, the coded transmitting module serially encodes the TOD frame to be transmitted to the receiving end; the phase locked loop frequency multiplying module of the receiving end recovers the clock information from the received TOD encoded data stream, and finds the symbol through the second sampling module. The intermediate time is sampled, and the frame synchronization module performs frame synchronization by searching for the frame header information to determine whether there is frame loss.
  • the TOD frame that finds the frame header information is decoded and deframed to obtain each field, and the TOD frame is checked in a checksum manner.
  • the check field is checked; when the TOD frame check is correct and there is no loss, the TOD maintenance module updates the local TOD with the correct TOD, and adds a TOD maintenance clock cycle ⁇ X every clock cycle to complete the TOD real-time and the transmit TOD. Synchronization; for TOD frame loss or verification error, the TOD maintenance module uses the last correctly received TOD frame to add a TOD maintenance clock cycle ⁇ X TOD synchronization.
  • the frame synchronization module searches for a specific pattern of the frame header in a sliding shift register manner to complete frame synchronization, by monitoring the time interval between the frame headers of the two TOD frames and the two TOD frames at the transmitting end. Whether the sampling transmission interval is equal to determine whether there is a frame loss.
  • the coding scheme of the encoded TOD frame is that the information bit 1 is represented by the symbol 1000, the information bit 0 is represented by the symbol 1110, and the idle information filling the gap of the two frames is represented by the symbol 1100;
  • the specific pattern of the header is 01110110.
  • the local clock domain sampled by the TOD of the transmitting end is 125M, and the TOD frame after the framing adopts the rate of encoding chips of 25 Mbits/s, that is, the effective information data stream of 6.25 Mbits/s is actually transmitted to the receiving.
  • the clock domain of the frequency-recovery of the phase-locked loop of the receiving end is 125M, and the clock is simultaneously used as the sampling clock for receiving the TOD and the TOD maintenance clock, that is, a TOD maintenance clock period ⁇ X is equal to the TOD sampling receiving clock period. Both are 8ns.
  • B102 Determine whether the receiving nanosecond is greater than or equal to 10 9 - ⁇ T, where ⁇ T is the time interval between two TOD transmission frames, and if so, enter B103; if not, enter B 104;
  • B105 Determine whether the local nanosecond portion is greater than or equal to 10 9 - ⁇ X, and if so, enter B106; if not, enter B107;
  • the TOD maintenance module performs a nanosecond partial update including the following steps:
  • A101 Determine whether the TOD frame header arrives, the TOD frame is not lost and the check is correct, and if so, enter A 102; if not, enter A 105;
  • a 102 Determine whether the receiving nanosecond is greater than or equal to 10 9 - ⁇ T, where ⁇ T is the time interval between two TOD transmission frames, and if so, enter A 103; if not, enter A 104;
  • a 104. Local nanoseconds receiving nanoseconds + ⁇ T, ending;
  • a 105 Determine whether the local nanosecond portion is greater than or equal to 10 9 - ⁇ X, where ⁇ X is the period of the TOD maintenance clock, and if so, enter A106; if not, enter A107;
  • Local nanosecond local nanosecond + ⁇ X-10 9 , end;
  • the invention also provides a 1PPS+TOD information single bus transmission synchronization system, comprising a transmitting end and a receiving end, wherein the transmitting end and the receiving end are connected by a backplane bus;
  • the sending end includes:
  • a first sampling module configured to set a sampling frequency of the local TOD information and sample
  • a framing module configured to encapsulate the TOD information in the storage module into a TOD frame to be sent;
  • the TOD frame includes a frame header, a frame sequence number, a type, a length, a TOD data payload, a check field, and a gap for filling the two TOD frames.
  • a verification module configured to calculate a check field of the TOD frame to be sent
  • a code sending module configured to send a TOD frame code, the encoded TOD frame carries a clock rising edge information of the transmitting end, and is further configured to send the encoded TOD frame to the receiving end;
  • the receiving end includes:
  • a second sampling module configured to find an intermediate moment of a symbol of the TOD encoded bit stream and sample in a local clock domain provided by the receiving end;
  • a frame synchronization module configured to find a frame header specific pattern to complete frame synchronization, and transmit whether there is frame loss information to the TOD maintenance module;
  • a decoding module configured to decode the received TOD serial bit information into a TOD frame
  • a deframing module configured to decompose the decoded TOD frame into respective fields and transmit the same to the verification module
  • the first sampling module samples the local TOD information at a frequency of 10000 times per second with a clock of 125M, and the sampling module of the second sampling module is the same as the sampling period of the first sampling module.
  • the code sending module modulates the falling edge phase of the transmitting clock by using the bit information stream of the TOD frame to be transmitted, and the rising edge phase remains unchanged, and the modulated serial TOD information is 25 Mbits/s encoding.
  • the rate of the chip, the effective information rate of the modulated bearer is 6.25 Mbits/s.
  • the local TOD information sampling clock of the transmitting end is a 125M clock domain, which includes 80 bits of information, 48 bits of second value, 32 bits of nanosecond value, and the position of the PPS pulse when the TOD nanosecond value is 0;
  • the receiving TOD sampling clock provided by the terminal is a 125M clock domain, which is used as both the sampling clock for receiving the TOD and the TOD maintenance clock, that is, one TOD maintenance clock period ⁇ X is equal to the TOD sampling reception clock period, which is 8 ns.
  • the invention also provides a PPS+TOD information single bus transmission synchronization method, which comprises: the sending end sets the sampling times of the local TOD information per second through the first sampling module, and samples and stores the data in the storage module, and the framing module uses the verification.
  • the check field calculated by the module performs framing once for each acquired TOD information, and then the coded transmitting module serially encodes the TOD frame to be transmitted to the receiving end; the second sampling module of the receiving end provides the local at the receiving end In the clock domain, the intermediate moment of the symbol of the TOD encoded bit stream is found and sampled, and the frame synchronization module performs frame synchronization by searching for the frame header information to determine whether there is frame loss; then decoding and de-frameing the TOD frame that finds the frame header information, and solving Each field is verified by the checksum in the check field of the TOD frame; when the TOD frame is verified correctly and there is no loss, the TOD maintenance module updates the local TOD with the correct TOD, Real-time TOD synchronization is completed by adding one TOD maintenance clock cycle ⁇ X per clock cycle; for TOD frame loss or verification error, the TOD maintenance module completes real-time TOD synchronization by adding a TOD maintenance clock cycle ⁇ X to the most correctly received TOD frame. .
  • the frame synchronization module searches for a specific pattern of the frame header in a sliding shift register manner to complete frame synchronization, by monitoring the time interval between the frame headers of the two TOD frames and the two TOD frames at the transmitting end. Whether the sampling transmission interval is equal to determine whether there is a frame loss.
  • the coding scheme of the encoded TOD frame is that the information bit 1 is represented by the symbol 1000, the information bit 0 is represented by the symbol 1110, and the idle information filling the gap of the two frames is represented by the symbol 1100;
  • the specific pattern of the header is 01110110.
  • the local clock domain of the transmitting end is 125M
  • the TOD frame after the framing adopts a coded chip rate of 25 Mbits/s, that is, the effective information data stream of 6.25 Mbits/s is actually transmitted to the receiving end; the receiving end
  • the TOD local sampling receive clock is 125M.
  • This clock is used as both the sampling clock for receiving the TOD and the TOD maintenance clock. That is, one TOD maintenance clock period ⁇ X is equal to the TOD sampling reception clock period, which is 8 ns.
  • the local 125M clock of the transmitting end and the local 125M clock of the receiving end are mutually independent clock domains, and the frequency offset of the two 125M clock domains is controlled within 100 ppm, and the TOD real-time recovered by the receiving end is real-time.
  • the accuracy of the time and the TOD real time of the transmitting end is within ⁇ 10 ns.
  • the transmitting end serially encodes the TOD frame by the encoding and transmitting module, and the encoding and transmitting module modulates the falling edge phase of the transmitting clock by using the bit information stream of the TOD frame to be transmitted, and the rising edge phase remains unchanged, and the encoded TOD frame carries the originating clock.
  • the rising edge information therefore, the transmission of 1PPS+TOD information can be realized through one bus, which maximizes the saving of backplane bus resources, and the communication process is more stable and reliable than the scheme of multiple parallel buses.
  • the receiving end uses the phase-locked loop multiplier or the local TOD information to decode and verify the received TOD frame to ensure the synchronous transmission of the TOD frame and improve the synchronization accuracy.
  • FIG. 1 is a schematic diagram of a transmitting end of a PPS+TOD information single bus transmission synchronization system according to Embodiment 1 of the present invention
  • FIG. 2 is a schematic diagram of a receiving end of a PPS+TOD information single bus transmission synchronization system according to a first embodiment of the present invention
  • FIG. 3 is a schematic diagram of a receiving end of a PPS+TOD information single bus transmission synchronization system according to a second embodiment of the present invention.
  • the transmitting end 1 the first sampling module 11, the storage module 12, the framing module 13, the verification module 14, the encoding and transmitting module 15;
  • the PPS+TOD information single bus transmission synchronization system of the embodiment 1 includes a transmitting end 1 and a receiving end 2, and the transmitting end 1 and the receiving end 2 are connected by a backplane bus.
  • the transmitting end 1 includes a first sampling module 11 , a storage module 12 , a framing module 13 , a verification module 14 , and a code sending module 15 .
  • the first sampling module 11 is configured to set the sampling times of the local TOD information (that is, how many frames are transmitted per second) and sample.
  • the first sampling module 11 samples the local frequency by a frequency of 125 M according to a frequency of 10000 times per second.
  • the local TOD information of the sender 1 is a 125M clock domain, which contains 80 bits of information, a 48-bit second value, a 32-bit nanosecond value, and a TOD nanosecond value of 0 is the position of the PPS pulse.
  • the coding scheme of the encoded TOD frame is: the information bit 1 is represented by the symbol "1000”, the information bit 0 is represented by the symbol "1110", the idle information filling the gap of the two frames is represented by the symbol "1100”; the specific header is included in the frame header Type, the specific pattern in this embodiment is "01110110".
  • the position corresponding to the falling edge of the clock of the transmitting end carries the TOD data information, and the rising edge carries the rising edge information of the clock of the transmitting end.
  • the local clock domain of the TOD sampling is 125M
  • the clock is simultaneously used as the sampling clock for receiving the TOD and the TOD maintenance clock, that is, one TOD maintenance clock period ⁇ X is equal to the TOD sampling reception clock period, which is 8 ns.
  • the transmission rate of the TOD frame obtained after sampling the frame is measured at a rate of 25 Mbits/s (derived by the local 125M), that is, the actual information stream of 6.25 Mbits/s is actually transmitted to the receiving end, and the 6.25 Mbits/
  • the rising edge of the s bit stream is fixed in phase.
  • 25Mbits/s and 6.25Mbits/s are the same as the local 125M clock, so the rising edge of 6.25Mbits/s also reflects the rising edge of the 125M clock.
  • the receiving end 2 includes a phase locked loop frequency multiplying module 20, a second sampling module 21, a frame synchronization module 22, a decoding module 23, a deframing module 24, a verification module 25, and a TOD maintenance module 26.
  • the phase locked loop multiplier module 20 is configured to recover 125 M of clock information from the received TOD frame data stream.
  • the second sampling module 21 is configured to find and sample the intermediate moments of the symbols of the 25M serial TOD encoded bitstream in the recovered clock domain.
  • the frame synchronization module 22 is configured to find a frame header specific pattern to complete frame synchronization, and determine whether there is frame loss by monitoring whether the time interval between the frame headers of the two TOD frames and the sampling transmission interval between the two TOD frames at the transmitting end are equal.
  • the decoding module 23 is configured to decode the received TOD serial bit information into a TOD frame according to an encoding rule described by the transmitting end encoding.
  • the demapping module 24 is configured to decompose the decoded TOD frame into various fields and transmit the same to the verification module 25.
  • the verification module 25 verifies the TOD frame in a checksum manner. If the verification is incorrect, the frame is discarded; the verification module 25 also needs to send the verification result to the TOD maintenance module 26.
  • the TOD frame that was correctly received last time is automatically maintained by a TOD maintenance clock cycle ⁇ X, and the real-time synchronization between the TOD of the receiving end and the TOD of the transmitting end is completed.
  • the locally maintained TOD nanosecond portion is 0, the PPS pulse is recovered from the TOD, and the pulse width of the PPS can be dynamically configured.
  • the first embodiment 1PPS+TOD information single bus transmission synchronization method includes the following steps:
  • the transmitting end 1 sets the sampling of the local TOD information every second through the first sampling module 11 The number of times, and the sample is stored in the storage module 12, and the verification module calculates a verification field.
  • the framing module 13 uses the check field to perform framing for each acquired TOD information.
  • the TOD frame includes a frame header, a frame number, and Type, length, TOD data payload, check field, and empty symbols used to fill the gap between the two TOD frames.
  • the TOD frame to be transmitted is serially encoded by the code transmitting module 15 and then transmitted to the receiving end 2.
  • the receiving end 2 phase-locked loop frequency multiplying module 20 recovers the clock information from the TOD frame data stream from the transmitting end 1, and specifically, uses the receiving phase-locked loop (the FPGA has its own phase-locked loop) to raise the clock of the carrying transmitter.
  • the 25M serial TOD frame code stream along the information is multiplied to 125M, and the phase relationship between the 125M clock obtained by the multiplication and the originating 125M clock is locked.
  • the optimal sampling point (i.e., the intermediate time of the symbol) of the 25M serial TOD encoded bit stream is then found and sampled by the second sampling module 21 under the control of the counter.
  • the frame synchronization module 22 searches for the frame header information (including the frame header specific pattern) in a sliding shift register for frame synchronization, and monitors the sampling interval between the two frame headers and the sampling between the two TOD frames at the transmitting end. Whether the transmission time interval is equal is judged whether there is a frame loss, and the result is notified to the TOD maintenance module 26.
  • the TOD frame in which the header information is found is then decoded by the decoding module 23, and the decoding rule is the same as the encoding rule of the transmitting end 1.
  • the decoded TOD data frame is further decomposed into fields by the deframing module 24 and transmitted to the verification module 25.
  • the check module 25 checks the check field in the TOD frame in a checksum manner, and sends the check result to the TOD maintenance module 26; if the check module 25 checks the error, the TOD frame is discarded.
  • the real-time TOD is synchronized with the transmitting terminal TOD; for TOD frame loss or verification error, the TOD maintenance module 26 uses the TOD frame that was correctly received last time to add a TOD maintenance clock cycle ⁇ X to complete the TOD real-time and the transmitting TOD. Synchronize.
  • B102 Determine whether the receiving nanosecond is greater than or equal to 10 9 - ⁇ T, where ⁇ T is the time interval between two TOD transmission frames, and if so, enter B103; if not, enter B 104;
  • Local seconds receiving seconds, that is, the receiving seconds part directly replaces the local seconds part to realize the second partial maintenance, and ends;
  • B105 Determine whether the local nanosecond portion is greater than or equal to 10 9 - ⁇ X; if yes, enter B106; if not, enter B107;
  • FIG. 5 is a flowchart of a nanosecond partial update process performed by the TOD maintenance module of the present invention, specifically including the steps:
  • A101 Determine whether the TOD frame header arrives, the TOD frame is not lost and the check is correct, and if so, enter A 102; if not, enter A 105;
  • a 102 Determine whether the receiving nanosecond is greater than or equal to 10 9 - ⁇ T, where ⁇ T is the time interval between two TOD transmission frames, and if so, enter A 103; if not, enter A 104;
  • Local nanoseconds receiving nanoseconds + ⁇ T-10 9 , receiving nanoseconds + ⁇ T-10 9 results in place of local nanoseconds to complete maintenance, where ⁇ T is the time interval between two TOD transmission frames, ending ;
  • a 105 Determine whether the local nanosecond portion is greater than or equal to 10 9 - ⁇ X, where ⁇ X is a TOD maintenance clock period (equal to the TOD sampling reception clock period, which is 8 ns in this embodiment), and if so, enter A 106; if not, enter A 107;
  • Local nanosecond local nanosecond + ⁇ X-10 9 , realize local nanosecond partial self-maintaining carry and clear, end;
  • Local nanosecond local nanosecond + ⁇ X, the local nanosecond part realizes the maintenance of self-adding ⁇ X, and ends.
  • the PPS+TOD information single bus transmission synchronization system of the present embodiment includes a transmitting end 1 and a receiving end 2, and the transmitting end 1 and the receiving end 2 are connected by a backplane bus.
  • the transmitting end has the same structure and function as the transmitting end 1 of the first embodiment.
  • the receiving end 2' is similar to the receiving end 2 of the first embodiment, except that the receiving end 2' of the embodiment does not include the phase locked loop multiplying module 20, and includes the second sampling module 21, frame synchronization.
  • Module 22, decoding module 23, deframing module 24, verification module 25, TOD maintenance module 26 are similar to the receiving end 2 of the first embodiment, except that the receiving end 2' of the embodiment does not include the phase locked loop multiplying module 20, and includes the second sampling module 21, frame synchronization.
  • the second sampling module is configured to find the intermediate moment of the symbol of the TOD encoded bit stream and sample in the local clock domain provided by the receiving end 2'; the structure and use of the remaining modules of the receiving end 2' and the first
  • the second embodiment can directly perform TOD sampling reception by using a local 125M clock; however, for a system with more accurate time synchronization, the receiving end should adopt the first embodiment, that is, The first embodiment is more accurate than the second embodiment.
  • the PPS+TOD information single bus transmission synchronization method includes the following steps:
  • the second sampling module 21 of the receiving end 2' finds the intermediate time of the symbol of the TOD encoded bit stream and samples it in the local clock domain provided by the receiving end, and then the frame synchronization module 22 searches for the frame header information by means of the sliding shift register. (including the frame header specific pattern) to perform frame synchronization, and determine whether there is frame loss by monitoring whether the time interval between the frame headers of the two frames and the interval between the two TOD frames of the transmitting end are equal, and notifying the result TOD maintenance module 26.
  • the TOD frame in which the header information is found is then decoded by the decoding module 23, and the decoding rule is the same as the encoding rule of the transmitting end 1.
  • the decoded TOD data frame is further decomposed into the respective fields by the demapping module 24, and then sent to the verification module 25.
  • the check module 25 checks the check field in the TOD frame in a checksum manner, and sends the check result to the TOD maintenance module 26; if the check module 25 fails the check, the TOD frame is discarded.
  • the TOD maintenance module 26 updates the local TOD with the correct TOD, and adds a TOD maintenance clock cycle ⁇ X every clock cycle (equal to the TOD sample receive clock cycle, which is 8 ns in this embodiment).
  • Real-time TOD synchronization is completed; for TOD frame loss or verification error, the TOD maintenance module 26 performs real-time TOD synchronization by adding a TOD maintenance clock period ⁇ X using the most correctly received TOD frame.
  • the local clock domain of the transmitting end is 125M
  • the TOD frame after the framing adopts a coded chip rate of 25 Mbits/s, that is, the effective information data stream of 6.25 Mbits/s is actually transmitted to the receiving end.
  • the difference between this embodiment and the first embodiment is that the receiving end 2' directly uses the second sampling module 21 to complete TOD sampling reception on the local 125M clock; This clock is used as both the sampling clock for receiving the TOD and the TOD maintenance clock, that is, one TOD maintenance clock period ⁇ X is equal to the TOD sampling reception clock period, which is 8 ns.
  • the local 125M clock of the transmitting end and the local 125M clock of the receiving end are mutually independent clock domains.
  • the frequency offset of the two 125M clock domains needs to be controlled within 100ppm.
  • the TOD real-time time recovered by the receiving end and the TOD real-time time of the transmitting end are recovered.
  • the accuracy can be controlled within ⁇ 10ns.
  • the second partial update and the nanosecond partial update are the same as those in the first embodiment, and details are not described herein again.

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Abstract

一种1PPS+TOD信息单总线传送同步系统及方法，涉及时钟同步领域，发送端通过第一采样模块设置每秒对本地TOD采样次数，组帧模块将采样的TOD信息组成TOD帧，经校验模块生成校验字段，编码发送模块编码后串行传给接收端；接收端锁相环倍频模块从TOD串行数据流恢复时钟后第二采样模块利用恢复时钟，或直接由本地时钟对串行TOD采样，帧同步模块完成帧同步后，进行解码、解帧、帧校验；当TOD帧校验正确且无丢失时，TOD维护模块用正确TOD更新本地TOD；当TOD帧丢失或校验错误时，用最近一次正确接收的TOD自加ΔX完成同步。本发明通过单根总线传送1PPS+TOD信息，节约背板总线资源，提高通信稳定性。

Description

一种1PPS+TOD信息单总线传送同步系统及方法 技术领域
本发明涉及时钟同步领域，具体来讲涉及一种1PPS+TOD信息单总线传送同步系统及方法。
背景技术
随着通信技术不断发展及技术指标的不断提高，时间同步(含频率同步和相位同步)功能成为网络通信设备必须支持的基本功能。1588时间同步是一种高精度的时间同步协议，其实现过程是将源节点的提供的时钟源的1PPS(秒脉冲)和TOD(日时间)以报文交互的形式传递到各个从节点，实现从节点与源节点的时间同步。
而在各网元节点内部，业务板卡和主控板卡之间的实时时间同样需要同步。1588同步核心单元位于主控板卡上，主控板卡需要将本地实时时间传送到业务盘卡，以便业务板卡准确更新1588时戳。主控板卡和业务板卡之间通过背板总线实现通信。按照常规方案，要在背板上传送1PPS+TOD信息，需要时钟、PPS端口和串行TOD端口，至少占用3根背板总线。
在核心网络通信设备中，背板总线用来实现各单板之间的信号互连，是构成设备的重要元素。随着设备容量越来越大、单板密度越来越高，背板总线速率、带宽和集成度不断提高，但是背板总线资源有限，占用背板总线根数越多，通信的稳定性越差。另外，多背板总线通信中，多根背板总线之间存在相互干扰的情况，为了同步的需要，要求各背板总线长度相同，如果长度不同，对于同步传输会产生一定 影响。
发明内容
针对现有技术中存在的缺陷，本发明的目的在于提供一种1PPS+TOD信息单总线传送同步系统及方法，通过单根总线传送1PPS+TOD信息，节约背板总线资源，提高通信稳定性，不影响同步传输。
为达到以上目的，本发明采取一种1PPS+TOD信息单总线传送同步系统，包括发送端和接收端，发送端和接收端通过一根背板总线相连；
所述发送端包括：
第一采样模块，用于设置对本地TOD信息的采样次数并采样；
存储模块，用于存储采样得到的TOD信息；
组帧模块，用于将存储模块中TOD信息封装成待发送的TOD帧；TOD帧包括帧头、帧序号、类型、长度、TOD数据净荷、校验字段和用于填充两个TOD帧间隙的空符号；
校验模块，用于计算待发送TOD帧的校验字段；
编码发送模块，用于对待发送TOD帧编码，编码后的TOD帧携带发送端的时钟上升沿信息，还用于将编码后的TOD帧发送至接收端；
所述接收端包括：
锁相环倍频模块，用于从接收到的TOD帧编码数据流中恢复出时钟信息；
第二采样模块，用于在恢复出的时钟域内，找到TOD编码比特流的码元的中间时刻并采样；
帧同步模块，用于寻找帧头特定码型完成帧同步，并将是否有帧 丢失信息传送给TOD维护模块；
解码模块，用于对接收的TOD串行比特信息解码成TOD帧；
解帧模块，用于将解码后的TOD帧分解为各个字段，传送给校验模块；
校验模块，用于通过校验和的方式校验TOD帧，并将校验结果传送给TOD维护模块；
TOD维护模块，用于TOD帧未丢失且校验正确时，利用当前接收TOD更新接收端本地TOD，在每个时钟周期，本地TOD自加一个TOD维护时钟周期ΔX完成接收端TOD实时与发送端TOD同步；或者用于在TOD帧丢失或TOD校验错误时，利用最近一次正确接收的TOD帧自加一个TOD维护时钟周期ΔX完成实时TOD同步。
在上述技术方案的基础上，所述第一采样模块以125M的时钟按照1秒10000次的频率采样本地TOD信息，第二采样模块与第一采样模块采样周期相同。
在上述技术方案的基础上，所述编码发送模块采用待发送TOD帧的比特信息流调制发送时钟的下降沿相位，上升沿相位保持不变，调制后的串行TOD信息是25Mbits/s的编码码片的速率，调制后承载的有效信息速率为6.25Mbits/s。
在上述技术方案的基础上，所述发送端本地TOD信息为125M时钟域，包含80比特信息，48比特秒值，32比特纳秒值，TOD纳秒值为0时是PPS脉冲的位置；所述接收端从锁相环倍频恢复出的时钟为125M，该时钟同时用作接收TOD的采样时钟和TOD维护时钟，即一个TOD维护时钟周期ΔX等于TOD采样接收时钟周期，均为8ns。
本发明还提供一种1PPS+TOD信息单总线传送同步方法，包括： 发送端通过第一采样模块设置每秒对本地TOD信息的采样次数，并采样存储到存储模块中，组帧模块使用校验模块计算的校验字段、对每次采集的TOD信息进行一次组帧，再由编码发送模块对待发送TOD帧进行串行编码后传送给接收端；接收端的锁相环倍频模块从收到的TOD编码数据流中恢复出时钟信息，通过第二采样模块找到码元的中间时刻并采样，帧同步模块通过寻找帧头信息进行帧同步，判断是否有帧丢失；然后将找到帧头信息的TOD帧通过解码和解帧得到各个字段，以校验和的方式对TOD帧中校验字段进行校验；当TOD帧校验正确且无丢失时，TOD维护模块利用正确的TOD更新本地TOD，在每个时钟周期自加一个TOD维护时钟周期ΔX完成TOD实时与发送端TOD同步；对于TOD帧丢失或校验错误时，TOD维护模块利用最近一次正确接收的TOD帧自加一个TOD维护时钟周期ΔX完成实时TOD同步。
在上述技术方案的基础上，帧同步模块以滑动移位寄存器的方式寻找帧头的特定码型完成帧同步，通过监测两个TOD帧帧头的时间间隔与发送端两个TOD帧之间的采样发送时间间隔是否相等判断是否有帧丢失。
在上述技术方案的基础上，所述编码TOD帧的编码方案为，用码元1000表示信息比特1，用码元1110表示信息比特0，用码元1100表示填充两帧间隙的空闲信息；帧头的特定码型为01110110。
在上述技术方案的基础上，发送端TOD采样的本地时钟域为125M，组帧后的TOD帧采用25Mbits/s编码码片的速率，即实际以6.25Mbits/s的有效信息数据流传送给接收端；接收端锁相环倍频恢复的时钟域为125M，该时钟同时用作接收TOD的采样时钟和TOD维护时钟，即一个TOD维护时钟周期ΔX等于TOD采样接收时钟周期， 均为8ns。
在上述技术方案的基础上，所述TOD维护模块进行秒部分更新包括步骤：
B101.判断是否TOD帧头到达、TOD帧无丢失且校验正确，若是，进入B102；若否，进入B 105；
B102.判断接收纳秒是否大于等于109-ΔT，其中ΔT为两个TOD发送帧之间的时间间隔，若是，进入B103；若否，进入B 104；
B103.本地秒＝接收秒+1，结束；
B104.本地秒＝接收秒，结束；
B105.判断本地纳秒部分是否大于等于109-ΔX，若是，进入B106；若否，进入B107；
B106.本地秒＝本地秒+1，结束；
B107.本地秒＝本地秒，结束。
在上述技术方案的基础上，所述TOD维护模块进行纳秒部分更新包括步骤：
A101.判断是否TOD帧头到达、TOD帧无丢失且校验正确，若是，进入A 102；若否，进入A 105；
A 102.判断接收纳秒是否大于等于109-ΔT，其中ΔT为两个TOD发送帧之间的时间间隔，若是，进入A 103；若否，进入A 104；
A 103.本地纳秒＝接收纳秒+ΔT-109，结束；
A 104.本地纳秒＝接收纳秒+ΔT，结束；
A 105.判断本地纳秒部分是否大于等于109-ΔX，其中ΔX为TOD维护时钟的周期，若是，进入A106；若否，进入A107；
A 106.本地纳秒＝本地纳秒+ΔX-109，结束；
A 107.本地纳秒＝本地纳秒+ΔX，结束。
本发明还提供一种1PPS+TOD信息单总线传送同步系统，包括发送端和接收端，发送端和接收端通过一根背板总线相连；
所述发送端包括：
第一采样模块，用于设置对本地TOD信息的采样次数并采样；
存储模块，用于存储采样得到的TOD信息；
组帧模块，用于将存储模块中TOD信息封装成待发送的TOD帧；TOD帧包括帧头、帧序号、类型、长度、TOD数据净荷、校验字段和用于填充两个TOD帧间隙的空符号；
校验模块，用于计算待发送TOD帧的校验字段；
编码发送模块，用于对待发送TOD帧编码，编码后的TOD帧携带发送端的时钟上升沿信息，还用于将编码后的TOD帧发送至接收端；
所述接收端包括：
第二采样模块，用于在接收端提供的本地时钟域内，找到TOD编码比特流的码元的中间时刻并采样；
帧同步模块，用于寻找帧头特定码型完成帧同步，并将是否有帧丢失信息传送给TOD维护模块；
解码模块，用于对接收的TOD串行比特信息解码成TOD帧；
解帧模块，用于将解码后的TOD帧分解为各个字段，传送给校验模块；
校验模块，用于通过校验和的方式校验TOD帧，并将校验结果传送给TOD维护模块；
TOD维护模块，用于TOD帧未丢失且校验正确时，利用当前接收TOD更新接收端本地TOD，在每个时钟周期，本地TOD自加一个TOD维护时钟周期ΔX完成接收端TOD实时与发送端TOD同步； 或者用于在TOD帧丢失或TOD校验错误时，利用最近一次正确接收的TOD帧自加一个TOD维护时钟周期ΔX完成实时TOD同步。
在上述技术方案的基础上，所述第一采样模块以125M的时钟按照1秒10000次的频率采样本地TOD信息，第二采样模块与第一采样模块采样周期相同。
在上述技术方案的基础上，所述编码发送模块采用待发送TOD帧的比特信息流调制发送时钟的下降沿相位，上升沿相位保持不变，调制后的串行TOD信息是25Mbits/s的编码码片的速率，调制后承载的有效信息速率为6.25Mbits/s。
在上述技术方案的基础上，发送端本地TOD信息采样时钟为125M时钟域，包含80比特信息，48比特秒值，32比特纳秒值，TOD纳秒值为0时是PPS脉冲的位置；接收端本地提供的接收TOD采样时钟为125M时钟域，该时钟同时用作接收TOD的采样时钟和TOD维护时钟，即一个TOD维护时钟周期ΔX等于TOD采样接收时钟周期，均为8ns。
本发明还提供一种PPS+TOD信息单总线传送同步方法，包括：发送端通过第一采样模块设置每秒对本地TOD信息的采样次数，并采样存储到存储模块中，组帧模块使用校验模块计算的校验字段、对每次采集的TOD信息进行一次组帧，再由编码发送模块对待发送TOD帧进行串行编码后传送给接收端；接收端的第二采样模块在接收端提供的本地时钟域内，找到TOD编码比特流的码元的中间时刻并采样，帧同步模块通过寻找帧头信息进行帧同步，判断是否有帧丢失；然后对找到帧头信息的TOD帧进行解码和解帧，解出的各个字段，以校验和的方式对TOD帧中校验字段进行校验；当TOD帧校验正确且无丢失时，TOD维护模块利用正确的TOD更新本地TOD，在 每个时钟周期自加一个TOD维护时钟周期ΔX完成实时TOD同步；对于TOD帧丢失或校验错误时，TOD维护模块利用最近一次正确接收的TOD帧自加一个TOD维护时钟周期ΔX完成实时TOD同步。
在上述技术方案的基础上，帧同步模块以滑动移位寄存器的方式寻找帧头的特定码型完成帧同步，通过监测两个TOD帧帧头的时间间隔与发送端两个TOD帧之间的采样发送时间间隔是否相等判断是否有帧丢失。
在上述技术方案的基础上，所述编码TOD帧的编码方案为，用码元1000表示信息比特1，用码元1110表示信息比特0，用码元1100表示填充两帧间隙的空闲信息；帧头的特定码型为01110110。
在上述技术方案的基础上，发送端本地时钟域为125M，组帧后的TOD帧采用25Mbits/s编码码片速率，即实际以6.25Mbits/s的有效信息数据流传送给接收端；接收端TOD本地采样接收时钟为125M，该时钟同时用作接收TOD的采样时钟和TOD维护时钟，即一个TOD维护时钟周期ΔX等于TOD采样接收时钟周期，均为8ns。
在上述技术方案的基础上，发送端的本地125M时钟和接收端的本地125M时钟为相互独立的时钟域，这两个125M时钟域的频偏控制在100ppm之内，此时接收端恢复出的TOD实时时间和发送端TOD实时时间的精度在±10ns以内。
本发明的有益效果在于：
发送端通过编码发送模块对TOD帧进行串行编码，编码发送模块采用待发送TOD帧的比特信息流调制发送时钟的下降沿相位，上升沿相位保持不变，且编码过后的TOD帧携带发端时钟上升沿信息；因此通过一根总线即可实现1PPS+TOD信息的传送，最大化节约背板总线资源，相对于多根并行总线的方案，通信过程更加稳定可靠。
接收端采用锁相环倍频或者采用本地TOD信息的方式，对接收到的TOD帧进行解码并校验，保证TOD帧同步传输，提高同步精确度。
附图说明
图1为本发明实施例1PPS+TOD信息单总线传送同步系统的发送端示意图；
图2为本发明第一实施例1PPS+TOD信息单总线传送同步系统的接收端示意图；
图3为本发明第二实施例1PPS+TOD信息单总线传送同步系统的接收端示意图；
图4为本发明TOD维护模块进行秒部分更新流程图；
图5为本发明TOD维护模块进行纳秒部分更新流程图。
附图标记：
发送端1，第一采样模块11，存储模块12，组帧模块13，校验模块14，编码发送模块15；
接收端(2，2′)，锁相环倍频模块20，第二采样模块21，帧同步模块22，解码模块23，解帧模块24，校验模块25，TOD维护模块26。
具体实施方式
以下结合附图及实施例对本发明作进一步详细说明。
第一实施例
如图1和图2所示，本实施例1PPS+TOD信息单总线传送同步系统，包括发送端1和接收端2，发送端1和接收端2通过一根背板总线相连。
如图1所示，发送端1包括第一采样模块11、存储模块12、组帧模块13、校验模块14和编码发送模块15。第一采样模块11用于设置对本地TOD信息的采样次数(即每秒发送多少帧)并采样，第一施例中，第一采样模块11以125M的时钟按照1秒10000次的频率采样本地TOD信息，发送端1的本地TOD信息为125M时钟域，包含80比特信息，48比特秒值，32比特纳秒值，TOD纳秒值为0时是PPS脉冲的位置。存储模块12用于以寄存器形式存储采样得到的TOD信息。组帧模块13用于将存储模块12中TOD信息封装成待发送的TOD帧，TOD帧包括帧头、帧序号、类型、长度、TOD数据净荷、校验字段和用于填充两个TOD帧间隙的空符号。校验模块14用于计算待发送TOD帧的校验字段。编码发送模块15用于对待发送TOD帧编码，采用待发送TOD帧的比特信息流去调制发送时钟的下降沿相位，而上升沿相位保持不变，相当于一种脉冲宽度调制。编码TOD帧的编码方案为：用码元“1000”表示信息比特1，用码元“1110”表示信息比特0，用码元“1100”表示填充两帧间隙的空闲信息；帧头包含特定码型，本实施例中特定码型为“01110110”。编码之后，相当于发送端时钟的下降沿的位置携带了TOD数据信息，而上升沿携带的是发送端的时钟上升沿信息。本实施例中，TOD采样的本地时钟域为125M，该时钟同时用作接收TOD的采样时钟和TOD维护时钟，即一个TOD维护时钟周期ΔX等于TOD采样接收时钟周期，均为8ns。采样组帧后得到的TOD帧的发送速率采用25Mbits/s(由本地125M分频得到)编码码片的速率，即实际以6.25Mbits/s的有效信息数据流传送给接收端，该6.25Mbits/s比特流的上升沿相位是固定的。这里25Mbits/s、6.25Mbits/s与发端本地125M时钟同源，所以6.25Mbits/s的上升沿也反映了125M时钟的上升沿。
如图2所示，接收端2包括锁相环倍频模块20、第二采样模块21、帧同步模块22、解码模块23、解帧模块24、校验模块25和TOD维护模块26。锁相环倍频模块20用于从接收到的TOD帧数据流中恢复出125M的时钟信息。第二采样模块21用于在恢复出的时钟域内，找到25M串行TOD编码比特流的码元的中间时刻并采样。帧同步模块22用于寻找帧头特定码型完成帧同步，并通过监测两个TOD帧帧头的时间间隔与发送端两个TOD帧之间的采样发送时间间隔是否相等判断是否有帧丢失，将是否有帧丢失信息发送至TOD维护模块26。解码模块23用于将接收的TOD串行比特信息按照发送端编码描述的编码规则解码成TOD帧。解帧模块24用于将解码后的TOD帧分解为各个字段，并传送给校验模块25。校验模块25以校验和的方式校验TOD帧，如果校验错误，丢弃该帧；校验模块25还需要将校验结果发送至TOD维护模块26。TOD维护模块26用于在TOD帧未丢失且校验正确时，利用当前接收TOD更新本地TOD，并利用校验正确的TOD信息，在每个125M时钟周期自加一个TOD维护时钟周期ΔX，(ΔX＝1s/125MHz＝8ns)完成接收端TOD实时与发送端TOD维护，实现接收端TOD与发送端TOD的实时同步；TOD维护模块26还用于在TOD帧丢失或TOD校验错误时，利用最近一次正确接收的TOD帧自加间隔时间一个TOD维护时钟周期ΔX进行维护，完成接收端TOD与发送端TOD的实时同步。当本地维护的TOD纳秒部分为0时，从TOD中恢复出PPS脉冲，并且PPS的脉冲宽度可以动态配置。
第一实施例1PPS+TOD信息单总线传送同步方法，包括如下步骤：
发送端1通过第一采样模块11设置每秒对本地TOD信息的采样 次数，并采样存储到存储模块12中，校验模块14计算的校验字段，组帧模块13使用校验字段对每次采集的TOD信息进行一次组帧，TOD帧包括帧头、帧序号、类型、长度、TOD数据净荷、校验字段和用于填充两个TOD帧间隙的空符号。最后由编码发送模块15对待发送TOD帧进行串行编码后，传送给接收端2。
接收端2锁相环倍频模块20从来自发送端1的TOD帧数据流中恢复出时钟信息，具体的，利用接收锁相环(FPGA有自带锁相环)，将携带发送端时钟上升沿信息的25M串行TOD帧编码码流倍频到125M，倍频得到的125M时钟与发端125M时钟的相位关系是锁定的。然后通过第二采样模块21在计数器的控制下，找到25M串行TOD编码比特流的最佳采样点(即码元的中间时刻)并采样。再由帧同步模块22以滑动移位寄存器的方式寻找帧头信息(含有帧头特定码型)进行帧同步，并通过监测两帧帧头的时间间隔与发送端两个TOD帧之间的采样发送时间间隔是否相等判断是否有帧丢失，并将该结果通知给TOD维护模块26。然后通过解码模块23对找到帧头信息的TOD帧进行解码，解码规则与发送端1的编码规则相同。再通过解帧模块24将解码后的TOD数据帧分解为各个字段，并传送给校验模块25。再由校验模块25以校验和的方式对TOD帧中校验字段进行校验，并将校验结果发送给TOD维护模块26；校验模块25如果校验错误时，丢弃该TOD帧。当TOD帧校验正确且无丢失时，TOD维护模块26利用正确的TOD更新本地TOD，在每个时钟周期自加一个TOD维护时钟周期ΔX(等于TOD采样接收时钟周期，本实施例ΔX＝8ns)完成实时TOD与发送端TOD同步同步；对于TOD帧丢失或校验错误时，TOD维护模块26利用最近一次正确接收的TOD帧自加一个TOD维护时钟周期ΔX完成TOD实时与发送端TOD 同步。
图4为本发明TOD维护模块进行秒部分更新流程，具体包括如下步骤：
B101.判断是否TOD帧头到达、TOD帧无丢失且校验正确，若是，进入B102；若否，进入B 105；
B102.判断接收纳秒是否大于等于109-ΔT，其中ΔT为两个TOD发送帧之间的时间间隔，若是，进入B103；若否，进入B 104；
B103.本地秒＝接收秒+1，即使用接收秒部分+1的结果取代本地秒部分，完成维护秒部分的进位，其中ΔT为两个TOD发送帧之间的时间间隔，本设计由于发送端每1秒完成10000次实时TOD采样及组帧发送，所以△T＝0.1ms，结束；
B104.本地秒＝接收秒，即接收秒部分直接取代本地秒部分实现秒部分维护，结束；
B105.判断本地纳秒部分是否大于等于109-ΔX；若是，进入B106；若否，进入B107；
B106.本地秒＝本地秒+1，实现本地秒部分自维护进位，结束；
B107.本地秒＝本地秒，保持本地秒部分维持不变，结束。
图5为本发明TOD维护模块进行纳秒部分更新流程，具体包括步骤：
A101.判断是否TOD帧头到达、TOD帧无丢失且校验正确，若是，进入A 102；若否，进入A 105；
A 102.判断接收纳秒是否大于等于109-ΔT，其中ΔT为两个TOD发送帧之间的时间间隔，若是，进入A 103；若否，进入A 104；
A 103.本地纳秒＝接收纳秒+ΔT-109，接收纳秒部分+ΔT-109的结果取代本地纳秒部分完成维护，其中ΔT为两个TOD发送帧之间 的时间间隔，结束；
A 104.本地纳秒＝接收纳秒+ΔT，接收纳秒部+ΔT取代本地纳秒部分完成维护，结束；
A 105.判断本地纳秒部分是否大于等于109-ΔX，其中ΔX为一个TOD维护时钟周期(等于TOD采样接收时钟周期，本实施例中为8ns)，若是，进入A 106；若否，进入A 107；
A 106.本地纳秒＝本地纳秒+ΔX-109，实现本地纳秒部分自维护进位和清零，结束；
A 107.本地纳秒＝本地纳秒+ΔX，本地纳秒部分实现自加ΔX的维护，结束。
第二实施例
如图1和图3所示，本实施例1PPS+TOD信息单总线传送同步系统，包括发送端1和接收端2，发送端1和接收端2通过一根背板总线相连。本实施例的系统中，发送端与第一实施例发送端1结构和作用相同。如图2所示，接收端2′与第一实施例接收端2类似，区别在于，本实施例的接收端2′不包括锁相环倍频模块20，包括第二采样模块21，帧同步模块22，解码模块23，解帧模块24，校验模块25，TOD维护模块26。本实施例中，第二采样模块用于在接收端2′提供的本地时钟域内，找到TOD编码比特流的码元的中间时刻并采样；接收端2′的其余模块的结构和用途与第一实施例相同，出于设计的简易性考虑，第二实施例可直接采用本地的125M时钟完成TOD采样接收；但是对于时间同步要求更精确的系统，接收端宜采用第一实施例，也就是说，第一实施例比第二实施例的精确度更高。
本实施例1PPS+TOD信息单总线传送同步方法，包括步骤：
发送端1通过第一采样模块11设置每秒对本地TOD信息的采样 次数，并采样存储到存储模块12中，校验模块14计算的校验字段，组帧模块13使用校验字段对每次采集的TOD信息进行一次组帧，TOD帧包括帧头、帧序号、类型、长度、TOD数据净荷、校验字段和用于填充两个TOD帧间隙的空符号。最后由编码发送模块15对待发送TOD帧进行串行编码后，传送给接收端22′。
接收端2′的第二采样模块21在接收端提供的本地时钟域内，找到TOD编码比特流的码元的中间时刻并采样，再由帧同步模块22以滑动移位寄存器的方式寻找帧头信息(含有帧头特定码型)进行帧同步，并通过监测两帧帧头的时间间隔与发送端两个TOD帧之间的采样发送时间间隔是否相等判断是否有帧丢失，并将该结果通知给TOD维护模块26。然后通过解码模块23对找到帧头信息的TOD帧进行解码，解码规则与发送端1的编码规则相同。再通过解帧模块24将解码后TOD数据帧分解为各个字段后发送给校验模块25。再由校验模块25以校验和的方式对TOD帧中校验字段进行校验，并将校验结果发送给TOD维护模块26；校验模块25如果校验错误，丢弃该TOD帧。当TOD帧校验正确且无丢失时，TOD维护模块26利用正确的TOD更新本地TOD，在每个时钟周期自加一个TOD维护时钟周期ΔX(等于TOD采样接收时钟周期，本实施例中为8ns)完成实时TOD同步；对于TOD帧丢失或校验错误时，TOD维护模块26利用最近一次正确接收的TOD帧自加一个TOD维护时钟周期ΔX完成实时TOD同步。
本实施例方法中，发送端本地时钟域为125M，组帧后的TOD帧采用25Mbits/s编码码片速率，即实际以6.25Mbits/s的有效信息数据流传送给接收端。本实施例与第一实施例的不同之处在于，接收端2′直接使用第二采样模块21对本地的125M时钟完成TOD采样接收； 该时钟同时用作接收TOD的采样时钟和TOD维护时钟，即一个TOD维护时钟周期ΔX等于TOD采样接收时钟周期，均为8ns。发送端的本地125M时钟和接收端的本地125M时钟为相互独立的时钟域，这两个125M时钟域的频偏需要控制在100ppm之内，此时接收端恢复出的TOD实时时间和发送端TOD实时时间的精度可以控制在±10ns以内。本实施例在TOD维护模块26中，进行秒部分更新和纳秒部分更新与第一实施例相同，此处不再赘述。
本发明不局限于上述实施方式，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围之内。本说明书中未作详细描述的内容属于本领域专业技术人员公知的现有技术。

Claims (19)

  1. 一种1PPS+TOD信息单总线传送同步系统，包括发送端和接收端，其特征在于，发送端和接收端通过一根背板总线相连；
    所述发送端包括：
    第一采样模块，用于设置对本地TOD信息的采样次数并采样；
    存储模块，用于存储采样得到的TOD信息；
    组帧模块，用于将存储模块中TOD信息封装成待发送的TOD帧；TOD帧包括帧头、帧序号、类型、长度、TOD数据净荷、校验字段和用于填充两个TOD帧间隙的空符号；
    校验模块，用于计算待发送TOD帧的校验字段；
    编码发送模块，用于对待发送TOD帧编码，编码后的TOD帧携带发送端的时钟上升沿信息，还用于将编码后的TOD帧发送至接收端；
    所述接收端包括：
    锁相环倍频模块，用于从接收到的TOD帧编码数据流中恢复出时钟信息；
    第二采样模块，用于在恢复出的时钟域内，找到TOD编码比特流的码元的中间时刻并采样；
    帧同步模块，用于寻找帧头特定码型完成帧同步，并将是否有帧丢失信息传送给TOD维护模块；
    解码模块，用于对接收的TOD串行比特信息解码成TOD帧；
    解帧模块，用于将解码后的TOD帧分解为各个字段，传送给校验模块；
    校验模块，用于通过校验和的方式校验TOD帧，并将校验结果传送给TOD维护模块；
    TOD维护模块，用于TOD帧未丢失且校验正确时，利用当前接收TOD更新接收端本地TOD，在每个时钟周期，本地TOD自加一个TOD维护时钟周期ΔX完成接收端TOD实时与发送端TOD同步；或者用于在TOD帧丢失或TOD校验错误时，利用最近一次正确接收的TOD帧自加一个TOD维护时钟周期ΔX完成实时TOD同步。
  2. 如权利要求1所述的1PPS+TOD信息单总线传送同步系统，其特征在于：所述第一采样模块以125M的时钟按照1秒10000次的频率采样本地TOD信息，第二采样模块与第一采样模块采样周期相同。
  3. 如权利要求2所述的1PPS+TOD信息单总线传送同步系统，其特征在于：所述编码发送模块采用待发送TOD帧的比特信息流调制发送时钟的下降沿相位，上升沿相位保持不变，调制后的串行TOD信息是25Mbits/s的编码码片的速率，调制后承载的有效信息速率为6.25Mbits/s。
  4. 如权利要求1所述的1PPS+TOD信息单总线传送同步系统，其特征在于：所述发送端本地TOD信息为125M时钟域，包含80比特信息，48比特秒值，32比特纳秒值，TOD纳秒值为0时是PPS脉冲的位置；所述接收端从锁相环倍频恢复出的时钟为125M，该时钟同时用作接收TOD的采样时钟和TOD维护时钟，即一个TOD维护时钟周期ΔX等于TOD采样接收时钟周期，均为8ns。
  5. 一种基于权利要求1系统的1PPS+TOD信息单总线传送同步方法，其特征在于，包括：
    发送端通过第一采样模块设置每秒对本地TOD信息的采样次数，并采样存储到存储模块中，组帧模块使用校验模块计算的校验字段、对每次采集的TOD信息进行一次组帧，再由编码发送模块对待发送 TOD帧进行串行编码后传送给接收端；
    接收端的锁相环倍频模块从收到的TOD编码数据流中恢复出时钟信息，通过第二采样模块找到码元的中间时刻并采样，帧同步模块通过寻找帧头信息进行帧同步，判断是否有帧丢失；然后将找到帧头信息的TOD帧通过解码和解帧得到各个字段，以校验和的方式对TOD帧中校验字段进行校验；当TOD帧校验正确且无丢失时，TOD维护模块利用正确的TOD更新本地TOD，在每个时钟周期自加一个TOD维护时钟周期ΔX完成TOD实时与发送端TOD同步；对于TOD帧丢失或校验错误时，TOD维护模块利用最近一次正确接收的TOD帧自加一个TOD维护时钟周期ΔX完成实时TOD同步。
  6. 如权利要求5所述的1PPS+TOD信息单总线传送同步方法，其特征在于：帧同步模块以滑动移位寄存器的方式寻找帧头的特定码型完成帧同步，通过监测两个TOD帧帧头的时间间隔与发送端两个TOD帧之间的采样发送时间间隔是否相等判断是否有帧丢失。
  7. 如权利要求5所述基于相位调制的1PPS+TOD信息单总线传送方法，其特征在于：所述编码TOD帧的编码方案为，用码元1000表示信息比特1，用码元1110表示信息比特0，用码元1100表示填充两帧间隙的空闲信息；帧头的特定码型为01110110。
  8. 如权利要求5所述的1PPS+TOD信息单总线传送同步方法，其特征在于：发送端TOD采样的本地时钟域为125M，组帧后的TOD帧采用25Mbits/s编码码片的速率，即实际以6.25Mbits/s的有效信息数据流传送给接收端；接收端锁相环倍频恢复的时钟域为125M，该时钟同时用作接收TOD的采样时钟和TOD维护时钟，即一个TOD维护时钟周期ΔX等于TOD采样接收时钟周期，均为8ns。
  9. 如权利要求5所述基于相位调制的1PPS+TOD信息单总线传 送方法，其特征在于，所述TOD维护模块进行秒部分更新包括步骤：
    B101.判断是否TOD帧头到达、TOD帧无丢失且校验正确，若是，进入B102；若否，进入B105；
    B102.判断接收纳秒是否大于等于109-ΔT，其中ΔT为两个TOD发送帧之间的时间间隔，若是，进入B103；若否，进入B104；
    B103.本地秒＝接收秒+1，结束；
    B104.本地秒＝接收秒，结束；
    B105.判断本地纳秒部分是否大于等于109-ΔX，若是，进入B106；若否，进入B107；
    B106.本地秒＝本地秒+1，结束；
    B107.本地秒＝本地秒，结束。
  10. 如权利要求5所述基于相位调制的1PPS+TOD信息单总线传送方法，其特征在于，所述TOD维护模块进行纳秒部分更新包括步骤：
    A101.判断是否TOD帧头到达、TOD帧无丢失且校验正确，若是，进入A102；若否，进入A105；
    A102.判断接收纳秒是否大于等于109-ΔT，其中ΔT为两个TOD发送帧之间的时间间隔，若是，进入A103；若否，进入A104；
    A103.本地纳秒＝接收纳秒+ΔT-109，结束；
    A104.本地纳秒＝接收纳秒+ΔT，结束；
    A105.判断本地纳秒部分是否大于等于109-ΔX，其中ΔX为TOD维护时钟的周期，若是，进入A106；若否，进入A107；
    A106.本地纳秒＝本地纳秒+ΔX-109，结束；
    A107.本地纳秒＝本地纳秒+ΔX，结束。
  11. 一种1PPS+TOD信息单总线传送同步系统，包括发送端和 接收端，其特征在于，发送端和接收端通过一根背板总线相连；
    所述发送端包括：
    第一采样模块，用于设置对本地TOD信息的采样次数并采样；
    存储模块，用于存储采样得到的TOD信息；
    组帧模块，用于将存储模块中TOD信息封装成待发送的TOD帧；TOD帧包括帧头、帧序号、类型、长度、TOD数据净荷、校验字段和用于填充两个TOD帧间隙的空符号；
    校验模块，用于计算待发送TOD帧的校验字段；
    编码发送模块，用于对待发送TOD帧编码，编码后的TOD帧携带发送端的时钟上升沿信息，还用于将编码后的TOD帧发送至接收端；
    所述接收端包括：
    第二采样模块，用于在接收端提供的本地时钟域内，找到TOD编码比特流的码元的中间时刻并采样；
    帧同步模块，用于寻找帧头特定码型完成帧同步，并将是否有帧丢失信息传送给TOD维护模块；
    解码模块，用于对接收的TOD串行比特信息解码成TOD帧；
    解帧模块，用于将解码后的TOD帧分解为各个字段，传送给校验模块；
    校验模块，用于通过校验和的方式校验TOD帧，并将校验结果传送给TOD维护模块；
    TOD维护模块，用于TOD帧未丢失且校验正确时，利用当前接收TOD更新接收端本地TOD，在每个时钟周期，本地TOD自加一个TOD维护时钟周期ΔX完成接收端TOD实时与发送端TOD同步；或者用于在TOD帧丢失或TOD校验错误时，利用最近一次正确接收 的TOD帧自加一个TOD维护时钟周期ΔX完成实时TOD同步。
  12. 如权利要求11所述的1PPS+TOD信息单总线传送同步系统，其特征在于：所述第一采样模块以125M的时钟按照1秒10000次的频率采样本地TOD信息，第二采样模块与第一采样模块采样周期相同。
  13. 如权利要求12所述的1PPS+TOD信息单总线传送同步系统，其特征在于：所述编码发送模块采用待发送TOD帧的比特信息流调制发送时钟的下降沿相位，上升沿相位保持不变，调制后的串行TOD信息是25Mbits/s的编码码片的速率，调制后承载的有效信息速率为6.25Mbits/s。
  14. 如权利要求11所述的1PPS+TOD信息单总线传送同步系统，其特征在于：发送端本地TOD信息采样时钟为125M时钟域，包含80比特信息，48比特秒值，32比特纳秒值，TOD纳秒值为0时是PPS脉冲的位置；接收端本地提供的接收TOD采样时钟为125M时钟域，该时钟同时用作接收TOD的采样时钟和TOD维护时钟，即一个TOD维护时钟周期ΔX等于TOD采样接收时钟周期，均为8ns。
  15. 一种基于权利要求11系统的1PPS+TOD信息单总线传送同步方法，其特征在于，包括：
    发送端通过第一采样模块设置每秒对本地TOD信息的采样次数，并采样存储到存储模块中，组帧模块使用校验模块计算的校验字段、对每次采集的TOD信息进行一次组帧，再由编码发送模块对待发送TOD帧进行串行编码后传送给接收端；
    接收端的第二采样模块在接收端提供的本地时钟域内，找到TOD编码比特流的码元的中间时刻并采样，帧同步模块通过寻找帧头信息进行帧同步，判断是否有帧丢失；然后对找到帧头信息的TOD帧进 行解码和解帧，解出的各个字段，以校验和的方式对TOD帧中校验字段进行校验；当TOD帧校验正确且无丢失时，TOD维护模块利用正确的TOD更新本地TOD，在每个时钟周期自加一个TOD维护时钟周期ΔX完成实时TOD同步；对于TOD帧丢失或校验错误时，TOD维护模块利用最近一次正确接收的TOD帧自加一个TOD维护时钟周期ΔX完成实时TOD同步。
  16. 如权利要求15所述的1PPS+TOD信息单总线传送同步方法，其特征在于：帧同步模块以滑动移位寄存器的方式寻找帧头的特定码型完成帧同步，通过监测两个TOD帧帧头的时间间隔与发送端两个TOD帧之间的采样发送时间间隔是否相等判断是否有帧丢失。
  17. 如权利要求15所述基于相位调制的1PPS+TOD信息单总线传送方法，其特征在于：所述编码TOD帧的编码方案为，用码元1000表示信息比特1，用码元1110表示信息比特0，用码元1100表示填充两帧间隙的空闲信息；帧头的特定码型为01110110。
  18. 如权利要求15所述的1PPS+TOD信息单总线传送同步方法，其特征在于：发送端本地时钟域为125M，组帧后的TOD帧采用25Mbits/s编码码片速率，即实际以6.25Mbits/s的有效信息数据流传送给接收端；接收端TOD本地采样接收时钟为125M，该时钟同时用作接收TOD的采样时钟和TOD维护时钟，即一个TOD维护时钟周期ΔX等于TOD采样接收时钟周期，均为8ns。
  19. 如权利要求15所述的1PPS+TOD信息单总线传送同步方法，其特征在于：发送端的本地125M时钟和接收端的本地125M时钟为相互独立的时钟域，这两个125M时钟域的频偏控制在100ppm之内，此时接收端恢复出的TOD实时时间和发送端TOD实时时间的精度在±10ns以内。
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