WO2018205173A1 - 射频电路开关芯片、射频电路、天线装置及电子设备 - Google Patents

射频电路开关芯片、射频电路、天线装置及电子设备 Download PDF

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Publication number
WO2018205173A1
WO2018205173A1 PCT/CN2017/083840 CN2017083840W WO2018205173A1 WO 2018205173 A1 WO2018205173 A1 WO 2018205173A1 CN 2017083840 W CN2017083840 W CN 2017083840W WO 2018205173 A1 WO2018205173 A1 WO 2018205173A1
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WIPO (PCT)
Prior art keywords
switch
frequency
port
radio frequency
signal
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Application number
PCT/CN2017/083840
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English (en)
French (fr)
Inventor
丛明
冯斌
Original Assignee
广东欧珀移动通信有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 广东欧珀移动通信有限公司 filed Critical 广东欧珀移动通信有限公司
Priority to CN201780089455.7A priority Critical patent/CN110546891B/zh
Priority to PCT/CN2017/083840 priority patent/WO2018205173A1/zh
Publication of WO2018205173A1 publication Critical patent/WO2018205173A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a radio frequency circuit switch chip, a radio frequency circuit, an antenna device, and an electronic device.
  • LTE Long Term The Evolution, Long Term Evolution communication signal may include signals having a frequency between 700 MHz and 2700 MHz.
  • the radio frequency signals that the mobile terminal can support can be divided into a low frequency signal, an intermediate frequency signal, and a high frequency signal.
  • the low frequency signal, the intermediate frequency signal, and the high frequency signal each include a plurality of sub-band signals. Each sub-band signal needs to be transmitted to the outside through the antenna.
  • carrier aggregation carrier Aggregation
  • CA carrier aggregation
  • multiple sub-band signals can be aggregated together to improve the uplink and downlink transmission rates of the network.
  • the frequency resources of various communication markets around the world are different. Communication operators in different areas have different communication spectrum allocations, and there are different combinations of carrier aggregation frequency bands.
  • the terminal when the terminal is in a carrier aggregation state, that is, receiving a radio frequency signal combined with different frequency bands, the radio frequency signal needs to be frequency-divided to obtain a radio frequency signal of a specific frequency band.
  • the current frequency division method is single and lacks diversity, which cannot meet the above requirements.
  • the embodiment of the invention provides a radio frequency circuit switch chip, a radio frequency circuit, an antenna device and an electronic device, which can improve the diversity of the frequency division of the radio frequency signal by the electronic device.
  • an embodiment of the present invention provides a radio frequency circuit switch chip, including a first switch, a second switch, a first frequency divider, and a second frequency divider, where the first switch is configured to receive a high frequency signal or an intermediate frequency a signal, the second switch is for receiving a low frequency signal;
  • the first input port and the second input port of the first switch When the first input port and the second input port of the first switch are respectively used to receive different signals, the first input port and the second input port of the first switch selectively connect the first frequency divider, the first The frequency divider divides the received signal into a high frequency signal and an intermediate frequency signal; and when the first frequency divider and the second switch selectively turn on the second frequency divider, the first frequency divider and the second frequency The frequency divider divides the received signal into a high frequency signal, an intermediate frequency signal, and a low frequency signal;
  • the second frequency divider divides the received signal into an intermediate frequency signal and a low frequency signal, or a high frequency signal and a low frequency signal.
  • an embodiment of the present invention provides a radio frequency circuit, including a radio frequency transceiver, a radio frequency circuit switch chip, and an antenna, where the radio frequency transceiver, the radio frequency circuit switch chip, and the antenna are sequentially connected;
  • the radio frequency circuit switch chip includes a first switch, a second switch, a first frequency divider and a second frequency divider, and the first input port and the second input port of the first switch are used for receiving a high frequency signal or an intermediate frequency signal
  • the second switch is configured to receive a low frequency signal
  • the first input port and the second input port of the first switch When the first input port and the second input port of the first switch are respectively used to receive different signals, the first input port and the second input port of the first switch selectively turn on the first frequency divider, The first frequency divider divides the received signal into a high frequency signal and an intermediate frequency signal; and when the first frequency divider and the second switch selectively turn on the second frequency divider, the a frequency divider and the second frequency divider divide the received signal into a high frequency signal, an intermediate frequency signal, and a low frequency signal;
  • the second frequency divider divides the received signal into an intermediate frequency signal and a low frequency signal, or is high. Frequency signal and low frequency signal.
  • an embodiment of the present invention provides an antenna apparatus, including the foregoing radio frequency circuit.
  • an embodiment of the present invention provides an electronic device including a housing and a circuit board.
  • the circuit board is mounted inside the housing.
  • the circuit board is provided with a radio frequency circuit, and the radio frequency circuit is the radio frequency circuit.
  • the embodiment of the invention provides a radio frequency circuit switch chip, a radio frequency circuit, an antenna device and an electronic device, which can improve the diversity of the frequency division of the radio frequency signal by the electronic device.
  • FIG. 1 is an exploded perspective view of an electronic device according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a first structure of a radio frequency circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a second structure of a radio frequency circuit according to an embodiment of the present invention.
  • FIG. 5 is a third schematic structural diagram of a radio frequency circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a fourth structure of a radio frequency circuit according to an embodiment of the present invention.
  • FIG. 7 is a fifth structural diagram of a radio frequency circuit according to an embodiment of the present invention.
  • FIG. 8 is a sixth structural diagram of a radio frequency circuit according to an embodiment of the present invention.
  • FIG. 9 is a seventh structural diagram of a radio frequency circuit according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram showing an eighth structure of a radio frequency circuit according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram showing a ninth structure of a radio frequency circuit according to an embodiment of the present invention.
  • FIG. 12 is a schematic diagram of a tenth structure of a radio frequency circuit according to an embodiment of the present invention.
  • FIG. 13 is a schematic structural diagram of an eleventh embodiment of a radio frequency circuit according to an embodiment of the present invention.
  • FIG. 14 is a twelfth structural diagram of a radio frequency circuit according to an embodiment of the present invention.
  • FIG. 15 is a first schematic structural diagram of a radio frequency circuit switch chip according to an embodiment of the present invention.
  • FIG. 16 is a second schematic structural diagram of a radio frequency circuit switch chip according to an embodiment of the present invention.
  • FIG. 17 is a third schematic structural diagram of a radio frequency circuit switch chip according to an embodiment of the present invention.
  • FIG. 18 is a fourth structural diagram of a radio frequency circuit switch chip according to an embodiment of the present invention.
  • FIG. 19 is a third structural schematic diagram of a radio frequency circuit according to an embodiment of the present invention.
  • FIG. 20 is another schematic structural diagram of an electronic device according to an embodiment of the present invention.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include one or more of the described features either explicitly or implicitly.
  • the meaning of "a plurality” is two or more unless specifically and specifically defined otherwise.
  • connection In the description of the present invention, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise explicitly defined and defined. Connected, or integrally connected; may be mechanically connected, may be electrically connected or may communicate with each other; may be directly connected, or may be indirectly connected through an intermediate medium, may be internal communication of two elements or interaction of two elements relationship.
  • Connected, or integrally connected may be mechanically connected, may be electrically connected or may communicate with each other; may be directly connected, or may be indirectly connected through an intermediate medium, may be internal communication of two elements or interaction of two elements relationship.
  • the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.
  • the first feature "on” or “under” the second feature may include direct contact of the first and second features, and may also include first and second features, unless otherwise specifically defined and defined. It is not in direct contact but through additional features between them.
  • the first feature "above”, “above” and “above” the second feature includes the first feature directly above and above the second feature, or merely indicating that the first feature level is higher than the second feature.
  • the first feature “below”, “below” and “below” the second feature includes the first feature directly below and below the second feature, or merely the first feature level being less than the second feature.
  • Embodiments of the present invention provide an electronic device.
  • the electronic device can be a device such as a smartphone or a tablet.
  • the electronic device 100 includes a cover 101, a display screen 102, a circuit board 103, a battery 104, and a housing 105.
  • the cover plate 101 is mounted to the display screen 102 to cover the display screen 102.
  • the cover plate 101 may be a transparent glass cover.
  • the cover plate 101 can be a glass cover plate made of a material such as sapphire.
  • the display screen 102 is mounted on the housing 105 to form a display surface of the electronic device 100.
  • the display screen 102 can include a display area 102A and a non-display area 102B.
  • the display area 102A is for displaying information such as images, texts, and the like.
  • the non-display area 102B does not display information.
  • the bottom of the non-display area 102B may be provided with functional components such as a fingerprint module and a touch circuit.
  • the circuit board 103 is mounted inside the housing 105.
  • the circuit board 103 can be a motherboard of the electronic device 100.
  • Functional components such as a camera, a proximity sensor, and a processor can be integrated on the circuit board 103.
  • the display screen 102 can be electrically connected to the circuit board 103.
  • the radio frequency (RF, Radio) is provided on the circuit board 103.
  • Frequency Frequency
  • the radio frequency circuit can communicate with a network device (eg, a server, a base station, etc.) or other electronic device (eg, a smart phone, etc.) through a wireless network to complete transceiving information with the network device or other electronic device.
  • a network device eg, a server, a base station, etc.
  • other electronic device eg, a smart phone, etc.
  • the radio frequency circuit 200 includes a radio frequency transceiver 21, a power amplifying unit 22, a filtering unit 23, a radio frequency circuit switching chip 24, and an antenna 25.
  • the power amplifying unit 22, the filtering unit 23, the radio frequency circuit switching chip 24, and the antenna 25 are sequentially connected.
  • the radio frequency transceiver 21 has a transmit port TX and a receive port RX.
  • the transmitting port TX is used to transmit a radio frequency signal (uplink signal), and the receiving port RX is used to receive a radio frequency signal (downlink signal).
  • the transmitting port TX of the radio frequency transceiver 21 is connected to the power amplifying unit 22, and the receiving port RX is connected to the filtering unit 23.
  • the power amplifying unit 22 is configured to amplify the uplink signal transmitted by the radio frequency transceiver 21 and send the amplified uplink signal to the filtering unit 23.
  • the filtering unit 23 is configured to filter the uplink signal transmitted by the radio frequency transceiver 21 and send the filtered uplink signal to the antenna 25.
  • the filtering unit 23 is further configured to filter the downlink signal received by the antenna 25, and send the filtered downlink signal to the radio frequency transceiver 21.
  • the RF circuit switch chip 24 is used to selectively turn on the communication band between the RF transceiver 21 and the antenna 25.
  • the detailed structure and function of the RF circuit switch chip 24 will be described below.
  • the antenna 25 is configured to transmit an uplink signal sent by the radio frequency transceiver 21 to the outside, or receive a radio frequency signal from the outside, and send the received downlink signal to the radio frequency transceiver 21.
  • the radio frequency circuit 200 also includes a control circuit 26.
  • the control circuit 26 is connected to the RF circuit switch chip 24.
  • Control circuitry 26 may also be coupled to a processor in electronic device 100 to control the state of radio frequency circuit switch chip 24 in accordance with instructions from the processor.
  • the radio frequency circuit 200 further includes a low noise amplifying unit 27.
  • a low noise amplifying unit 27 is connected between the receiving port RX of the radio frequency transceiver 21 and the filtering unit 23, and the low noise amplifying unit 27 is used for amplifying the weak signal to reduce noise in the downlink signal.
  • the radio frequency circuit 200 further includes phase shifting (Phase). Shift) unit 28.
  • a phase shifting unit 28 is further connected between the filtering unit 23 and the radio frequency circuit switching chip 24 .
  • the phase shifting unit 28 is for adjusting the phase of the signal amplitude of the uplink signal or the downlink signal.
  • the radio frequency circuit 200 further includes a low noise amplifying unit 27 and a phase shifting unit 28.
  • the low noise amplifying unit 27 is connected between the receiving port RX of the radio frequency transceiver 21 and the filtering unit 23; the low noise amplifying unit 27 is used for amplifying the weak signal and reducing noise in the downlink signal.
  • a phase shifting unit 28 is further connected between the filtering unit 23 and the radio frequency circuit switching chip 24; the phase shifting unit 28 is for adjusting the phase of the signal amplitude of the uplink signal or the downlink signal.
  • the radio frequency transceiver 21 includes a high frequency port 21H, an intermediate frequency port 21M, and a low frequency port 21L.
  • the high frequency port 21H, the intermediate frequency port 21M, and the low frequency port 21L may respectively include a plurality of radio frequency transmitting ports and a plurality of radio frequency receiving ports.
  • the high frequency port 21H is used for transmitting and receiving high frequency radio frequency signals
  • the intermediate frequency port 21M is used for transmitting and receiving intermediate frequency radio frequency signals
  • the low frequency port 21L is used for transmitting and receiving low frequency radio frequency signals.
  • the above-mentioned high frequency radio frequency signal, intermediate frequency radio frequency signal, and low frequency radio frequency signal are only relative concepts, and there is no absolute frequency range distinction.
  • the low frequency signal is 700-960MHz (megahertz) and the intermediate frequency signal is 1710-2170.
  • MHz high frequency signal is 2300-2690MHz.
  • the radio frequency transceiver 21 includes nine radio frequency transmitting ports a1, a2, a3, a4, a5, a6, a7, a8, a9, and nine radio frequency receiving ports b1, b2, b3, b4, b5, b6, b7, B8, b9.
  • a1, a2, and a3 are intermediate frequency transmission ports for transmitting intermediate frequency radio frequency signals (for example, radio frequency signals in bands such as Band1, Band3, Band34 or Band39).
  • B1, b2, and b3 are intermediate frequency receiving ports for receiving intermediate frequency radio frequency signals.
  • A4, a5, and a6 are high-frequency transmitting ports for transmitting high-frequency RF signals (for example, RF signals in Band7, Band40, Band41, etc.).
  • B4, b5, and b6 are high frequency receiving ports for receiving high frequency RF signals.
  • A7, a8, and a9 are low-frequency transmit ports for transmitting low-frequency RF signals (for example, RF signals in Band8, Band12, Band20, or Band26).
  • B7, b8, and b9 are low frequency receiving ports for receiving low frequency RF signals.
  • the above embodiment only takes the high frequency port 21H, the intermediate frequency port 21M, and the low frequency port 21L of the radio frequency transceiver 21 as three radio frequency transmitting ports and three radio frequency receiving ports as an example for description.
  • the high frequency port 21H, the intermediate frequency port 21M, and the low frequency port 21L may also include other numbers of radio frequency transmitting ports and radio frequency receiving ports, respectively. It suffices that the number of the radio frequency transmitting port and the radio frequency receiving port included in each of the high frequency port 21H, the intermediate frequency port 21M, and the low frequency port 21L is the same and greater than one.
  • the power amplifying unit 22 includes nine amplifiers 221, 222, 223, 224, 225, 226, 227, 228, 229.
  • the amplifiers 221, 222, 223, 224, 225, 226, 227, 228, 229 are respectively connected to the radio frequency transmitting ports a1, a2, a3, a4, a5, a6, a7, a8, a9 of the radio frequency transceiver 21.
  • the filtering unit 23 includes nine duplexers 231, 232, 233, 234, 235, 236, 237, 238, 239. Among them, the duplexers 231, 232, 233, 234, 235, 236, 237, 238, 239 are connected to the amplifiers 221, 222, 223, 224, 225, 226, 227, 228, 229, respectively. And, the duplexers 231, 232, 233, 234, 235, 236, 237, 238, 239 are respectively connected to the radio frequency receiving ports b1, b2, b3, b4, b5, b6, b7, b8, b9 of the radio frequency transceiver 21. .
  • the side of the connected antenna is defined as an output
  • the side of the connected filter is defined as an input.
  • the input of the RF circuit switch chip 24 includes nine sub-input ports c1, c2, c3, c4, c5, c6, c7, c8, c9.
  • the sub-input ports c1, c2, c3, c4, c5, c6, c7, c8, and c9 are connected to the duplexers 231, 232, 233, 234, 235, 236, 237, 238, and 239, respectively.
  • the filtering unit 23 includes a filter 235, a filter 236, and seven duplexers 231, 232, 233, 234, 237, 238, 239.
  • the filter 235 and the filter 236 are respectively connected to the amplifiers 225 and 226, and the seven duplexers 231, 232, 233, 234, 237, 238, and 239 are respectively coupled to the amplifiers 221, 222, 223, 224, 227, and 228. 229 connections.
  • the filter 235 and the filter 236 are respectively connected to the radio frequency receiving ports b5 and b6 of the radio frequency transceiver 21, and the radio frequency of the seven duplexers 231, 232, 233, 234, 237, 238, and 239 and the radio frequency transceiver 21, respectively.
  • the receiving ports b1, b2, b3, b4, b7, b8, and b9 are connected.
  • the side of the connected antenna is defined as an output
  • the side of the connected filter is defined as an input.
  • the input of the RF circuit switch chip 24 includes nine sub-input ports c1, c2, c3, c4, c5, c6, c7, c8, c9.
  • the sub-input ports c5 and c6 are respectively connected to the filter 235 and the filter 236, and the sub-input ports c1, c2, c3, c4, c7, c8, and c9 are respectively connected to the seven duplexers 231, 232, 233, and 234. 237, 238, 239 connections.
  • filtering unit 23 may also include other numbers of filters and duplexers.
  • the antenna 25 may be a diversity antenna for receiving signals, and the antenna 25 is configured to receive a radio frequency signal from the outside and transmit the received downlink signal to the radio frequency transceiver 21.
  • the filtering unit 23 includes nine filters 231, 232, 233, 234, 235, 236, 237, 238, 239.
  • the filters 231, 232, 233, 234, 235, 236, 237, 238, 239 are respectively connected to the radio frequency receiving ports b1, b2, b3, b4, b5, b6, b7, b8, b9 of the radio frequency transceiver 21.
  • the side of the connection antenna is defined as an input terminal, and the side of the connection filter is defined as an output terminal.
  • the output of the RF circuit switch chip 24 includes nine sub-output ports c1, c2, c3, c4, c5, c6, c7, c8, c9.
  • the sub-output ports c1, c2, c3, c4, c5, c6, c7, c8, and c9 are connected to the filter units 231, 232, 233, 234, 235, 236, 237, 238, and 239, respectively.
  • the antenna 25 receives the radio frequency signal from the outside, passes the received downlink signal to the filtering unit 23 through the radio frequency switch chip 24, performs filtering by the filtering unit 23, and then transmits the signal to the radio frequency transceiver 21.
  • the radio frequency circuit 200 further includes a phase shifting unit 28.
  • phase shifting unit 28 includes nine phase shifters 281, 282, 283, 284, 285, 286, 287, 288, 289.
  • phase shifters 281, 282, 283, 284, 285, 286, 287, 288, 289 are connected to the filters 231, 232, 233, 234, 235, 236, 237, 238, 239, respectively;
  • the other ends of 281, 282, 283, 284, 285, 286, 287, 288, 289 are respectively connected to the nine sub-output ports c1, c2, c3, c4, c5, c6, c7, c8, c9 of the radio frequency circuit switch chip 24. .
  • the filtering unit 23 includes a 2-in-1 filter 231, a 2-in-1 filter 233, and filters 232, 234, 235, 236, 237, 238, and 239.
  • the two ports on the same side of the two-in-one filter 231 are simultaneously connected to the radio frequency receiving ports b1 and b2 of the radio frequency transceiver 21, and the port on the other side of the two-in-one filter 231 and the sub output port of the radio frequency circuit switch chip 24.
  • C1 connection For example, the output end of the 2-in-1 filter 231 is connected to the sub-receiving ports b1 and b2 of the band Band1 and Band3, and the input end of the 2-in-1 filter 231 is connected to the output end of the RF circuit switch chip 24, and the two-in-one filter The 231 is configured to filter the downlink signals of the intermediate frequency bands Band1 and Band3.
  • the 2-in-1 filter 231 can be connected to the radio frequency transmitting port of the radio frequency transceiver 21, such as a carrier configured to uplink signals of the intermediate frequency bands Band1 and Band3. .
  • the two ports on the same side of the two-in-one filter 233 are simultaneously connected to the radio frequency receiving ports b4 and b5 of the radio frequency transceiver 21, and the port on the other side of the two-in-one filter 233 is connected to the sub output port c3 of the radio frequency circuit switch chip 24. .
  • the output end of the 2-in-1 filter 233 is connected to the sub-receiving ports b4 and b5 of the Band 34 and Band 39, and the input end of the 2-in-1 filter 233 is connected to the RF circuit switch chip 24.
  • the 2-in-1 filter 233 is configured to filter the downlink signals of the intermediate frequency bands Band34 and Band39.
  • the 2-in-1 filter 233 can be connected to the radio frequency transmitting port of the radio frequency transceiver 21, for example, configured to perform carrier signals on the uplink signals of the intermediate frequency bands Band34 and Band39.
  • the output end of the 2-in-1 filter 233 is connected to the sub-receiving ports b4 and b5 of the Band 41 and Band 39, and the input end of the 2-in-1 filter 233 is connected to the output end of the RF circuit switch chip 24.
  • the 2-in-1 filter 233 is configured to filter the downlink signal of the high frequency band Band41 and the intermediate frequency band Band39.
  • the 2-in-1 filter 233 can be connected to the radio frequency transmitting port of the radio frequency transceiver 21, for example, configured for the high frequency band Band41 and the intermediate frequency band Band39.
  • the uplink signal is used for carrier aggregation.
  • filters 232, 234, 235, 236, 237, 238, 239 are respectively connected to the radio frequency receiving ports b3, b6, b7, b8, b9, b10, b11 of the radio frequency transceiver 21, and the filters 232, 234, 235,
  • the other ends of 236, 237, 238, and 239 are respectively connected to the sub-output ports c2, c4, c5, c6, c7, c8, and c9 of the radio frequency circuit switch chip 24.
  • filters 232, 234, 235, 236, 237, 238, and 239 are respectively configured to perform carrier signals on uplink signals of Band25, Band41, Band40, Band7, Band26, Band8, and Band20.
  • the filters 232, 234, 235, 236, 237, 238, 239 are respectively configured to perform carrier signals on the uplink signals of the bands Band25, Band34, Band40, Band7, Band26, Band8, Band20.
  • the filtering unit 23 includes a 2-in-1 filter 231, a 3-in-1 filter 233, and filters 232, 235, 236, 237, 238, 239.
  • the two ports on the same side of the two-in-one filter 231 are simultaneously connected to the radio frequency receiving ports b1 and b2 of the radio frequency transceiver 21, and the port on the other side of the two-in-one filter 231 and the sub output port of the radio frequency circuit switch chip 24.
  • C1 connection For example, the output end of the 2-in-1 filter 231 is connected to the sub-receiving ports b1 and b2 of the band Band1 and Band3, and the input end of the 2-in-1 filter 231 is connected to the output end of the RF circuit switch chip 24, and the two-in-one filter The 231 is configured to filter the downlink signals of the intermediate frequency bands Band1 and Band3.
  • the 2-in-1 filter 231 can be connected to the radio frequency transmitting port of the radio frequency transceiver 21, such as a carrier configured to uplink signals of the intermediate frequency bands Band1 and Band3. .
  • the three ports on the same side of the three-in-one filter 233 are simultaneously connected to the radio frequency receiving ports b4, b5, and b6 of the radio frequency transceiver 21, the port on the other side of the three-in-one filter 233, and the sub-output port of the radio frequency circuit switch chip 24.
  • the output end of the three-in-one filter 233 is connected to the sub-receiving ports b4, b5, and b6 of the Band 41, Band 34, and Band 39, and the input end of the 2-in-1 filter 233 is connected to the radio frequency circuit.
  • the output of the switch chip 24, the three-in-one filter 233 is configured to filter the downlink signals of the high frequency band Band41, the intermediate frequency band Band34, and the intermediate frequency band Band39.
  • the three-in-one filter 233 can be connected to the radio frequency transmitting port of the radio frequency transceiver 21, for example, configured to be in the high frequency band Band41, the intermediate frequency band Band34, and the middle.
  • the uplink signal of the frequency band Band39 is subjected to carrier aggregation.
  • filters 232, 235, 236, 237, 238, 239 are respectively connected to the radio frequency receiving ports b3, b7, b8, b9, b10, b11 of the radio frequency transceiver 21, and the filters 232, 235, 236, 237, 238, The other ends of 239 are respectively connected to sub-output ports c2, c5, c6, c7, c8, c9 of the radio frequency circuit switch chip 24.
  • filters 232, 235, 236, 237, 238, and 239 are respectively configured to perform carrier signals on uplink signals of Band25, Band40, Band7, Band26, Band8, and Band20.
  • LTE communication frequency band is divided into frequency division duplex (Frequency Division Duplex (FDD for short) and time division duplex (Time Division Duplex, referred to as TDD, is two types.
  • FDD Frequency Division Duplex
  • TDD Time Division Duplex
  • the uplink and downlink communication links use different frequencies.
  • the duplexer needs to filter the uplink and downlink communication signals in the RF circuit.
  • the uplink and downlink communication links use the same frequency to transmit RF signals in different time slots.
  • the RF circuit needs a filter to filter the uplink and downlink communication signals.
  • the number of filters and the number of duplexers included in the filtering unit 23 depend on the duplex mode in which the radio frequency signals of the respective frequency bands transmitted by the radio frequency transceiver 21 are located.
  • the RF transmit port and the RF receive port are connected to a duplexer; in the TDD mode, the RF transmit port and the RF receive port are connected to a filter.
  • the Band1 and Band2 bands operate in FDD mode, and the transmit and receive ports of the Band1 and Band2 RF signals are connected to the duplexer; while the Band40 and Band41 bands operate in the TDD mode, and the transmit and receive ports of the Band40 and Band41 RF signals are used. Connected to the filter.
  • the radio frequency circuit switch chip 24 includes a first switch 241, a second switch 242, and a frequency divider 243.
  • the first switch 241 is a double-pole multi-throw switch
  • the second switch 242 is a single-pole multi-throw switch.
  • the antenna 25 is a diversity antenna for receiving signals
  • the first switch 241 includes three first signal type sub-output ports c1, c2, and c3, and further includes three second signal type sub-output ports c4, c5, and c6.
  • the first switch 241 includes a first input port 2411 and a second input port 2412; the second switch 242 includes three third signal type sub-output ports c7, c8, c9.
  • the inputs of the first switch 241 and the second switch 242 are both connected to the output of the frequency divider 243.
  • the frequency divider 243 can be a three-frequency frequency divider.
  • the input of the frequency divider 243 is connected to the antenna 25.
  • connection relationship only indicates a direct connection between components, and does not mean that the components connected to each other are electrically connected.
  • the sub-output ports c1, c2, c3 may be respectively connected to the intermediate frequency ports in the radio frequency transceiver 21, and the sub-output ports c4, c5, c6 may be respectively connected to the high frequency ports in the radio frequency transceiver 21,
  • the output ports c7, c8, c9 can be respectively connected to the low frequency ports in the radio frequency transceiver 21.
  • the switch 242 When the first input port 2411 of the switch 241 is turned on by any one of c1, c2, and c3, the second input port 2412 of the switch 241 is turned on by any one of c4, c5, and c6, and the switch 242 is turned off.
  • 243 can divide the carrier aggregation signal into a high frequency signal and an intermediate frequency signal.
  • the frequency divider 243 can divide the carrier aggregation signal into an intermediate frequency signal and a low frequency signal. Or when the first input port 2411 of the switch 241 is turned off, the second input port 2412 of the switch 241 is turned on by any one of c1, c2, and c3, and when the switch 242 is turned on by any one of c7, c8, and c9, the frequency is divided.
  • the 243 can divide the carrier aggregation signal into an intermediate frequency signal and a low frequency signal.
  • the frequency divider is turned on.
  • 243 can divide the carrier aggregation signal into a high frequency signal and a low frequency signal. Or when the first input port 2412 of the switch 241 is turned on by any one of c4, c5, and c6, the second input port 2412 of the switch 241 is turned off, and the switch 242 is turned on by any one of c7, c8, and c9, and the frequency is divided.
  • the 243 can divide the carrier aggregation signal into a high frequency signal and a low frequency signal.
  • the frequency divider 243 can divide the carrier aggregation signal into a high frequency signal, an intermediate frequency signal, and a low frequency signal.
  • the frequency divider 243 can divide the carrier aggregation signal into a high frequency signal, an intermediate frequency signal, and a low frequency signal.
  • the device position of the frequency divider 243 can also be replaced with a combiner 2453.
  • the combiner 243 is used to implement a carrier of the multi-band signal. polymerization.
  • the RF circuit switch chip 24 includes a first switch 241, a second switch 242, a switch component 246, and a first frequency divider 244, a second frequency divider 245.
  • the first switch 241 is a double-pole multi-throw switch
  • the second switch 242 is a single-pole multi-throw switch.
  • the first switch 241 includes three first signal type sub-output ports c1, c2, c3, and further includes three second signal type sub-output ports c4, c5, c6, and the first switch 241 includes a first input port 2411 and The second input port 2412; the second switch 242 includes three third signal type sub-output ports c7, c8, c9.
  • the first input port 2411 of the first switch 241 and the second input port 2412 are connected to the switch assembly 246.
  • the input of the second switch 242 is coupled to the second output port of the second frequency divider 245.
  • Switch assembly 246 has three output ports P1, P2, P3 and three input ports Q1, Q2, Q3.
  • the output port P1 is connected to the first input port 2411 of the switch 241.
  • the output port P2 is connected to the second input port 2411 of the switch 241.
  • the output port P3 is connected to the input of the first frequency divider 244.
  • the input port Q1 is connected to the first output port of the frequency divider 244.
  • the input port Q2 is connected to the second output port of the frequency divider 244.
  • the input terminal Q3 is connected to the first output of the second frequency divider 245.
  • the first frequency divider 244 and the second frequency divider 245 are both dual frequency frequency dividers.
  • the input of the second frequency divider 245 is connected to the antenna 25.
  • switch assembly 246 includes switches K1, K2.
  • the switch K1 is a single-pole double-throw switch
  • K2 is a single-pole single-throw switch.
  • the fixed end of the single-pole double-throw switch K1 is connected to the second output port P2 of the switch assembly 246, and the gates of the single-pole double-throw switch K1 are respectively connected to the second input port Q2 and the second input port Q3 of the switch assembly 246;
  • the throw switch K1 can selectively turn on the second output port P2 and the second input port Q2 or the second input port Q3.
  • the output end and the input end of the single-pole single-throw switch K2 are respectively connected to the third output port P3 and the third input port Q3 of the switch assembly 246; the single-pole single-throw switch K2 can selectively turn on the third output port P3 and the third input port. Q3.
  • the sub-output ports c1, c2, c3 may be respectively connected to the intermediate frequency ports in the radio frequency transceiver 21, and the sub-output ports c4, c5, c6 may be respectively connected to the high frequency ports in the radio frequency transceiver 21,
  • the output ports c7, c8, c9 can be respectively connected to the low frequency ports in the radio frequency transceiver 21.
  • the frequency divider 244 can divide the carrier aggregation signal into a high frequency signal and an intermediate frequency signal.
  • the frequency divider 244 and the frequency divider 245 can divide the carrier aggregation signal into a high frequency signal and an intermediate frequency signal. , low frequency signal.
  • the frequency divider 245 can divide the carrier aggregation signal into an intermediate frequency signal and a low frequency signal.
  • the frequency divider 245 can The carrier aggregation signal is divided into a high frequency signal and a low frequency signal.
  • the sub-output port c2 can be connected to the IF band Band3 transmit port in the RF transceiver 21
  • the sub-output port c5 can be connected to the HF band Band 40 transmit port in the RF transceiver 21
  • the sub-output port c8 can be transceived with the RF.
  • the frequency divider 244 can divide the carrier aggregation signal into Band3 and Band40.
  • the frequency divider 244 and the frequency divider 245 can divide the carrier aggregation signal into Band3, Band40, and Band8.
  • the frequency divider 245 can divide the carrier aggregation signal. Into Band3 and Band8.
  • the frequency divider 245 can divide the carrier aggregation signal. to make Band40 and Band8.
  • switch assembly 246 includes switches K1, K2.
  • the switch K1 is a single-pole single-throw switch
  • K2 is a single-pole double-throw switch.
  • the output end and the input end of the single-pole single-throw switch K1 are respectively connected to the second output port P2 and the second input port Q2 of the switch assembly 246; the single-pole single-throw switch K1 can selectively connect the second output port P2 and the second input port Q2. .
  • the fixed end of the single-pole double-throw switch K2 is connected to the third input port Q3 of the switch assembly 246, and the gates of the single-pole double-throw switch K2 are respectively connected to the second output port P2 and the third output port P3 of the switch assembly 246;
  • the throw switch K2 can selectively connect the third input port Q3 with the second output port P2 or the third output port P3.
  • the sub-output ports c1, c2, c3 may be respectively connected to the intermediate frequency ports in the radio frequency transceiver 21, and the sub-output ports c4, c5, c6 may be respectively connected to the high frequency ports in the radio frequency transceiver 21,
  • the output ports c7, c8, c9 can be respectively connected to the low frequency ports in the radio frequency transceiver 21.
  • the frequency divider 244 can divide the carrier aggregation signal into a high frequency signal and an intermediate frequency signal.
  • the frequency divider 244 and the frequency divider 245 can implement a high frequency signal, an intermediate frequency signal, and a low frequency signal.
  • the frequency divider 245 can divide the carrier aggregation signal into an intermediate frequency signal and a low frequency signal.
  • the frequency divider 245 can divide the carrier aggregation signal into a high frequency signal and a low frequency signal.
  • the sub-output port c2 can be connected to the IF band Band3 transmit port in the RF transceiver 21
  • the sub-output port c5 can be connected to the HF band Band 40 transmit port in the RF transceiver 21
  • the sub-output port c8 can be transceived with the RF.
  • the frequency divider 244 can divide the carrier aggregation signal into Band3 and Band40.
  • the frequency divider 244 and the frequency divider 245 can divide the carrier aggregation signal into Band3, Band40, and Band8.
  • the frequency divider 245 can divide the carrier aggregation signal. Into Band3 and Band8.
  • the frequency divider 245 can divide the carrier aggregation signal. to make Band40 and Band8.
  • the first switch 241 and the second switch 242 may be packaged to form the first chip 247.
  • switch assembly 246 includes switches K1, K2, K3.
  • the switch K1, K2, and K3 are single-pole single-throw switches.
  • the output end and the input end of the single-pole single-throw switch K1 are respectively connected to the second output port P2 and the second input port Q2 of the switch assembly 246; the single-pole single-throw switch K1 can selectively connect the second output port P2 and the second input port Q2. .
  • the output end and the input end of the single-pole single-throw switch K2 are respectively connected to the second output port P2 and the third input port Q3 of the switch assembly 246; the single-pole single-throw switch K2 can selectively connect the second output port P2 and the second input port Q3. .
  • the output end and the input end of the single-pole single-throw switch K3 are respectively connected to the third output port P3 and the third input port Q3 of the switch assembly 246; the single-pole single-throw switch K3 can selectively connect the third output port P3 and the third input port Q3. .
  • the sub-output ports c1, c2, c3 may be respectively connected to the intermediate frequency ports in the radio frequency transceiver 21, and the sub-output ports c4, c5, c6 may be respectively connected to the high frequency ports in the radio frequency transceiver 21,
  • the output ports c7, c8, c9 can be respectively connected to the low frequency ports in the radio frequency transceiver 21.
  • the frequency divider 244 can divide the carrier aggregation signal into a high frequency signal and an intermediate frequency signal.
  • the switch K2 when the switch K2 is turned off, the switch K3 is turned on P3 and Q3, and the switch 242 is turned on any one of c7, c8, c9, the frequency divider 244 and the frequency divider 245 can divide the carrier aggregation signal into high. Frequency signal, intermediate frequency signal, low frequency signal.
  • the frequency divider 245 can divide the carrier aggregation signal into an intermediate frequency signal and a low frequency signal.
  • the frequency divider 245 can divide the carrier aggregation signal into a high frequency signal and a low frequency signal.
  • the sub-output port c2 can be connected to the IF band Band3 transmit port in the RF transceiver 21
  • the sub-output port c5 can be connected to the HF band Band 40 transmit port in the RF transceiver 21
  • the sub-output port c8 can be transceived with the RF.
  • the frequency divider 244 can divide the carrier aggregation signal into Band3 and Band40.
  • the switch K2 when the switch K2 is turned off, the switch K3 is turned on P3 and Q3, and the switch 242 is turned on c8, the frequency divider 244 and the frequency divider 245 can implement Band3, Band40, and Band8.
  • the frequency divider 245 can The carrier aggregation signal is divided into Band3 and Band8.
  • the frequency divider 245 can Carrier aggregation signal is divided into Band40 and Band8.
  • the first switch 241, the second switch 242, and the switch assembly 246 can be packaged to form the second chip 248.
  • the device locations of the frequency divider 244 and the frequency divider 245 may also be replaced with a combiner 244 and a combiner 245.
  • the 244 and combiner 245 are used to implement carrier aggregation of multi-band signals.
  • FIG. 19 is a schematic structural diagram of a radio frequency circuit 200.
  • the radio frequency transceiver 21 includes nine radio frequency transmitting ports a1, a2, a3, a4, a5, a6, a7, a8, a9, and nine radio frequency receiving ports b1, b2, b3, b4, b5, b6, b7, B8, b9.
  • a1, a2, and a3 are intermediate frequency transmission ports for transmitting intermediate frequency radio frequency signals (for example, radio frequency signals in bands such as Band1, Band3, Band34 or Band39).
  • B1, b2, and b3 are intermediate frequency receiving ports for receiving intermediate frequency radio frequency signals.
  • A4, a5, and a6 are high-frequency transmitting ports for transmitting high-frequency RF signals (for example, RF signals in Band7, Band40, Band41, etc.).
  • B4, b5, and b6 are high frequency receiving ports for receiving high frequency RF signals.
  • A7, a8, and a9 are low-frequency transmit ports for transmitting low-frequency RF signals (for example, RF signals in Band8, Band12, Band20, or Band26).
  • B7, b8, and b9 are low frequency receiving ports for receiving low frequency RF signals.
  • the above embodiment only takes the high frequency port 21H, the intermediate frequency port 21M, and the low frequency port 21L of the radio frequency transceiver 21 as three radio frequency transmitting ports and three radio frequency receiving ports as an example for description.
  • the high frequency port 21H, the intermediate frequency port 21M, and the low frequency port 21L may also include other numbers of radio frequency transmitting ports and radio frequency receiving ports, respectively. It suffices that the number of the radio frequency transmitting port and the radio frequency receiving port included in each of the high frequency port 21H, the intermediate frequency port 21M, and the low frequency port 21L is the same and greater than one.
  • the power amplifying unit 22 includes nine amplifiers 221, 222, 223, 224, 225, 226, 227, 228, 229.
  • the amplifiers 221, 222, 223, 224, 225, 226, 227, 228, 229 are respectively connected to the radio frequency transmitting ports a1, a2, a3, a4, a5, a6, a7, a8, a9 of the radio frequency transceiver 21.
  • the filtering unit 23 includes nine duplexers 231, 232, 233, 234, 235, 236, 237, 238, 239. Among them, the duplexers 231, 232, 233, 234, 235, 236, 237, 238, 239 are connected to the amplifiers 221, 222, 223, 224, 225, 226, 227, 228, 229, respectively. And, the duplexers 231, 232, 233, 234, 235, 236, 237, 238, 239 are respectively connected to the radio frequency receiving ports b1, b2, b3, b4, b5, b6, b7, b8, b9 of the radio frequency transceiver 21. .
  • the RF circuit switch chip 24 includes a first switch 241, a second switch 242, a switch component 246, and a first frequency divider 244 and a second frequency divider 245.
  • the first switch 241 is a double-pole multi-throw switch
  • the second switch 242 is a single-pole multi-throw switch.
  • the first switch 241 includes three first signal type sub-output ports c1, c2, c3, and further includes three second signal type sub-output ports c4, c5, c6, and the first switch 241 includes a first input port 2411 and The second input port 2412; the second switch 242 includes three third signal type sub-output ports c7, c8, c9.
  • the first input port 2411 of the first switch 241 and the second input port 2412 are connected to the switch assembly 246.
  • the input of the second switch 242 is coupled to the second output port of the second frequency divider 245.
  • Switch assembly 246 has three output ports P1, P2, P3 and three input ports Q1, Q2, Q3.
  • the output port P1 is connected to the first input port 2411 of the switch 241.
  • the output port P2 is connected to the second input port 2411 of the switch 241.
  • the output port P3 is connected to the input of the first frequency divider 244.
  • the input port Q1 is connected to the first output port of the frequency divider 244.
  • the input port Q2 is connected to the second output port of the frequency divider 244.
  • the input terminal Q3 is connected to the first output of the second frequency divider 245.
  • the sub-output ports c1, c2, c3, c4, c5, c6, c7, c8, and c9 of the RF circuit switch chip 24 are respectively connected to the duplexers 231, 232, 233, 234, 235, 236, 237, 238, 239. connection.
  • the first frequency divider 244 and the second frequency divider 245 are both dual frequency frequency dividers.
  • the input of the second frequency divider 245 is connected to the antenna 25.
  • the radio frequency circuit switch chip 24 can control the high frequency port and the intermediate frequency port of the radio frequency transceiver 21 to be connected to the first frequency divider 244 to divide the carrier aggregation signal into a high frequency signal and an intermediate frequency signal;
  • the high frequency port and the intermediate frequency port of the radio frequency transceiver 21 are connected to the first frequency divider 244, and the first frequency divider 244 and the low frequency port of the radio frequency transceiver 21 are connected to the second frequency divider 245 to divide the carrier aggregation signal.
  • the high frequency signal, the intermediate frequency signal, and the low frequency signal are frequency-divided; the high frequency port and the low frequency port of the radio frequency transceiver 21 can be controlled to be connected to the second frequency divider 245 to divide the carrier aggregation signal into a high frequency signal and a low frequency signal; The intermediate frequency port and the low frequency port of the radio frequency transceiver 21 can be controlled to be connected to the second frequency divider 245 to divide the carrier aggregation signal into an intermediate frequency signal and a low frequency signal.
  • the RF circuit switch chip 24 is capable of dividing the carrier aggregation signal, thereby improving the diversity of the frequency division of the carrier aggregation signal by the electronic device 100.
  • the battery 104 is mounted inside the casing 105. Battery 104 is used to provide electrical energy to electronic device 100.
  • the housing 105 is used to form an outer contour of the electronic device 100.
  • the material of the casing 105 may be plastic or metal.
  • the housing 105 can be integrally formed.
  • FIG. 20 is another schematic structural diagram of an electronic device 100 according to an embodiment of the present invention.
  • the electronic device 100 includes an antenna device 10, a memory 20, a display unit 30, a power source 40, and a processor 50.
  • Those skilled in the art can understand that the structure of the electronic device 100 shown in FIG. 20 does not constitute a limitation on the electronic device 100.
  • Electronic device 100 may include more or fewer components than illustrated, or some components in combination, or different component arrangements.
  • the antenna device 10 includes the radio frequency circuit 200 described in any of the above embodiments.
  • the antenna device 10 can communicate with a network device (eg, a server) or other electronic device (eg, a smart phone) over a wireless network to perform transceiving of information with a network device or other electronic device.
  • a network device eg, a server
  • other electronic device eg, a smart phone
  • Memory 20 can be used to store applications and data.
  • the application stored in the memory 20 contains executable program code.
  • Applications can form various functional modules.
  • the processor 50 executes various functional applications and data processing by running an application stored in the memory 20.
  • the display unit 30 can be used to display information input by the user to the electronic device 100 or information provided to the user and various graphical user interfaces of the electronic device 100. These graphical user interfaces can be composed of graphics, text, icons, video, and any combination thereof.
  • the display unit 30 may include a display panel.
  • the power source 40 is used to power various components of the electronic device 100.
  • the power source 40 can be logically coupled to the processor 50 through a power management system to enable functions such as managing charging, discharging, and power management through the power management system.
  • the processor 50 is a control center of the electronic device 100.
  • the processor 50 connects various parts of the entire electronic device 100 using various interfaces and lines, performs various functions of the electronic device 100 by running or executing an application stored in the memory 20, and calling data stored in the memory 20.
  • the data is processed to perform overall monitoring of the electronic device 100.
  • the electronic device 100 may further include a camera module, a Bluetooth module, and the like, and details are not described herein again.
  • the radio frequency circuit switch chip, the radio frequency circuit, the antenna device and the electronic device provided by the embodiments of the present invention are described in detail.
  • the principles and implementation manners of the present invention are described in the specific examples. The description of the above embodiments is only used. To help understand the invention. In the meantime, the present invention is not limited by the scope of the present invention.

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Abstract

一种射频电路开关芯片，可以通过第一开关、第二开关与第一分频器、第二分频器之间不同的导通状态，可以将接收信号分频成高频信号与中频信号、分频成高频信号与低频信号、分频成中频信号与低频信号、或者分频成高频信号、中频信号、低频信号。本发明还提供一种射频电路、天线装置及电子设备。

Description

射频电路开关芯片、射频电路、天线装置及电子设备 技术领域
本发明涉及通信技术领域，特别涉及一种射频电路开关芯片、射频电路、天线装置及电子设备。
 背景技术
随着通信技术的发展，移动终端能够支持的通信频段越来越多。例如，LTE（Long Term Evolution，长期演进）通信信号可以包括频率在700MHz至2700MHz之间的信号。
移动终端能够支持的射频信号可以分为低频信号、中频信号和高频信号。其中，低频信号、中频信号以及高频信号各自又包括多个子频段信号。每个子频段信号都需要通过天线发射到外界。
由此，产生了载波聚合（Carrier Aggregation，简称CA）技术。通过载波聚合，可以将多个子频段信号聚合在一起，以提高网络上下行传输速率。
目前，全球各个通信市场的频率资源互不相同。不同区域的通信运营商拥有不同的通信频谱分配，存在不同的载波聚合的频段组合需求。相应的，当终端处于载波聚合状态即接收到不同频段组合的射频信号时，需要对射频信号进行分频操作，以得到特定频段的射频信号。然而，当前的分频方式单一，缺乏多样性，无法满足上述需求。
 技术问题
本发明实施例提供一种射频电路开关芯片、射频电路、天线装置及电子设备，可以提高电子设备对射频信号进行分频的多样性。
 技术解决方案
第一方面，本发明实施例提供一种射频电路开关芯片，包括第一开关、第二开关、第一分频器以及第二分频器，所述第一开关用于接收高频信号或者中频信号，所述第二开关用于接收低频信号；
当该第一开关的第一输入端口与第二输入端口分别用于接收不同信号，该第一开关的第一输入端口与第二输入端口选择性接通该第一分频器，该第一分频器将接收信号分频成高频信号与中频信号；且当该第一分频器与该第二开关选择性接通该第二分频器，该第一分频器与该第二分频器将接收信号分频成高频信号、中频信号、低频信号；
当该第一开关的第二输入端口、该第二开关选择性接通该第二分频器，该第二分频器将接收信号分频成中频信号与低频信号、或者高频信号与低频信号。
第二方面，本发明实施例提供一种射频电路，包括射频收发器、射频电路开关芯片以及天线，该射频收发器、射频电路开关芯片以及天线依次连接；
该射频电路开关芯片包括第一开关、第二开关、第一分频器以及第二分频器，所述第一开关的第一输入端口与第二输入端口用于接收高频信号或者中频信号，所述第二开关用于接收低频信号；
当所述第一开关的第一输入端口与第二输入端口分别用于接收不同信号，所述第一开关的第一输入端口与第二输入端口选择性接通所述第一分频器，所述第一分频器将接收信号分频成高频信号与中频信号；且当所述第一分频器与所述第二开关选择性接通所述第二分频器，所述第一分频器与所述第二分频器将接收信号分频成高频信号、中频信号、低频信号；
当所述第一开关的第二输入端口、所述第二开关选择性接通所述第二分频器，所述第二分频器将接收信号分频成中频信号与低频信号、或者高频信号与低频信号。
第三方面，本发明实施例提供一种天线装置，包括上述射频电路。
第四方面，本发明实施例提供一种电子设备，包括壳体和电路板，该电路板安装在该壳体内部，该电路板上设置有射频电路，该射频电路为上述射频电路。
 有益效果
本发明实施例提供一种射频电路开关芯片、射频电路、天线装置及电子设备，可以提高电子设备对射频信号进行分频的多样性。
 附图说明
图1是本发明实施例提供的电子设备的分解示意图。
图2是本发明实施例提供的电子设备的结构示意图。
图3是本发明实施例提供的射频电路的第一种结构示意图。
图4是本发明实施例提供的射频电路的第二种结构示意图。
图5是本发明实施例提供的射频电路的第三种结构示意图。
图6是本发明实施例提供的射频电路的第四种结构示意图。
图7是本发明实施例提供的射频电路的第五种结构示意图。
图8是本发明实施例提供的射频电路的第六种结构示意图。
图9是本发明实施例提供的射频电路的第七种结构示意图。
图10是本发明实施例提供的射频电路的第八种结构示意图。
图11是本发明实施例提供的射频电路的第九种结构示意图。
图12是本发明实施例提供的射频电路的第十种结构示意图。
图13是本发明实施例提供的射频电路的第十一种结构示意图。
图14是本发明实施例提供的射频电路的第十二种结构示意图。
图15是本发明实施例提供的射频电路开关芯片的第一种结构示意图。
图16是本发明实施例提供的射频电路开关芯片的第二种结构示意图。
图17是本发明实施例提供的射频电路开关芯片的第三种结构示意图。
图18是本发明实施例提供的射频电路开关芯片的第四种结构示意图。
图19是本发明实施例提供的射频电路的第十三种结构示意图。
图20是本发明实施例提供的电子设备的另一结构示意图。
 本发明的最佳实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
本发明实施例提供一种电子设备。该电子设备可以是智能手机、平板电脑等设备。参考图1和图2，电子设备100包括盖板101、显示屏102、电路板103、电池104以及壳体105。
其中，盖板101安装到显示屏102上，以覆盖显示屏102。盖板101可以为透明玻璃盖板。在一些实施例中，盖板101可以是用诸如蓝宝石等材料制成的玻璃盖板。
显示屏102安装在壳体105上，以形成电子设备100的显示面。显示屏102可以包括显示区域102A和非显示区域102B。显示区域102A用于显示图像、文本等信息。非显示区域102B不显示信息。非显示区域102B的底部可以设置指纹模组、触控电路等功能组件。
电路板103安装在壳体105内部。电路板103可以为电子设备100的主板。电路板103上可以集成有摄像头、接近传感器以及处理器等功能组件。同时，显示屏102可以电连接至电路板103。
在一些实施例中，电路板103上设置有射频（RF，Radio Frequency）电路。射频电路可以通过无线网络与网络设备（例如，服务器、基站等）或其他电子设备（例如，智能手机等）通信，以完成与网络设备或其他电子设备之间的信息收发。
在一些实施例中，如图3所示，射频电路200包括射频收发器21、功率放大单元22、滤波单元23、射频电路开关芯片24以及天线25。其中，功率放大单元22、滤波单元23、射频电路开关芯片24以及天线25依次连接。
射频收发器21具有发射端口TX和接收端口RX。发射端口TX用于发射射频信号（上行信号），接收端口RX用于接收射频信号（下行信号）。射频收发器21的发射端口TX与功率放大单元22连接，接收端口RX与滤波单元23连接。
功率放大单元22用于对射频收发器21发射的上行信号进行放大，并将放大后的上行信号发送到滤波单元23。
滤波单元23用于对射频收发器21发射的上行信号进行滤波，并将滤波后的上行信号发送到天线25。滤波单元23还用于对天线25接收的下行信号进行滤波，并将滤波后的下行信号发送到射频收发器21。
射频电路开关芯片24用于选择性接通射频收发器21与天线25之间的通信频段。射频电路开关芯片24的详细结构和功能将在下文进行描述。
天线25用于将射频收发器21发送的上行信号发射到外界，或者从外界接收射频信号，并将接收到的下行信号发送到射频收发器21。
在一些实施例中，如图4所示，射频电路200还包括控制电路26。其中，控制电路26与射频电路开关芯片24连接。控制电路26还可以与电子设备100中的处理器连接，以根据处理器的指令控制射频电路开关芯片24的状态。
在一些实施例中，如图5所示，射频电路200还包括低噪声放大单元27。其中，在射频收发器21的接收端口RX与滤波单元23之间连接有低噪声放大单元27，低噪声放大单元27用于对弱信号的放大，降低下行信号中的噪声。
在一些实施例中，如图6所示，射频电路200还包括相位平移（Phase Shift）单元28。其中，在滤波单元23与射频电路开关芯片24之间还连接有相位平移单元28。相位平移单元28用于调整上行信号或者下行信号的信号幅值的相位。
在一些实施例中，如图7所示，射频电路200还包括低噪音放大单元27和相位平移单元28。其中，在射频收发器21的接收端口RX与滤波单元23之间连接有低噪声放大单元27；低噪声放大单元27用于对弱信号的放大，降低下行信号中的噪声。在滤波单元23与射频电路开关芯片24之间还连接有相位平移单元28；相位平移单元28用于调整上行信号或者下行信号的信号幅值的相位。
在一些实施例中，如图8所示，射频收发器21包括高频端口21H、中频端口21M以及低频端口21L。其中，高频端口21H、中频端口21M、低频端口21L可以分别包括多个射频发射端口和多个射频接收端口。高频端口21H用于收发高频射频信号，中频端口21M用于收发中频射频信号，低频端口21L用于收发低频射频信号。
需要说明的是，上述高频射频信号、中频射频信号、低频射频信号只是相对概念，并无绝对的频率范围区分。例如，低频信号为700-960MHz（兆赫兹），中频信号为1710-2170 MHz，高频信号为2300-2690MHz。
例如，射频收发器21包括9个射频发射端口a1、a2、a3、a4、a5、a6、a7、a8、a9，以及9个射频接收端口b1、b2、b3、b4、b5、b6、b7、b8、b9。
其中，a1、a2、a3为中频发射端口，用于发射中频射频信号（例如，Band1、Band3、Band34或Band39等频段的射频信号）。b1、b2、b3为中频接收端口，用于接收中频射频信号。a4、a5、a6为高频发射端口，用于发射高频射频信号（例如，Band7、Band40、Band41等频段的射频信号）。b4、b5、b6为高频接收端口，用于接收高频射频信号。a7、a8、a9为低频发射端口，用于发射低频射频信号（例如，Band8、Band12、Band20或Band26等频段的射频信号）。b7、b8、b9为低频接收端口，用于接收低频射频信号。
需要说明的是，上述实施例仅以射频收发器21的高频端口21H、中频端口21M、低频端口21L分别包括3个射频发射端口和3个射频接收端口为例进行说明。在其他一些实施例中，高频端口21H、中频端口21M、低频端口21L还可以分别包括其他数量的射频发射端口和射频接收端口。只需满足高频端口21H、中频端口21M、低频端口21L各自所包括的射频发射端口和射频接收端口的数量相同并且大于1即可。
功率放大单元22包括9个放大器221、222、223、224、225、226、227、228、229。其中，放大器221、222、223、224、225、226、227、228、229分别与射频收发器21的射频发射端口a1、a2、a3、a4、a5、a6、a7、a8、a9连接。
滤波单元23包括9个双工器231、232、233、234、235、236、237、238、239。其中，双工器231、232、233、234、235、236、237、238、239分别与放大器221、222、223、224、225、226、227、228、229连接。并且，双工器231、232、233、234、235、236、237、238、239分别与射频收发器21的射频接收端口b1、b2、b3、b4、b5、b6、b7、b8、b9连接。
当天线25为可以用于发射信号或者接收信号的主集天线时，则连接天线一侧定义为输出端，连接滤波器一侧定义为输入端。射频电路开关芯片24的输入端包括9个子输入端口c1、c2、c3、c4、c5、c6、c7、c8、c9。其中，子输入端口c1、c2、c3、c4、c5、c6、c7、c8、c9分别与双工器231、232、233、234、235、236、237、238、239连接。
在一些实施例中，如图9所示，滤波单元23包括滤波器235、滤波器236以及7个双工器231、232、233、234、237、238、239。其中，滤波器235、滤波器236分别与放大器225、226连接，7个双工器231、232、233、234、237、238、239分别与放大器221、222、223、224、227、228、229连接。并且，滤波器235、滤波器236分别与射频收发器21的射频接收端口b5、b6连接，7个双工器231、232、233、234、237、238、239分别与射频收发器21的射频接收端口b1、b2、b3、b4、b7、b8、b9连接。
当天线25为可以用于发射信号或者接收信号的主集天线时，则连接天线一侧定义为输出端，连接滤波器一侧定义为输入端。射频电路开关芯片24的输入端包括9个子输入端口c1、c2、c3、c4、c5、c6、c7、c8、c9。其中，子输入端口c5、c6分别与滤波器235、滤波器236连接，子输入端口c1、c2、c3、c4、c7、c8、c9分别与7个双工器231、232、233、234、237、238、239连接。
需要说明的是，上述实施例仅以滤波单元23包括2个滤波器以及7个双工器为例进行说明。在其他一些实施例中，滤波单元23还可以包括其他数量的滤波器和双工器。
在一些实施例中，如图10-14所示，天线25可以为用于接收信号的分集天线，天线25用于从外界接收射频信号，并将接收到的下行信号发送到射频收发器21。
如图10所示，例如滤波单元23包括9个滤波器231、232、233、234、235、236、237、238、239。其中，滤波器231、232、233、234、235、236、237、238、239分别与射频收发器21的射频接收端口b1、b2、b3、b4、b5、b6、b7、b8、b9连接。
当天线25为用于接收信号的分集天线时，则连接天线一侧定义为输入端，连接滤波器一侧定义为输出端。射频电路开关芯片24的输出端包括9个子输出端口c1、c2、c3、c4、c5、c6、c7、c8、c9。其中，子输出端口c1、c2、c3、c4、c5、c6、c7、c8、c9分别与滤波器器231、232、233、234、235、236、237、238、239连接。
天线25从外界接收射频信号，将接收到的下行信号经过射频开关芯片24进入滤波单元23，通过滤波单元23进行滤波之后再发送到射频收发器21。
如图11所示，射频电路200还包括相位平移单元28。例如相位平移单元28包括9个相位平移器281、282、283、284、285、286、287、288、289。
其中，相位平移器281、282、283、284、285、286、287、288、289的一端分别与滤波器231、232、233、234、235、236、237、238、239连接；相位平移器281、282、283、284、285、286、287、288、289的另一端分别与射频电路开关芯片24的9个子输出端口c1、c2、c3、c4、c5、c6、c7、c8、c9连接。
如图12及图13所示，例如滤波单元23包括二合一滤波器231、二合一滤波器233以及滤波器232、234、235、236、237、238、239。
其中，二合一滤波器231同侧的两个端口同时与射频收发器21的射频接收端口b1、b2连接，二合一滤波器231另一侧的端口与射频电路开关芯片24的子输出端口c1连接。例如，二合一滤波器231的输出端连接于频段为Band1、Band3的子接收端口b1、b2，二合一滤波器231的输入端连接于射频电路开关芯片24的输出端，二合一滤波器231被配置为对中频频段Band1、Band3的下行信号进行滤波。一些实施例中，当天线25为用于发送信号的天线时，二合一滤波器231可以连接射频收发器21的射频发射端口，比如被配置为对中频频段Band1、Band3的上行信号进行载波。
二合一滤波器233同侧的两个端口同时与射频收发器21的射频接收端口b4、b5连接，二合一滤波器233另一侧的端口与射频电路开关芯片24的子输出端口c3连接。如图12所示，譬如二合一滤波器233的输出端连接于频段为Band34、Band39的子接收端口b4、b5，所述二合一滤波器233的输入端连接于射频电路开关芯片24的输出端，二合一滤波器233被配置为对中频频段Band34、Band39的下行信号进行滤波。一些实施例中，当天线25为用于发送信号的天线时，二合一滤波器233可以连接射频收发器21的射频发射端口，比如被配置为对中频频段Band34、Band39的上行信号进行载波。如图13所示，譬如二合一滤波器233的输出端连接于频段为Band41、Band39的子接收端口b4、b5，二合一滤波器233的输入端连接于射频电路开关芯片24的输出端，二合一滤波器233被配置为对高频频段Band41、中频频段Band39的下行信号进行滤波。一些实施例中，当天线25为用于发送信号的天线时，二合一滤波器233可以连接射频收发器21的射频发射端口，比如被配置为对高频频段为Band41、中频频段Band39的上行信号进行载波聚合。
滤波器232、234、235、236、237、238、239的一端分别与射频收发器21的射频接收端口b3、b6、b7、b8、b9、b10、b11连接，滤波器232、234、235、236、237、238、239的另一端分别与射频电路开关芯片24的子输出端口c2、c4、c5、c6、c7、c8、c9连接。如图12所示，譬如滤波器232、234、235、236、237、238、239分别被配置为对频段为Band25、Band41、Band40、Band7、Band26、Band8、Band20的上行信号进行载波。如图13所示，譬如滤波器232、234、235、236、237、238、239分别被配置为对对频段为Band25、Band34、Band40、Band7、Band26、Band8、Band20的上行信号进行载波。
如图14所示，例如滤波单元23包括二合一滤波器231、三合一滤波器233以及滤波器232、235、236、237、238、239。
其中，二合一滤波器231同侧的两个端口同时与射频收发器21的射频接收端口b1、b2连接，二合一滤波器231另一侧的端口与射频电路开关芯片24的子输出端口c1连接。例如，二合一滤波器231的输出端连接于频段为Band1、Band3的子接收端口b1、b2，二合一滤波器231的输入端连接于射频电路开关芯片24的输出端，二合一滤波器231被配置为对中频频段Band1、Band3的下行信号进行滤波。一些实施例中，当天线25为用于发送信号的天线时，二合一滤波器231可以连接射频收发器21的射频发射端口，比如被配置为对中频频段Band1、Band3的上行信号进行载波。
三合一滤波器233同侧的三个端口同时与射频收发器21的射频接收端口b4、b5、b6连接，三合一滤波器233另一侧的端口与射频电路开关芯片24的子输出端口c3连接。如图14所示，譬如三合一滤波器233的输出端连接于频段为Band41、Band34、Band39的子接收端口b4、b5、b6，所述二合一滤波器233的输入端连接于射频电路开关芯片24的输出端，三合一滤波器233被配置为对高频频段Band41、中频频段Band34、中频频段Band39的下行信号进行滤波。一些实施例中，当天线25为用于发送信号的天线时，三合一滤波器233可以连接射频收发器21的射频发射端口，比如被配置为对高频频段Band41、中频频段Band34、中频频段Band39的上行信号进行载波聚合。
滤波器232、235、236、237、238、239的一端分别与射频收发器21的射频接收端口b3、b7、b8、b9、b10、b11连接，滤波器232、235、236、237、238、239的另一端分别与射频电路开关芯片24的子输出端口c2、c5、c6、c7、c8、c9连接。如图14所示，譬如滤波器232、235、236、237、238、239分别被配置为对对频段为Band25、Band40、Band7、Band26、Band8、Band20的上行信号进行载波。
需要说明的是，上述实施例举例的滤波器、双工器、相位平移器、以及各个端口的个数和连接关系不作为对本发明的限定。
在长期演进（Long Term Evolution，简称LTE）通讯网络中，根据双工方式的不同，LTE的通讯频段分为频分双工（Frequency Division Duplex，简称FDD）和时分双工（Time Division Duplex，简称TDD）两种类型。处在FDD模式下的通讯频段，上下行通讯链路使用不同的频率，此时射频电路中需要双工器对上下行通讯信号进行滤波处理。处在TDD模式下的通讯频段，上下行通讯链路使用相同的频率，在不同的时隙进行射频信号的传输，此时射频电路中需要滤波器对上下行通讯信号进行滤波处理。
因此，实际应用中，滤波单元23中包括的滤波器数量和双工器数量取决于射频收发器21发射的各个频段的射频信号所处的双工模式。处于FDD模式的频段，射频发射端口和射频接收端口连接的是双工器；处于TDD模式的频段，射频发射端口和射频接收端口连接的是滤波器。例如，Band1、Band2频段工作在FDD模式，Band1、Band2射频信号的发射端口和接收端口连接的是双工器；而Band40、Band41频段工作在TDD模式，Band40、Band41射频信号的发射端口和接收端口连接的是滤波器。
参考图15，在一些实施例中，射频电路开关芯片24包括第一开关241、第二开关242以及分频器243。
其中，第一开关241为双刀多掷开关，第二开关242为单刀多掷开关。例如，天线25为用于接收信号的分集天线，第一开关241包括3个第一信号类型子输出端口c1、c2、c3，还包括3个第二信号类型子输出端口c4、c5、c6，第一开关241包括第一输入端口2411与第二输入端口2412；第二开关242包括3个第三信号类型子输出端口c7、c8、c9。第一开关241、第二开关242的输入端均连接到分频器243的输出端。
分频器243可以为三频分频器。分频器243的输入端连接到天线25。
需要说明的是，上述连接关系仅表示元器件之间的直接连接，并不代表互相连接的元器件之间处于电性接通状态。
在一些实施例中，子输出端口c1、c2、c3可以分别与射频收发器21中的中频端口连接，子输出端口c4、c5、c6可以分别与射频收发器21中的高频端口连接，子输出端口c7、c8、c9可以分别与射频收发器21中的低频端口连接。
当开关241的第一输入端口2411接通c1、c2、c3中的任意一路，开关241的第二输入端口2412接通c4、c5、c6中的任意一路，开关242断开时，分频器243可以将载波聚合信号分频成高频信号与中频信号。
当开关241的第一输入端口2411接通c1、c2、c3中的任意一路，开关241的第二输入端口2412断开，开关242接通c7、c8、c9中的任意一路时，分频器243可以将载波聚合信号分频成中频信号与低频信号。或者当开关241的第一输入端口2411断开，开关241的第二输入端口2412接通c1、c2、c3中的任意一路，开关242接通c7、c8、c9中的任意一路时，分频器243可以将载波聚合信号分频成中频信号与低频信号。
当开关241的第一输入端口2411断开，开关241的第二输入端口2412接通c4、c5、c6中的任意一路，开关242接通c7、c8、c9中的任意一路时，分频器243可以将载波聚合信号分频成高频信号与低频信号。或者当开关241的第一输入端口2412接通c4、c5、c6中的任意一路，开关241的第二输入端口2412断开，开关242接通c7、c8、c9中的任意一路时，分频器243可以将载波聚合信号分频成高频信号与低频信号。
当开关241的第一输入端口2411接通c1、c2、c3中的任意一路，开关241的第二输入端口2412接通c4、c5、c6中的任意一路，开关242接通c7、c8、c9中的任意一路时，分频器243可以将载波聚合信号分频成高频信号、中频信号与低频信号。或者当开关241的第二输入端口2412接通c1、c2、c3中的任意一路，开关241的第一输入端口2411接通c4、c5、c6中的任意一路，开关242接通c7、c8、c9中的任意一路时，分频器243可以将载波聚合信号分频成高频信号、中频信号与低频信号。
在一些实施例中，分频器243的器件位置也可以替换成合路器2453，当天线25为用于发射信号或者接收信号的主集天线时，合路器243用于实现多频段信号的载波聚合。
参考图16至图18，在一些实施例中，射频电路开关芯片24包括第一开关241、第二开关242、开关组件246以及第一分频器244、第二分频器245。
其中，第一开关241为双刀多掷开关，第二开关242为单刀多掷开关。例如，第一开关241包括3个第一信号类型子输出端口c1、c2、c3，还包括3个第二信号类型子输出端口c4、c5、c6，第一开关241包括第一输入端口2411与第二输入端口2412；第二开关242包括3个第三信号类型子输出端口c7、c8、c9。第一开关241的第一输入端口2411与第二输入端口2412连接到开关组件246。第二开关242的输入端连接到第二分频器245的第二输出端口。开关组件246具有3个输出端口P1、P2、P3以及3个输入端口Q1、Q2、Q3。其中，输出端口P1与开关241的第一输入端口2411连接。输出端口P2与开关241的第二输入端口2411连接。输出端口P3与第一分频器244的输入端连接。输入端口Q1与分频器244的第一输出端口连接。输入端口Q2与分频器244的第二输出端口连接。输入端Q3与第二分频器245的第一输出端连接。
其中，第一分频器244、第二分频器245都为双频分频器。第二分频器245的输入端连接到天线25。
在一些实施例中，如图16所示，开关组件246包括开关K1、K2。其中，开关K1为单刀双掷开关，K2为单刀单掷开关。
单刀双掷开关K1的固定端与开关组件246的第二输出端口P2连接，单刀双掷开关K1的选通端分别与开关组件246的第二输入端口Q2和第二输入端口Q3连接；单刀双掷开关K1可以选择性接通第二输出端口P2与第二输入端口Q2或第二输入端口Q3。
单刀单掷开关K2的输出端和输入端分别与开关组件246的第三输出端口P3和第三输入端口Q3连接；单刀单掷开关K2可选择性接通第三输出端口P3与第三输入端口Q3。
在一些实施例中，子输出端口c1、c2、c3可以分别与射频收发器21中的中频端口连接，子输出端口c4、c5、c6可以分别与射频收发器21中的高频端口连接，子输出端口c7、c8、c9可以分别与射频收发器21中的低频端口连接。
当开关241的第一输入端口2411接通c1、c2、c3中的任意一路，开关241的第二输入端口2412接通c4、c5、c6中的任意一路，开关K1接通P2与Q2时，分频器244可以将载波聚合信号分频成高频信号与中频信号。
进一步地，当开关K2接通P3与Q3，开关242接通c7、c8、c9中的任意一路时，分频器244与分频器245可以将载波聚合信号分频成高频信号、中频信号、低频信号。
当开关241的第一输入端口2411断开，开关241的第二输入端口2412接通c1、c2、c3中的任意一路，开关K1接通P2与Q3，开关242接通c7、c8、c9中的任意一路时，分频器245可以将载波聚合信号分频成中频信号与低频信号。
当开关241的第二输入端口2412接通c4、c5、c6中的任意一路，开关K1接通P2与Q3，开关242接通c7、c8、c9中的任意一路时，分频器245可以将载波聚合信号分频成高频信号与低频信号。
例如，子输出端口c2可以与射频收发器21中的中频频段Band3发射端口连接，子输出端口c5可以与射频收发器21中的高频频段Band40发射端口连接，子输出端口c8可以与射频收发器21中的低频频段Band8发射端口连接。
当开关241的第一输入端口2411接通c2，开关241的第二输入端口2412接通c5，开关K1接通P2与Q2时，分频器244可以将载波聚合信号分频成Band3与Band40。
进一步地，当开关K2接通P3与Q3，开关242接通c8时，分频器244与分频器245可以将载波聚合信号分频成Band3、Band40、Band8。
当开关241的第一输入端口2411断开，开关241的第二输入端口2412接通c2，开关K1接通P2与Q3，开关242接通c8时，分频器245可以将载波聚合信号分频成Band3与Band8。
当开关241的第一输入端口2411断开，开关241的第二输入端口2412接通c5，开关K1接通P2与Q3，开关242接通c8时，分频器245可以将载波聚合信号分频成 Band40与Band8。
在一些实施例中，如图17所示，开关组件246包括开关K1、K2。其中，开关K1为单刀单掷开关，K2为单刀双掷开关。
单刀单掷开关K1的输出端和输入端分别与开关组件246的第二输出端口P2和第二输入端口Q2连接；单刀单掷开关K1可选择性连通第二输出端口P2与第二输入端口Q2。
单刀双掷开关K2的固定端与开关组件246的第三输入端口Q3连接，单刀双掷开关K2的选通端分别与开关组件246的第二输出端口P2、第三输出端口P3连接；单刀双掷开关K2可选择性连通第三输入端口Q3与第二输出端口P2或第三输出端口P3。
在一些实施例中，子输出端口c1、c2、c3可以分别与射频收发器21中的中频端口连接，子输出端口c4、c5、c6可以分别与射频收发器21中的高频端口连接，子输出端口c7、c8、c9可以分别与射频收发器21中的低频端口连接。
当开关241的第一输入端口2411接通c1、c2、c3中的任意一路，开关241的第二输入端口2412接通c4、c5、c6中的任意一路，开关K1接通P2与Q2时，分频器244可以将载波聚合信号分频成高频信号与中频信号。
进一步地，当开关K2接通P3与Q3，开关242接通c7、c8、c9中的任意一路时，分频器244与分频器245可以实现高频信号、中频信号、低频信号。
当开关241的第一输入端口2411断开，开关241的第二输入端口2412接通c1、c2、c3中的任意一路，开关K2接通P2与Q3，开关242接通c7、c8、c9中的任意一路时，分频器245可以将载波聚合信号分频成中频信号与低频信号。
当开关241的第一输入端口2411断开，开关241的第二输入端口2412接通c4、c5、c6中的任意一路，开关K2接通P2与Q3，开关242接通c7、c8、c9中的任意一路时，分频器245可以将载波聚合信号分频成高频信号与低频信号。
例如，子输出端口c2可以与射频收发器21中的中频频段Band3发射端口连接，子输出端口c5可以与射频收发器21中的高频频段Band40发射端口连接，子输出端口c8可以与射频收发器21中的低频频段Band8发射端口连接。
当开关241的第一输入端口2411接通c2，开关241的第二输入端口2412接通c5，开关K1接通P2与Q2时，分频器244可以将载波聚合信号分频成Band3与Band40。
进一步地，当开关K2接通P3与Q3，开关242接通c8时，分频器244与分频器245可以将载波聚合信号分频成Band3、Band40、Band8。
当开关241的第一输入端口2411断开，开关241的第二输入端口2412接通c2，开关K2接通P2与Q3，开关242接通c8时，分频器245可以将载波聚合信号分频成Band3与Band8。
当开关241的第一输入端口2411断开，开关241的第二输入端口2412接通c5，开关K2接通P2与Q3，开关242接通c8时，分频器245可以将载波聚合信号分频成 Band40与Band8。
在一些实施例中，第一开关241、第二开关242可以封装形成第一芯片247。
在一些实施例中，如图18所示，开关组件246包括开关K1、K2、K3。其中，开关 K1、K2、K3均为单刀单掷开关。
单刀单掷开关K1的输出端和输入端分别与开关组件246的第二输出端口P2和第二输入端口Q2连接；单刀单掷开关K1可选择性连通第二输出端口P2与第二输入端口Q2。
单刀单掷开关K2的输出端和输入端分别与开关组件246的第二输出端口P2和第三输入端口Q3连接；单刀单掷开关K2可选择性连通第二输出端口P2与第二输入端口Q3。
单刀单掷开关K3的输出端和输入端分别与开关组件246的第三输出端口P3和第三输入端口Q3连接；单刀单掷开关K3可选择性连通第三输出端口P3与第三输入端口Q3。
在一些实施例中，子输出端口c1、c2、c3可以分别与射频收发器21中的中频端口连接，子输出端口c4、c5、c6可以分别与射频收发器21中的高频端口连接，子输出端口c7、c8、c9可以分别与射频收发器21中的低频端口连接。
当开关241的第一输入端口2411接通c1、c2、c3中的任意一路，开关241的第二输入端口2412接通c4、c5、c6中的任意一路，开关K1接通P2与Q2时，分频器244可以将载波聚合信号分频成高频信号与中频信号。
进一步地，当开关K2断开，开关K3接通P3与Q3，开关242接通c7、c8、c9中的任意一路时，分频器244与分频器245可以将载波聚合信号分频成高频信号、中频信号、低频信号。
当开关241的第一输入端口2411断开，开关241的第二输入端口2412接通c1、c2、c3中的任意一路，开关K2接通P2与Q3，开关K3断开，开关242接通c7、c8、c9中的任意一路时，分频器245可以将载波聚合信号分频成中频信号与低频信号。
当开关241的第一输入端口2411断开，开关241的第二输入端口2412接通c4、c5、c6中的任意一路，开关K2接通P2与Q3，开关K3断开，开关242接通c7、c8、c9中的任意一路时，分频器245可以将载波聚合信号分频成高频信号与低频信号。
例如，子输出端口c2可以与射频收发器21中的中频频段Band3发射端口连接，子输出端口c5可以与射频收发器21中的高频频段Band40发射端口连接，子输出端口c8可以与射频收发器21中的低频频段Band8发射端口连接。
当开关241的第一输入端口2411接通c2，开关241的第二输入端口2412接通c5，开关K1接通P2与Q2时，分频器244可以将载波聚合信号分频成Band3与Band40。
进一步地，当开关K2断开，开关K3接通P3与Q3，开关242接通c8时，分频器244与分频器245可以实现Band3、Band40、Band8。
当开关241的第一输入端口2411断开，开关241的第二输入端口2412接通c2，开关K2接通P2与Q3，开关K3断开，开关242接通c8时，分频器245可以将载波聚合信号分频成Band3与Band8。
当开关241的第一输入端口2411断开，开关241的第二输入端口2412接通c5，开关K2接通P2与Q3，开关K3断开，开关242接通c8时，分频器245可以将载波聚合信号分频成 Band40与Band8。
在一些实施例中，第一开关241、第二开关242、以及开关组件246可以封装形成第二芯片248。
在一些实施例中，分频器244与分频器245的器件位置也可以替换成合路器244与合路器245，当天线25为用于发射信号或者接收信号的主集天线时，合路器244与合路器245用于实现多频段信号的载波聚合。
参考图19，图19为射频电路200的结构示意图。其中，射频收发器21包括9个射频发射端口a1、a2、a3、a4、a5、a6、a7、a8、a9，以及9个射频接收端口b1、b2、b3、b4、b5、b6、b7、b8、b9。
其中，a1、a2、a3为中频发射端口，用于发射中频射频信号（例如，Band1、Band3、Band34或Band39等频段的射频信号）。b1、b2、b3为中频接收端口，用于接收中频射频信号。a4、a5、a6为高频发射端口，用于发射高频射频信号（例如，Band7、Band40、Band41等频段的射频信号）。b4、b5、b6为高频接收端口，用于接收高频射频信号。a7、a8、a9为低频发射端口，用于发射低频射频信号（例如，Band8、Band12、Band20或Band26等频段的射频信号）。b7、b8、b9为低频接收端口，用于接收低频射频信号。
需要说明的是，上述实施例仅以射频收发器21的高频端口21H、中频端口21M、低频端口21L分别包括3个射频发射端口和3个射频接收端口为例进行说明。在其他一些实施例中，高频端口21H、中频端口21M、低频端口21L还可以分别包括其他数量的射频发射端口和射频接收端口。只需满足高频端口21H、中频端口21M、低频端口21L各自所包括的射频发射端口和射频接收端口的数量相同并且大于1即可。
功率放大单元22包括9个放大器221、222、223、224、225、226、227、228、229。其中，放大器221、222、223、224、225、226、227、228、229分别与射频收发器21的射频发射端口a1、a2、a3、a4、a5、a6、a7、a8、a9连接。
滤波单元23包括9个双工器231、232、233、234、235、236、237、238、239。其中，双工器231、232、233、234、235、236、237、238、239分别与放大器221、222、223、224、225、226、227、228、229连接。并且，双工器231、232、233、234、235、236、237、238、239分别与射频收发器21的射频接收端口b1、b2、b3、b4、b5、b6、b7、b8、b9连接。
射频电路开关芯片24包括第一开关241、第二开关242、开关组件246以及第一分频器244、第二分频器245。
其中，第一开关241为双刀多掷开关，第二开关242为单刀多掷开关。例如，第一开关241包括3个第一信号类型子输出端口c1、c2、c3，还包括3个第二信号类型子输出端口c4、c5、c6，第一开关241包括第一输入端口2411与第二输入端口2412；第二开关242包括3个第三信号类型子输出端口c7、c8、c9。第一开关241的第一输入端口2411与第二输入端口2412连接到开关组件246。第二开关242的输入端连接到第二分频器245的第二输出端口。开关组件246具有3个输出端口P1、P2、P3以及3个输入端口Q1、Q2、Q3。其中，输出端口P1与开关241的第一输入端口2411连接。输出端口P2与开关241的第二输入端口2411连接。输出端口P3与第一分频器244的输入端连接。输入端口Q1与分频器244的第一输出端口连接。输入端口Q2与分频器244的第二输出端口连接。输入端Q3与第二分频器245的第一输出端连接。
其中，射频电路开关芯片24的子输出端口c1、c2、c3、c4、c5、c6、c7、c8、c9分别与双工器231、232、233、234、235、236、237、238、239连接。
其中，第一分频器244、第二分频器245都为双频分频器。第二分频器245的输入端连接到天线25。
本发明实施例中，射频电路开关芯片24可以控制射频收发器21的高频端口与中频端口接通第一分频器244，以将载波聚合信号分频成高频信号与中频信号；可以控制射频收发器21的高频端口、中频端口接通第一分频器244，同时第一分频器244、射频收发器21的低频端口接通第二分频器245，以将载波聚合信号分频成高频信号、中频信号、低频信号；还可以控制射频收发器21的高频端口与低频端口接通第二分频器245，以将载波聚合信号分频成高频信号与低频信号；可以控制射频收发器21的中频端口与低频端口接通第二分频器245，以将载波聚合信号分频成中频信号与低频信号。射频电路开关芯片24能够对载波聚合信号进行分频，从而可以提高电子设备100对载波聚合信号进行分频的多样性。
继续参考图1和图2。其中，电池104安装在壳体105内部。电池104用于为电子设备100提供电能。
壳体105用于形成电子设备100的外部轮廓。壳体105的材质可以为塑料或金属。壳体105可以一体成型。
参考图20，图20为本发明实施例提供的电子设备100的另一结构示意图。电子设备100包括天线装置10、存储器20、显示单元30、电源40以及处理器50。本领域技术人员可以理解，图20中示出的电子设备100的结构并不构成对电子设备100的限定。电子设备100可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
其中，天线装置10包括上述任一实施例中所描述的射频电路200。天线装置10可以通过无线网络与网络设备（例如，服务器）或其他电子设备（例如，智能手机）通信，完成与网络设备或其他电子设备之间的信息收发。
存储器20可用于存储应用程序和数据。存储器20存储的应用程序中包含有可执行程序代码。应用程序可以组成各种功能模块。处理器50通过运行存储在存储器20的应用程序，从而执行各种功能应用以及数据处理。
显示单元30可用于显示由用户输入到电子设备100的信息或提供给用户的信息以及电子设备100的各种图形用户接口。这些图形用户接口可以由图形、文本、图标、视频和其任意组合来构成。显示单元30可包括显示面板。
电源40用于给电子设备100的各个部件供电。在一些实施例中，电源40可以通过电源管理系统与处理器50逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。
处理器50是电子设备100的控制中心。处理器50利用各种接口和线路连接整个电子设备100的各个部分，通过运行或执行存储在存储器20内的应用程序，以及调用存储在存储器20内的数据，执行电子设备100的各种功能和处理数据，从而对电子设备100进行整体监控。
此外，电子设备100还可以包括摄像头模块、蓝牙模块等，在此不再赘述。
以上对本发明实施例提供的射频电路开关芯片、射频电路、天线装置及电子设备进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明。同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (20)

  1. 一种射频电路开关芯片，其中，包括第一开关、第二开关、第一分频器以及第二分频器，所述第一开关的第一输入端口与第二输入端口用于接收高频信号或者中频信号，所述第二开关用于接收低频信号；
    当所述第一开关的第一输入端口与第二输入端口分别用于接收不同信号，所述第一开关的第一输入端口与第二输入端口选择性接通所述第一分频器，所述第一分频器将接收信号分频成高频信号与中频信号；且当所述第一分频器与所述第二开关选择性接通所述第二分频器，所述第一分频器与所述第二分频器将接收信号分频成高频信号、中频信号、低频信号；
    当所述第一开关的第二输入端口、所述第二开关选择性接通所述第二分频器，所述第二分频器将接收信号分频成中频信号与低频信号、或者高频信号与低频信号。
  2. 根据权利要求1所述的射频电路开关芯片，其中：
    所述第一开关的第一输入端口与所述第一分频器的第一输出端口连接；
    所述第一开关的第二输入端口与所述第一分频器的第二输出端口、所述第二分频器的第一输出端口连接；
    所述第二开关的输入端与所述第二分频器的第二输出端口连接；以及
    所述第一分频器的输入端与所述第二分频器的第一输出端口连接。
  3. 根据权利要求2所述的射频电路开关芯片，其中，所述第一开关、第二开关封装形成第一芯片。
  4. 根据权利要求2所述的射频电路开关芯片，其中，还包括开关组件，所述开关组件分别与所述第一开关的输入端、以及所述第一分频器的输出端和输入端、所述第二分频器的输出端连接。
  5. 根据权利要求4所述的射频电路开关芯片，其中，所述开关组件的第一输出端口、第二输出端口、第三输出端口分别与所述第一开关的第一输入端口、第一开关的第二输入端口、第一分频器的输入端连接，所述开关组件的第一输入端口、第二输入端口、第三输入端口分别与所述第一分频器的第一输出端口、所述第一分频器的第二输出端口、所述第二分频器的第一输出端口连接。
  6. 根据权利要求5所述的射频电路开关芯片，其中：
    所述开关组件的第一输出端口接通所述开关组件的第一输入端口；
    所述开关组件的第二输出端口选择性接通所述开关组件的第二输入端口或第三输入端口；
    所述开关组件的第三输出端口选择性接通所述开关组件的第三输入端口。
  7. 根据权利要求6所述的射频电路开关芯片，其中，所述开关组件包括单刀双掷开关以及单刀单掷开关；
    所述单刀双掷开关的固定端与所述开关组件的第二输出端口连接，所述单刀双掷开关的选通端分别与所述开关组件的第二输入端口和第三输入端口连接；所述单刀单掷开关的输出端和输入端分别与所述开关组件的第三输出端口和第三输入端口连接；或者
    所述单刀单掷开关的输出端和输入端分别与所述开关组件的第二输出端口和第二输入端口连接；所述单刀双掷开关的固定端与所述开关组件的第三输入端口连接，所述单刀双掷开关的选通端分别与所述开关组件的第二输出端口、第三输出端口连接。
  8. 根据权利要求6所述的射频电路开关芯片，其中，所述开关组件包括三个单刀单掷开关，其中：
    第一单刀单掷开关的输出端和输入端分别与所述开关组件的第二输出端口和第二输入端口连接；
    第二单刀单掷开关的输出端和输入端分别与所述开关组件的第二输出端口和第三输入端口连接；
    第三单刀单掷开关的输出端和输入端分别与所述开关组件的第三输出端口和第三输入端口连接。
  9. 根据权利要求4所述的射频电路开关芯片，其中，所述第一开关、第二开关、开关组件封装形成第二芯片。
  10. 根据权利要求1所述的射频电路开关芯片，其中，所述第一分频器、第二分频器均为双频分频器。
  11. 一种射频电路，其中，所述射频电路包括射频收发器、射频电路开关芯片以及天线，所述射频收发器、射频电路开关芯片以及天线依次连接；
    所述射频电路开关芯片包括第一开关、第二开关、第一分频器以及第二分频器，所述第一开关的第一输入端口与第二输入端口用于接收高频信号或者中频信号，所述第二开关用于接收低频信号；
    当所述第一开关的第一输入端口与第二输入端口分别用于接收不同信号，所述第一开关的第一输入端口与第二输入端口选择性接通所述第一分频器，所述第一分频器将接收信号分频成高频信号与中频信号；且当所述第一分频器与所述第二开关选择性接通所述第二分频器，所述第一分频器与所述第二分频器将接收信号分频成高频信号、中频信号、低频信号；
    当所述第一开关的第二输入端口、所述第二开关选择性接通所述第二分频器，所述第二分频器将接收信号分频成中频信号与低频信号、或者高频信号与低频信号。
  12. 根据权利要求11所述的射频电路，其中：
    所述第一开关的第一输入端口与所述第一分频器的第一输出端口连接；
    所述第一开关的第二输入端口与所述第一分频器的第二输出端口、所述第二分频器的第一输出端口连接；
    所述第二开关的输入端与所述第二分频器的第二输出端口连接；以及
    所述第一分频器的输入端与所述第二分频器的第一输出端口连接；
    所述第二分频器的输入端与所述天线连接。
  13. 根据权利要求12所述的射频电路，其中，所述射频收发器包括高频端口、中频端口以及低频端口，所述高频端口、中频端口分别与所述第一开关中对应的输出端口连接，所述低频端口与所述第二开关的输出端连接。
  14. 根据权利要求13所述的射频电路，其中：
    所述中频端口包括N1个不同频段的子发射端口以及N1个不同频段的子接收端口，所述高频端口包括N2个不同频段的子发射端口以及N2个不同频段的子接收端口，所述第一开关的输出端包括N1个第一信号类型子输出端口和N2个第二信号类型子输出端口，所述N1个子发射端口和所述N1个子接收端口分别与所述N1个第一信号类型子输出端口一一连接；所述N2个子发射端口和所述N2个子接收端口分别与所述N2个第二信号类型子输出端口一一连接；
    所述低频端口包括N3个不同频段的子发射端口以及N3个不同频段的子接收端口，所述第二开关的输出端包括N3个子输出端口，所述N3个子发射端口和所述N3个子接收端口分别与所述N3个子输出端口一一连接；
    其中，N1、N2、N3均为大于1的自然数。
  15. 根据权利要求14所述的射频电路，其中，在所述射频收发器与所述射频电路开关芯片之间还连接有功率放大单元，所述功率放大单元包括多个功率放大器，每一个所述子发射端口与每一个所述子输出端口之间连接有所述功率放大器。
  16. 根据权利要求14所述的射频电路，其中，在所述射频收发器与所述射频电路开关芯片之间还连接有低噪声放大单元，每一个所述子接收端口与每一个所述子输出端口之间连接有所述低噪声放大器。
  17. 根据权利要求14所述的射频电路，其中，在所述射频收发器与所述射频电路开关芯片之间还连接有滤波单元，所述滤波单元包括多个双工器或者滤波器，每一个所述子端口与每一个所述子输出端口之间连接有所述双工器或滤波器。
  18. 根据权利要求17所述的射频电路，其中，在所述滤波单元与所述射频电路开关芯片之间还连接有相位平移单元，所述相位平移单元包括多个相位平移器，每一个所述双工器或滤波器与每一个所述子输出端口之间连接有所述相位平移器。
  19. 一种天线装置，其中，所述天线装置包括权利要求11所述的射频电路。
  20. 一种电子设备，其中，所述电子设备包括壳体和电路板，所述电路板安装在所述壳体内部，所述电路板上设置有射频电路，所述射频电路为权利要求11所述的射频电路。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110808757A (zh) * 2019-10-29 2020-02-18 Tcl移动通信科技（宁波）有限公司 射频前端电路及终端设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101794928A (zh) * 2010-01-08 2010-08-04 中兴通讯股份有限公司 分解和合成三频段码分多址信号的方法、分合路器及终端
CN204761429U (zh) * 2015-06-24 2015-11-11 陈林 一种终端设备
CN105471557A (zh) * 2014-08-15 2016-04-06 深圳市中兴微电子技术有限公司 一种载波聚合装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110117862A1 (en) * 2009-11-16 2011-05-19 Oluf Bagger Multiband RF Device
CN102111176B (zh) * 2011-02-25 2014-03-12 华为技术有限公司 射频模块、射频信号收发设备及方法、基站系统
CN204391286U (zh) * 2015-01-28 2015-06-10 中兴通讯股份有限公司 天线和三载波天线

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101794928A (zh) * 2010-01-08 2010-08-04 中兴通讯股份有限公司 分解和合成三频段码分多址信号的方法、分合路器及终端
CN105471557A (zh) * 2014-08-15 2016-04-06 深圳市中兴微电子技术有限公司 一种载波聚合装置
CN204761429U (zh) * 2015-06-24 2015-11-11 陈林 一种终端设备

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110808757A (zh) * 2019-10-29 2020-02-18 Tcl移动通信科技（宁波）有限公司 射频前端电路及终端设备

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