WO2018201967A1

WO2018201967A1 - Storage processing method and apparatus

Info

Publication number: WO2018201967A1
Application number: PCT/CN2018/084651
Authority: WO
Inventors: 信恒超; 曾红义; 夏晶
Original assignee: 华为技术有限公司
Priority date: 2017-05-05
Filing date: 2018-04-26
Publication date: 2018-11-08
Also published as: CN108804020B; CN108804020A

Abstract

Disclosed in an embodiment of the present application are a storage processing method and apparatus, said method comprising: when a memory access request is received, detecting the request type of said memory access request; if the memory access request is detected as being an instruction request, and the backup status of target data which is requested by the memory access request is detected as being exclusive, then executing response processing for the memory access request according to an instruction of a first processing strategy; if the memory access request is detected as being an instruction request, and the backup status of the target data which is requested by the memory access request is detected as being shared, then executing response processing for the memory access request according to an instruction of a second processing strategy; the manner of response processing as instructed by the first processing strategy differs from the manner of response processing as instructed by the second processing strategy. By applying the embodiment of the present application, targeted processing of data may be carried out for data having different backup statuses, thus saving software and hardware resources of a terminal to a certain extent, and increasing storage efficiency.

Description

Storage processing method and device

Technical field

The present application relates to the field of computer technologies, and in particular, to a storage processing method and apparatus.

Background technique

Cache (also known as cache) is located between the processor and memory (Memory), mainly to solve the problem of processor speed and memory read and write speed mismatch. In a multi-core system (Multi-core) system, the Cache structure can cache data in the memory in the Cache, and accelerate the process of acquiring data by the multi-core.

The data cached in the cache can have two backup states, namely, a shared state (Shared state, referred to as S state) and an exclusive state (Exclusive state, referred to as an E state). If the backup status of a data is Shared, it means that the data may be backed up in multiple caches. If the backup status of a data is Exclusive, it means that the data is only backed up in a certain cache. How to store the data in the shared state or the data in the exclusive state in the cache becomes a hot issue of research.

Summary of the invention

The embodiment of the present application provides a storage processing method and device, which can perform targeted processing on data according to different backup states of data.

In a first aspect, an embodiment of the present application provides a storage processing method, including: when receiving a memory access request, first detecting a request type of the memory access request, and detecting target data requested by the memory access request a backup state, the request type of the memory access request includes a data request and an instruction request, and the backup state of the target data includes an exclusive state and a shared state; and then performing corresponding response processing on the memory access request according to the detection result, and if the When the memory access request is an instruction request, and the backup state of the target data is detected as an exclusive state, the response processing is performed on the memory access request according to the indication of the first processing policy; if the memory access request is detected as an instruction request, and Detecting that the backup state of the target data is a shared state, performing a response process on the memory access request according to the indication of the second processing policy; wherein the response processing mode indicated by the first processing policy and the response indicated by the second processing policy Different treatment methods. With the embodiment of the present application, the data can be processed in a targeted manner for different backup states of the data, thereby saving the software and hardware resources of the terminal to a certain extent and improving the storage efficiency.

In a possible embodiment, if the memory access request is detected as a data request, whether the backup state of the target data is an exclusive state or a shared state, the response to the memory access request is performed according to the indication of the third processing policy. Processing, so that different processing strategies are adopted for different types of memory access requests, which can save the software and hardware resources of the terminal to a certain extent and improve storage efficiency.

In a possible embodiment, the response processing manner indicated by the first processing policy may include: first creating a first directory entry corresponding to the target data according to the memory access request, where the first directory entry records the target The cache identifier of the Cache of the data and the backup state of the target data; and then performing response processing on the target data according to the detected type of the memory access request and the backup state of the target data. The response processing includes reading, writing, modifying, and protocol-defined handshake actions.

In a possible embodiment, the response processing manner indicated by the first processing policy may further include: performing broadcast monitoring on the managed Cache according to the identifier of the target data, and receiving a Detect that each Cache returns for the broadcast interception. Listening to the response, the identifier of the target data may be a physical memory address of the target data; and then obtaining a first set according to the received listening response, the first set including one or more cache identifiers of the cache storing the target data, The cache identifier may be an address of the cache; if the cache identifier that is not included in the first directory entry is found in the first set, the target data is reclaimed but the cache identifier is not included in the first directory entry. The Cache's permissions on the target data.

In a possible embodiment, if the memory access request is detected as an instruction request, and the backup state of the target data requested by the memory access request is detected as a shared state, the memory access request is directly obtained according to the detection. The type and the backup status of the target data perform response processing on the target data requested by the memory access request, and the response processing includes a reading and a handshake action specified by the protocol.

In a possible embodiment, the response processing manner indicated by the third processing policy may include: first creating a second directory entry corresponding to the target data according to the memory access request, where the second directory entry records the target The cache identifier of the Cache of the data and the backup state of the target data; and then performing response processing on the target data according to the detected type of the memory access request and the backup state of the target data. The response processing includes reading, writing, modifying, and protocol-defined handshake actions.

In a possible embodiment, before detecting the request type of the memory access request, the method further includes: first receiving a memory access request, where the memory access request is sent by the central processing unit, carrying the request type identifier, and then detecting Whether the third directory entry corresponding to the target data requested by the memory access request is included in the preset directory, where the third directory entry records the cache identifier of the cache storing the target data and the backup status of the target data; If not, determining the miss data, and performing the step of detecting the request type of the memory access request; if the detection result is included, determining the hit data, and obtaining the second set according to the target data, the second set includes a second set Or a cache identifier of the cache that stores the target data; if the cache identifier that is not included in the third directory entry is found in the second set, the third directory entry is updated. The update process includes adding an entry in the third directory entry that corresponds to a cache identifier in the second set that is not included in the third directory entry.

In a second aspect, an embodiment of the present application provides a storage processing apparatus, including: a detection module, an execution module, a receiving module, and an update module, where each module is used to execute the method described in the above aspects.

In a third aspect, an embodiment of the present application provides a storage processing apparatus, including: a processor, a memory, the memory, and the memory are connected by a bus, where the memory stores executable program code, and the processor is used by the processor. The executable program code is invoked to execute the storage processing method according to any one of claims 1 to 8.

In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, wherein the computer readable storage medium stores instructions that, when run on a computer, cause the computer to perform the methods described in the above aspects.

In a fifth aspect, an embodiment of the present application provides a computer program product comprising instructions, which when executed on a computer, cause the computer to perform the method described in the above aspects.

In the embodiment of the present application, when receiving the memory access request, first detecting the request type of the memory access request, and detecting the backup status of the target data requested by the memory access request, and then according to the request type of the memory access request and the target data. Different backup states use different strategies to perform response processing on the memory access request. Therefore, the data can be targeted for different backup states of the data, which saves the software and hardware resources of the terminal to a certain extent and improves storage efficiency.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background art, the drawings to be used in the embodiments of the present application or the background art will be described below.

1 is a schematic diagram of a Cache structure provided by an embodiment of the present application;

2 is a schematic diagram of a hardware structure provided by an embodiment of the present application;

3 is a schematic flowchart of a storage processing method provided by an embodiment of the present application;

4 is a schematic flowchart of another storage processing method provided by an embodiment of the present application;

FIG. 5 is a schematic flowchart of still another storage processing method according to an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a storage processing apparatus according to an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of another storage processing apparatus according to an embodiment of the present application.

detailed description

The embodiments of the present application are described below in conjunction with the accompanying drawings in the embodiments of the present application.

Referring to FIG. 1, FIG. 1 is a schematic diagram of a Cache structure provided by an embodiment of the present application. The Cache structure described in FIG. 1 is a layered Cache structure, including a level 1 cache L1 (Level 1), a level 2 cache L2 (Level 2), and a level 3 cache L3 (Level 3), wherein L1 adopts a high speed and small capacity. Cache, L2 uses a cache with medium speed and large capacity, and L3 uses a low-speed and large-capacity Cache. The Home Agent (HA) is a module that maintains data consistency in the processor. It mainly implements serialized access of the processor to the same address and parallel access to different addresses.

A storage processing method described in the embodiment of the present application implements multi-core cache coherency through hierarchical maintenance. Taking Figure 1 as an example, L2 maintains the consistency between several L1s corresponding to it, L3 maintains the consistency between several L2s corresponding to it, and HA maintains the relationship between several L3s corresponding to it. Consistency, maintain consistency across multiple cores by using a directory-based coherency protocol at all levels. Taking HA as an example, the HA records the backup of the data in the upper Cache (for example, L3) by establishing a directory in the directory cache. The directory records the address of the cache in which the data is stored in the upper Cache, and the data is in the directory. The backup status in the Cache. If the processor needs to operate on a certain data, the Cache address for storing the certain data may be obtained by querying the directory, and the certain data in the Cache is performed according to the backup status of the certain data and the indication of the operation. Corresponding processing.

As the number of processor chip cores increases, the on-chip Cache capacity also increases rapidly. The on-chip cache of each processor chip can be up to tens of megabytes (Mega Byte, MB), and the total capacity of multiple chips can reach even 100 MB. Therefore, the directory capacity of HA, L1, L2, and L3 is a big problem.

In the embodiment of the present application, HA is taken as an example. The HA directory uses an accurate directory, a Sparse structure, and stores the directory in an on-chip static random access memory (SRAM), but in view of the fact that the processor system usually has fewer modifications to the instructions, the embodiment of the present application The described storage processing method uses different processing strategies for the instruction and data type requests respectively, so as to effectively reduce the directory capacity overhead or increase the effective expansion ratio under the same directory capacity. Based on the above, the storage processing method described in the embodiment of the present application is based on the following ideas: 1. The HA receives a memory access request sent by the processor, and the memory access request carries an instruction or a data type indication. 2. According to the type indication of the memory access request, the HA adopts different processing strategies for the memory access request of the instruction and the data type. 3. For the data type access request, whether the state of the target data requested by the memory access request is the E state or the S state, if the HA directory is missed, the new directory entry is newly created and responded to the memory access request. The newly created directory entry is used to record in which cache or caches the target data corresponding to the memory access request is stored. 4. For the fetch request of the instruction type, if the state of the target data requested by the fetch request is S state, the directory is not created after the query directory is missed, and only the response request is processed in response to the fetch request; The status of the requested target data is E state, the new directory is queried after the HA directory is missed, and the listener is broadcasted and responded to in response to the memory access request.

A storage processing method described in the embodiment of the present application can be divided into a request parsing unit, a directory query unit, a directory update/establishment unit, a snooping sending unit, and a request processing unit in hardware implementation, as shown in FIG. 2 . The request parsing unit is configured to parse the request type of the memory access request, determine whether the request type of the memory access request is an instruction type or a data type, and determine whether the backup status of the target data requested by the memory access request is an E state or an S state. Wait. The directory query unit is configured to identify, according to the target data carried by the memory access request, whether the directory corresponding to the target data has been established. The directory update/establishment unit is configured to generate a new directory value according to the request type of the memory access request and in combination with the original directory value. The listening sender unit is used to send a listening request and collect a listening response. The request processing unit is configured to complete the actions specified by the protocol according to the type of request.

In the embodiment of the present application, the execution subject is described by taking the HA as an example. If the execution entities of the caches L1, L2, and L3 implement the storage processing method described in the embodiment of the present application, and so on.

Referring to FIG. 3, FIG. 3 is a storage processing method provided by an embodiment of the present application, and the method may be applied to the Cache structure shown in FIG. 1. The method includes but is not limited to the following steps:

S301. The HA detects a request type of the memory access request when receiving the memory access request.

In the embodiment of the present application, the memory access request received by the HA may be sent by a central processing unit (CPU), where the memory access request carries a request type tag, and carries the target requested by the memory access request. The backup status flag for the data. The request type tag includes an instruction type tag, a data type tag; the backup status tag includes a first backup status flag, and a second backup status flag. The first backup state may be an exclusive state E state, and the second backup state may be a shared state S state. It should be noted that the memory access request may also be issued by other types of processors.

Specifically, when receiving the memory access request, the HA detects the request type of the memory access request based on the request type identifier carried by the memory access request. The request type of the memory access request includes a data type (ie, a data request) and an instruction type (ie, an instruction request), and the data type request is used to request data, including for reading data or writing data, etc.; The request is for a request instruction, including for reading an instruction or writing an instruction.

S302. If the HA detects that the memory access request is an instruction request, and detects that the backup status of the target data requested by the memory access request is an exclusive state, the access is performed according to the indication of the first processing policy. The save request performs response processing.

In the embodiment of the present application, the target data includes a target instruction, and if the HA detects the access request as an instruction request based on the request type tag carried by the memory access request, and based on the backup status of the target data carried by the memory access request The flag detects that the backup state of the target instruction requested by the memory access request is an exclusive state, and performs a response process on the memory access request according to the indication of the first processing policy. The response processing manner indicated by the first processing policy includes: first, the HA establishes a first directory entry corresponding to the target instruction according to the memory access request, where the first directory entry records a cache identifier of the cache storing the target instruction, and the The backup status of the target instruction. The cache identifier may be the address of the Cache that stores the target instruction, or may be the sequence number of the Cache. Secondly, the HA broadcasts the Cache of the managed Cache according to the identifier of the target instruction, and receives the Cache response of the Cache for the broadcast interception. The identifier of the target instruction may be a physical memory address of the target instruction. Then, the HA obtains a first set according to the received listening response, and the first set includes one or more cache identifiers of the cache storing the target instruction, and the cache identifier may be an address of the cache. Then, the HA queries the first directory entry according to the cache identifier in the first set. If the cache identifier that is not included in the first directory entry is found in the first set, the target instruction but the cache is reclaimed and stored. The Cache that is not included in the first directory entry identifies the authority of the target instruction, that is, invalidates the target instruction. Finally, the HA performs a response process on the target instruction according to an instruction of the instruction request and an operation permitted by the target instruction of the exclusive state specified by the protocol, the response processing including reading, writing, modifying, and protocol-defined actions (eg, handshake Action) and so on. Taking the backup state as the E state as an example, for an instruction whose backup state is the E state, operations specified by reading, writing, modifying, and other protocols are allowed.

S303. If the HA detects that the memory access request is an instruction request, and detects that the backup state of the target data requested by the memory access request is a shared state, the memory is accessed according to the indication of the second processing policy. Request to perform response processing.

In the embodiment of the present application, the response processing manner indicated by the first processing policy is different from the response processing manner indicated by the second processing policy, and the target data includes a target instruction.

Specifically, if the HA detects that the memory access request is an instruction request based on the request type flag carried by the memory access request, and the backup status flag of the target data carried based on the memory access request detects the requested by the memory access request The backup state of the target instruction is a shared state, and the response processing is performed on the memory access request according to the indication of the second processing policy. The response processing manner indicated by the second processing policy includes: the HA performs a response processing on the target instruction according to an instruction of the instruction request and an operation permitted by the target instruction of the sharing state specified by the protocol, where the response processing includes reading and protocol-specified Handshake action, etc. Taking the backup state as the S state as an example, for an instruction whose backup state is the S state, other operations specified by the protocol and the protocol are allowed, but other operations specified by the protocol such as writing and modification are not allowed.

In some feasible implementation manners, if the HA detects that the memory access request is a data request, whether the backup status of the target data requested by the memory access request is an exclusive state or a shared state, according to the indication of the third processing policy. A response process is performed on the memory access request. The response processing manner indicated by the third processing policy may be the same as the response processing manner indicated by the first processing policy, or may be different from the response processing manner indicated by the first processing policy. The response processing manner indicated by the third processing policy may include: first, the HA creates a second directory entry corresponding to the target data according to the memory access request, where the second directory entry includes a cache identifier of the cache that stores the target data, and The backup status of the target data; then the HA performs response processing on the target data according to an indication of the data request and an operation permitted by the backup status of the target data specified by the protocol, the response processing including reading, writing, modifying, and protocol provisioning The action and so on. For data whose backup status is E state, it is allowed to be read, written, modified, and the actions specified by other protocols; for data whose backup state is S state, it is allowed to read and other operations specified by the protocol, but not Other operations specified by the protocol such as writing, modification, etc. are allowed.

In the embodiment of the present application, when receiving the access request, the HA first detects the request type of the memory access request, and detects the backup status of the target data requested by the memory access request, and then according to the request type and target of the memory access request. The different backup states of the data use different strategies to perform response processing on the memory access request. Therefore, the data can be targeted for different backup states of the data, which saves the software and hardware resources of the terminal to a certain extent and improves storage efficiency.

Referring to FIG. 4, FIG. 4 is another storage processing method provided by an embodiment of the present application, where the method includes but is not limited to the following steps:

S401. The HA receives the memory access request.

In the embodiment of the present application, the memory access request received by the HA may be sent by the central processing unit, and the memory access request carries a request type tag, and the request type tag includes an instruction type tag and a data type tag. It should be noted that the memory access request may also be issued by other types of processors. The request type of the memory access request includes a data type, that is, a data request, an instruction type, that is, an instruction request, and a data type request is used for requesting data, including for reading data or writing data, etc.; The request instruction includes a read instruction or a write instruction.

S402. Detect whether the memory access request is an instruction request. If not, perform step S403 and step S404; if yes, perform step S405 and subsequent steps.

Specifically, after receiving the access request, the HA detects the request type of the memory access request based on the request type identifier carried by the memory access request, and if the memory access request is detected as a data request, step S403 and step S404 are performed. If it is detected that the memory access request is an instruction request, step S405 and subsequent steps are performed.

S403. The HA creates a second directory entry corresponding to the target data requested by the memory access request according to the memory access request.

In the embodiment of the present application, if the HA detects that the memory access request is a data request, the backup state of the target data requested by the memory access request is an exclusive state or a shared state, and the new access and the access are performed according to the memory access request. The second directory entry corresponding to the target data requested by the request is stored. The second directory includes a cache identifier of the cache that stores the target data and a backup state of the target data. The cache identifier may be an address of a cache that stores the target data, or may be a sequence number of the cache.

Specifically, the HA searches for the Cache that stores the target data in the Cache managed by the HA according to the identifier of the target data carried in the memory access request, and if yes, returns a cache identifier of the Cache that stores the target data and the cache identifier in the Cache. The backup state of the target data; if not, the data corresponding to the target data identifier in the memory is loaded into a cache managed by the HA, and the cache identifier of a certain cache storing the target data is returned, and the target data is The backup status in this Cache. Then, a second directory entry corresponding to the target data is created in the directory of the HA, where the second directory entry includes a cache identifier of the cache that stores the target data and a backup state of the target data in the cache. It should be noted that the HA can perform a broadcast interception on the Cache managed by the HA to query whether the Cache managed by the Cache has a Cache for storing the target data. The identifier of the target data may be a physical memory address of the target data.

S404. The HA performs a response process on the target data requested by the memory access request.

Specifically, the HA performs response processing on the target data according to an instruction of the data request and an operation permitted by the backup state of the target data specified by the protocol, and the response processing includes reading, writing, modifying, and an action specified by the protocol. For data whose backup status is E state, it is allowed to be read, written, modified, and the actions specified by other protocols; for data whose backup state is S state, it is allowed to read and other operations specified by the protocol, but not Other operations specified by the protocol such as writing, modification, etc. are allowed.

S405. The HA detects whether the backup status of the target data requested by the memory access request is an exclusive state. If not, step S406 is performed; if yes, steps S407 to S409 are performed.

In the embodiment of the present application, the memory access request further carries a backup status flag of the target data requested by the memory access request. The backup status flag includes a first backup status flag and a second backup status flag. The first backup state may be an exclusive state E state, and the second backup state may be a shared state S state. The target data includes target instructions.

Specifically, the HA detects the backup status of the target instruction requested by the memory access request based on the backup status flag of the target data carried by the memory access request. If the HA detects that the backup status of the target instruction is the shared status, the step is performed. S405. If the HA detects that the backup state of the target command is the exclusive state, step S407 to step S409 are performed.

S406. The HA performs a response process on the target data requested by the memory access request.

Specifically, if the HA detects that the backup state of the target instruction requested by the memory access request is a shared state, performing response processing on the target instruction according to an instruction of the instruction request and an operation permitted by the target instruction of the shared state specified by the protocol. The response processing includes reading and a handshake action specified by the protocol. For an instruction whose backup state is S state, it is allowed to read and other operations specified by the protocol, but other operations specified by the protocol such as writing, modification, etc. are not allowed.

S407. The HA newly creates a first directory entry corresponding to the target data according to the memory access request.

In the embodiment of the present application, if the HA detects that the backup status of the target instruction requested by the memory access request is an exclusive state based on the backup status flag of the target data carried in the memory access request, the HA establishes the The first directory entry corresponding to the target instruction, the specific process of this step may refer to the description in step S403, and details are not described herein again. The first directory entry records the cache identifier of the cache storing the target instruction and the backup of the target instruction. status.

S408: The HA performs broadcast interception on the managed Cache, and performs recovery processing on the target data according to the received listening response returned by each Cache for the broadcast interception.

Specifically, first, the HA performs broadcast interception on the Cache managed by the HA according to the identifier of the target instruction, and receives a listening response of each Cache for the broadcast interception. Then, the HA obtains a first set according to the received listening response, and the first set includes one or more cache identifiers of the Cache storing the target instruction. Then, the HA queries the first directory entry according to the cache identifier in the first set. If the cache identifier that is not included in the first directory entry is found in the first set, the target instruction but the cache is reclaimed and stored. The Cache that is not included in the first directory entry identifies the authority of the target instruction, that is, invalidates the target instruction. Take the backup state as the exclusive state E state as an example. For data or instructions whose backup state is the E state, such data or instructions can only be backed up to a certain cache. Therefore, the purpose of broadcast interception is to query whether there is still The other Caches back up the E-state data or instructions, and if so, the other Caches are reclaimed for the E-state data or instructions, that is, the E-state data or instructions in other Caches are invalidated.

S409. The HA performs a response process on the target data requested by the memory access request.

Specifically, the HA performs response processing on the target instruction according to an instruction of the instruction request and an operation permitted by the target instruction of the exclusive state specified by the protocol, and the response processing includes reading, writing, modifying, and an action specified by the protocol. For instructions whose backup state is E, the actions specified by the read, write, modify, and other protocols are allowed.

In the embodiment of the present application, in some feasible implementation manners, when receiving the access request, the HA may first detect the backup status of the target data requested by the memory access request, and if the backup status of the target data is detected as independent If the state of the target data is detected as a shared state, detecting whether the memory access request is an instruction request, and if yes, executing a response to the target instruction requested by the memory access request Processing, if no, executing steps S403 and S404.

Referring to FIG. 5, FIG. 5 is still another storage processing method provided by an embodiment of the present application, where the method includes but is not limited to the following steps:

S501. The HA receives the memory access request.

In the embodiment of the present application, the memory access request received by the HA may be sent by the central processing unit, and the memory access request carries a request type tag and a backup status flag carrying the target data requested by the memory access request. The request type tag includes an instruction type tag, a data type tag; the backup status tag includes a first backup status flag, and a second backup status flag. The first backup state may be an exclusive state E state, and the second backup state may be a shared state S state. It should be noted that the memory access request may also be issued by other types of processors.

S502, the HA detects whether the third directory entry corresponding to the target data requested by the memory access request is included in the preset directory, and if the detection result is included, determining the hit data, and performing step S503; If not, the miss data is determined, and step S504 and its subsequent steps are performed.

In the embodiment of the present application, the target data may be data or an instruction. Specifically, after receiving the access request, the HA queries, according to the target data identifier carried in the memory access request, whether the directory entry existing in the HA preset directory includes a third directory corresponding to the target data requested by the memory access request. If yes, step S503 is performed; if no, step S504 and subsequent steps are performed. The identifier of the target data may be a physical memory address of the target data, and the third directory entry records a cache identifier of the cache storing the target data and a backup status of the target data, where the cache identifier may be the target data. The address of the Cache can also be the sequence number of the Cache.

S503. The HA updates the third directory entry according to the memory access request and performs response processing in response to the memory access request.

Specifically, the HA first queries the Cache managed by the HA according to the identifier of the target data, and obtains a second set according to the cached identifier of the Cache that stores the target data, and the second set includes one or more of the target data. Cache identifier of the Cache; then the HA queries the third directory entry according to the cache identifier in the second set, and if the second set contains the cache identifier not included in the third directory entry, the first The three directory entries are updated. The update process includes adding an entry in the third directory entry that corresponds to a cache identifier in the second set that is not included in the third directory entry. Finally, after updating the third directory entry, the HA responds to the target data requested by the memory access request according to the type of the memory access request and the operation of the backup state of the target data specified by the protocol, and the response is processed. Processing includes reading, writing, modifying, and protocol-defined handshake actions.

S504. The HA detects whether the memory access request is an instruction request. If not, step S505 is performed; if yes, step S506 and subsequent steps are performed.

Specifically, the HA detects the request type of the memory access request based on the request type tag carried by the memory access request, and if it is detected that the memory access request is a data request, step S505 is performed; if the memory access request is detected as an instruction request Then, step S506 and subsequent steps are performed.

S505. The HA performs a response process on the memory access request according to the indication of the third processing policy.

In the embodiment of the present application, if the HA detects that the memory access request is a data request, the backup state of the target data requested by the memory access request is an exclusive state or a shared state, and the new The second directory entry corresponding to the target data requested by the fetch request. The second directory includes a cache identifier of the cache storing the target data and a backup status of the target data.

Specifically, the HA searches for the Cache that stores the target data in the Cache managed by the HA according to the identifier of the target data carried in the memory access request, and if yes, returns a cache identifier of the Cache that stores the target data and the cache identifier in the Cache. The backup state of the target data; if not, the data corresponding to the target data identifier in the memory is loaded into a cache managed by the HA, and the cache identifier of a certain cache storing the target data is returned, and the target data is The backup status in this Cache. Then, a second directory entry corresponding to the target data is created in the directory of the HA, where the second directory entry includes a cache identifier of the cache that stores the target data and a backup state of the target data in the cache. It should be noted that the HA can perform a broadcast interception on the Cache managed by the HA to query whether the Cache managed by the Cache has a Cache for storing the target data.

Then, the HA performs response processing on the target data according to an instruction of the data request and an operation permitted by the backup state of the target data specified by the protocol, and the response processing includes reading, writing, modifying, and an action specified by the protocol. For data whose backup status is E state, it is allowed to be read, written, modified, and the actions specified by other protocols; for data whose backup state is S state, it is allowed to read and other operations specified by the protocol, but not Other operations specified by the protocol such as writing, modification, etc. are allowed.

S506. The HA detects whether the backup status of the target data requested by the memory access request is an exclusive state. If not, step S507 is performed; if yes, step S508 is performed.

Specifically, the HA detects a backup status of the target instruction requested by the memory access request based on a backup status flag of the target data requested by the memory access request carried by the memory access request. If the HA detects that the backup state of the target command is the shared state, step S507 is performed; if the HA detects that the backup state of the target data is the exclusive backup state, step S508 is performed.

S507. The HA performs a response process on the memory access request according to the indication of the second processing policy.

S508. The HA performs a response process on the memory access request according to the indication of the first processing policy.

In the embodiment of the present application, the response processing manner indicated by the first processing policy is different from the response processing manner indicated by the second processing policy. The response processing manner indicated by the first processing policy includes: first, the HA establishes, according to the memory access request, a first directory entry corresponding to the target instruction requested by the memory access request, where the first directory entry records the target instruction The cache ID of the Cache and the backup status of the target instruction. Secondly, the HA broadcasts the Cache of the managed Cache according to the identifier of the target instruction, and receives the Cache response of the Cache for the broadcast interception. Then, the HA obtains a first set according to the received listening response, and the first set includes one or more cache identifiers of the Cache storing the target instruction. Then, the HA queries the first directory entry according to the cache identifier in the first set. If the cache identifier that is not included in the first directory entry is found in the first set, the target instruction but the cache is reclaimed and stored. The Cache that is not included in the first directory entry identifies the authority of the target instruction, that is, invalidates the target instruction. Finally, the HA performs response processing on the target instruction according to an instruction of the instruction request and an operation permitted by the target instruction of the first backup state specified by the protocol, and the response processing includes reading, writing, modifying, and an action specified by the protocol. It should be noted that, the manner of the response processing indicated by the first processing policy may refer to the description of step S407 to step S409 in the foregoing embodiment, and details are not described herein again.

In the embodiment of the present application, in some feasible implementation manners, when receiving the access request, the HA first detects whether the preset directory includes a third directory entry corresponding to the target data requested by the memory access request, and if so, And updating the third directory entry according to the memory access request and performing a response process in response to the memory access request; if not, executing step S506, detecting whether the backup state of the target data requested by the memory access request is an exclusive state; And performing a response process on the memory access request according to the indication of the first processing policy; if not, executing step S504, detecting whether the memory access request is an instruction request, and if yes, requesting the memory access according to the indication of the second processing policy Executing a response process; if not, performing a response process on the memory access request according to an indication of the third processing policy.

In the embodiment of the present application, when receiving the access request, the HA first detects the request type of the memory access request, and detects the backup status of the target data requested by the memory access request, and then according to different request types of the memory access request and The different backup states of the target data use different strategies to perform response processing on the memory access request. Therefore, the data can be targeted for different backup states of the data, which saves the software and hardware resources of the terminal to a certain extent and improves storage efficiency.

The above describes the method of the embodiment of the present application in detail, and the apparatus of the embodiment of the present application is provided below.

Referring to FIG. 6, FIG. 6 is a schematic structural diagram of a storage processing apparatus according to an embodiment of the present application. The storage processing device shown in FIG. 6 may include a detection module 601, an execution module 602, a receiving module 603, and an update module 604. The detailed description of each module is as follows.

The detecting module 601 is configured to detect a request type of the memory access request when receiving the memory access request.

The executing module 602 is configured to: if the detecting module 601 detects that the memory access request is an instruction request, and detects that the backup state of the target data requested by the memory access request is an exclusive state, according to the first processing policy The indication performs a response process on the memory access request.

The execution module 602 is further configured to: if the detecting module 601 detects that the memory access request is an instruction request, and detects that the backup state of the target data requested by the memory access request is a shared state, according to the second An indication of the processing policy performs a response process on the fetch request.

The response processing manner indicated by the first processing policy is different from the response processing manner indicated by the second processing policy.

In some possible implementations, the executing module 602 is further configured to: if the detecting module 601 detects that the memory access request is a data request, perform a response to the memory access request according to an indication of a third processing policy. deal with.

In some possible implementations, the executing module 602 includes:

The first new unit 6021 is configured to create a first directory entry corresponding to the target data according to the memory access request, where the first directory entry records a cache identifier of the cache storing the target data, and the target data. Backup status.

The first processing unit 6022 is configured to perform response processing on the target data requested by the memory access request according to the type of the memory access request and the backup status of the target data.

In some possible implementations, the executing module 602 further includes:

The listening unit 6023 is configured to perform broadcast interception on the managed Cache according to the target data, and receive a listening response returned by each Cache for the broadcast interception.

The first obtaining unit 6024 is configured to obtain a first set according to the listening response, where the first set includes one or more cache identifiers of the Cache storing the target data.

The first processing unit 6022 is further configured to: if the cache identifier that is not included in the first directory entry is queried in the first set, perform the collection process on the target data.

In some possible implementations, the executing module 602 further includes:

The second processing unit 6025 is configured to perform response processing on the target data requested by the memory access request according to the type of the memory access request and the backup status of the target data.

In some possible implementations, the executing module 602 further includes:

a second new unit 6026, configured to create a second directory entry corresponding to the target data according to the memory access request, where the second directory entry records a cache identifier of the cache cache that stores the target data, and the target The backup status of the data;

The third processing unit 6027 is configured to perform response processing on the target data requested by the memory access request according to the type of the memory access request and the backup status of the target data.

In some possible implementations, the apparatus further includes:

The receiving module 603 is configured to receive a memory access request.

The detecting module 602 is further configured to detect whether the third directory entry corresponding to the target data requested by the memory access request is included in the preset directory.

The detecting module 602 is further configured to: if the detection result is not included, determine the miss data, and perform the step of detecting the request type of the memory access request.

In some possible implementations, the detecting module 602 is further configured to: if the detection result is a third directory entry corresponding to the target data requested by the memory access request, determine hit data, the device further includes :

The update module 604 is configured to update the third directory entry according to the memory access request.

The update module 604 includes:

The second obtaining unit 6041 is configured to obtain a second set according to the target data, where the second set includes one or more cache identifiers of the Cache storing the target data.

The updating unit 6042 is configured to perform an update process on the third directory item if the cache identifier that is not included in the third directory entry is queried in the second set.

It should be noted that the functions of the functional modules and the units of the storage processing apparatus in the embodiments of the present application may be specifically implemented according to the method in the foregoing method embodiments. For the specific implementation process, reference may be made to the related description of the foregoing method embodiments. Let me repeat.

In the embodiment of the present application, when receiving the access request, the receiving module 603 triggers the detection module 601 to detect the request type of the memory access request, and detects the backup status of the target data requested by the memory access request, and then triggers the execution module 602. According to different request types of the memory access request and different backup states of the target data, different policies are used to perform response processing on the memory access request. Therefore, the data can be targeted for different backup states of the data, which saves the software and hardware resources of the terminal to a certain extent and improves storage efficiency.

Referring to FIG. 7, FIG. 7 is a schematic structural diagram of a storage processing apparatus according to an embodiment of the present disclosure. The storage processing apparatus described in the embodiment of the present application includes: a processor 701 and a memory 702. The processor 701 and the memory 702 can be connected by using a bus or other manners. The embodiment of the present application is exemplified by a bus connection.

The processor 701 (for example, a central processing unit (CPU)) is a computing core and a control core of the storage processing device. The memory 702 (Memory) is a memory device of the storage processing device for storing programs and data. It can be understood that the memory 702 herein may be a high speed RAM memory, or may be a non-volatile memory, such as at least one disk memory; optionally, at least one of the processors 701 may be located away from the foregoing processor 701. Storage device. The memory 702 provides a storage space, which stores an operating system and executable program code of the storage processing device, and may include, but is not limited to, a Windows system (an operating system), a Linux (an operating system) system, and the like. The application is not limited.

In the embodiment of the present application, the processor 701 performs the following operations by running the executable program code in the memory 702:

The processor 701 is configured to detect a request type of the memory access request when receiving the memory access request.

The processor 701 is further configured to: if detecting that the memory access request is an instruction request, and detecting that the backup state of the target data requested by the memory access request is an exclusive state, according to the indication of the first processing policy A response process is performed on the memory access request.

The processor 701 is further configured to: if detecting that the memory access request is an instruction request, and detecting that the backup state of the target data requested by the memory access request is a shared state, according to the indication of the second processing policy The memory access request performs a response process.

The first processing policy and the second processing policy are different.

In some possible implementations, the processor 701 is further configured to:

If it is detected that the memory access request is a data request, the response processing is performed on the memory access request according to the indication of the third processing policy.

In some possible implementations, the processor 701 is further configured to:

The first directory entry corresponding to the target data is newly created according to the access request, and the first directory entry records a cache identifier of the cache that stores the target data, and a backup state of the target data.

And performing response processing on the target data requested by the memory access request according to the type of the memory access request and the backup status of the target data.

In some possible implementations, the processor 701 is further configured to:

Performing broadcast listening on the managed Cache according to the target data, and receiving a listening response returned by each Cache for the broadcast interception.

Obtaining a first set according to the listening response, where the first set includes one or more cache identifiers of a cache storing the target data.

If the cache identifier that is not included in the first directory entry is found in the first set, the target data is recycled.

In some possible implementations, the processor 701 is further configured to:

And creating, by the fetching request, a second directory entry corresponding to the target data, where the second directory entry records a cache identifier of the cache cache that stores the target data, and a backup state of the target data; Determining the type of the memory request and the backup status of the target data, and performing response processing on the target data requested by the memory access request.

In some possible implementations, the processor 701 is further configured to:

Receiving a memory access request, and detecting whether a third directory entry corresponding to the target data requested by the memory access request is included in the preset directory; if the detection result is not included, determining the miss data, performing the detecting The step of fetching the request type of the request.

In some possible implementations, the processor 701 is further configured to:

If the detection result is a third directory entry corresponding to the target data requested by the memory access request, the hit data is determined, and the third directory entry is updated according to the memory access request.

In some possible implementations, the processor 701 is specifically configured to:

Determining, according to the target data, a second set, where the second set includes one or more cache identifiers of the cache storing the target data; if the second set of entries in the second set is not included in the third directory entry In the cache identifier, the third directory entry is updated.

In a specific implementation, the processor 701 and the memory 702 described in the embodiment of the present application may be implemented in the process of the storage processing method provided in FIG. 3, FIG. 4 or FIG. 5 of the embodiment of the present application, and may also be implemented. The implementations described in the storage processing apparatus provided in FIG. 6 of the embodiment of the present application are not described herein.

In the embodiment of the present application, when receiving the memory access request, the processor 701 first detects the request type of the memory access request, and detects the backup status of the target data requested by the memory access request, and then according to the request type of the memory access request. And different backup states of the target data use different strategies to perform response processing on the memory access request. Therefore, the data can be targeted for different backup states of the data, which saves the software and hardware resources of the terminal to a certain extent and improves storage efficiency.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present application are generated in whole or in part. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be from a website site, computer, server or data center Transmission to another website site, computer, server or data center by wire (eg coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (eg infrared, microwave, etc.). The computer readable storage medium can be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that includes one or more available media. The usable medium may be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a Solid State Disk (SSD)) or the like.

In summary, the above embodiments are only used to explain the technical solutions of the present application, and are not limited thereto; although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still The technical solutions described in the embodiments are modified, or equivalent to some of the technical features are included; and the modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

A storage processing method, the method comprising:

When receiving the memory access request, detecting a request type of the memory access request;

If it is detected that the memory access request is an instruction request, and detecting that the backup status of the target data requested by the memory access request is an exclusive state, performing response processing on the memory access request according to the indication of the first processing policy ;

If it is detected that the memory access request is an instruction request, and detecting that the backup status of the target data requested by the memory access request is a shared state, performing a response process on the memory access request according to the indication of the second processing policy;

The response processing manner indicated by the first processing policy is different from the response processing manner indicated by the second processing policy.
The method of claim 1 further comprising:

If the memory access request is detected as a data request, the response processing is performed on the memory access request according to the indication of the third processing policy.
The method according to claim 1, wherein the performing the response processing on the memory access request according to the indication of the first processing policy comprises:

And creating, by the fetching request, a first directory entry corresponding to the target data, where the first directory entry records a cache identifier of the cache cache that stores the target data, and a backup state of the target data;

And performing response processing on the target data requested by the memory access request according to the type of the memory access request and the backup status of the target data.
The method of claim 3, wherein the method further comprises:

Performing broadcast listening on the managed Cache according to the target data, and receiving a listening response returned by each Cache for the broadcast interception;

Obtaining a first set according to the listening response, where the first set includes one or more cache identifiers of a cache that stores the target data;

If the cache identifier that is not included in the first directory entry is found in the first set, the target data is recycled.
The method according to claim 1, wherein the performing the response processing on the memory access request according to the indication of the second processing policy comprises:

And performing response processing on the target data requested by the memory access request according to the type of the memory access request and the backup status of the target data.
The method according to claim 2, wherein the performing the response processing on the memory access request according to the indication of the third processing policy comprises:

And creating, by the fetching request, a second directory entry corresponding to the target data, where the second directory entry records a cache identifier of the cache cache that stores the target data, and a backup state of the target data;

And performing response processing on the target data requested by the memory access request according to the type of the memory access request and the backup status of the target data.
The method according to any one of claims 1 to 6, wherein before the detecting the request type of the memory access request, the method further comprises:

Receiving a memory access request;

Detecting whether a third directory entry corresponding to the target data requested by the memory access request is included in the preset directory;

If the detection result is not included, the miss data is determined, and the step of detecting the request type of the memory access request is performed.
The method of claim 7, wherein the method further comprises:

If the detection result is a third directory entry corresponding to the target data requested by the memory access request, determining hit data, and updating the third directory entry according to the memory access request;

Updating the third directory entry according to the memory access request includes:

Obtaining a second set according to the target data, where the second set includes one or more cache identifiers of the cache storing the target data;

If the cache identifier that is not included in the third directory entry is found in the second set, the third directory entry is updated.
A storage processing device, characterized in that the device comprises:

a detecting module, configured to detect a request type of the memory access request when receiving the memory access request;

An execution module, configured to: if the detection module detects that the memory access request is an instruction request, and detects that the backup status of the target data requested by the memory access request is an exclusive state, according to the indication of the first processing policy Performing response processing on the memory access request;

The execution module is further configured to: if the detecting module detects that the memory access request is an instruction request, and detects that the backup state of the target data requested by the memory access request is a shared state, according to the second processing policy Instructing to perform response processing on the memory access request;

The response processing manner indicated by the first processing policy is different from the response processing manner indicated by the second processing policy.
The device of claim 9 wherein:

The execution module is further configured to: if the detecting module detects that the memory access request is a data request, perform a response process on the memory access request according to the indication of the third processing policy.
The apparatus according to claim 9, wherein the execution module comprises:

a first new unit, configured to create a first directory entry corresponding to the target data according to the memory access request, where the first directory entry records a cache identifier of the cache storing the target data, and the target data Backup status

And a first processing unit, configured to perform a response process on the target data requested by the memory access request according to the type of the memory access request and the backup status of the target data.
The apparatus according to claim 11, wherein the execution module further comprises:

a listening unit, configured to perform broadcast listening on the managed Cache according to the target data, and receive a listening response returned by each Cache for the broadcast interception;

a first acquiring unit, configured to obtain a first set according to the listening response, where the first set includes one or more cache identifiers of a cache that stores the target data;

The first processing unit is further configured to: when querying, in the first set, a cache identifier that is not included in the first directory entry, perform processing on the target data.
The apparatus according to claim 9, wherein the execution module further comprises:

And a second processing unit, configured to perform a response process on the target data requested by the memory access request according to the type of the memory access request and the backup status of the target data.
The apparatus according to claim 10, wherein the execution module further comprises:

a second new unit, configured to create a second directory entry corresponding to the target data according to the memory access request, where the second directory entry records a cache identifier of the cache cache that stores the target data, and the target data Backup status

And a third processing unit, configured to perform a response process on the target data requested by the memory access request according to the type of the memory access request and the backup status of the target data.
The device according to any one of claims 9 to 14, wherein the device further comprises:

a receiving module, configured to receive a memory access request;

The detecting module is further configured to detect whether a third directory entry corresponding to the target data requested by the memory access request is included in the preset directory.

The detecting module is further configured to: if the detection result is not included, determine the miss data, and perform the step of detecting the request type of the memory access request.
The device of claim 15 wherein:

The detecting module is further configured to determine hit data if the detection result is a third directory entry corresponding to the target data requested by the memory access request;

The device also includes:

An update module, configured to update the third directory entry according to the memory access request;

The update module specifically includes:

a second acquiring unit, configured to obtain a second set according to the target data, where the second set includes one or more cache identifiers of the Cache storing the target data;

And an updating unit, configured to perform an update process on the third directory item if the cached identifier that is not included in the third directory entry is queried in the second set.
A storage processing device, comprising: a processor, a memory, the processor, the memory being connected by a bus, the memory storing executable program code, the processor for calling the executable program The code executes the storage processing method according to any one of claims 1 to 8.