WO2018201377A1 - Générateur de code détecteur d'erreurs et de code correcteur d'erreurs unifié - Google Patents

Générateur de code détecteur d'erreurs et de code correcteur d'erreurs unifié Download PDF

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Publication number
WO2018201377A1
WO2018201377A1 PCT/CN2017/083003 CN2017083003W WO2018201377A1 WO 2018201377 A1 WO2018201377 A1 WO 2018201377A1 CN 2017083003 W CN2017083003 W CN 2017083003W WO 2018201377 A1 WO2018201377 A1 WO 2018201377A1
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Prior art keywords
bits
addon
information bits
information
generating means
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PCT/CN2017/083003
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English (en)
Inventor
Keeth Saliya JAYASINGHE
Yu Chen
Dongyang DU
Jie Chen
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Nokia Technologies Oy
Alcatel-Lucent Shanghai Bell Co., Ltd.
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Application filed by Nokia Technologies Oy, Alcatel-Lucent Shanghai Bell Co., Ltd. filed Critical Nokia Technologies Oy
Priority to CN201780090309.6A priority Critical patent/CN110603759B/zh
Priority to PCT/CN2017/083003 priority patent/WO2018201377A1/fr
Publication of WO2018201377A1 publication Critical patent/WO2018201377A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Definitions

  • the present invention relates to an apparatus, a method, and a computer program product related to error detection.
  • Polar code proposed in [1] is decided to be used for 5G eMBB control channel and maybe also for mMTC, because it has a few advantages compared to the other candidate coding schemes, e.g. low complexity, capacity achieving.
  • polar codes are constructed based on channel polarization principle. It refers to the fact that a set of identical channels (i.e., many uses of the same channel over time) can be converted into a set of channels that consists only of almost perfect channels or almost useless channels. This conversion can be done in a simple recursive manner. E.g., two identical copies of a binary-input channel P: X 1 ⁇ Y 1 are converted to two new channels and Since is a 1--1 transform, it follows that Some thought also shows that I (P 1 ) ⁇ I (P) ⁇ I (P 2 ) , i.e. P 1 is a worse channel than P, and P 2 is better. In that sense, the channel is polarized.
  • U i 0
  • a key aspect is to identify the locations of the data bits and frozen bits.
  • the inventors proposed a CRC distribution scheme for Polar code where the CRC bits are distributed inside the information bits to assist the Polar decoding.
  • the scheme was well received and it is considered to be a promising solution for Polar code for eMBB control channel. And it was listed as one of the alternatives in the meeting agreements.
  • ⁇ J CRC bits are provided (which may be used for error detection and may also be used to assist decoding and potentially for early termination)
  • - J may be different in DL and UL
  • - J may depend on the payload size in the UL (0 not precluded)
  • J’assistance bits are provided in reliable locations (which may be used to assist decoding and potentially for early termination)
  • n FAR 16 (at least for eMBB-related DCI)
  • n FAR 8 or 16 (at least for eMBB-related UCI; note that this applies for UL cases with CRC)
  • the J’ (and J”if any) bits may be CRC and/or PC and/or hash bits (downscope if possible)
  • J + J’+ J bits may be supported for error detection and error correction.
  • the J’+J” J * bits may also be named assistance bits, which describes that the bits may be used to improve the decoding performance, including decoding paths pruning, early termination.
  • assistance bits which describes that the bits may be used to improve the decoding performance, including decoding paths pruning, early termination.
  • Fig. 1 One straightforward implementation example is shown in Fig. 1.
  • the information bits are processed by a first module to generate the J’assistance bits, and then by a second module to generate the J”assistance bits, and then by the CRC module to generate the J CRC bits.
  • a permutation module so that the J’assistance bits are transmitted, by the polar encoding module, on the reliable subchannels and the J”bits are transmitted on the unreliable subchannels.
  • the same process may be followed to do tree pruning and error detection with these assistance bits. So this makes the encoding and decoding complex and may take a longer processing time.
  • Parity check bits do not follow any specific order. Hence, in the view of the inventors, they are useless when protecting a block of information bits. CRC is more suited for correcting/detecting an information block. Still, when comparing single CRC bit versus a first parity bit, it could appear the same. But, if one considers more than one parity bit, the other parity bits do not have any relation to the previous parity bit or information bits. In contrast, CRC bits may cover overlapping sets of information bits.
  • an apparatus comprising generating means comprising J registers and configured to generate J addon bits if K information bits are sequentially inputted into the generating means; retrieving means configured to retrieve J * addon bits from the J registers after at least one of the K information bits had been inputted into the generating means and before the K information bits are inputted into the generating means; constructing means configured to construct a codeblock comprising each of the K information bits, the J addon bits, and the J * addon bits, wherein each of the K information bits, the J addon bits, and the J * addon bits is at a respective predetermined position of the codeblock; encoding means configured to polar encode the codeblock.
  • the retrieving means may be configured to retrieve each of the J * addon bits from a respective predetermined register after a respective predetermined input number of the K information bits is inputted into the generating means, wherein each of the predetermined input numbers is smaller than K.
  • the respective predetermined registers may be the same for all of the J * addon bits.
  • the respective predetermined input numbers may be the same for all the J * addon bits.
  • Each of the J addon bits and the J * addon bits may be based on a different subset of the K information bits.
  • the retrieving means may be configured to retrieve each of the J addon bits and J * addon bits such that it is generated based on at least a predetermined number of information bits, wherein the predetermined number is equal to or larger than 2.
  • One of the J * addon bits may be based on m information bits; m ⁇ K; and the constructing means may be configured to arrange the one of the J * addon bits in the codeblock immediately before the first one of the m information bits, between the m information bits, or immediately after the m information bits.
  • the constructing means may comprise a permutating means configured to permutate at least two of the the J addon bits and the J * addon bits.
  • the J addon bits may be an error detection code, and the J * addon bits may be assistance bits.
  • the generating means may be a cyclic redundancy check generator and the J addon bits may be a cyclic redundancy check code.
  • a method comprising generating J addon bits if K information bits are sequentially inputted into a generating means comprising J registers; retrieving J * addon bits from the J registers after at least one of the K information bits had been inputted into the generating means and before the K information bits are inputted into the generating means; constructing a codeblock comprising each of the K information bits, the J addon bits, and the J * addon bits, wherein each of the K information bits, the J addon bits, and the J * addon bits is at a respective predetermined position of the codeblock; polar encoding the codeblock.
  • the retrieving may comprise retrieving each of the J * addon bits from a respective predetermined register after a respective predetermined input number of the K information bits is inputted into the generating means, wherein each of the predetermined input numbers is smaller than K.
  • the respective predetermined registers may be the same for all of the J * addon bits.
  • the respective predetermined input numbers may be the same for all the J * addon bits.
  • Each of the J addon bits and the J * addon bits may be based on a different subset of the K information bits.
  • the retrieving may comprise retrieving each of the J addon bits and J * addon bits such that it is generated based on at least a predetermined number of information bits, wherein the predetermined number is equal to or larger than 2.
  • One of the J * addon bits may be based on m information bits; m ⁇ K; and the constructing may comprise arranging the one of the J * addon bits in the codeblock immediately before the first one of the m information bits, between the m information bits, or immediately after the m information bits.
  • the constructing may comprise permutating at least two of the the J addon bits and the J * addon bits.
  • the J addon bits may be an error detection code, and the J * addon bits may be assistance bits.
  • the generating means may be a cyclic redundancy check generator and the J addon bits may be a cyclic redundancy check code.
  • the method may be a method of coding.
  • a computer program product comprising a set of instructions which, when executed on an apparatus, is configured to cause the apparatus to carry out the method according to the second aspect.
  • the computer program product may be embodied as a computer-readable medium or directly Ioadable into a computer.
  • Fig. 1 shows an encoding unit
  • Fig. 2 shows a CRC generator included in some embodiments of the invention
  • Fig. 3 shows an addon bit generator used in variant 1 according to some embodiments of the invention
  • Fig. 4 shows a principle of addon bit generation and placing of variant 2 according to some embodiments of the invention
  • Fig. 5 shows an addon bit generator used in variant 3 according to some embodiments of the invention
  • Fig. 6 shows a principle of addon bit generation and placing of variant 3 according to some embodiments of the invention
  • Fig. 7 shows a CRC generator corresponding to x 3 +x 2 +1 included in some embodiments of the invention
  • Fig. 8 shows a CCITT CRC-16 generator included in some embodiments of the invention.
  • Fig. 9 shows an apparatus according to an embodiment of the invention.
  • Fig. 10 shows a method according to an embodiment of the invention.
  • Fig. 11 shows an apparatus according to an embodiment of the invention.
  • the apparatus is configured to perform the corresponding method, although in some cases only the apparatus or only the method are described.
  • these J+J’+J”bits may be also named “addon bits” .
  • J’or J” may be 0.
  • the addon bits may be used for error detection and error correction in the decoding of the information bits after polar encoding.
  • a CRC generator is used to generate not only the J CRC bits, but also the J’and J”assistance bits. More precisely, a J bit CRC generator is used to generate all the error detection bits and error correction bits (addon bits) . Part of these addon bits (including J CRC bits, J’+J”assistance bits) are obtained from the shift registers when all the information bits are input into it, similarly to the conventional CRC generation, and part of these addon bits are generated from a respective intermediate value of the shift registers, i.e. when only part of the information bits are inputted into the CRC generator.
  • intermediate output or “intermediate value” means a value of the respective register when at least one of the information bits is inputted into the CRC generator and before all the information bits of the information block are input into the CRC generator.
  • Fig. 2 The concept of a CRC generator used in some embodiments of the invention is shown in Fig. 2.
  • the information bits are inputted sequentially into the shift registers. Between some of the shift registers, there is a respective XOR operator where the value of the preceding register is added to the value of the last register (feedback) . At any time of the shifting operation the values in the registers may be generated by a different number of information bits, and these values depend on the number of XOR operators and the consecutive registers between two XOR operators. “Adding bits” means applying an XOR operation on the bits (i.e., disregarding overflow) .
  • Variant 1 All the addon bits are generated on the fly and no permutation is used
  • the subchannel indices of the polar encoder are sorted by their reliability ⁇ q0, q1, q2, ..., qk ⁇ .
  • the index indicates the reliability from high to Iow.
  • the subchanels with high reliability are those at the end of the polar code input and the unreliable subchannels are generally at the beginning, though some reliable subchannels and unreliable subchannels could be interlaced.
  • the number of J’and J”assistance bits to be generated and the subchannels for their transmission may be obtained by some algorithm or based on a specification. Some examples are given later.
  • the subchannel indices for the J’assistance bits may be: ⁇ IR 0 , IR 1 , ...IR J’-1 ⁇
  • the indices for the J”assistance bits are ⁇ IU 0 , IU 1 , ...IU J”-1 ⁇
  • IR i denotes a reliable subchannel
  • IU i denotes an unreliable subchannel.
  • the J CRC bits may follow the information bits and the (potentially interlaced) assistance bits.
  • Generating and placing the addon bits into the “correct” subchannels may be done as follows: The subchannels are filled one after the other, substantially in parallel with inputting the information bits into the CRC generator. This is called “on the fly” . If the subchannel index of the subchannel to be filled indicates that the subchannel carries an information bit, fill the information bit in it. If the subchannel index of the subchannel to be filled indicates that the subchannel carries a J’type of assistance bit, take the value of one of the shift registers and fill it in the respective subchannel. If the subchannel index of the subchannel to be filled indicates that the subchannel carries a J”type of assistance bit, take the value of one of the shift registers and fill it in the respective subchannel.
  • One example of such a register is the one just after an XOR operator.
  • Another example is using different registers for subsequent assistance bits. For example, wherein the register for a subsequent assistance bit is the next register just after the previous register. If needed, this may be done in a cyclic manner.
  • a fixed shift register e.g. the first one, is used to generate all the assistance bits. Duplication of information should be avoided when selecting the registers for generating the assistance bits, i.e., each of the assistance bits should be based on a different combination of the information bits.
  • at least one information bit should be inputted into the CRC register between two assistance bits.
  • the value of the shift registers may be taken as the J CRC bits.
  • part or all of the J CRC bits may be generated similarly on the fly if the CRC bits are interlaced with the information bits. That is, part or all of the J CRC may not be obtained as the final values of the shift registers when all information bits are inputted. This may be very useful to satisfy the early termination requirement. In this case, part or all of the J’+J”-J * assistance bits may be obtained when all the information bits are inputted into the CRC register.
  • Fig. 3 shows how the CRC generator of variant 1 generates the J CRC bits, the J’assistance bits, and the J”assistance bits.
  • Variant 2 is based on variant 1.
  • the assistance bits are generated only after B information bits (B>0) were inputted into the CRC generator.
  • the assistance bits are generated in the same manner as in variant 1 by looking up the subchannel index.
  • the first B information bits are transmitted after the K-B information bits where there are totally K information bits to be transmitted.
  • the CRC bits or part of the CRC bits are transmitted after the first B information bits.
  • the assistance bits are generated when the shift registers have enough feedbacks. Namely, each XOR operation results in a feedback, and hence the value of some of the shift registers are the binary sum of multiple information bits. When there are enough feedbacks, one assistance bit may link to multiple information bits, providing better error correction and error detection capability.
  • Variant 3 All the addon bits are generated on the fly with real permutation
  • the J’and J”assistance bits and the CRC bits are all generated by the CRC generator, similar to variants 1 and 2. Then, a permutation is performed to achieve better flexibility (see Fig. 5) .
  • some of the J CRC bits are interlaced in the information bits, too. Thus, only Jx (Jx ⁇ J) CRC bits are appended.
  • Some/all the CRC bits may be transmitted forward to better support early termination.
  • the information bits related to a specific CRC bit may be transmitted forward so that the checking can be performed for that CRC bit early.
  • the related information bits for the J’assistance bits which are transmitted on the reliable subchannels may be placed on the reliable or unreliable subchannels to achieve better performance in terms of error detection and error correction. If used for error detection, it is found placing these assistance bits on the reliable subchannels may achieve better performance.
  • the related information bits for the J”assistance bits which are transmitted on the unreliable subchannels may be placed on the reliable or unreliable subchannels to achieve better performance in terms of error detection and error correction. If used for error correction, it is found placing these assistance bits on the unreliable subchannel may achieve better performance.
  • the better flexibility of this variant also includes that a ratio of the number of related information bits to the number of assistance bits is controllable.
  • the maximum number of information bits related to an assistance bit is determined by the number of feedbacks performed. The reason is that when the number of inputted information bits exceeds the number of shift registers, the mentioned feedback happens. So with this scheme, arbitrary number of summed information bits based on the assistance bit to be generated can be obtained as long as there are information bits yet to be processed.
  • An example of a shift register based CRC generator can be found in Fig. 2.
  • the assistance bits are obtained by multiple shift registers at the same time.
  • One example of the specific register is the register just after an XOR operator.
  • the registers and K 1 , K 2 , .. K j’ values are selected to avoid duplication in the assistance bits. l.e., two assistance bits should not be based on the same combination of information bits.
  • the assistance bits may be selected such that the number of information bits involved in the XOR operation exceeds a specific threshold.
  • the assistance bits may be taken from the first J’or J”shift registers, or from the registers starting from that register which has the maximum number information bits involved in the XOR operation.
  • the receiver may use a CRC detector corresponding to the CRC generator.
  • the same assistance bit will be generated when the decoded information bits are inputted it.
  • the receiver can compare the received assistance bit (s) and the locally generated bit (s) to check if the path is correct.
  • the paths that do not pass the CRC bit check will be given a penalty of any real number.
  • the penalty value may be ⁇ 1 3 5 15, ⁇ .
  • Penalty is a value used to alter the path metric. A path is considered to be more unreliable the higher the penalty is.
  • a penalty may be given this corresponding value to reduce its path metric. Paths with lower path metric are easier to be dropped during decoding.
  • the above-mentioned operations and parameters may be known by both the transmitter and the receiver (e.g. defined in the 3GPP specifications) , or they could also be configured by signaling, e.g. RRC signaling, so that they are known by the transmitter and the receiver.
  • signaling e.g. RRC signaling
  • J 16 (16 bit CRC) for downlink and 8 (8 bit CRC) for uplink.
  • J’ may be 3 (3 assistance bits on reliable channels)
  • J” may be 2 (2 bits on unreliable channels) .
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • a CRC generator corresponding to x 3 +x 2 +1 is used.
  • 3 assistance bits are to be generated.
  • a similar method may be used.
  • One scheme to generate the 3 assistance bits is based on the number of inputted information bits.
  • the assistance bits are obtained as the value of the first register R1 when 4, 6, and 8 information bits are inputted, respectively.
  • c 1 b 1 +b 2 +b 3 +b 6 (value of the second register R2 when 8 information bits b 0 to b 7 are inputted)
  • c 2 b 1 +b 3 +b 4 +b 5 (value of the third register R3 when 8 information bits b 0 to b7 are inputted)
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • CCITT CRC-16 generator shown in Fig. 3 is used. It comprises 16 registers denoted by R0 ⁇ R15, and three XOR operators.
  • Information bits [b n-1 , b n-2 , ..., b 2 , b 1 , b 0 ] are to be processed.
  • the information bits are sent into the CRC generator one by one based on the ascending order or its index.
  • the 16 CRC bits are obtained when all the n information bits are input into the generator, by taking out of the register values.
  • the number of assistance bits J’ 4.
  • the assistance bits are obtained by taking the value of the register R5 when 18, 19, 20, 21 information bits are inputted into the CRC generator, respectively. Then the four assistance bits are:
  • the assistance bits are transmitted after a permutation so that they follow their corresponding information bits.
  • the transmission sequence may be:
  • Fig. 4 shows an apparatus according to an embodiment of the invention.
  • the apparatus may be an encoding unit of an eNodeB or a UE or an element thereof.
  • Fig. 5 shows a method according to an embodiment of the invention.
  • the apparatus according to Fig. 4 may perform the method of Fig. 5 but is not limited to this method.
  • the method of Fig. 5 may be performed by the apparatus of Fig. 4 but is not limited to being performed by this apparatus.
  • the apparatus comprises generating means 10, retrieving means 20, constructing means 30, and encoding means 40.
  • Each of the generating means 10, retrieving means 20, constructing means 30, and encoding means 40 may be a generating processor, retrieving processor, constructing processor, and encoding processor, respectively.
  • Each of the generating means 10, retrieving means 20, constructing means 30, and encoding means 40 may be a generator, retriever, constructor, and encoder, respectively.
  • the generating means 10 comprises J registers. It may consist of J registers.
  • the generating means 10 generates J addon bits (e.g. an error detection code such as a CRC code) of J bits if K information bits are sequentially inputted into the generating means 10 (S10) .
  • the K information bits may be denoted as an information block.
  • the retrieving means 20 retrieves J * addon bits from the J registers after at least one of the K information bits had been inputted into the generating means 10 and before the K information bits are inputted into the generating means 10 (S20) . That is, the retrieving means 20 retrieves the J * addon bits as intermediate values of the registers.
  • J * may be predetermined.
  • the constructing means 30 constructs a codeblock comprising each of the K information bits, the J addon bits generated by the generating means 10 if the K information bits are inputted into the generating means 10, and the J * addon bits retrieved by the retrieving means 20 (S30) .
  • the constructing means 30 constructs the codeblock such that each of the K information bits, the J addon bits, and the J * addon bits is at a respective predetermined position of the codeblock.
  • the codeblock may consist of the K information bits, the J addon bits, and the J * addon bits.
  • Fig. 6 shows an apparatus according to an embodiment of the invention.
  • the apparatus comprises at least one processor 410, at least one memory 420 including computer program code, and the at least one processor 410, with the at least one memory 420 and the computer program code, being arranged to cause the apparatus to at least perform at least the method according to Fig. 5.
  • Some embodiments of the invention may be employed in 3GPP devices, e.g. in the encoding unit thereof. However, embodiments of the invention are not limited to 3GPP devices. They may be employed in any kind of devices where polar coding is employed.
  • Some embodiments of the invention may use another error detection code than CRC if this error detection code can generate intermediate values.
  • this error detection code can generate intermediate values.
  • any block code with Hamming distance t can detect t-1 errors.
  • An example are Hamming codes.
  • One piece of information may be transmitted in one or plural messages from one entity to another entity. Each of these messages may comprise further (different) pieces of information.
  • Names of network elements, protocols, and methods are based on current standards. In other versions or other technologies, the names of these network elements and/or protocols and/or methods may be different, as long as they provide a corresponding functionality.
  • each of the entities described in the present description may be based on a different hardware, or some or all of the entities may be based on the same hardware. It does not necessarily mean that they are based on different software. That is, each of the entities described in the present description may be based on different software, or some or all of the entities may be based on the same software.
  • Each of the entities described in the present description may be embodied in the cloud.
  • example embodiments of the present invention provide, for example, a base station such as a eNodeB, or a component such as a TX path or an encoding unit thereof, or a terminal such as a User Equipment or a MTC device, or a component such as a TX path or an encoding unit thereof, an apparatus embodying the same, a method for controlling and/or operating the same, and computer program (s) controlling and/or operating the same as well as mediums carrying such computer program (s) and forming computer program product (s) .
  • a base station such as a eNodeB
  • a component such as a TX path or an encoding unit thereof
  • a terminal such as a User Equipment or a MTC device
  • a component such as a TX path or an encoding unit thereof
  • Implementations of any of the above described blocks, apparatuses, systems, techniques or methods include, as non-limiting examples, implementations as hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
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  • Probability & Statistics with Applications (AREA)
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  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

L'invention concerne un procédé comprenant la génération de J bits additionnels si K bits d'information sont consécutivement entrés dans un moyen de génération comprenant J registres ; la récupération de J* bits additionnels à partir des J registres après qu'au moins un des K bits d'information a été entré dans le moyen de génération et avant que les K bits d'information ne soient entrés dans le moyen de génération ; la construction d'un bloc de code comprenant chacun des K bits d'information, des J bits additionnels et des J* bits additionnels, chacun des K bits d'information, des J bits additionnels et des J* bits additionnels étant au niveau d'une position prédéfinie respective du bloc de code ; le codage polaire du bloc de code.
PCT/CN2017/083003 2017-05-04 2017-05-04 Générateur de code détecteur d'erreurs et de code correcteur d'erreurs unifié WO2018201377A1 (fr)

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CN201780090309.6A CN110603759B (zh) 2017-05-04 2017-05-04 统一的纠错和检错码生成器
PCT/CN2017/083003 WO2018201377A1 (fr) 2017-05-04 2017-05-04 Générateur de code détecteur d'erreurs et de code correcteur d'erreurs unifié

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PCT/CN2017/083003 WO2018201377A1 (fr) 2017-05-04 2017-05-04 Générateur de code détecteur d'erreurs et de code correcteur d'erreurs unifié

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WO2018201377A1 true WO2018201377A1 (fr) 2018-11-08

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CN104219019A (zh) * 2013-05-31 2014-12-17 华为技术有限公司 编码方法及编码设备
CN105227189A (zh) * 2015-09-24 2016-01-06 电子科技大学 分段crc辅助的极化码编译码方法

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