WO2018198604A1 - Laminated balun - Google Patents

Laminated balun Download PDF

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Publication number
WO2018198604A1
WO2018198604A1 PCT/JP2018/010977 JP2018010977W WO2018198604A1 WO 2018198604 A1 WO2018198604 A1 WO 2018198604A1 JP 2018010977 W JP2018010977 W JP 2018010977W WO 2018198604 A1 WO2018198604 A1 WO 2018198604A1
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WO
WIPO (PCT)
Prior art keywords
inductor
terminal
balanced
electrode
unbalanced
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PCT/JP2018/010977
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French (fr)
Japanese (ja)
Inventor
谷口 哲夫
清弘 樫内
博志 増田
Original Assignee
株式会社村田製作所
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Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to TW107112978A priority Critical patent/TWI712261B/en
Publication of WO2018198604A1 publication Critical patent/WO2018198604A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F19/00Fixed transformers or mutual inductances of the signal type
    • H01F19/04Transformers or mutual inductances suitable for handling frequencies considerably beyond the audio range
    • H01F19/06Broad-band transformers, e.g. suitable for handling frequencies well down into the audio range
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01Frequency selective two-port networks
    • H03H7/09Filters comprising mutual inductance
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/42Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/46Networks for connecting several sources or loads, working on different frequencies or frequency bands, to a common load or source

Definitions

  • the present invention relates to a laminated balun that performs signal conversion between an unbalanced signal and a balanced signal.
  • a balanced line may be used as a signal line in order to reduce the influence of external noise.
  • the Rx signal may be input from the antenna to the RF circuit and the Tx signal may be output from the RF circuit to the antenna through a balanced line.
  • FIG. 6 is an equivalent circuit diagram of the laminated balance filter 200 disclosed in Japanese Patent Laid-Open No. 2013-138410.
  • the laminated balance filter 200 has one unbalanced terminal UB and a balanced terminal B composed of a first terminal B1 and a second terminal B2.
  • the laminated balance filter 200 outputs the unbalanced signal input to the unbalanced terminal UB as a balanced signal from the balanced terminal B (first terminal B1 and second terminal B2), and the balanced terminal B (first terminal B1 and second terminal).
  • the balanced signal input to the terminal B2) is output as an unbalanced signal from the unbalanced terminal UB.
  • the laminated balance filter 200 is manufactured by forming an inductor conductor pattern, a capacitor conductor pattern, a ground conductor pattern, a via conductor pattern, and the like inside a laminate in which a plurality of dielectric layers are laminated. Between the unbalanced terminal UB and the balanced terminal B, band-pass filters LC1 and LC2 configured by LC parallel resonators are inserted. A mutual inductance M10 is generated between the inductor L10 of the bandpass filter LC1 and the inductor L20 of the bandpass filter LC2, and a mutual inductance M20 is generated between the inductor L20 and the balanced inductor L30.
  • FIG. 7 is a diagram illustrating an example of a balanced / unbalanced conversion circuit configured by connecting one divider 300 and two stacked balanced filters 200.
  • the divider 300 includes a first terminal 101, a second terminal 102, and a third terminal 103.
  • the divider 300 distributes a signal input to the first terminal 101 and outputs the signal from the second terminal 102 and the third terminal 103. 102, the signals input to the third terminal 103 are combined and output from the first terminal.
  • the antenna Ant and the first terminal 101 of the divider 300 are connected by an unbalanced line.
  • the second terminal 102 of the divider 300 and the unbalanced terminal UB of one laminated balance filter 200 are connected by an unbalanced line, and the third terminal 103 of the divider 300 and the unbalanced terminal UB of the other laminated balance filter 200 are connected to each other.
  • a balanced line on the Tx side is connected to the balanced terminal B (first terminal B1 and second terminal B2) of one multilayer balanced filter 200, and the balanced terminal B (first terminal B1 and first terminal B1) of the other multilayer balanced filter 200 is connected.
  • a balanced line on the Rx side is connected to the two terminals B2).
  • the output of the Tx signal from the RF circuit and the input of the Rx signal to the RF circuit are performed by a balanced line, and the transmission of the Tx signal and the reception of the Rx signal are performed.
  • the conventional method using one divider 300 and two laminated balance filters 200 in order to share one antenna Ant there are the following problems.
  • the signal line connected to the antenna Ant is branched by the divider 300, there is a problem that insertion loss occurs in the signal.
  • the Rx signal sent from the antenna Ant to the RF circuit has been attenuated by about 3 dB by passing through the divider.
  • each insertion balance filter 200 also has an insertion loss, there is a problem that the total insertion loss becomes large.
  • the present disclosure has been made to solve the above-described problem, and an object thereof is to provide a small-sized laminated balun including an unbalanced terminal and two pairs of balanced terminals and having a small signal insertion loss. To do.
  • a multilayer balun includes a multilayer body in which a plurality of dielectric layers are stacked, a plurality of inductor conductor patterns formed between layers of the multilayer body, and a plurality of layers formed on a surface of the multilayer body.
  • the plurality of terminals include an unbalanced terminal, a first balanced terminal, a second balanced terminal, and a ground terminal.
  • Each of the first balanced terminal and the second balanced terminal has a first terminal and a second terminal.
  • the plurality of inductor conductor patterns include at least one unbalanced inductor conductor pattern electrically connected between the unbalanced terminal and the ground terminal, the first terminal of the first balanced terminal, and the first terminal.
  • a region surrounded by the first balanced-side inductor conductor pattern overlaps a region surrounded by the at least one unbalanced-side inductor conductive pattern
  • At least a part of the region surrounded by the second balanced inductor conductor pattern overlaps the region surrounded by the at least one unbalanced inductor conductor pattern.
  • the first balanced inductor conductor pattern and the second balanced inductor conductor pattern are formed between the same layers of the multilayer body.
  • the plurality of dielectric layers include first to third dielectric layers that are successively stacked.
  • the at least one unbalanced inductor conductor pattern includes an inductor conductor pattern formed between the first dielectric layer and the second dielectric layer.
  • the first balanced-side inductor conductor pattern and the second balanced-side inductor conductor pattern are formed between the second dielectric layer and the third dielectric layer.
  • the plurality of dielectric layers include a fourth dielectric layer stacked on the opposite side of the third dielectric layer from the second dielectric layer.
  • the at least one unbalanced inductor conductor pattern includes a first unbalanced inductor conductor pattern and a second unbalanced inductor conductor pattern.
  • the first unbalanced inductor conductor pattern is formed between the first dielectric layer and the second dielectric layer.
  • the second unbalanced inductor conductor pattern is formed between the third dielectric layer and the fourth dielectric layer.
  • At least one unbalanced inductor conductor pattern has a shape in which two open annular portions are connected. At least a part of a region surrounded by the first balanced-side inductor conductor pattern overlaps a region surrounded by one annular portion of at least one unbalanced-side inductor conductor pattern. At least a portion of the region surrounded by the second balanced-side inductor conductor pattern overlaps with the region surrounded by the other annular portion of the at least one unbalanced-side inductor conductor pattern.
  • the multilayer balun of the present disclosure includes an unbalanced terminal and two pairs of balanced terminals, since no divider is used, there is no signal insertion loss due to passing through the divider, and overall insertion loss is reduced. small.
  • the multilayer balun according to the present disclosure is configured such that the function conventionally performed by using one divider and two baluns is performed by one balun, and the size is reduced. Therefore, in a communication device in which the multilayer balun of the present disclosure is mounted, the space required for mounting can be reduced.
  • FIG. 1 is an equivalent circuit diagram of a laminated balun according to an embodiment of the present invention. It is an external appearance perspective view of a laminated balun. It is a disassembled perspective view of a laminated balun. It is a disassembled perspective view which shows the modification of a laminated balun. It is a disassembled perspective view which shows a part of another modification of a lamination
  • 6 is an equivalent circuit diagram of a multilayer balance filter described in Patent Document 1.
  • FIG. It is an equivalent circuit diagram showing an example of a balun circuit configured by connecting one divider and two laminated balance filters.
  • FIG. 1 to 3 show a laminated balun 100 according to an embodiment of the present invention.
  • FIG. 1 is an equivalent circuit diagram of the laminated balun 100 according to the embodiment of the present invention.
  • FIG. 2 is an external perspective view of the laminated balun 100.
  • FIG. 3 is an exploded perspective view of the laminated balun 100.
  • the laminated balun 100 includes one unbalanced terminal UB.
  • the laminated balun 100 includes a first balanced terminal Tx having a first terminal Tx1 and a second terminal Tx2, and a second balanced terminal Rx having a first terminal Rx1 and a second terminal Rx2.
  • two pairs of balanced terminals are shown as a first balanced terminal Tx and a second balanced terminal Rx for convenience, but the usage of each balanced terminal is arbitrary, and the first balanced terminal is designated as Tx.
  • the terminal is not limited to using the second balanced terminal as the Rx terminal.
  • the laminated balun 100 includes a low-pass filter.
  • the low-pass filter includes a first inductor L1, a first capacitor C1 inserted between one end of the first inductor L1 and the ground, and a second capacitor inserted between the other end of the first inductor L1 and the ground. And C2.
  • One end of the first inductor L1 (one end of the first capacitor C1) is connected to the unbalanced terminal UB.
  • a ⁇ -type low-pass filter is employed as the low-pass filter, but the type of the low-pass filter is not limited to the ⁇ -type, and other types may be used.
  • the multilayer balun 100 includes a third capacitor C3 connected in parallel with the first inductor L1 of the low-pass filter.
  • the third capacitor C3 is for forming a trap on the high frequency side outside the pass band of the low-pass filter, and for improving the function of the low-pass filter.
  • the multilayer balun 100 includes an unbalanced inductor L2.
  • the unbalanced inductor L2 is connected in parallel with the second capacitor C2 of the low pass filter.
  • the unbalanced inductor L2 and the second capacitor C2 connected in parallel constitute an LC parallel resonator.
  • the multilayer balun 100 includes a first balanced-side inductor in which a first inductor portion L31, a second inductor portion L32, and a third inductor portion L33 are connected in series.
  • the first balanced-side inductor is connected between the first terminal Tx1 and the second terminal Tx2 of the first balanced terminal Tx.
  • a DC feed terminal DCfeed is connected to an intermediate portion of the second inductor portion L32.
  • the multilayer balun 100 includes a second balanced-side inductor in which a first inductor portion L41, a second inductor portion L42, and a third inductor portion L43 are connected in series.
  • the second balanced-side inductor is connected between the first terminal Rx1 and the second terminal Rx2 of the second balanced terminal Rx.
  • the unbalanced inductor L2 is electromagnetically coupled to the first balanced inductor.
  • the unbalanced inductor L2 is electromagnetically coupled to the second inductor portion L32 of the first balanced inductor. That is, a mutual inductance M1 is generated between the unbalanced inductor L2 and the second inductor portion L32 of the first balanced inductor.
  • the unbalanced inductor L2 is electromagnetically coupled to the second balanced inductor.
  • the unbalanced inductor L2 is electromagnetically coupled to the second inductor portion L42 of the second balanced inductor. That is, a mutual inductance M2 is generated between the unbalanced inductor L2 and the second inductor portion L42 of the second balanced inductor.
  • the multilayer balun 100 further includes a fourth capacitor C4 inserted between the first terminal Tx1 and the second terminal Tx2 of the first balanced terminal Tx.
  • the fourth capacitor C4 forms an LC parallel resonator with the first balanced inductors (L31, L32, L33), and the LC parallel resonator formed with the unbalanced inductor L2 and the second capacitor C2 described above. Together, they constitute a first band pass filter.
  • the first band pass filter passes only a signal in an arbitrarily selected frequency band between the unbalanced terminal UB and the first balanced terminal Tx.
  • the impedance on the first balanced terminal Tx (Tx1, Tx2) side is adjusted by selecting the constants of the first balanced inductors (L31, L32, L33) and the fourth capacitor C4. Can do.
  • the multilayer balun 100 further includes a fifth capacitor C5 inserted between the first terminal Rx1 and the second terminal Rx2 of the second balanced terminal Rx.
  • the fifth capacitor C5 forms an LC parallel resonator with the second balanced-side inductors (L41, L42, L43), and the LC parallel resonator configured with the unbalanced-side inductor L2 and the second capacitor C2 described above. Together, they constitute a second bandpass filter.
  • the second band pass filter passes only a signal in an arbitrarily selected frequency band between the unbalanced terminal UB and the second balanced terminal Rx.
  • the impedance of the second balanced terminal Rx (Rx1, Rx2) side is adjusted by selecting the constants of the second balanced inductors (L41, L42, L43) and the fifth capacitor C5. Can do.
  • the laminated balun 100 composed of the above equivalent circuits can output the balanced signal input to the first balanced terminal Tx as an unbalanced signal from the unbalanced terminal UB. Note that if DC power is supplied to the DC feed terminal DCfeed, the strength of the unbalanced signal output from the unbalanced terminal UB can be increased. Furthermore, the unbalanced signal input to the unbalanced terminal UB can be output as a balanced signal from the second balanced terminal Rx.
  • balanced signals having substantially the same amplitude and different phases are input to the first terminal Tx1 and the second terminal Tx2 of the first balanced terminal Tx. Furthermore, balanced signals having substantially the same amplitude and different phases are output from the first terminal Rx1 and the second terminal Rx2 of the second balanced terminal Rx.
  • the laminated balun 100 composed of the above equivalent circuits can be constituted by, for example, the laminated body 1 shown in FIGS.
  • the laminated balun 100 includes a laminated body 1 in which a plurality of dielectric layers are laminated, and a plurality of terminals formed on the surface of the laminated body 1.
  • the plurality of terminals are formed on the side surfaces when the pair of main surfaces having the largest area of the rectangular parallelepiped laminated body 1 are the upper surface and the bottom surface.
  • the laminated body 1 is formed by laminating dielectric layers 1a to 1p made of ceramic, for example, in order from the bottom.
  • first terminals Tx1 and second terminals Tx2 of the first balanced terminal Tx are provided on the surface of the laminated body 1.
  • Rx2 a first ground terminal G1, a second ground terminal G2, a DC feed terminal DCfeed, a first floating terminal F1, and a second floating terminal F2 are formed.
  • the first floating terminal F1, the second floating terminal F2, the first ground terminal G1, and the unbalanced terminal UB are sequentially arranged on the side surface on the near side of the stacked body 1 in FIG. It is formed.
  • a second ground terminal G2 is formed on the left side surface of the multilayer body 1 in FIG.
  • a DC feed terminal DCfeed is formed on the right side surface of the laminate 1 in FIG. Note that both ends of each terminal are formed to extend on the lower main surface and the upper main surface of the laminate 1, respectively.
  • the first floating terminal F1 and the second floating terminal F2 are not connected to a circuit inside the stacked body 1, and are bonded to a land electrode such as a substrate when the stacked balun 100 is mounted, thereby increasing mounting strength. Used for.
  • Unbalanced terminal UB first terminal Tx1 and second terminal Tx2 of first balanced terminal Tx, first terminal Rx1 and second terminal Rx2 of second balanced terminal Rx, first ground terminal G1, second ground terminal G2, DC
  • the feed terminal DCfeed, the first floating terminal F1, and the second floating terminal F2 can be formed of, for example, a metal whose main component is Ag, Cu, or an alloy thereof.
  • a plating layer containing Ni, Sn, Au or the like as a main component may be formed over one layer or a plurality of layers as necessary.
  • the laminated balun 100 includes capacitor conductor patterns (hereinafter simply referred to as “capacitor electrodes”) 2a to 2q, connecting conductors formed between the dielectric layers 1a to 1p constituting the laminated body 1.
  • a pattern (hereinafter simply referred to as “connection electrode”) 3a and an inductor conductor pattern (hereinafter simply referred to as “inductor electrode”) 4a to 4p are provided.
  • the laminated balun 100 includes via conductor patterns (hereinafter simply referred to as “via electrodes”) 5a to 5p formed in the laminated body 1 in the laminating direction of the dielectric layers 1a to 1p.
  • a capacitor electrode 2a and a connection electrode 3a are formed on the upper main surface of the dielectric layer 1b.
  • the capacitor electrode 2a is connected to the second ground terminal G2.
  • the connection electrode 3a is connected to the DC feed terminal DCfeed.
  • a capacitor electrode 2b is formed on the upper main surface of the dielectric layer 1c.
  • the capacitor electrode 2b is connected to the unbalanced terminal UB.
  • capacitor electrodes 2c, 2d, 2e, 2f are formed on the upper main surface of the dielectric layer 1d.
  • the capacitor electrode 2c is connected to the first terminal Tx1 of the first balanced terminal Tx
  • the capacitor electrode 2d is connected to the second terminal Tx2 of the first balanced terminal Tx
  • the capacitor electrode 2e is connected to the first terminal Rx1 of the second balanced terminal Rx
  • the capacitor electrode 2f is connected to the second terminal Rx2 of the second balanced terminal Rx.
  • Two capacitor electrodes 2g and 2h are formed on the upper main surface of the dielectric layer 1e.
  • Four capacitor electrodes 2i, 2j, 2k, 2l are formed on the upper main surface of the dielectric layer 1f.
  • the capacitor electrode 2i is connected to the first terminal Tx1 of the first balanced terminal Tx
  • the capacitor electrode 2j is connected to the second terminal Tx2 of the first balanced terminal Tx
  • the capacitor electrode 2k is connected to the first terminal Rx1 of the second balanced terminal Rx
  • 2l is connected to the second terminal Rx2 of the second balanced terminal Rx, respectively.
  • Three capacitor electrodes 2m, 2n, 2o are formed on the upper main surface of the dielectric layer 1g.
  • the capacitor electrode 2m is connected to the first ground terminal G1.
  • a capacitor electrode 2p is formed on the upper main surface of the dielectric layer 1h.
  • Capacitor electrode 2q is formed on the upper main surface of dielectric layer 1i. The capacitor electrode 2q is connected to the unbalanced terminal UB.
  • Two inductor electrodes 4a and 4b are formed on the upper main surface of the dielectric layer 1j. One end of the inductor electrode 4a is connected to the first terminal Tx1 of the first balanced terminal Tx, and one end of the inductor electrode 4b is connected to the second terminal Rx2 of the second balanced terminal Rx.
  • the inductor electrode 4d has an open ring shape. One end of the inductor electrode 4d is connected to the first ground terminal G1.
  • Two inductor electrodes 4f, 4g, and 4h are formed on the upper main surface of the dielectric layer 1l.
  • the inductor electrodes 4g and 4h have an open ring shape. When viewed from the stacking direction of the dielectric layers 1a to 1p, each of the regions surrounded by the annular inductor electrodes 4g and 4h overlaps at least a part of the region surrounded by the annular inductor electrode 4d.
  • the inductor electrode 4j has an open annular shape. When viewed from the stacking direction of the dielectric layers 1a to 1p, at least a part of the region surrounded by the annular inductor electrode 4j overlaps with the region surrounded by the annular inductor electrode 4g. Furthermore, at least a part of the region surrounded by the annular inductor electrode 4j overlaps with the region surrounded by the annular inductor electrode 4h.
  • Three inductor electrodes 4m, 4n, 4o are formed on the upper main surface of the dielectric layer 1n.
  • One end of the inductor electrode 4n is connected to the second terminal Tx2 of the first balanced terminal Tx, and one end of the inductor electrode 4o is connected to the first terminal Rx1 of the second balanced terminal Rx.
  • An inductor electrode 4p is formed on the upper main surface of the dielectric layer 1o. One end of the inductor electrode 4p is connected to the unbalanced terminal UB.
  • the via electrode 5a penetrates the dielectric layers 1i to 1k and connects the capacitor electrode 2p and one end of the inductor electrode 4c.
  • the via electrode 5a is formed integrally with a via electrode 5h, which will be described later, but for convenience of explaining the connection relationship, the lower portion of the via electrode is denoted by reference numeral 5a and the upper portion is denoted by reference numeral 5h. It shows by.
  • the via electrode 5b penetrates the dielectric layer 1k and connects the other end of the inductor electrode 4b and one end of the inductor electrode 4e.
  • the via electrode 5c penetrates the dielectric layer 11 and connects the other end of the inductor electrode 4c and one end of the inductor electrode 4f.
  • the via electrode 5d passes through the dielectric layers 1c to 1l and connects the connection electrode 3a and the intermediate portion of the inductor electrode 4g.
  • the via electrode 5e passes through the dielectric layers 1k and 1l and connects the other end of the inductor electrode 4a and one end of the inductor electrode 4g.
  • the via electrode 5f penetrates the dielectric layer 11 and connects the other end of the inductor electrode 4e and one end of the inductor electrode 4h.
  • the via electrode 5g penetrates the dielectric layer 1m and connects the other end of the inductor electrode 4f and one end of the inductor electrode 4i.
  • the via electrode 5h penetrates the dielectric layers 11 and 1m and connects one end of the inductor electrode 4c and one end of the inductor electrode 4j.
  • the via electrode 5i passes through the dielectric layers 11 and 1m and connects the other end of the inductor electrode 4d and the other end of the inductor electrode 4j.
  • the via electrode 5j penetrates the dielectric layer 1m and connects the other end of the inductor electrode 4g and one end of the inductor electrode 4k.
  • the via electrode 5k penetrates the dielectric layer 1m and connects the other end of the inductor electrode 4h and one end of the inductor electrode 4l.
  • the via electrode 5l penetrates the dielectric layer 1n and connects the other end of the inductor electrode 4i and one end of the inductor electrode 4m.
  • the via electrode 5m penetrates the dielectric layer 1n and connects the other end of the inductor electrode 4k and the other end of the inductor electrode 4n.
  • the via electrode 5n penetrates the dielectric layer 1n and connects the other end of the inductor electrode 4l and the other end of the inductor electrode 4o.
  • the via electrode 5o passes through the dielectric layer 1o and connects the other end of the inductor electrode 4m and the other end of the inductor electrode 4p.
  • the capacitor electrodes 2a to 2q, the connection electrodes 3a, the inductor electrodes 4a to 4p, and the via electrodes 5a to 5o described above can be formed of, for example, Ag, Cu, or a metal mainly composed of these alloys.
  • the laminated balun 100 of the present embodiment constituted by the laminated body in which the dielectric layers are laminated having the above-described configuration is manufactured by a general manufacturing method conventionally used for manufacturing a laminated balun. can do.
  • the low-pass filter is composed of a first inductor L1, a first capacitor C1, and a second capacitor C2.
  • the inductor electrode 4m, the via electrode 5l, the inductor electrode 4i, the via electrode 5g, the inductor electrode 4f, the via electrode 5c, and the inductor electrode 4c are formed by a line having one end of the inductor electrode 4c as an end point.
  • the first capacitor C1 of the low-pass filter is formed by a capacitance formed between the capacitor electrode 2b connected to the unbalanced terminal UB and the capacitor electrode 2a connected to the second ground terminal G2.
  • the second capacitor C2 of the low-pass filter is between the capacitor electrode 2p connected to one end of the inductor electrode 4c that is the end point of the first inductor L1 by the via electrode 5a and the capacitor electrode 2m connected to the first ground terminal G1. It is formed by the capacity
  • the third capacitor C3 connected in parallel with the first inductor L1 of the low-pass filter has a capacitor electrode 2q connected to the unbalanced terminal UB, and one end of the inductor electrode 4c that is the end point of the first inductor L1 by the via electrode 5a. It is formed by a capacitor formed between the connected capacitor electrode 2p.
  • the unbalanced inductor L2 starts from one end of the inductor electrode 4c, which is the end point of the first inductor L1, and passes through the via electrode 5h, the inductor electrode 4j, the via electrode 5i, and the inductor electrode 4d to connect the first ground terminal G1. It is formed by a track that is the end point.
  • the other end of the inductor electrode 4c is electrically connected to the unbalanced terminal UB via each electrode constituting the first inductor L1. Therefore, each of the inductor electrodes 4j and 4d constituting the unbalanced inductor L2 is electrically connected between the unbalanced terminal UB and the first ground terminal G1.
  • the “electrically connected” state means a state connected by a conductive path or a state connected through a capacitor, and is not limited to a directly connected state, but another element is interposed therebetween. It also includes a state of being indirectly connected.
  • the inductor electrode 4d corresponds to the lower inductor electrode
  • the inductor electrode 4j corresponds to the upper inductor electrode.
  • the inductor electrode 4d as the lower inductor electrode and the inductor electrode 4k as the upper inductor electrode are connected by the via electrode 5i.
  • the first balanced-side inductor starts from the first terminal Tx1 of the first balanced terminal Tx and passes through the inductor electrode 4a, the via electrode 5e, the inductor electrode 4g, the via electrode 5j, the inductor electrode 4k, the via electrode 5m, and the inductor electrode 4n.
  • the first balanced terminal Tx is formed by a line having the second terminal Tx2 as an end point. That is, each of the inductor electrodes 4a, 4g, 4k, and 4n is electrically connected between the first terminal Tx1 and the second terminal Tx2 of the first balanced terminal Tx.
  • the inductor electrode 4g formed so as to surround a region overlapping with a part of the region surrounded by any of the annular inductor electrodes 4j and 4d when viewed from the stacking direction is the first balanced-side inductor.
  • 2 inductor part L32 is constituted.
  • the region surrounded by the inductor electrode 4g and the region surrounded by any one of the inductor electrodes 4i and 4d are overlapped, so that the unbalanced structure configured by the second inductor portion L32 configured by the inductor electrode 4g and the inductor electrodes 4i and 4d is formed.
  • the side inductor L2 is electromagnetically coupled.
  • the inductor electrode 4a and the via electrode 5e electrically connected between the first terminal Tx1 of the first balanced terminal Tx and the inductor electrode 4g constitute a first inductor portion L31 of the first balanced side inductor.
  • the via electrode 5j, the inductor electrode 4k, the via electrode 5m, and the inductor electrode 4n that are electrically connected between the inductor electrode 4g and the second terminal Tx2 of the first balanced terminal Tx are the third balanced inductors.
  • the inductor portion L33 is configured.
  • the intermediate portion of the inductor electrode 4g constituting the second inductor portion L32 of the first balanced inductor is connected to the DC feed terminal DCfeed via the via electrode 5d and the connection electrode 3a.
  • the second balanced-side inductor starts from the first terminal Rx1 of the second balanced terminal Rx, and starts from the inductor electrode 4o, via electrode 5n, inductor electrode 41, via electrode 5k, inductor electrode 4h, via electrode 5f, inductor electrode 4e, via It is formed by a line having the second terminal Rx2 of the second balanced terminal Rx as an end point via the electrode 5b and the inductor electrode 4b. That is, each of the inductor electrodes 4o, 4l, 4h, 4e, and 4b is electrically connected between the first terminal Rx1 and the second terminal Rx2 of the second balanced terminal Rx.
  • the inductor electrode 4h formed so as to surround a region overlapping with a part of the region surrounded by either of the annular inductor electrodes 4j and 4d is the second balanced-side inductor.
  • 2 inductor part L42 is comprised.
  • the region surrounded by the inductor electrode 4h and the region surrounded by any one of the inductor electrodes 4i and 4d are overlapped, so that an unbalance formed by the second inductor portion L42 formed by the inductor electrode 4h and the inductor electrodes 4i and 4d is formed.
  • the side inductor L2 is electromagnetically coupled.
  • the inductor electrode 4o, the via electrode 5n, the inductor electrode 4l and the via electrode 5k, which are electrically connected between the first terminal Rx1 of the second balanced terminal Rx and the inductor electrode 4h, are the first balanced-side inductor first.
  • the inductor portion L41 is configured.
  • the via electrode 5f, the inductor electrode 4e, the via electrode 5b, and the inductor electrode 4b, which are electrically connected between the inductor electrode 4h and the second terminal Rx2 of the second balanced terminal Rx, are the third balanced-side inductor third.
  • the inductor portion L43 is configured.
  • the fourth capacitor C4 mainly includes capacitor electrodes 2c and 2i connected to the first terminal Tx1 of the first balanced terminal Tx via the capacitor electrodes 2g and 2n which are not connected to the terminals and become floating electrodes,
  • the capacitor is formed by a capacitor formed between the capacitor electrodes 2d and 2j connected to the second terminal Tx2 of the first balanced terminal Tx.
  • the fifth capacitor C5 mainly includes capacitor electrodes 2e and 2k connected to the first terminal Rx1 of the second balanced terminal Rx via the capacitor electrodes 2h and 2o which are not connected to the terminals and are floating electrodes,
  • the capacitor is formed by a capacitor formed between the capacitor electrodes 2f and 2l connected to the second terminal Rx2 of the second balanced terminal Rx.
  • the inductor electrode 4g constituting the second inductor portion L32 of the first balanced-side inductor and the second inductor portion L42 of the second balanced-side inductor are configured.
  • the inductor electrode 4h to be formed is formed on the upper main surface of the same dielectric layer 1l. That is, the inductor electrode 4g and the inductor electrode 4h are formed between the same layers between the dielectric layer 11 and the dielectric layer 1m. Thereby, the laminated body 1 which comprises the laminated balun 100 can be made low-profile.
  • a first inductor is provided between the inductor electrode 4d constituting the lower inductor electrode of the unbalanced inductor L2 divided into two and the inductor electrode 4j constituting the upper inductor electrode.
  • An inductor electrode 4g constituting the second inductor portion L32 of the balanced-side inductor and an inductor electrode 4h constituting the second inductor portion L42 of the second balanced-side inductor are sandwiched and arranged.
  • the unbalanced inductor L2 and the second inductor portion L32 of the first balanced inductor are electromagnetically coupled.
  • the unbalanced inductor L2 and the second inductor section L42 of the second balanced inductor are electromagnetically coupled.
  • the magnetic flux formed by the via electrode 5i that connects the inductor electrode 4d that forms the lower inductor electrode of the unbalanced inductor L2 and the inductor electrode 4j that forms the upper inductor electrode, and the first The magnetic flux formed by the inductor electrode 4g of the second inductor portion L32 of the balanced inductor is orthogonal to each other, and interference between the two is suppressed. Therefore, a decrease in Q is suppressed in both the unbalanced inductor L2 and the first balanced inductor (second inductor portion L32).
  • the laminated balun 100 of the present embodiment includes the laminated body 1 in which the plurality of dielectric layers 1a to 1p are laminated, the plurality of inductor electrodes formed between the layers of the laminated body 1, and the laminated body 1 And a plurality of terminals formed on the surface.
  • the plurality of terminals include an unbalanced terminal UB, a first balanced terminal Tx, a second balanced terminal Rx, and a first ground terminal G1.
  • the first balanced terminal Tx has a first terminal Tx1 and a second terminal Tx2.
  • the second balanced terminal Rx has a first terminal Rx1 and a second terminal Rx2.
  • the plurality of inductor electrodes include inductor electrodes (unbalanced-side inductor conductor patterns) 4d and 4j electrically connected between the unbalanced terminal UB and the first ground terminal G1, and a first terminal of the first balanced terminal Tx. Between the inductor electrode (first balanced-side inductor conductor pattern) 4g electrically connected between Tx1 and the second terminal Tx2, and between the first terminal Rx1 and the second terminal Rx2 of the second balanced terminal Rx Connected inductor electrode (second balanced-side inductor conductor pattern) 4h.
  • the inductor electrode 4g When viewed from the stacking direction of the plurality of dielectric layers 1a to 1p, at least a part of the region surrounded by the inductor electrode 4g overlaps the region surrounded by the inductor electrodes 4d and 4j. Furthermore, at least a part of the region surrounded by the inductor electrode 4h overlaps the region surrounded by the inductor electrodes 4d and 4j.
  • the inductor electrodes 4g and 4h are formed between the same layers of the multilayer body 1 (here, between the dielectric layer 1l and the dielectric layer 1m).
  • the unbalanced inductor L2 constituted by the inductor electrodes 4d and 4j can be electromagnetically coupled to the second inductor portion L32 of the first balanced inductor constituted by the inductor electrode 4g, and the inductor electrode 4h.
  • the second inductor portion L42 of the second balanced-side inductor constituted by the electromagnetic field coupling can also be performed.
  • the inductor electrodes 4g and 4h are formed between the same layers, the stacked body 1 can be reduced in height.
  • insertion loss due to passing through the divider can be suppressed, and the number of parts can be reduced. As a result, it is possible to realize a small-sized laminated balun including an unbalanced terminal and two pairs of balanced terminals and having a small signal insertion loss.
  • the plurality of dielectric layers include a dielectric layer (first dielectric layer) 1k, a dielectric layer (second dielectric layer) 1l, and a dielectric layer (third dielectric layer) 1m that are sequentially stacked.
  • the inductor electrode constituting the unbalanced inductor L2 includes an inductor electrode (first unbalanced inductor conductor pattern) 4d formed between the dielectric layers 1k and 1l.
  • the inductor electrodes 4g and 4h are formed between the dielectric layers 1l and 1m.
  • the plurality of dielectric layers include a dielectric layer (fourth dielectric layer) 1n laminated on the opposite side of the dielectric layer 1m from the dielectric layer 1l.
  • the inductor electrode constituting the unbalanced inductor L2 includes an inductor electrode (second unbalanced inductor conductor pattern) 4j formed between the dielectric layers 1m and 1n in addition to the inductor electrode 4d.
  • the electromagnetic field coupling between the unbalanced inductor L2 and the second inductor portion L32 of the first balanced inductor constituted by the inductor electrode 4g can be further strengthened.
  • electromagnetic field coupling between the unbalanced inductor L2 and the second inductor portion L42 of the second balanced inductor configured by the inductor electrode 4h can be further strengthened.
  • FIG. 4 is an exploded perspective view showing a modified example of the laminated balun according to the present embodiment.
  • FIG. 4 shows only a part of the dielectric layers constituting the laminated balun.
  • the laminated balun according to the modified example includes a dielectric layer 1q instead of the dielectric layer 1k, and includes dielectric layers 1r and 1s instead of the dielectric layers 1m to 1o. It differs only in the point provided.
  • Inductor electrodes 4c, 4e, and 4q are formed on the upper main surface of the dielectric layer 1q.
  • the dielectric layer 1q differs from the dielectric layer 1k shown in FIG. 3 only in that an inductor electrode 4q is formed instead of the inductor electrode 4d.
  • One end of the inductor electrode 4q is connected to the first ground terminal G1, and the other end of the inductor electrode 4q is connected to one end of the inductor electrode 4c.
  • a via electrode 5a is connected to a connection point between the inductor electrode 4c and the inductor electrode 4q.
  • the inductor electrode 4q is an open ring.
  • a part of the region surrounded by the inductor electrode 4q overlaps the region surrounded by the inductor electrode 4g formed on the upper main surface of the dielectric layer 1l.
  • a part of the region surrounded by the inductor electrode 4q overlaps the region surrounded by the inductor electrode 4h formed on the upper main surface of the dielectric layer 11.
  • Inductor electrodes 4i, 4k, 4l are formed on the upper main surface of the dielectric layer 1r.
  • the dielectric layer 1r differs from the dielectric layer 1m shown in FIG. 3 only in that the inductor electrode 4j is not formed.
  • Inductor electrodes 4n, 4o, 4r are formed on the upper main surface of the dielectric layer 1s.
  • the dielectric layer 1s differs from the dielectric layer 1n shown in FIG. 3 only in that an inductor electrode 4r is formed instead of the inductor electrode 4m.
  • One end of the inductor electrode 4r is connected to the unbalanced terminal UB.
  • the other end of the inductor electrode 4r is connected to the other end of the inductor electrode 4i by a via electrode 5p that penetrates the dielectric layer 1s.
  • the inductor electrodes 4q and 4r can be formed of, for example, Ag, Cu, or a metal mainly composed of these alloys.
  • the unbalanced inductor L2 is a line that starts from one end of the inductor electrode 4c that is the end point of the first inductor L1, passes through the inductor electrode 4q, and ends at the first ground terminal G1. It is formed.
  • the inductor electrode 4q constituting the unbalanced inductor L2 is formed between the dielectric layer (first dielectric layer) 1q and the dielectric layer 1l.
  • a dielectric layer (third dielectric layer) 1r laminated on the inductor electrodes 4g and 4i and a dielectric layer laminated on the opposite side of the dielectric layer 1l of the dielectric layer 1r (The inductor electrode constituting the unbalanced inductor L2 is not formed between the fourth dielectric layer) 1s.
  • the number of inductor electrodes constituting the unbalanced inductor L2 can be reduced, and the laminated balun can be reduced in height.
  • FIG. 5 is an exploded perspective view showing a part of another modified example of the laminated balun. In FIG. 5, other than the dielectric layer on which the inductor electrode constituting the unbalanced inductor L2, the second inductor portion L32 of the first balanced inductor, and the second inductor portion L42 of the second balanced inductor is formed. The dielectric layer is omitted.
  • the stacked body constituting the stacked balun includes adjacent dielectric layers 1t and 1u.
  • the inductor electrode 4s formed on the upper main surface of the dielectric layer 1t constitutes an unbalanced inductor L2.
  • the inductor electrode 4s has a shape in which two open annular portions 4s1 and 4s2 are connected.
  • the inductor electrode 4t formed on the upper main surface of the dielectric layer 1u constitutes the second inductor portion L32 of the first balanced-side inductor and has an open annular shape.
  • the inductor electrode 4u formed on the upper main surface of the same dielectric layer 1u constitutes the second inductor portion L42 of the second balanced-side inductor and has an open annular shape.
  • the inductor electrodes 4s to 4u can be made of, for example, Ag, Cu, or a metal mainly composed of these alloys.
  • at least a part of the region surrounded by the inductor electrode 4t overlaps the region surrounded by the one annular portion 4s1 in the inductor electrode 4s.
  • at least a part of the region surrounded by the inductor electrode 4u overlaps the region surrounded by the other annular portion 4s2 in the inductor electrode 4s.
  • the unbalanced inductor L2 can be electromagnetically coupled to each of the second inductor portion L32 of the first balanced side inductor and the second inductor portion L42 of the second balanced side inductor.
  • the unbalanced inductor L2 is connected in parallel with the second capacitor C2, but may be connected in series with the capacitor.
  • the unbalanced inductor L2 and the capacitor may be connected in series in this order between the other end of the first inductor L1 and the ground.
  • the laminated balun 100 can also be expressed as follows.
  • the laminated balun 100 includes one unbalanced terminal UB, a first balanced terminal Tx having a first terminal Tx1 and a second terminal Tx2, and a second balanced terminal having a first terminal Rx1 and a second terminal Rx2. Rx.
  • An unbalanced inductor L2 is inserted between the unbalanced terminal UB and the ground, a first balanced inductor is inserted between the first terminal Tx1 and the second terminal Tx2 of the first balanced terminal Tx, A second balanced-side inductor is inserted between the first terminal Rx1 and the second terminal Rx2 of the two balanced terminals Rx.
  • the unbalanced inductor L2 is electromagnetically coupled to both the first balanced inductor and the second balanced inductor.
  • a low-pass filter is inserted between the unbalanced terminal UB and the unbalanced inductor L2.
  • the low-pass filter includes a first inductor L1, a first capacitor C1 inserted between one end of the first inductor L1 and the ground, and a second capacitor inserted between the other end of the first inductor L1 and the ground. C2.
  • the unbalanced inductor L2 is preferably connected in parallel with the second capacitor C2. In this case, the frequency band of the signal passing between the unbalanced terminal UB and the first balanced terminal Tx and the signal passing between the unbalanced terminal UB and the second balanced terminal Rx by the low-pass filter. The frequency band can be adjusted.
  • the third capacitor C3 is connected in parallel with the first inductor L1 of the low-pass filter.
  • a trap can be formed on the high frequency side outside the pass band of the low-pass filter, and the function of the low-pass filter can be improved.
  • a fourth capacitor C4 is further inserted between the first terminal Tx1 and the second terminal Tx2 of the first balanced terminal Tx, and between the first terminal Rx1 and the second terminal Rx2 of the second balanced terminal Rx, Furthermore, it is preferable that the fifth capacitor C5 is inserted.
  • the first parallel-side inductor and the fourth capacitor C4 constitute an LC parallel resonator.
  • the second balanced-side inductor and the fifth capacitor C5 constitute an LC parallel resonator.
  • the LC parallel resonator composed of the first balanced-side inductor and the fourth capacitor C4 is the LC parallel resonator formed by the unbalanced-side inductor L2 and the second capacitor C2 described above.
  • the first band pass filter is configured independently.
  • the first band-pass filter passes only a signal in an arbitrarily selected frequency band between the unbalanced terminal UB and the first balanced terminal Tx.
  • the LC parallel resonator constituted by the second balanced-side inductor and the fifth capacitor C5 is an LC parallel resonator when the above-described unbalanced-side inductor L2 and the second capacitor C2 constitute an LC parallel resonator.
  • a second band pass filter is configured independently.
  • the second band pass filter passes only a signal in an arbitrarily selected frequency band between the unbalanced terminal UB and the second balanced terminal Rx. Even when the fourth capacitor C4 and the fifth capacitor C5 are not inserted, the LC parallel resonator constituted by the unbalanced inductor L2 and the second capacitor C2 described above can be used as a bandpass filter or Functions as part of a bandpass filter.
  • the first balanced inductor includes a first inductor portion L31, a second inductor portion L32, and a third inductor portion L33 connected in series in order.
  • the unbalanced inductor L2 is mainly electromagnetically coupled to the second inductor portion L32 of the first balanced inductor.
  • the second balanced-side inductor includes a first inductor portion L41, a second inductor portion L42, and a third inductor portion L43 that are connected in series in order. It is preferable that the unbalanced inductor L2 is mainly electromagnetically coupled to the second inductor portion L42 of the second balanced inductor.
  • the second inductor portion is mainly used for adjusting the electromagnetic field coupling with the unbalanced-side inductor.
  • the first inductor portion and the third inductor portion are mainly used for adjusting the impedance of the first balanced terminal or the second balanced terminal, respectively.
  • a DC feed terminal DCfeed is connected to an intermediate portion of the first balanced inductor.
  • the strength of the Tx signal transmitted from the antenna can be increased by supplying DC power to the DC feed terminal DCfeed.
  • the impedance of the first balanced terminal Tx is different from the impedance of the second balanced terminal Rx.
  • the laminated balun 100 can be connected as it is.
  • the impedance of the first balanced terminal Tx and the impedance of the second balanced terminal Rx can be designed independently of each other.
  • the frequency of the pass band formed between the unbalanced terminal UB and the first balanced terminal Tx is different from the frequency of the pass band formed between the unbalanced terminal UB and the second balanced terminal Rx. Also good.
  • the frequency of the pass band formed between the unbalanced terminal UB and the first balanced terminal Tx is the same as the frequency of the pass band formed between the unbalanced terminal UB and the second balanced terminal Rx. It may be.
  • the laminated balun 100 can be used for TDD (Time Division Duplex) communication.
  • the laminated balun 100 includes a laminated body 1 in which a plurality of dielectric layers are laminated, a plurality of inductor electrodes laminated between the dielectric layers, and a plurality of via electrodes formed through the dielectric layers. Prepare. It is preferable that the unbalanced-side inductor L2, the first balanced-side inductor, and the second balanced-side inductor are respectively formed by the inductor electrode or by the inductor electrode and the via electrode.
  • the multilayer balun 100 further includes a plurality of capacitor electrodes stacked between the dielectric layers, and the first capacitor C1, the second capacitor C2, the third capacitor C3, It is preferable that at least one of the fourth capacitor C4 and the fifth capacitor C5 is formed.
  • an inductor electrode forming the unbalanced inductor L2 is divided into at least an inductor electrode (lower inductor electrode) 4d and an inductor electrode (upper inductor electrode) 4j, and the inductor electrode 4d.
  • the inductor electrode 4j is preferably connected to the via electrode 5i.
  • an inductor electrode 4g that forms the second inductor portion L32 of the first balanced-side inductor and an inductor electrode 4h that forms the second inductor portion L42 of the second balanced-side inductor. Is sandwiched between the inductor electrode 4d and the inductor electrode 4j of the unbalanced inductor L2.
  • the unbalanced inductor L2 and the first balanced inductor can be electromagnetically coupled, and at the same time, the unbalanced inductor L2 and the second balanced inductor can be electromagnetically coupled.
  • the strength of these electromagnetic field couplings can be increased.
  • the inductor electrode 4g constituting the first balanced-side inductor and the inductor electrode 4h constituting the second balanced-side inductor are each formed in an annular shape.
  • the via electrode 5i that connects the inductor electrode 4d and the inductor electrode 4j of the unbalanced inductor L2 is disposed so as to penetrate the inside of the annular portion of the inductor electrode 4g of the second inductor portion L32 of the first balanced inductor.
  • the magnetic flux formed by the via electrode 5i connecting the inductor electrode 4d of the unbalanced inductor and the inductor electrode 4j, and the magnetic flux formed by the inductor electrode 4g of the second inductor portion L32 of the first balanced inductor are orthogonal to each other and their interference is suppressed, it is possible to suppress a decrease in Q in both the unbalanced inductor L2 and the first balanced inductor.

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Abstract

A plurality of inductor electrodes formed between the layers of a laminate (1) includes: inductor electrodes (4d, 4j) electrically connected between an unbalanced terminal (UB) and a first ground terminal (G1); an inductor electrode (4g) electrically connected between a first terminal (Tx1) and a second terminal (Tx2) of a first balanced terminal (Tx); and an inductor electrode (4h) electrically connected between a first terminal (Rx1) and a second terminal (Rx2) of a second balanced terminal (Rx). When viewed from the lamination direction of dielectric layers (1a-1p), the region enclosed by the inductor electrodes (4d, 4j) overlaps the region enclosed by the inductor electrode (4g) and the region enclosed by the inductor electrode (4h). The inductor electrodes (4g, 4h) are formed between the same layers of the laminate (1).

Description

積層バランLaminated balun
 本発明は、不平衡信号と平衡信号との間の信号変換を行なう積層バランに関する。 The present invention relates to a laminated balun that performs signal conversion between an unbalanced signal and a balanced signal.
 通信機器のRF(Radio Frequency)回路およびその周辺回路においては、外部からのノイズの影響を小さくするため、信号線路に平衡線路を用いる場合がある。たとえば、アンテナからRF回路へのRx信号の入力や、RF回路からアンテナへのTx信号の出力を、平衡線路により行なう場合がある。 In the RF (Radio Frequency) circuit of communication equipment and its peripheral circuits, a balanced line may be used as a signal line in order to reduce the influence of external noise. For example, the Rx signal may be input from the antenna to the RF circuit and the Tx signal may be output from the RF circuit to the antenna through a balanced line.
 従来、この場合において、Tx信号の送信とRx信号の受信とを1つのアンテナで共用したい場合、アンテナからの不平衡線路を、ディバイダにより2つの不平衡線路に分岐する必要があった。そして、それぞれの不平衡線路に、たとえば特開2013-138410号公報(特許文献1)に開示されたような積層バランスフィルタを接続し、更に、それぞれの積層バランスフィルタを平衡線路によりRF回路に接続する。 Conventionally, in this case, when it is desired to share the transmission of the Tx signal and the reception of the Rx signal with one antenna, it is necessary to branch the unbalanced line from the antenna into two unbalanced lines by a divider. Then, a multilayer balance filter as disclosed in, for example, Japanese Patent Laid-Open No. 2013-138410 (Patent Document 1) is connected to each unbalanced line, and further, each multilayer balance filter is connected to an RF circuit via a balanced line. To do.
 図6は、特開2013-138410号公報に開示された積層バランスフィルタ200の等価回路図である。積層バランスフィルタ200は、1つの不平衡端子UBと、第1端子B1と第2端子B2とからなる平衡端子Bとを有する。積層バランスフィルタ200は、不平衡端子UBに入力された不平衡信号を平衡端子B(第1端子B1および第2端子B2)から平衡信号として出力し、平衡端子B(第1端子B1および第2端子B2)に入力された平衡信号を不平衡端子UBから不平衡信号として出力する。なお、積層バランスフィルタ200は、複数の誘電体層が積層された積層体の内部にインダクタ導体パターン、キャパシタ導体パターン、グランド導体パターン、ビア導体パターンなどを形成して作製される。不平衡端子UBと平衡端子Bとの間に、LC並列共振器により構成されたバンドパスフィルタLC1,LC2が挿入される。バンドパスフィルタLC1のインダクタL10とバンドパスフィルタLC2のインダクタL20との間に相互インダクタンスM10が発生し、インダクタL20と平衡側のインダクタL30との間に相互インダクタンスM20が発生する。 FIG. 6 is an equivalent circuit diagram of the laminated balance filter 200 disclosed in Japanese Patent Laid-Open No. 2013-138410. The laminated balance filter 200 has one unbalanced terminal UB and a balanced terminal B composed of a first terminal B1 and a second terminal B2. The laminated balance filter 200 outputs the unbalanced signal input to the unbalanced terminal UB as a balanced signal from the balanced terminal B (first terminal B1 and second terminal B2), and the balanced terminal B (first terminal B1 and second terminal). The balanced signal input to the terminal B2) is output as an unbalanced signal from the unbalanced terminal UB. The laminated balance filter 200 is manufactured by forming an inductor conductor pattern, a capacitor conductor pattern, a ground conductor pattern, a via conductor pattern, and the like inside a laminate in which a plurality of dielectric layers are laminated. Between the unbalanced terminal UB and the balanced terminal B, band-pass filters LC1 and LC2 configured by LC parallel resonators are inserted. A mutual inductance M10 is generated between the inductor L10 of the bandpass filter LC1 and the inductor L20 of the bandpass filter LC2, and a mutual inductance M20 is generated between the inductor L20 and the balanced inductor L30.
 図7は、1つのディバイダ300と、2つの積層バランスフィルタ200とを接続して構成した平衡不平衡変換回路の一例を示す図である。 FIG. 7 is a diagram illustrating an example of a balanced / unbalanced conversion circuit configured by connecting one divider 300 and two stacked balanced filters 200.
 ディバイダ300は、第1端子101、第2端子102、第3端子103を備え、第1端子101に入力された信号を分配して第2端子102、第3端子103から出力し、第2端子102、第3端子103に入力された信号を合成して第1端子から出力する。 The divider 300 includes a first terminal 101, a second terminal 102, and a third terminal 103. The divider 300 distributes a signal input to the first terminal 101 and outputs the signal from the second terminal 102 and the third terminal 103. 102, the signals input to the third terminal 103 are combined and output from the first terminal.
 この平衡不平衡変換回路においては、アンテナAntとディバイダ300の第1端子101とが不平衡線路により接続される。ディバイダ300の第2端子102と一方の積層バランスフィルタ200の不平衡端子UBとが不平衡線路により接続されるとともに、ディバイダ300の第3端子103と他方の積層バランスフィルタ200の不平衡端子UBとが不平衡線路により接続される。更に、一方の積層バランスフィルタ200の平衡端子B(第1端子B1および第2端子B2)にTx側の平衡線路が接続され、他方の積層バランスフィルタ200の平衡端子B(第1端子B1および第2端子B2)にRx側の平衡線路が接続される。 In this balanced / unbalanced conversion circuit, the antenna Ant and the first terminal 101 of the divider 300 are connected by an unbalanced line. The second terminal 102 of the divider 300 and the unbalanced terminal UB of one laminated balance filter 200 are connected by an unbalanced line, and the third terminal 103 of the divider 300 and the unbalanced terminal UB of the other laminated balance filter 200 are connected to each other. Are connected by an unbalanced line. Further, a balanced line on the Tx side is connected to the balanced terminal B (first terminal B1 and second terminal B2) of one multilayer balanced filter 200, and the balanced terminal B (first terminal B1 and first terminal B1) of the other multilayer balanced filter 200 is connected. A balanced line on the Rx side is connected to the two terminals B2).
特開2013-138410号公報JP 2013-138410 A
 図7に示した平衡不平衡変換回路のように、Tx信号のRF回路からの出力とRx信号のRF回路への入力とを平衡線路により行ない、かつ、Tx信号の送信とRx信号の受信とを1つのアンテナAntで共用するために、1つのディバイダ300と2つの積層バランスフィルタ200とを使用する従来の方法には、次のような問題があった。 Like the balance-unbalance conversion circuit shown in FIG. 7, the output of the Tx signal from the RF circuit and the input of the Rx signal to the RF circuit are performed by a balanced line, and the transmission of the Tx signal and the reception of the Rx signal are performed. In the conventional method using one divider 300 and two laminated balance filters 200 in order to share one antenna Ant, there are the following problems.
 まず、アンテナAntに接続された信号線路をディバイダ300により分岐しているため、信号に挿入損失が発生するという問題があった。たとえば、アンテナAntからRF回路に送られるRx信号は、ディバイダを通過することにより、約3dB減衰してしまっていた。更に、各積層バランスフィルタ200においても挿入損失が発生するため、総合的な挿入損失が大きくなってしまうという問題があった。 First, since the signal line connected to the antenna Ant is branched by the divider 300, there is a problem that insertion loss occurs in the signal. For example, the Rx signal sent from the antenna Ant to the RF circuit has been attenuated by about 3 dB by passing through the divider. Furthermore, since each insertion balance filter 200 also has an insertion loss, there is a problem that the total insertion loss becomes large.
 更に、1つのディバイダ300と2つの積層バランスフィルタ200を使用しなければならず、部品点数が多いため、通信機器内に大きな実装スペースを必要とし、通信機器が大きくなってしまうという問題があった。更に、部品点数が多いため、製造が煩雑化してしまうという問題があった。 Furthermore, since one divider 300 and two laminated balance filters 200 must be used and the number of parts is large, there is a problem that a large mounting space is required in the communication device and the communication device becomes large. . Furthermore, since there are many parts, there existed a problem that manufacture became complicated.
 本開示は、上記課題を解決するためになされたものであって、不平衡端子と2対の平衡端子とを備えた、小型で、信号の挿入損失が小さい積層バランを提供することを目的とする。 The present disclosure has been made to solve the above-described problem, and an object thereof is to provide a small-sized laminated balun including an unbalanced terminal and two pairs of balanced terminals and having a small signal insertion loss. To do.
 本開示のある局面に従う積層バランは、複数の誘電体層が積層された積層体と、前記積層体の層間に形成された複数のインダクタ導体パターンと、前記積層体の表面に形成された複数の端子とを備える。前記複数の端子は、不平衡端子と、第1平衡端子と、第2平衡端子と、グランド端子とを含む。前記第1平衡端子と前記第2平衡端子との各々は、第1端子と第2端子とを有する。前記複数のインダクタ導体パターンは、前記不平衡端子と前記グランド端子との間に電気的に接続された少なくとも1つの不平衡側インダクタ導体パターンと、前記第1平衡端子の前記第1端子と前記第1平衡端子の前記第2端子との間に電気的に接続された第1平衡側インダクタ導体パターンと、前記第2平衡端子の前記第1端子と前記第2平衡端子の前記第2端子との間に電気的に接続された第2平衡側インダクタ導体パターンとを含む。前記複数の誘電体層の積層方向から見たとき、前記第1平衡側インダクタ導体パターンによって囲まれた領域の少なくとも一部分は、前記少なくとも1つの不平衡側インダクタ導体パターンによって囲まれた領域と重なり、かつ前記第2平衡側インダクタ導体パターンによって囲まれた領域の少なくとも一部分は、前記少なくとも1つの不平衡側インダクタ導体パターンによって囲まれた領域と重なる。前記第1平衡側インダクタ導体パターンと前記第2平衡側インダクタ導体パターンとは、前記積層体の同一の層間に形成される。 A multilayer balun according to an aspect of the present disclosure includes a multilayer body in which a plurality of dielectric layers are stacked, a plurality of inductor conductor patterns formed between layers of the multilayer body, and a plurality of layers formed on a surface of the multilayer body. Terminal. The plurality of terminals include an unbalanced terminal, a first balanced terminal, a second balanced terminal, and a ground terminal. Each of the first balanced terminal and the second balanced terminal has a first terminal and a second terminal. The plurality of inductor conductor patterns include at least one unbalanced inductor conductor pattern electrically connected between the unbalanced terminal and the ground terminal, the first terminal of the first balanced terminal, and the first terminal. A first balanced-side inductor conductor pattern electrically connected between the first balanced terminal and the second terminal; and the second balanced terminal first terminal and the second balanced terminal second terminal. And a second balanced inductor conductor pattern electrically connected therebetween. When viewed from the stacking direction of the plurality of dielectric layers, at least a part of a region surrounded by the first balanced-side inductor conductor pattern overlaps a region surrounded by the at least one unbalanced-side inductor conductive pattern, At least a part of the region surrounded by the second balanced inductor conductor pattern overlaps the region surrounded by the at least one unbalanced inductor conductor pattern. The first balanced inductor conductor pattern and the second balanced inductor conductor pattern are formed between the same layers of the multilayer body.
 好ましくは、前記複数の誘電体層は、連続して順に積層された第1~第3誘電体層を含む。前記少なくとも1つの不平衡側インダクタ導体パターンは、前記第1誘電体層と前記第2誘電体層との間に形成されたインダクタ導体パターンを含む。前記第1平衡側インダクタ導体パターンと前記第2平衡側インダクタ導体パターンとは、前記第2誘電体層と前記第3誘電体層との間に形成される。 Preferably, the plurality of dielectric layers include first to third dielectric layers that are successively stacked. The at least one unbalanced inductor conductor pattern includes an inductor conductor pattern formed between the first dielectric layer and the second dielectric layer. The first balanced-side inductor conductor pattern and the second balanced-side inductor conductor pattern are formed between the second dielectric layer and the third dielectric layer.
 好ましくは、前記複数の誘電体層は、前記第3誘電体層の前記第2誘電体層とは反対側に積層された第4誘電体層を含む。前記少なくとも1つの不平衡側インダクタ導体パターンは、第1不平衡側インダクタ導体パターンと第2不平衡側インダクタ導体パターンとを含む。前記第1不平衡側インダクタ導体パターンは、前記第1誘電体層と前記第2誘電体層との間に形成される。前記第2不平衡側インダクタ導体パターンは、前記第3誘電体層と第4誘電体層との間に形成される。 Preferably, the plurality of dielectric layers include a fourth dielectric layer stacked on the opposite side of the third dielectric layer from the second dielectric layer. The at least one unbalanced inductor conductor pattern includes a first unbalanced inductor conductor pattern and a second unbalanced inductor conductor pattern. The first unbalanced inductor conductor pattern is formed between the first dielectric layer and the second dielectric layer. The second unbalanced inductor conductor pattern is formed between the third dielectric layer and the fourth dielectric layer.
 好ましくは、少なくとも1つの不平衡側インダクタ導体パターンは、2つの開いた環状部分を連結させた形状を有する。第1平衡側インダクタ導体パターンによって囲まれた領域の少なくとも一部分は、少なくとも1つの不平衡側インダクタ導体パターンの一方の環状部分によって囲まれた領域と重なる。第2平衡側インダクタ導体パターンによって囲まれた領域の少なくとも一部分は、少なくとも1つの不平衡側インダクタ導体パターンの他方の環状部分によって囲まれた領域と重なる。 Preferably, at least one unbalanced inductor conductor pattern has a shape in which two open annular portions are connected. At least a part of a region surrounded by the first balanced-side inductor conductor pattern overlaps a region surrounded by one annular portion of at least one unbalanced-side inductor conductor pattern. At least a portion of the region surrounded by the second balanced-side inductor conductor pattern overlaps with the region surrounded by the other annular portion of the at least one unbalanced-side inductor conductor pattern.
 本開示の積層バランは、不平衡端子と2対の平衡端子とを備えているが、ディバイダを使用していないため、ディバイダを通過することによる信号の挿入損失がなく、総合的な挿入損失が小さい。 Although the multilayer balun of the present disclosure includes an unbalanced terminal and two pairs of balanced terminals, since no divider is used, there is no signal insertion loss due to passing through the divider, and overall insertion loss is reduced. small.
 更に、本開示の積層バランは、従来、1つのディバイダと2つのバランを使用して果たしていた機能を、1つのバランで果たすようにしたものであり、小型化が図られている。したがって、本開示の積層バランが実装される通信機器においては、実装に要するスペースを小さくすることができる。 Furthermore, the multilayer balun according to the present disclosure is configured such that the function conventionally performed by using one divider and two baluns is performed by one balun, and the size is reduced. Therefore, in a communication device in which the multilayer balun of the present disclosure is mounted, the space required for mounting can be reduced.
本発明の実施の形態にかかる積層バランの等価回路図である。1 is an equivalent circuit diagram of a laminated balun according to an embodiment of the present invention. 積層バランの外観斜視図である。It is an external appearance perspective view of a laminated balun. 積層バランの分解斜視図である。It is a disassembled perspective view of a laminated balun. 積層バランの変形例を示す分解斜視図である。It is a disassembled perspective view which shows the modification of a laminated balun. 積層バランの別の変形例の一部分を示す分解斜視図である。It is a disassembled perspective view which shows a part of another modification of a lamination | stacking balun. 特許文献1に記載された積層バランスフィルタの等価回路図である。6 is an equivalent circuit diagram of a multilayer balance filter described in Patent Document 1. FIG. 1つのディバイダと、2つの積層バランスフィルタとを接続して構成した平衡不平衡変換回路の一例を示す等価回路図である。It is an equivalent circuit diagram showing an example of a balun circuit configured by connecting one divider and two laminated balance filters.
 本発明の実施の形態について、図面を参照しながら詳細に説明する。なお、図中の同一または相当部分については、同一符号を付してその説明は繰返さない。なお、各実施形態は、本発明の実施の形態を例示的に示したものであり、本発明が実施形態の内容に限定されることはない。また、異なる実施形態に記載された内容を組合せて実施することも可能であり、その場合の実施内容も本発明に含まれる。また、図面は、実施形態の理解を助けるためのものであり、必ずしも厳密に描画されていない場合がある。たとえば、描画された構成要素ないし構成要素間の寸法の比率が、明細書に記載されたそれらの寸法の比率と一致していない場合がある。また、明細書に記載されている構成要素が、図面において省略されている場合や、個数を省略して描画されている場合などがある。 Embodiments of the present invention will be described in detail with reference to the drawings. Note that the same or corresponding parts in the drawings are denoted by the same reference numerals and description thereof will not be repeated. Each embodiment shows an embodiment of the present invention exemplarily, and the present invention is not limited to the content of the embodiment. Moreover, it is also possible to implement combining the content described in different embodiment, and the implementation content in that case is also included in this invention. Further, the drawings are for helping understanding of the embodiment, and may not be drawn strictly. For example, a drawn component or a dimensional ratio between the components may not match the dimensional ratio described in the specification. In addition, the constituent elements described in the specification may be omitted in the drawings or may be drawn with the number omitted.
 図1~図3に、本発明の実施形態にかかる積層バラン100を示す。ただし、図1は、本発明の実施の形態にかかる積層バラン100の等価回路図である。図2は、積層バラン100の外観斜視図である。図3は、積層バラン100の分解斜視図である。 1 to 3 show a laminated balun 100 according to an embodiment of the present invention. However, FIG. 1 is an equivalent circuit diagram of the laminated balun 100 according to the embodiment of the present invention. FIG. 2 is an external perspective view of the laminated balun 100. FIG. 3 is an exploded perspective view of the laminated balun 100.
 まず、図1を参照して、積層バラン100の等価回路について説明する。積層バラン100は、1つの不平衡端子UBを備える。積層バラン100は、第1端子Tx1と第2端子Tx2とを備えた第1平衡端子Txと、第1端子Rx1と第2端子Rx2とを備えた第2平衡端子Rxとを備える。なお、本実施形態においては、2対の平衡端子を、便宜上、第1平衡端子Txと第2平衡端子Rxとして示しているが、各平衡端子の用途は任意であり、第1平衡端子をTx端子として、第2平衡端子をRx端子として使用することに限定されるものではない。 First, an equivalent circuit of the laminated balun 100 will be described with reference to FIG. The laminated balun 100 includes one unbalanced terminal UB. The laminated balun 100 includes a first balanced terminal Tx having a first terminal Tx1 and a second terminal Tx2, and a second balanced terminal Rx having a first terminal Rx1 and a second terminal Rx2. In the present embodiment, two pairs of balanced terminals are shown as a first balanced terminal Tx and a second balanced terminal Rx for convenience, but the usage of each balanced terminal is arbitrary, and the first balanced terminal is designated as Tx. The terminal is not limited to using the second balanced terminal as the Rx terminal.
 積層バラン100は、ローパスフィルタを備える。ローパスフィルタは、第1インダクタL1と、第1インダクタL1の一端とグランドとの間に挿入された第1キャパシタC1と、第1インダクタL1の他端とグランドとの間に挿入された第2キャパシタC2とで構成される。そして第1インダクタL1の一端(第1キャパシタC1の一端)は、不平衡端子UBに接続される。このローパスフィルタにより、積層バラン100は、任意に選択した周波数帯の信号のみを通過させることができる。 The laminated balun 100 includes a low-pass filter. The low-pass filter includes a first inductor L1, a first capacitor C1 inserted between one end of the first inductor L1 and the ground, and a second capacitor inserted between the other end of the first inductor L1 and the ground. And C2. One end of the first inductor L1 (one end of the first capacitor C1) is connected to the unbalanced terminal UB. With this low-pass filter, the laminated balun 100 can pass only signals in an arbitrarily selected frequency band.
 なお、本実施形態においては、ローパスフィルタとしてπ型のローパスフィルタを採用したが、ローパスフィルタの種類はπ型には限られず、他の種類のものであっても良い。 In this embodiment, a π-type low-pass filter is employed as the low-pass filter, but the type of the low-pass filter is not limited to the π-type, and other types may be used.
 積層バラン100は、ローパスフィルタの第1インダクタL1と並列に接続された第3キャパシタC3を備える。第3キャパシタC3は、ローパスフィルタの通過帯域外の高周波側にトラップを形成するためのものであり、ローパスフィルタの機能を向上させるためのものである。 The multilayer balun 100 includes a third capacitor C3 connected in parallel with the first inductor L1 of the low-pass filter. The third capacitor C3 is for forming a trap on the high frequency side outside the pass band of the low-pass filter, and for improving the function of the low-pass filter.
 積層バラン100は、不平衡側インダクタL2を備える。不平衡側インダクタL2は、ローパスフィルタの第2キャパシタC2と並列に接続されている。そして、並列に接続された不平衡側インダクタL2と第2キャパシタC2とは、LC並列共振器を構成する。 The multilayer balun 100 includes an unbalanced inductor L2. The unbalanced inductor L2 is connected in parallel with the second capacitor C2 of the low pass filter. The unbalanced inductor L2 and the second capacitor C2 connected in parallel constitute an LC parallel resonator.
 積層バラン100は、第1インダクタ部L31、第2インダクタ部L32、第3インダクタ部L33が直列に接続された、第1平衡側インダクタを備える。第1平衡側インダクタは、第1平衡端子Txの第1端子Tx1と第2端子Tx2との間に接続されている。なお、本実施形態においては、第2インダクタ部L32の中間部分に、DCフィード端子DCfeedが接続されている。 The multilayer balun 100 includes a first balanced-side inductor in which a first inductor portion L31, a second inductor portion L32, and a third inductor portion L33 are connected in series. The first balanced-side inductor is connected between the first terminal Tx1 and the second terminal Tx2 of the first balanced terminal Tx. In the present embodiment, a DC feed terminal DCfeed is connected to an intermediate portion of the second inductor portion L32.
 更に、積層バラン100は、第1インダクタ部L41、第2インダクタ部L42、第3インダクタ部L43が直列に接続された、第2平衡側インダクタを備える。第2平衡側インダクタは、第2平衡端子Rxの第1端子Rx1と第2端子Rx2との間に接続されている。 Furthermore, the multilayer balun 100 includes a second balanced-side inductor in which a first inductor portion L41, a second inductor portion L42, and a third inductor portion L43 are connected in series. The second balanced-side inductor is connected between the first terminal Rx1 and the second terminal Rx2 of the second balanced terminal Rx.
 不平衡側インダクタL2は、第1平衡側インダクタと電磁界結合している。不平衡側インダクタL2は、第1平衡側インダクタの第2インダクタ部L32と電磁界結合している。すなわち、不平衡側インダクタL2と第1平衡側インダクタの第2インダクタ部L32との間には相互インダクタンスM1が発生する。 The unbalanced inductor L2 is electromagnetically coupled to the first balanced inductor. The unbalanced inductor L2 is electromagnetically coupled to the second inductor portion L32 of the first balanced inductor. That is, a mutual inductance M1 is generated between the unbalanced inductor L2 and the second inductor portion L32 of the first balanced inductor.
 更に、不平衡側インダクタL2は、第2平衡側インダクタと電磁界結合している。不平衡側インダクタL2は、第2平衡側インダクタの第2インダクタ部L42と電磁界結合している。すなわち、不平衡側インダクタL2と第2平衡側インダクタの第2インダクタ部L42との間には相互インダクタンスM2が発生する。 Furthermore, the unbalanced inductor L2 is electromagnetically coupled to the second balanced inductor. The unbalanced inductor L2 is electromagnetically coupled to the second inductor portion L42 of the second balanced inductor. That is, a mutual inductance M2 is generated between the unbalanced inductor L2 and the second inductor portion L42 of the second balanced inductor.
 積層バラン100は、更に、第1平衡端子Txの第1端子Tx1と第2端子Tx2との間に挿入された第4キャパシタC4を備える。 The multilayer balun 100 further includes a fourth capacitor C4 inserted between the first terminal Tx1 and the second terminal Tx2 of the first balanced terminal Tx.
 第4キャパシタC4は、第1平衡側インダクタ(L31,L32,L33)とでLC並列共振器を構成し、上述した不平衡側インダクタL2と第2キャパシタC2とで構成されたLC並列共振器と共働して、第1バンドパスフィルタを構成している。第1バンドパスフィルタは、任意に選択した周波数帯の信号のみを、不平衡端子UBと第1平衡端子Txとの間に通過させる。 The fourth capacitor C4 forms an LC parallel resonator with the first balanced inductors (L31, L32, L33), and the LC parallel resonator formed with the unbalanced inductor L2 and the second capacitor C2 described above. Together, they constitute a first band pass filter. The first band pass filter passes only a signal in an arbitrarily selected frequency band between the unbalanced terminal UB and the first balanced terminal Tx.
 なお、積層バラン100においては、第1平衡側インダクタ(L31,L32,L33)および第4キャパシタC4の定数を選定することにより、第1平衡端子Tx(Tx1,Tx2)側のインピーダンスを調整することができる。 In the multilayer balun 100, the impedance on the first balanced terminal Tx (Tx1, Tx2) side is adjusted by selecting the constants of the first balanced inductors (L31, L32, L33) and the fourth capacitor C4. Can do.
 積層バラン100は、更に、第2平衡端子Rxの第1端子Rx1と第2端子Rx2との間に挿入された第5キャパシタC5を備える。 The multilayer balun 100 further includes a fifth capacitor C5 inserted between the first terminal Rx1 and the second terminal Rx2 of the second balanced terminal Rx.
 第5キャパシタC5は、第2平衡側インダクタ(L41,L42,L43)とでLC並列共振器を構成し、上述した不平衡側インダクタL2と第2キャパシタC2とで構成されたLC並列共振器と共働して、第2バンドパスフィルタを構成している。第2バンドパスフィルタは、任意に選択した周波数帯の信号のみを、不平衡端子UBと第2平衡端子Rxとの間に通過させる。 The fifth capacitor C5 forms an LC parallel resonator with the second balanced-side inductors (L41, L42, L43), and the LC parallel resonator configured with the unbalanced-side inductor L2 and the second capacitor C2 described above. Together, they constitute a second bandpass filter. The second band pass filter passes only a signal in an arbitrarily selected frequency band between the unbalanced terminal UB and the second balanced terminal Rx.
 なお、積層バラン100においては、第2平衡側インダクタ(L41,L42,L43)および第5キャパシタC5の定数を選定することにより、第2平衡端子Rx(Rx1,Rx2)側のインピーダンスを調整することができる。 In the multilayer balun 100, the impedance of the second balanced terminal Rx (Rx1, Rx2) side is adjusted by selecting the constants of the second balanced inductors (L41, L42, L43) and the fifth capacitor C5. Can do.
 以上の等価回路からなる積層バラン100は、第1平衡端子Txに入力された平衡信号を、不平衡端子UBから不平衡信号として出力することができる。なお、DCフィード端子DCfeedに直流電力を供給すれば、不平衡端子UBから出力される不平衡信号の強度を高めることができる。更に、不平衡端子UBに入力された不平衡信号を、第2平衡端子Rxから平衡信号として出力することができる。 The laminated balun 100 composed of the above equivalent circuits can output the balanced signal input to the first balanced terminal Tx as an unbalanced signal from the unbalanced terminal UB. Note that if DC power is supplied to the DC feed terminal DCfeed, the strength of the unbalanced signal output from the unbalanced terminal UB can be increased. Furthermore, the unbalanced signal input to the unbalanced terminal UB can be output as a balanced signal from the second balanced terminal Rx.
 なお、第1平衡端子Txの第1端子Tx1と第2端子Tx2とには、相互に位相が180度異なり、振幅がほぼ等しい平衡信号が入力される。更に、第2平衡端子Rxの第1端子Rx1と第2端子Rx2からは、相互に位相が180度異なり、振幅がほぼ等しい平衡信号が出力される。 Note that balanced signals having substantially the same amplitude and different phases are input to the first terminal Tx1 and the second terminal Tx2 of the first balanced terminal Tx. Furthermore, balanced signals having substantially the same amplitude and different phases are output from the first terminal Rx1 and the second terminal Rx2 of the second balanced terminal Rx.
 以上の等価回路からなる積層バラン100は、たとえば、図2および図3に示す積層体1により構成することができる。積層バラン100は、複数の誘電体層が積層された積層体1と、積層体1の表面に形成された複数の端子とを備える。複数の端子は、直方体形状の積層体1の最も面積の大きい一対の主面を上面および底面としたときの側面に形成される。 The laminated balun 100 composed of the above equivalent circuits can be constituted by, for example, the laminated body 1 shown in FIGS. The laminated balun 100 includes a laminated body 1 in which a plurality of dielectric layers are laminated, and a plurality of terminals formed on the surface of the laminated body 1. The plurality of terminals are formed on the side surfaces when the pair of main surfaces having the largest area of the rectangular parallelepiped laminated body 1 are the upper surface and the bottom surface.
 積層体1は、下から順に、たとえばセラミックからなる誘電体層1a~1pが積層されたものからなる。 The laminated body 1 is formed by laminating dielectric layers 1a to 1p made of ceramic, for example, in order from the bottom.
 図2に示すように、積層体1の表面には、不平衡端子UB、第1平衡端子Txの第1端子Tx1および第2端子Tx2、第2平衡端子Rxの第1端子Rx1および第2端子Rx2、第1グランド端子G1、第2グランド端子G2、DCフィード端子DCfeed、第1浮遊端子F1、第2浮遊端子F2が形成されている。具体的には、図2における積層体1の手前側の側面に、時計回り方向に見て、順に、第1浮遊端子F1、第2浮遊端子F2、第1グランド端子G1、不平衡端子UBが形成される。図2における積層体1の左側の側面に第2グランド端子G2が形成される。図2における積層体1の奥側の側面に、時計回り方向に見て、順に、第1平衡端子Txの第1端子Tx1、第2端子Tx2、第2平衡端子Rxの第1端子Rx1、第2端子Rx2が形成される。図2における積層体1の右側の側面にDCフィード端子DCfeedが形成される。なお、各端子の両端は、積層体1の下側の主面および上側の主面に、それぞれ延出して形成される。 As shown in FIG. 2, on the surface of the laminated body 1, unbalanced terminals UB, first terminals Tx1 and second terminals Tx2 of the first balanced terminal Tx, first terminals Rx1 and second terminals of the second balanced terminal Rx are provided. Rx2, a first ground terminal G1, a second ground terminal G2, a DC feed terminal DCfeed, a first floating terminal F1, and a second floating terminal F2 are formed. Specifically, the first floating terminal F1, the second floating terminal F2, the first ground terminal G1, and the unbalanced terminal UB are sequentially arranged on the side surface on the near side of the stacked body 1 in FIG. It is formed. A second ground terminal G2 is formed on the left side surface of the multilayer body 1 in FIG. 2, the first terminal Tx1 of the first balanced terminal Tx, the second terminal Tx2, the first terminal Rx1 of the second balanced terminal Rx, the first terminal Rx1, the second balanced terminal Rx, and so on. Two terminals Rx2 are formed. A DC feed terminal DCfeed is formed on the right side surface of the laminate 1 in FIG. Note that both ends of each terminal are formed to extend on the lower main surface and the upper main surface of the laminate 1, respectively.
 第1浮遊端子F1、第2浮遊端子F2は、積層体1の内部において回路には接続されておらず、積層バラン100を実装する際に、基板などのランド電極に接合され、実装強度を高めるために利用される。 The first floating terminal F1 and the second floating terminal F2 are not connected to a circuit inside the stacked body 1, and are bonded to a land electrode such as a substrate when the stacked balun 100 is mounted, thereby increasing mounting strength. Used for.
 不平衡端子UB、第1平衡端子Txの第1端子Tx1および第2端子Tx2、第2平衡端子Rxの第1端子Rx1および第2端子Rx2、第1グランド端子G1、第2グランド端子G2、DCフィード端子DCfeed、第1浮遊端子F1、第2浮遊端子F2は、それぞれ、たとえば、Ag、Cuや、これらの合金などを主成分とする金属により形成することができる。これらの端子の表面には、必要に応じて、Ni、Sn、Auなどを主成分にするめっき層を、1層または複数層にわたって形成しても良い。 Unbalanced terminal UB, first terminal Tx1 and second terminal Tx2 of first balanced terminal Tx, first terminal Rx1 and second terminal Rx2 of second balanced terminal Rx, first ground terminal G1, second ground terminal G2, DC The feed terminal DCfeed, the first floating terminal F1, and the second floating terminal F2 can be formed of, for example, a metal whose main component is Ag, Cu, or an alloy thereof. On the surface of these terminals, a plating layer containing Ni, Sn, Au or the like as a main component may be formed over one layer or a plurality of layers as necessary.
 図3に示すように、積層バラン100は、積層体1を構成する誘電体層1a~1pの層間に形成された、キャパシタ導体パターン(以下、単に「キャパシタ電極」という)2a~2q、接続導体パターン(以下、単に「接続電極」という)3a、インダクタ導体パターン(以下、単に「インダクタ電極」という)4a~4pを備える。更に、積層バラン100は、積層体1の内部において誘電体層1a~1pの積層方向に形成されたビア導体パターン(以下、単に「ビア電極」という)5a~5pを備える。 As shown in FIG. 3, the laminated balun 100 includes capacitor conductor patterns (hereinafter simply referred to as “capacitor electrodes”) 2a to 2q, connecting conductors formed between the dielectric layers 1a to 1p constituting the laminated body 1. A pattern (hereinafter simply referred to as “connection electrode”) 3a and an inductor conductor pattern (hereinafter simply referred to as “inductor electrode”) 4a to 4p are provided. Further, the laminated balun 100 includes via conductor patterns (hereinafter simply referred to as “via electrodes”) 5a to 5p formed in the laminated body 1 in the laminating direction of the dielectric layers 1a to 1p.
 具体的には、誘電体層1bの上側の主面には、キャパシタ電極2aと、接続電極3aとが形成される。キャパシタ電極2aは、第2グランド端子G2に接続される。接続電極3aは、DCフィード端子DCfeedに接続される。 Specifically, a capacitor electrode 2a and a connection electrode 3a are formed on the upper main surface of the dielectric layer 1b. The capacitor electrode 2a is connected to the second ground terminal G2. The connection electrode 3a is connected to the DC feed terminal DCfeed.
 誘電体層1cの上側の主面には、キャパシタ電極2bが形成される。キャパシタ電極2bは、不平衡端子UBに接続される。 A capacitor electrode 2b is formed on the upper main surface of the dielectric layer 1c. The capacitor electrode 2b is connected to the unbalanced terminal UB.
 誘電体層1dの上側の主面には、4つのキャパシタ電極2c,2d,2e,2fが形成される。そして、キャパシタ電極2cは第1平衡端子Txの第1端子Tx1に、キャパシタ電極2dは第1平衡端子Txの第2端子Tx2に、キャパシタ電極2eは第2平衡端子Rxの第1端子Rx1に、キャパシタ電極2fは第2平衡端子Rxの第2端子Rx2に、それぞれ接続される。 Four capacitor electrodes 2c, 2d, 2e, 2f are formed on the upper main surface of the dielectric layer 1d. The capacitor electrode 2c is connected to the first terminal Tx1 of the first balanced terminal Tx, the capacitor electrode 2d is connected to the second terminal Tx2 of the first balanced terminal Tx, and the capacitor electrode 2e is connected to the first terminal Rx1 of the second balanced terminal Rx. The capacitor electrode 2f is connected to the second terminal Rx2 of the second balanced terminal Rx.
 誘電体層1eの上側の主面には、2つのキャパシタ電極2g,2hが形成される。
 誘電体層1fの上側の主面には、4つのキャパシタ電極2i,2j,2k,2lが形成される。キャパシタ電極2iは第1平衡端子Txの第1端子Tx1に、キャパシタ電極2jは第1平衡端子Txの第2端子Tx2に、キャパシタ電極2kは第2平衡端子Rxの第1端子Rx1に、キャパシタ電極2lは第2平衡端子Rxの第2端子Rx2に、それぞれ接続される。
Two capacitor electrodes 2g and 2h are formed on the upper main surface of the dielectric layer 1e.
Four capacitor electrodes 2i, 2j, 2k, 2l are formed on the upper main surface of the dielectric layer 1f. The capacitor electrode 2i is connected to the first terminal Tx1 of the first balanced terminal Tx, the capacitor electrode 2j is connected to the second terminal Tx2 of the first balanced terminal Tx, and the capacitor electrode 2k is connected to the first terminal Rx1 of the second balanced terminal Rx. 2l is connected to the second terminal Rx2 of the second balanced terminal Rx, respectively.
 誘電体層1gの上側の主面には、3つのキャパシタ電極2m,2n,2oが形成される。キャパシタ電極2mは、第1グランド端子G1に接続される。 Three capacitor electrodes 2m, 2n, 2o are formed on the upper main surface of the dielectric layer 1g. The capacitor electrode 2m is connected to the first ground terminal G1.
 誘電体層1hの上側の主面には、キャパシタ電極2pが形成される。
 誘電体層1iの上側の主面には、キャパシタ電極2qが形成される。キャパシタ電極2qは、不平衡端子UBに接続される。
A capacitor electrode 2p is formed on the upper main surface of the dielectric layer 1h.
Capacitor electrode 2q is formed on the upper main surface of dielectric layer 1i. The capacitor electrode 2q is connected to the unbalanced terminal UB.
 誘電体層1jの上側の主面には、2つのインダクタ電極4a,4bが形成される。インダクタ電極4aの一端は第1平衡端子Txの第1端子Tx1に、インダクタ電極4bの一端は第2平衡端子Rxの第2端子Rx2に、それぞれ接続される。 Two inductor electrodes 4a and 4b are formed on the upper main surface of the dielectric layer 1j. One end of the inductor electrode 4a is connected to the first terminal Tx1 of the first balanced terminal Tx, and one end of the inductor electrode 4b is connected to the second terminal Rx2 of the second balanced terminal Rx.
 誘電体層1kの上側の主面には、3つのインダクタ電極4c,4d,4eが形成される。インダクタ電極4dは開いた環状である。インダクタ電極4dの一端は、第1グランド端子G1に接続される。 Three inductor electrodes 4c, 4d, and 4e are formed on the upper main surface of the dielectric layer 1k. The inductor electrode 4d has an open ring shape. One end of the inductor electrode 4d is connected to the first ground terminal G1.
 誘電体層1lの上側の主面には、2つのインダクタ電極4f,4g,4hが形成される。インダクタ電極4g,4hは開いた環状である。誘電体層1a~1pの積層方向から見たときに、環状のインダクタ電極4g,4hによって囲まれる領域の各々は、環状のインダクタ電極4dによって囲まれる領域の少なくとも一部と重なる。 Two inductor electrodes 4f, 4g, and 4h are formed on the upper main surface of the dielectric layer 1l. The inductor electrodes 4g and 4h have an open ring shape. When viewed from the stacking direction of the dielectric layers 1a to 1p, each of the regions surrounded by the annular inductor electrodes 4g and 4h overlaps at least a part of the region surrounded by the annular inductor electrode 4d.
 誘電体層1mの上側の主面には、4つのインダクタ電極4i,4j,4k,4lが形成される。インダクタ電極4jは開いた環状である。誘電体層1a~1pの積層方向から見たときに、環状のインダクタ電極4jによって囲まれる領域の少なくとも一部は、環状のインダクタ電極4gによって囲まれる領域と重なる。更に、環状のインダクタ電極4jによって囲まれる領域の少なくとも一部は、環状のインダクタ電極4hによって囲まれる領域と重なる。 Four inductor electrodes 4i, 4j, 4k, 4l are formed on the upper main surface of the dielectric layer 1m. The inductor electrode 4j has an open annular shape. When viewed from the stacking direction of the dielectric layers 1a to 1p, at least a part of the region surrounded by the annular inductor electrode 4j overlaps with the region surrounded by the annular inductor electrode 4g. Furthermore, at least a part of the region surrounded by the annular inductor electrode 4j overlaps with the region surrounded by the annular inductor electrode 4h.
 誘電体層1nの上側の主面には、3つのインダクタ電極4m,4n,4oが形成される。インダクタ電極4nの一端は第1平衡端子Txの第2端子Tx2に、インダクタ電極4oの一端は第2平衡端子Rxの第1端子Rx1に、それぞれ接続される。 Three inductor electrodes 4m, 4n, 4o are formed on the upper main surface of the dielectric layer 1n. One end of the inductor electrode 4n is connected to the second terminal Tx2 of the first balanced terminal Tx, and one end of the inductor electrode 4o is connected to the first terminal Rx1 of the second balanced terminal Rx.
 誘電体層1oの上側の主面には、インダクタ電極4pが形成される。インダクタ電極4pの一端は、不平衡端子UBに接続される。 An inductor electrode 4p is formed on the upper main surface of the dielectric layer 1o. One end of the inductor electrode 4p is connected to the unbalanced terminal UB.
 積層体1内において、ビア電極5aは、誘電体層1i~1kを貫通して、キャパシタ電極2pとインダクタ電極4cの一端とを接続する。なお、ビア電極5aは、後述するビア電極5hと連続して一体的に形成されているが、接続関係を説明する便宜上、当該ビア電極の下側部分を符号5aにより示し、上側部分を符号5hにより示している。 In the laminated body 1, the via electrode 5a penetrates the dielectric layers 1i to 1k and connects the capacitor electrode 2p and one end of the inductor electrode 4c. The via electrode 5a is formed integrally with a via electrode 5h, which will be described later, but for convenience of explaining the connection relationship, the lower portion of the via electrode is denoted by reference numeral 5a and the upper portion is denoted by reference numeral 5h. It shows by.
 ビア電極5bは、誘電体層1kを貫通して、インダクタ電極4bの他端とインダクタ電極4eの一端とを接続する。 The via electrode 5b penetrates the dielectric layer 1k and connects the other end of the inductor electrode 4b and one end of the inductor electrode 4e.
 ビア電極5cは、誘電体層1lを貫通して、インダクタ電極4cの他端とインダクタ電極4fの一端とを接続する。 The via electrode 5c penetrates the dielectric layer 11 and connects the other end of the inductor electrode 4c and one end of the inductor electrode 4f.
 ビア電極5dは、誘電体層1c~1lを貫通して、接続電極3aとインダクタ電極4gの中間部とを接続する。 The via electrode 5d passes through the dielectric layers 1c to 1l and connects the connection electrode 3a and the intermediate portion of the inductor electrode 4g.
 ビア電極5eは、誘電体層1k,1lを貫通して、インダクタ電極4aの他端とインダクタ電極4gの一端とを接続する。 The via electrode 5e passes through the dielectric layers 1k and 1l and connects the other end of the inductor electrode 4a and one end of the inductor electrode 4g.
 ビア電極5fは、誘電体層1lを貫通して、インダクタ電極4eの他端とインダクタ電極4hの一端とを接続する。 The via electrode 5f penetrates the dielectric layer 11 and connects the other end of the inductor electrode 4e and one end of the inductor electrode 4h.
 ビア電極5gは、誘電体層1mを貫通して、インダクタ電極4fの他端とインダクタ電極4iの一端とを接続する。 The via electrode 5g penetrates the dielectric layer 1m and connects the other end of the inductor electrode 4f and one end of the inductor electrode 4i.
 ビア電極5hは、誘電体層1l,1mを貫通して、インダクタ電極4cの一端とインダクタ電極4jの一端とを接続する。 The via electrode 5h penetrates the dielectric layers 11 and 1m and connects one end of the inductor electrode 4c and one end of the inductor electrode 4j.
 ビア電極5iは、誘電体層1l,1mを貫通して、インダクタ電極4dの他端とインダクタ電極4jの他端とを接続する。 The via electrode 5i passes through the dielectric layers 11 and 1m and connects the other end of the inductor electrode 4d and the other end of the inductor electrode 4j.
 ビア電極5jは、誘電体層1mを貫通して、インダクタ電極4gの他端とインダクタ電極4kの一端とを接続する。 The via electrode 5j penetrates the dielectric layer 1m and connects the other end of the inductor electrode 4g and one end of the inductor electrode 4k.
 ビア電極5kは、誘電体層1mを貫通して、インダクタ電極4hの他端とインダクタ電極4lの一端とを接続する。 The via electrode 5k penetrates the dielectric layer 1m and connects the other end of the inductor electrode 4h and one end of the inductor electrode 4l.
 ビア電極5lは、誘電体層1nを貫通して、インダクタ電極4iの他端とインダクタ電極4mの一端とを接続する。 The via electrode 5l penetrates the dielectric layer 1n and connects the other end of the inductor electrode 4i and one end of the inductor electrode 4m.
 ビア電極5mは、誘電体層1nを貫通して、インダクタ電極4kの他端とインダクタ電極4nの他端とを接続する。 The via electrode 5m penetrates the dielectric layer 1n and connects the other end of the inductor electrode 4k and the other end of the inductor electrode 4n.
 ビア電極5nは、誘電体層1nを貫通して、インダクタ電極4lの他端とインダクタ電極4oの他端とを接続する。 The via electrode 5n penetrates the dielectric layer 1n and connects the other end of the inductor electrode 4l and the other end of the inductor electrode 4o.
 ビア電極5oは、誘電体層1oを貫通して、インダクタ電極4mの他端とインダクタ電極4pの他端とを接続する。 The via electrode 5o passes through the dielectric layer 1o and connects the other end of the inductor electrode 4m and the other end of the inductor electrode 4p.
 上述した、キャパシタ電極2a~2q、接続電極3a、インダクタ電極4a~4p、ビア電極5a~5oには、たとえば、Ag、Cuや、これらの合金を主成分とする金属により形成することができる。 The capacitor electrodes 2a to 2q, the connection electrodes 3a, the inductor electrodes 4a to 4p, and the via electrodes 5a to 5o described above can be formed of, for example, Ag, Cu, or a metal mainly composed of these alloys.
 以上の構成からなる、誘電体層が積層された積層体により構成された本実施形態の積層バラン100は、従来から、積層バランを製造するのに使用されている一般的な製造方法により、製造することができる。 The laminated balun 100 of the present embodiment constituted by the laminated body in which the dielectric layers are laminated having the above-described configuration is manufactured by a general manufacturing method conventionally used for manufacturing a laminated balun. can do.
 次に、図1と図3とを対比しながら、積層バラン100の等価回路と、積層体1内における構成との関係について説明する。 Next, the relationship between the equivalent circuit of the laminated balun 100 and the configuration in the laminated body 1 will be described by comparing FIG. 1 and FIG.
 ローパスフィルタは、第1インダクタL1と第1キャパシタC1と第2キャパシタC2とで構成されているが、そのうちの第1インダクタL1は、不平衡端子UBを起点にして、インダクタ電極4p、ビア電極5o、インダクタ電極4m、ビア電極5l、インダクタ電極4i、ビア電極5g、インダクタ電極4f、ビア電極5c、インダクタ電極4cを経由し、インダクタ電極4cの一端を終点とする線路により形成される。 The low-pass filter is composed of a first inductor L1, a first capacitor C1, and a second capacitor C2. The first inductor L1 of which starts from the unbalanced terminal UB, and starts from the inductor electrode 4p and the via electrode 5o. The inductor electrode 4m, the via electrode 5l, the inductor electrode 4i, the via electrode 5g, the inductor electrode 4f, the via electrode 5c, and the inductor electrode 4c are formed by a line having one end of the inductor electrode 4c as an end point.
 ローパスフィルタの第1キャパシタC1は、不平衡端子UBに接続されたキャパシタ電極2bと、第2グランド端子G2に接続されたキャパシタ電極2aとの間に形成される容量により形成される。 The first capacitor C1 of the low-pass filter is formed by a capacitance formed between the capacitor electrode 2b connected to the unbalanced terminal UB and the capacitor electrode 2a connected to the second ground terminal G2.
 ローパスフィルタの第2キャパシタC2は、ビア電極5aにより第1インダクタL1の終点であるインダクタ電極4cの一端と接続されたキャパシタ電極2pと、第1グランド端子G1に接続されたキャパシタ電極2mとの間に形成される容量により形成されている。 The second capacitor C2 of the low-pass filter is between the capacitor electrode 2p connected to one end of the inductor electrode 4c that is the end point of the first inductor L1 by the via electrode 5a and the capacitor electrode 2m connected to the first ground terminal G1. It is formed by the capacity | capacitance formed in this.
 ローパスフィルタの第1インダクタL1と並列に接続された第3キャパシタC3は、不平衡端子UBに接続されたキャパシタ電極2qと、ビア電極5aにより第1インダクタL1の終点であるインダクタ電極4cの一端と接続されたキャパシタ電極2pとの間に形成される容量により形成されている。 The third capacitor C3 connected in parallel with the first inductor L1 of the low-pass filter has a capacitor electrode 2q connected to the unbalanced terminal UB, and one end of the inductor electrode 4c that is the end point of the first inductor L1 by the via electrode 5a. It is formed by a capacitor formed between the connected capacitor electrode 2p.
 不平衡側インダクタL2は、第1インダクタL1の終点であるインダクタ電極4cの一端を起点にして、ビア電極5h、インダクタ電極4j、ビア電極5i、インダクタ電極4dを経由し、第1グランド端子G1を終点とする線路により形成される。インダクタ電極4cの他端は、第1インダクタL1を構成する各電極を介して、不平衡端子UBに電気的に接続される。そのため、不平衡側インダクタL2を構成するインダクタ電極4j,4dの各々は、不平衡端子UBと第1グランド端子G1との間に電気的に接続される。ここで、「電気的に接続」された状態とは、導電路により接続された状態またはキャパシタを通じて接続された状態を示し、直接的に接続される状態に限らず、別の素子を間に介在させて間接的に接続される状態も含む。 The unbalanced inductor L2 starts from one end of the inductor electrode 4c, which is the end point of the first inductor L1, and passes through the via electrode 5h, the inductor electrode 4j, the via electrode 5i, and the inductor electrode 4d to connect the first ground terminal G1. It is formed by a track that is the end point. The other end of the inductor electrode 4c is electrically connected to the unbalanced terminal UB via each electrode constituting the first inductor L1. Therefore, each of the inductor electrodes 4j and 4d constituting the unbalanced inductor L2 is electrically connected between the unbalanced terminal UB and the first ground terminal G1. Here, the “electrically connected” state means a state connected by a conductive path or a state connected through a capacitor, and is not limited to a directly connected state, but another element is interposed therebetween. It also includes a state of being indirectly connected.
 なお、不平衡側インダクタL2において、インダクタ電極4dが下側インダクタ電極に該当し、インダクタ電極4jが上側インダクタ電極に該当する。そして、下側インダクタ電極であるインダクタ電極4dと、上側インダクタ電極であるインダクタ電極4kとが、ビア電極5iにより接続されている。 In the unbalanced inductor L2, the inductor electrode 4d corresponds to the lower inductor electrode, and the inductor electrode 4j corresponds to the upper inductor electrode. The inductor electrode 4d as the lower inductor electrode and the inductor electrode 4k as the upper inductor electrode are connected by the via electrode 5i.
 第1平衡側インダクタは、第1平衡端子Txの第1端子Tx1を起点として、インダクタ電極4a、ビア電極5e、インダクタ電極4g、ビア電極5j、インダクタ電極4k、ビア電極5m、インダクタ電極4nを経由し、第1平衡端子Txの第2端子Tx2を終点とする線路により形成される。すなわち、インダクタ電極4a,4g,4k,4nの各々は、第1平衡端子Txの第1端子Tx1と第2端子Tx2との間に電気的に接続される。これらのうち、積層方向から見たときに、環状のインダクタ電極4j,4dのいずれかによって囲まれる領域の一部分と重なる領域を囲むように形成されたインダクタ電極4gが、第1平衡側インダクタの第2インダクタ部L32を構成する。インダクタ電極4gによって囲まれる領域とインダクタ電極4i,4dのいずれかによって囲まれる領域とが重なり合うことにより、インダクタ電極4gによって構成される第2インダクタ部L32とインダクタ電極4i,4dによって構成される不平衡側インダクタL2とが電磁界結合する。 The first balanced-side inductor starts from the first terminal Tx1 of the first balanced terminal Tx and passes through the inductor electrode 4a, the via electrode 5e, the inductor electrode 4g, the via electrode 5j, the inductor electrode 4k, the via electrode 5m, and the inductor electrode 4n. The first balanced terminal Tx is formed by a line having the second terminal Tx2 as an end point. That is, each of the inductor electrodes 4a, 4g, 4k, and 4n is electrically connected between the first terminal Tx1 and the second terminal Tx2 of the first balanced terminal Tx. Among these, the inductor electrode 4g formed so as to surround a region overlapping with a part of the region surrounded by any of the annular inductor electrodes 4j and 4d when viewed from the stacking direction is the first balanced-side inductor. 2 inductor part L32 is constituted. The region surrounded by the inductor electrode 4g and the region surrounded by any one of the inductor electrodes 4i and 4d are overlapped, so that the unbalanced structure configured by the second inductor portion L32 configured by the inductor electrode 4g and the inductor electrodes 4i and 4d is formed. The side inductor L2 is electromagnetically coupled.
 第1平衡端子Txの第1端子Tx1とインダクタ電極4gとの間に電気的に接続される、インダクタ電極4aおよびビア電極5eは、第1平衡側インダクタの第1インダクタ部L31を構成する。インダクタ電極4gと第1平衡端子Txの第2端子Tx2との間に電気的に接続される、ビア電極5j、インダクタ電極4k、ビア電極5mおよびインダクタ電極4nは、第1平衡側インダクタの第3インダクタ部L33を構成する。 The inductor electrode 4a and the via electrode 5e electrically connected between the first terminal Tx1 of the first balanced terminal Tx and the inductor electrode 4g constitute a first inductor portion L31 of the first balanced side inductor. The via electrode 5j, the inductor electrode 4k, the via electrode 5m, and the inductor electrode 4n that are electrically connected between the inductor electrode 4g and the second terminal Tx2 of the first balanced terminal Tx are the third balanced inductors. The inductor portion L33 is configured.
 なお、第1平衡側インダクタの第2インダクタ部L32を構成するインダクタ電極4gの中間部は、ビア電極5d,接続電極3aを経由して、DCフィード端子DCfeedに接続されている。 Note that the intermediate portion of the inductor electrode 4g constituting the second inductor portion L32 of the first balanced inductor is connected to the DC feed terminal DCfeed via the via electrode 5d and the connection electrode 3a.
 第2平衡側インダクタは、第2平衡端子Rxの第1端子Rx1を起点として、インダクタ電極4o、ビア電極5n、インダクタ電極4l、ビア電極5k、インダクタ電極4h、ビア電極5f、インダクタ電極4e、ビア電極5b、インダクタ電極4bを経由し、第2平衡端子Rxの第2端子Rx2を終点とする線路により形成される。すなわち、インダクタ電極4o,4l,4h,4e,4bの各々は、第2平衡端子Rxの第1端子Rx1と第2端子Rx2との間に電気的に接続される。これらのうち、積層方向から見たときに、環状のインダクタ電極4j,4dのいずれかによって囲まれる領域の一部分と重なる領域を囲むように形成されたインダクタ電極4hが、第2平衡側インダクタの第2インダクタ部L42を構成する。インダクタ電極4hによって囲まれる領域とインダクタ電極4i,4dのいずれかによって囲まれる領域とが重なり合うことにより、インダクタ電極4hによって構成される第2インダクタ部L42とインダクタ電極4i,4dによって構成される不平衡側インダクタL2とが電磁界結合する。 The second balanced-side inductor starts from the first terminal Rx1 of the second balanced terminal Rx, and starts from the inductor electrode 4o, via electrode 5n, inductor electrode 41, via electrode 5k, inductor electrode 4h, via electrode 5f, inductor electrode 4e, via It is formed by a line having the second terminal Rx2 of the second balanced terminal Rx as an end point via the electrode 5b and the inductor electrode 4b. That is, each of the inductor electrodes 4o, 4l, 4h, 4e, and 4b is electrically connected between the first terminal Rx1 and the second terminal Rx2 of the second balanced terminal Rx. Among these, when viewed from the stacking direction, the inductor electrode 4h formed so as to surround a region overlapping with a part of the region surrounded by either of the annular inductor electrodes 4j and 4d is the second balanced-side inductor. 2 inductor part L42 is comprised. The region surrounded by the inductor electrode 4h and the region surrounded by any one of the inductor electrodes 4i and 4d are overlapped, so that an unbalance formed by the second inductor portion L42 formed by the inductor electrode 4h and the inductor electrodes 4i and 4d is formed. The side inductor L2 is electromagnetically coupled.
 第2平衡端子Rxの第1端子Rx1とインダクタ電極4hとの間に電気的に接続される、インダクタ電極4o、ビア電極5n、インダクタ電極4lおよびビア電極5kは、第2平衡側インダクタの第1インダクタ部L41を構成する。インダクタ電極4hと第2平衡端子Rxの第2端子Rx2との間に電気的に接続される、ビア電極5f、インダクタ電極4e、ビア電極5bおよびインダクタ電極4bは、第2平衡側インダクタの第3インダクタ部L43を構成する。 The inductor electrode 4o, the via electrode 5n, the inductor electrode 4l and the via electrode 5k, which are electrically connected between the first terminal Rx1 of the second balanced terminal Rx and the inductor electrode 4h, are the first balanced-side inductor first. The inductor portion L41 is configured. The via electrode 5f, the inductor electrode 4e, the via electrode 5b, and the inductor electrode 4b, which are electrically connected between the inductor electrode 4h and the second terminal Rx2 of the second balanced terminal Rx, are the third balanced-side inductor third. The inductor portion L43 is configured.
 第4キャパシタC4は、主に、端子には接続されず浮き電極となったキャパシタ電極2g、2nを介して、第1平衡端子Txの第1端子Tx1と接続されたキャパシタ電極2c、2iと、第1平衡端子Txの第2端子Tx2と接続されたキャパシタ電極2d、2jと間に形成される容量により形成されている。 The fourth capacitor C4 mainly includes capacitor electrodes 2c and 2i connected to the first terminal Tx1 of the first balanced terminal Tx via the capacitor electrodes 2g and 2n which are not connected to the terminals and become floating electrodes, The capacitor is formed by a capacitor formed between the capacitor electrodes 2d and 2j connected to the second terminal Tx2 of the first balanced terminal Tx.
 第5キャパシタC5は、主に、端子には接続されず浮き電極となったキャパシタ電極2h、2oを介して、第2平衡端子Rxの第1端子Rx1と接続されたキャパシタ電極2e、2kと、第2平衡端子Rxの第2端子Rx2と接続されたキャパシタ電極2f、2lと間に形成される容量により形成されている。 The fifth capacitor C5 mainly includes capacitor electrodes 2e and 2k connected to the first terminal Rx1 of the second balanced terminal Rx via the capacitor electrodes 2h and 2o which are not connected to the terminals and are floating electrodes, The capacitor is formed by a capacitor formed between the capacitor electrodes 2f and 2l connected to the second terminal Rx2 of the second balanced terminal Rx.
 以上の等価回路および構成からなる本実施形態の積層バラン100においては、第1平衡側インダクタの第2インダクタ部L32を構成するインダクタ電極4gと、第2平衡側インダクタの第2インダクタ部L42を構成するインダクタ電極4hとは、同一の誘電体層1lの上側の主面に形成される。すなわち、インダクタ電極4gとインダクタ電極4hとは、誘電体層1lと誘電体層1mとの間の同一の層間に形成される。これにより、積層バラン100を構成する積層体1を低背化することができる。 In the multilayer balun 100 of the present embodiment having the above equivalent circuit and configuration, the inductor electrode 4g constituting the second inductor portion L32 of the first balanced-side inductor and the second inductor portion L42 of the second balanced-side inductor are configured. The inductor electrode 4h to be formed is formed on the upper main surface of the same dielectric layer 1l. That is, the inductor electrode 4g and the inductor electrode 4h are formed between the same layers between the dielectric layer 11 and the dielectric layer 1m. Thereby, the laminated body 1 which comprises the laminated balun 100 can be made low-profile.
 誘電体層1a~1pの積層方向において、2つに分割された不平衡側インダクタL2の下側インダクタ電極を構成するインダクタ電極4dと上側インダクタ電極を構成するインダクタ電極4jとの間に、第1平衡側インダクタの第2インダクタ部L32を構成するインダクタ電極4gと、第2平衡側インダクタの第2インダクタ部L42を構成するインダクタ電極4hとが挟み込まれて配置される。 In the laminating direction of the dielectric layers 1a to 1p, a first inductor is provided between the inductor electrode 4d constituting the lower inductor electrode of the unbalanced inductor L2 divided into two and the inductor electrode 4j constituting the upper inductor electrode. An inductor electrode 4g constituting the second inductor portion L32 of the balanced-side inductor and an inductor electrode 4h constituting the second inductor portion L42 of the second balanced-side inductor are sandwiched and arranged.
 この結果、積層バラン100の使用時には、不平衡側インダクタL2と、第1平衡側インダクタの第2インダクタ部L32とが電磁界結合する。更に、不平衡側インダクタL2と、第2平衡側インダクタの第2インダクタ部L42とが電磁界結合する。 As a result, when the multilayer balun 100 is used, the unbalanced inductor L2 and the second inductor portion L32 of the first balanced inductor are electromagnetically coupled. Further, the unbalanced inductor L2 and the second inductor section L42 of the second balanced inductor are electromagnetically coupled.
 2つに分割された不平衡側インダクタL2の下側インダクタ電極を構成するインダクタ電極4dと上側インダクタ電極を構成するインダクタ電極4jとを接続するビア電極5iが、ビア電極5hとともに、インダクタ電極4gの環状部分の内側を貫通するように配置される。 A via electrode 5i that connects the inductor electrode 4d that forms the lower inductor electrode of the unbalanced inductor L2 divided into two and the inductor electrode 4j that forms the upper inductor electrode, together with the via electrode 5h, It arrange | positions so that the inner side of an annular part may be penetrated.
 この結果、積層バラン100においては、不平衡側インダクタL2の下側インダクタ電極を構成するインダクタ電極4dと上側インダクタ電極を構成するインダクタ電極4jとを接続するビア電極5iが形成する磁束と、第1平衡側インダクタの第2インダクタ部L32のインダクタ電極4gが形成する磁束とが、相互に直交し、両者の干渉が抑制される。そのため、不平衡側インダクタL2および第1平衡側インダクタ(第2インダクタ部L32)の双方においてQの低下が抑制される。 As a result, in the multilayer balun 100, the magnetic flux formed by the via electrode 5i that connects the inductor electrode 4d that forms the lower inductor electrode of the unbalanced inductor L2 and the inductor electrode 4j that forms the upper inductor electrode, and the first The magnetic flux formed by the inductor electrode 4g of the second inductor portion L32 of the balanced inductor is orthogonal to each other, and interference between the two is suppressed. Therefore, a decrease in Q is suppressed in both the unbalanced inductor L2 and the first balanced inductor (second inductor portion L32).
 以上のように、本実施の形態の積層バラン100は、複数の誘電体層1a~1pが積層された積層体1と、積層体1の層間に形成された複数のインダクタ電極と、積層体1の表面に形成された複数の端子とを備える。 As described above, the laminated balun 100 of the present embodiment includes the laminated body 1 in which the plurality of dielectric layers 1a to 1p are laminated, the plurality of inductor electrodes formed between the layers of the laminated body 1, and the laminated body 1 And a plurality of terminals formed on the surface.
 複数の端子は、不平衡端子UBと、第1平衡端子Txと、第2平衡端子Rxと、第1グランド端子G1とを含む。第1平衡端子Txは、第1端子Tx1と第2端子Tx2とを有する。第2平衡端子Rxは、第1端子Rx1と第2端子Rx2とを有する。 The plurality of terminals include an unbalanced terminal UB, a first balanced terminal Tx, a second balanced terminal Rx, and a first ground terminal G1. The first balanced terminal Tx has a first terminal Tx1 and a second terminal Tx2. The second balanced terminal Rx has a first terminal Rx1 and a second terminal Rx2.
 複数のインダクタ電極は、不平衡端子UBと第1グランド端子G1との間に電気的に接続されたインダクタ電極(不平衡側インダクタ導体パターン)4d,4jと、第1平衡端子Txの第1端子Tx1と第2端子Tx2との間に電気的に接続されたインダクタ電極(第1平衡側インダクタ導体パターン)4gと、第2平衡端子Rxの第1端子Rx1と第2端子Rx2との間に電気的に接続されたインダクタ電極(第2平衡側インダクタ導体パターン)4hとを含む。 The plurality of inductor electrodes include inductor electrodes (unbalanced-side inductor conductor patterns) 4d and 4j electrically connected between the unbalanced terminal UB and the first ground terminal G1, and a first terminal of the first balanced terminal Tx. Between the inductor electrode (first balanced-side inductor conductor pattern) 4g electrically connected between Tx1 and the second terminal Tx2, and between the first terminal Rx1 and the second terminal Rx2 of the second balanced terminal Rx Connected inductor electrode (second balanced-side inductor conductor pattern) 4h.
 複数の誘電体層1a~1pの積層方向から見たとき、インダクタ電極4gによって囲まれた領域の少なくとも一部分は、インダクタ電極4d,4jによって囲まれた領域と重なる。更に、インダクタ電極4hによって囲まれた領域の少なくとも一部分は、インダクタ電極4d,4jによって囲まれた領域と重なる。インダクタ電極4g,4hは、積層体1の同一の層間(ここでは、誘電体層1lと誘電体層1mとの間)に形成される。 When viewed from the stacking direction of the plurality of dielectric layers 1a to 1p, at least a part of the region surrounded by the inductor electrode 4g overlaps the region surrounded by the inductor electrodes 4d and 4j. Furthermore, at least a part of the region surrounded by the inductor electrode 4h overlaps the region surrounded by the inductor electrodes 4d and 4j. The inductor electrodes 4g and 4h are formed between the same layers of the multilayer body 1 (here, between the dielectric layer 1l and the dielectric layer 1m).
 このような配置により、インダクタ電極4d,4jによって構成される不平衡側インダクタL2は、インダクタ電極4gによって構成される第1平衡側インダクタの第2インダクタ部L32と電磁界結合できるとともに、インダクタ電極4hによって構成される第2平衡側インダクタの第2インダクタ部L42とも電磁界結合できる。また、インダクタ電極4g,4hが同一の層間に形成されるため、積層体1を低背化することができる。更に、ディバイダを使用する必要がないため、ディバイダを通過することによる挿入損失を抑制できるとともに、部品点数を減らすことができる。その結果、不平衡端子と2対の平衡端子とを備えた、小型で、信号の挿入損失が小さい積層バランを実現できる。 With such an arrangement, the unbalanced inductor L2 constituted by the inductor electrodes 4d and 4j can be electromagnetically coupled to the second inductor portion L32 of the first balanced inductor constituted by the inductor electrode 4g, and the inductor electrode 4h. The second inductor portion L42 of the second balanced-side inductor constituted by the electromagnetic field coupling can also be performed. Further, since the inductor electrodes 4g and 4h are formed between the same layers, the stacked body 1 can be reduced in height. Furthermore, since there is no need to use a divider, insertion loss due to passing through the divider can be suppressed, and the number of parts can be reduced. As a result, it is possible to realize a small-sized laminated balun including an unbalanced terminal and two pairs of balanced terminals and having a small signal insertion loss.
 複数の誘電体層は、連続して順に積層された誘電体層(第1誘電体層)1k、誘電体層(第2誘電体層)1l、誘電体層(第3誘電体層)1mを含む。不平衡側インダクタL2を構成するインダクタ電極は、誘電体層1k,1lの間に形成されたインダクタ電極(第1不平衡側インダクタ導体パターン)4dを含む。インダクタ電極4g,4hは、誘電体層1l,1mの間に形成される。これにより、インダクタ電極4dとインダクタ電極4gとの間に1つの誘電体層1lのみが介在し、不平衡側インダクタL2とインダクタ電極4gによって構成される第1平衡側インダクタの第2インダクタ部L32との電磁界結合を強くすることができる。同様に、不平衡側インダクタL2と、インダクタ電極4hによって構成される第2平衡側インダクタの第2インダクタ部L42との電磁界結合を強くすることができる。 The plurality of dielectric layers include a dielectric layer (first dielectric layer) 1k, a dielectric layer (second dielectric layer) 1l, and a dielectric layer (third dielectric layer) 1m that are sequentially stacked. Including. The inductor electrode constituting the unbalanced inductor L2 includes an inductor electrode (first unbalanced inductor conductor pattern) 4d formed between the dielectric layers 1k and 1l. The inductor electrodes 4g and 4h are formed between the dielectric layers 1l and 1m. As a result, only one dielectric layer 11 is interposed between the inductor electrode 4d and the inductor electrode 4g, and the second inductor portion L32 of the first balanced-side inductor constituted by the unbalanced inductor L2 and the inductor electrode 4g, The electromagnetic field coupling can be strengthened. Similarly, electromagnetic field coupling between the unbalanced inductor L2 and the second inductor portion L42 of the second balanced inductor constituted by the inductor electrode 4h can be strengthened.
 更に、複数の誘電体層は、誘電体層1mの誘電体層1lとは反対側に積層された誘電体層(第4誘電体層)1nを含む。不平衡側インダクタL2を構成するインダクタ電極は、インダクタ電極4dの他に、誘電体層1m,1nの間に形成されるインダクタ電極(第2不平衡側インダクタ導体パターン)4jを含む。これにより、不平衡側インダクタL2と、インダクタ電極4gによって構成される第1平衡側インダクタの第2インダクタ部L32との電磁界結合を更に強くすることができる。同様に、不平衡側インダクタL2と、インダクタ電極4hによって構成される第2平衡側インダクタの第2インダクタ部L42との電磁界結合を更に強くすることができる。 Furthermore, the plurality of dielectric layers include a dielectric layer (fourth dielectric layer) 1n laminated on the opposite side of the dielectric layer 1m from the dielectric layer 1l. The inductor electrode constituting the unbalanced inductor L2 includes an inductor electrode (second unbalanced inductor conductor pattern) 4j formed between the dielectric layers 1m and 1n in addition to the inductor electrode 4d. Thereby, the electromagnetic field coupling between the unbalanced inductor L2 and the second inductor portion L32 of the first balanced inductor constituted by the inductor electrode 4g can be further strengthened. Similarly, electromagnetic field coupling between the unbalanced inductor L2 and the second inductor portion L42 of the second balanced inductor configured by the inductor electrode 4h can be further strengthened.
 図4は、本実施の形態の積層バランの変形例を示す分解斜視図である。なお、図4では、積層バランを構成する誘電体層のうちの一部の誘電体層のみが示される。変形例に係る積層バランは、図3に示す積層バラン100と比較して、誘電体層1kの代わりに誘電体層1qを備え、誘電体層1m~1oの代わりに誘電体層1r,1sを備える点でのみ相違する。 FIG. 4 is an exploded perspective view showing a modified example of the laminated balun according to the present embodiment. FIG. 4 shows only a part of the dielectric layers constituting the laminated balun. Compared with the laminated balun 100 shown in FIG. 3, the laminated balun according to the modified example includes a dielectric layer 1q instead of the dielectric layer 1k, and includes dielectric layers 1r and 1s instead of the dielectric layers 1m to 1o. It differs only in the point provided.
 誘電体層1qの上側の主面にはインダクタ電極4c,4e,4qが形成される。誘電体層1qは、図3に示す誘電体層1kと比較して、インダクタ電極4dの代わりにインダクタ電極4qが形成される点でのみ異なる。インダクタ電極4qの一端は第1グランド端子G1に接続され、インダクタ電極4qの他端はインダクタ電極4cの一端に接続される。インダクタ電極4cとインダクタ電極4qとの接続点にはビア電極5aが接続される。インダクタ電極4qは開いた環状である。誘電体層の積層方向から見たとき、インダクタ電極4qによって囲まれた領域の一部は、誘電体層1lの上側の主面に形成されたインダクタ電極4gによって囲まれた領域と重なる。同様に、インダクタ電極4qによって囲まれた領域の一部は、誘電体層1lの上側の主面に形成されたインダクタ電極4hによって囲まれた領域と重なる。 Inductor electrodes 4c, 4e, and 4q are formed on the upper main surface of the dielectric layer 1q. The dielectric layer 1q differs from the dielectric layer 1k shown in FIG. 3 only in that an inductor electrode 4q is formed instead of the inductor electrode 4d. One end of the inductor electrode 4q is connected to the first ground terminal G1, and the other end of the inductor electrode 4q is connected to one end of the inductor electrode 4c. A via electrode 5a is connected to a connection point between the inductor electrode 4c and the inductor electrode 4q. The inductor electrode 4q is an open ring. When viewed from the stacking direction of the dielectric layer, a part of the region surrounded by the inductor electrode 4q overlaps the region surrounded by the inductor electrode 4g formed on the upper main surface of the dielectric layer 1l. Similarly, a part of the region surrounded by the inductor electrode 4q overlaps the region surrounded by the inductor electrode 4h formed on the upper main surface of the dielectric layer 11.
 誘電体層1rの上側の主面にはインダクタ電極4i,4k,4lが形成される。誘電体層1rは、図3に示す誘電体層1mと比較して、インダクタ電極4jが形成されない点でのみ異なる。 Inductor electrodes 4i, 4k, 4l are formed on the upper main surface of the dielectric layer 1r. The dielectric layer 1r differs from the dielectric layer 1m shown in FIG. 3 only in that the inductor electrode 4j is not formed.
 誘電体層1sの上側の主面にはインダクタ電極4n,4o,4rが形成される。誘電体層1sは、図3に示す誘電体層1nと比較して、インダクタ電極4mの代わりにインダクタ電極4rが形成される点でのみ異なる。インダクタ電極4rの一端は不平衡端子UBに接続される。インダクタ電極4rの他端は、誘電体層1sを貫通するビア電極5pによってインダクタ電極4iの他端に接続される。 Inductor electrodes 4n, 4o, 4r are formed on the upper main surface of the dielectric layer 1s. The dielectric layer 1s differs from the dielectric layer 1n shown in FIG. 3 only in that an inductor electrode 4r is formed instead of the inductor electrode 4m. One end of the inductor electrode 4r is connected to the unbalanced terminal UB. The other end of the inductor electrode 4r is connected to the other end of the inductor electrode 4i by a via electrode 5p that penetrates the dielectric layer 1s.
 インダクタ電極4q,4rは、たとえば、Ag、Cuや、これらの合金を主成分とする金属により形成することができる。 The inductor electrodes 4q and 4r can be formed of, for example, Ag, Cu, or a metal mainly composed of these alloys.
 本変形例によれば、不平衡側インダクタL2は、第1インダクタL1の終点であるインダクタ電極4cの一端を起点にして、インダクタ電極4qを経由し、第1グランド端子G1を終点とする線路により形成される。不平衡側インダクタL2を構成するインダクタ電極4qは、誘電体層(第1誘電体層)1qと誘電体層1lとの間に形成される。本変形例では、インダクタ電極4g,4iの上側に積層される誘電体層(第3誘電体層)1rと、誘電体層1rの誘電体層1lとは反対側に積層された誘電体層(第4誘電体層)1sとの間には、不平衡側インダクタL2を構成するインダクタ電極が形成されない。これにより、不平衡側インダクタL2を構成するインダクタ電極の数を減らすことができ、積層バランを低背化することができる。 According to this modification, the unbalanced inductor L2 is a line that starts from one end of the inductor electrode 4c that is the end point of the first inductor L1, passes through the inductor electrode 4q, and ends at the first ground terminal G1. It is formed. The inductor electrode 4q constituting the unbalanced inductor L2 is formed between the dielectric layer (first dielectric layer) 1q and the dielectric layer 1l. In the present modification, a dielectric layer (third dielectric layer) 1r laminated on the inductor electrodes 4g and 4i and a dielectric layer laminated on the opposite side of the dielectric layer 1l of the dielectric layer 1r ( The inductor electrode constituting the unbalanced inductor L2 is not formed between the fourth dielectric layer) 1s. As a result, the number of inductor electrodes constituting the unbalanced inductor L2 can be reduced, and the laminated balun can be reduced in height.
 なお、不平衡側インダクタL2と、第1平衡側インダクタの第2インダクタ部L32と、第2平衡側インダクタの第2インダクタ部L42との各々を構成するインダクタ電極の形状は、特に限定されるものではない。図5は、積層バランの別の変形例の一部分を示す分解斜視図である。図5において、不平衡側インダクタL2と、第1平衡側インダクタの第2インダクタ部L32と、第2平衡側インダクタの第2インダクタ部L42とを構成するインダクタ電極が形成された誘電体層以外の誘電体層を省略している。 The shape of the inductor electrode constituting each of the unbalanced-side inductor L2, the second inductor portion L32 of the first balanced-side inductor, and the second inductor portion L42 of the second balanced-side inductor is particularly limited. is not. FIG. 5 is an exploded perspective view showing a part of another modified example of the laminated balun. In FIG. 5, other than the dielectric layer on which the inductor electrode constituting the unbalanced inductor L2, the second inductor portion L32 of the first balanced inductor, and the second inductor portion L42 of the second balanced inductor is formed. The dielectric layer is omitted.
 図5に示されるように、積層バランを構成する積層体は、隣接する誘電体層1t,1uを含む。誘電体層1tの上側の主面に形成されたインダクタ電極4sは不平衡側インダクタL2を構成する。インダクタ電極4sは、2つの開いた環状部分4s1,4s2を連結させた形状を有する。誘電体層1uの上側の主面に形成されたインダクタ電極4tは、第1平衡側インダクタの第2インダクタ部L32を構成し、開いた環状である。同じ誘電体層1uの上側の主面に形成されたインダクタ電極4uは、第2平衡側インダクタの第2インダクタ部L42を構成し、開いた環状である。インダクタ電極4s~4uは、たとえば、Ag、Cuや、これらの合金を主成分とする金属により形成することができる。誘電体層1t,1uの積層方向から見たとき、インダクタ電極4tによって囲まれた領域の少なくとも一部は、インダクタ電極4sにおける一方の環状部分4s1によって囲まれた領域と重なる。また、誘電体層1t,1uの積層方向から見たとき、インダクタ電極4uによって囲まれた領域の少なくとも一部は、インダクタ電極4sにおける他方の環状部分4s2によって囲まれた領域と重なる。これにより、不平衡側インダクタL2は、第1平衡側インダクタの第2インダクタ部L32および第2平衡側インダクタの第2インダクタ部L42のそれぞれと電磁界結合できる。また、不平衡側インダクタL2、第1平衡側インダクタの第2インダクタ部L32および第2平衡側インダクタの第2インダクタ部L42の各々のインピーダンス調整を行ないやすくなる。 As shown in FIG. 5, the stacked body constituting the stacked balun includes adjacent dielectric layers 1t and 1u. The inductor electrode 4s formed on the upper main surface of the dielectric layer 1t constitutes an unbalanced inductor L2. The inductor electrode 4s has a shape in which two open annular portions 4s1 and 4s2 are connected. The inductor electrode 4t formed on the upper main surface of the dielectric layer 1u constitutes the second inductor portion L32 of the first balanced-side inductor and has an open annular shape. The inductor electrode 4u formed on the upper main surface of the same dielectric layer 1u constitutes the second inductor portion L42 of the second balanced-side inductor and has an open annular shape. The inductor electrodes 4s to 4u can be made of, for example, Ag, Cu, or a metal mainly composed of these alloys. When viewed from the stacking direction of the dielectric layers 1t and 1u, at least a part of the region surrounded by the inductor electrode 4t overlaps the region surrounded by the one annular portion 4s1 in the inductor electrode 4s. Further, when viewed from the stacking direction of the dielectric layers 1t and 1u, at least a part of the region surrounded by the inductor electrode 4u overlaps the region surrounded by the other annular portion 4s2 in the inductor electrode 4s. As a result, the unbalanced inductor L2 can be electromagnetically coupled to each of the second inductor portion L32 of the first balanced side inductor and the second inductor portion L42 of the second balanced side inductor. In addition, it is easy to adjust the impedance of each of the unbalanced inductor L2, the second inductor portion L32 of the first balanced side inductor, and the second inductor portion L42 of the second balanced side inductor.
 上記の説明では、不平衡側インダクタL2は、第2キャパシタC2と並列に接続されるものとしたが、キャパシタと直列に接続されてもよい。たとえば、第1インダクタL1の他端とグランドとの間に、不平衡側インダクタL2とキャパシタとがこの順に直列に接続されてもよい。 In the above description, the unbalanced inductor L2 is connected in parallel with the second capacitor C2, but may be connected in series with the capacitor. For example, the unbalanced inductor L2 and the capacitor may be connected in series in this order between the other end of the first inductor L1 and the ground.
 上記の実施の形態に係る積層バラン100は、以下のようにも表現できる。
 積層バラン100は、1つの不平衡端子UBと、第1端子Tx1と第2端子Tx2とを備えた第1平衡端子Txと、第1端子Rx1と第2端子Rx2とを備えた第2平衡端子Rxとを備える。不平衡端子UBとグランドとの間に、不平衡側インダクタL2が挿入され、第1平衡端子Txの第1端子Tx1と第2端子Tx2との間に、第1平衡側インダクタが挿入され、第2平衡端子Rxの第1端子Rx1と第2端子Rx2との間に、第2平衡側インダクタが挿入される。不平衡側インダクタL2は、第1平衡側インダクタおよび第2平衡側インダクタの双方と、それぞれ電磁界結合される。
The laminated balun 100 according to the above embodiment can also be expressed as follows.
The laminated balun 100 includes one unbalanced terminal UB, a first balanced terminal Tx having a first terminal Tx1 and a second terminal Tx2, and a second balanced terminal having a first terminal Rx1 and a second terminal Rx2. Rx. An unbalanced inductor L2 is inserted between the unbalanced terminal UB and the ground, a first balanced inductor is inserted between the first terminal Tx1 and the second terminal Tx2 of the first balanced terminal Tx, A second balanced-side inductor is inserted between the first terminal Rx1 and the second terminal Rx2 of the two balanced terminals Rx. The unbalanced inductor L2 is electromagnetically coupled to both the first balanced inductor and the second balanced inductor.
 不平衡端子UBと不平衡側インダクタL2との間に、ローパスフィルタが挿入されることが好ましい。ローパスフィルタは、第1インダクタL1と、第1インダクタL1の一端とグランドとの間に挿入された第1キャパシタC1と、第1インダクタL1の他端とグランドとの間に挿入された第2キャパシタC2とを備える。不平衡側インダクタL2は、第2キャパシタC2と並列に接続されたものとすることが好ましい。この場合には、ローパスフィルタにより、不平衡端子UBと第1平衡端子Txとの間を通過する信号の周波数帯、および、不平衡端子UBと第2平衡端子Rxとの間を通過する信号の周波数帯を調整することができる。 It is preferable that a low-pass filter is inserted between the unbalanced terminal UB and the unbalanced inductor L2. The low-pass filter includes a first inductor L1, a first capacitor C1 inserted between one end of the first inductor L1 and the ground, and a second capacitor inserted between the other end of the first inductor L1 and the ground. C2. The unbalanced inductor L2 is preferably connected in parallel with the second capacitor C2. In this case, the frequency band of the signal passing between the unbalanced terminal UB and the first balanced terminal Tx and the signal passing between the unbalanced terminal UB and the second balanced terminal Rx by the low-pass filter. The frequency band can be adjusted.
 この場合において、ローパスフィルタの第1インダクタL1と並列に、第3キャパシタC3が接続されたものとすることが好ましい。この場合には、ローパスフィルタの通過帯域外の高周波側にトラップを形成することができ、ローパスフィルタの機能を向上させることができる。 In this case, it is preferable that the third capacitor C3 is connected in parallel with the first inductor L1 of the low-pass filter. In this case, a trap can be formed on the high frequency side outside the pass band of the low-pass filter, and the function of the low-pass filter can be improved.
 第1平衡端子Txの第1端子Tx1と第2端子Tx2との間に、更に、第4キャパシタC4が挿入され、第2平衡端子Rxの第1端子Rx1と第2端子Rx2との間に、更に、第5キャパシタC5が挿入されたものとすることが好ましい。この場合には、第1平衡側インダクタと第4キャパシタC4とでLC並列共振器が構成される。また、第2平衡側インダクタと第5キャパシタC5とでLC並列共振器が構成される。そして、第1平衡側インダクタと第4キャパシタC4とで構成されたLC並列共振器は、上述した不平衡側インダクタL2と第2キャパシタC2とでLC並列共振器が構成されている場合はそのLC並列共振器と共働で、第2キャパシタC2が省略されていてそのLC並列共振器が構成されていない場合は独自に、第1バンドパスフィルタを構成する。その第1バンドパスフィルタは、任意に選択した周波数帯の信号のみを不平衡端子UBと第1平衡端子Txとの間に通過させる。更に、第2平衡側インダクタと第5キャパシタC5とで構成されたLC並列共振器は、上述した不平衡側インダクタL2と第2キャパシタC2とでLC並列共振器が構成されている場合はそのLC並列共振器と共働で、第2キャパシタC2が省略されていてそのLC並列共振器が構成されていない場合は独自に、第2バンドパスフィルタを構成する。その第2バンドパスフィルタは、任意に選択した周波数帯の信号のみを不平衡端子UBと第2平衡端子Rxとの間に通過させる。なお、第4キャパシタC4と第5キャパシタC5とが挿入されていない場合においても、上述した不平衡側インダクタL2と第2キャパシタC2とで構成されるLC並列共振器は、バンドパスフィルタとして、あるいはバンドパスフィルタの一部として機能する。 A fourth capacitor C4 is further inserted between the first terminal Tx1 and the second terminal Tx2 of the first balanced terminal Tx, and between the first terminal Rx1 and the second terminal Rx2 of the second balanced terminal Rx, Furthermore, it is preferable that the fifth capacitor C5 is inserted. In this case, the first parallel-side inductor and the fourth capacitor C4 constitute an LC parallel resonator. Further, the second balanced-side inductor and the fifth capacitor C5 constitute an LC parallel resonator. The LC parallel resonator composed of the first balanced-side inductor and the fourth capacitor C4 is the LC parallel resonator formed by the unbalanced-side inductor L2 and the second capacitor C2 described above. When the second capacitor C2 is omitted and the LC parallel resonator is not configured in cooperation with the parallel resonator, the first band pass filter is configured independently. The first band-pass filter passes only a signal in an arbitrarily selected frequency band between the unbalanced terminal UB and the first balanced terminal Tx. Further, the LC parallel resonator constituted by the second balanced-side inductor and the fifth capacitor C5 is an LC parallel resonator when the above-described unbalanced-side inductor L2 and the second capacitor C2 constitute an LC parallel resonator. When the second capacitor C2 is omitted and the LC parallel resonator is not configured in cooperation with the parallel resonator, a second band pass filter is configured independently. The second band pass filter passes only a signal in an arbitrarily selected frequency band between the unbalanced terminal UB and the second balanced terminal Rx. Even when the fourth capacitor C4 and the fifth capacitor C5 are not inserted, the LC parallel resonator constituted by the unbalanced inductor L2 and the second capacitor C2 described above can be used as a bandpass filter or Functions as part of a bandpass filter.
 第1平衡側インダクタは、順に直列に接続された、第1インダクタ部L31、第2インダクタ部L32および第3インダクタ部L33を備える。不平衡側インダクタL2は、主に、第1平衡側インダクタの第2インダクタ部L32と電磁界結合される。第2平衡側インダクタは、順に直列に接続された、第1インダクタ部L41、第2インダクタ部L42および第3インダクタ部L43を備える。不平衡側インダクタL2は、主に、第2平衡側インダクタの第2インダクタ部L42と電磁界結合されたものとすることが好ましい。この場合には、不平衡側インダクタL2と第1平衡側インダクタとの電磁界結合の強さの調整が容易になるとともに、不平衡側インダクタL2と第2平衡側インダクタとの電磁界結合の強さの調整が容易になる。すなわち、第1平衡側インダクタおよび第2平衡側インダクタにおいて、それぞれ、主に第2インダクタ部が、不平衡側インダクタとの電磁界結合の調整に用いられる。一方、第1平衡側インダクタおよび第2平衡側インダクタにおいて、それぞれ、主に第1インダクタ部および第3インダクタ部が、第1平衡端子または第2平衡端子のインピーダンスの調整に用いられる。 The first balanced inductor includes a first inductor portion L31, a second inductor portion L32, and a third inductor portion L33 connected in series in order. The unbalanced inductor L2 is mainly electromagnetically coupled to the second inductor portion L32 of the first balanced inductor. The second balanced-side inductor includes a first inductor portion L41, a second inductor portion L42, and a third inductor portion L43 that are connected in series in order. It is preferable that the unbalanced inductor L2 is mainly electromagnetically coupled to the second inductor portion L42 of the second balanced inductor. In this case, it is easy to adjust the strength of electromagnetic coupling between the unbalanced inductor L2 and the first balanced inductor, and strong electromagnetic coupling between the unbalanced inductor L2 and the second balanced inductor. Adjustment of the thickness becomes easy. That is, in each of the first balanced-side inductor and the second balanced-side inductor, the second inductor portion is mainly used for adjusting the electromagnetic field coupling with the unbalanced-side inductor. On the other hand, in the first balanced-side inductor and the second balanced-side inductor, the first inductor portion and the third inductor portion are mainly used for adjusting the impedance of the first balanced terminal or the second balanced terminal, respectively.
 第1平衡側インダクタの中間部分に、DCフィード端子DCfeedが接続されたものとすることが好ましい。この場合には、DCフィード端子DCfeedに直流電力を供給することにより、たとえば、アンテナから送信されるTx信号の強度を高めることができる。 It is preferable that a DC feed terminal DCfeed is connected to an intermediate portion of the first balanced inductor. In this case, for example, the strength of the Tx signal transmitted from the antenna can be increased by supplying DC power to the DC feed terminal DCfeed.
 第1平衡端子Txのインピーダンスと、第2平衡端子Rxのインピーダンスとは、異なったものとすることが好ましい。この場合には、たとえば、接続されるRF回路のRx側のインピーダンスとTx側のインピーダンスとが異なっていても、積層バラン100をそのまま接続することができる。更に、第1平衡端子Txのインピーダンスと第2平衡端子Rxのインピーダンスとを、相互に独立して設計することができる。 It is preferable that the impedance of the first balanced terminal Tx is different from the impedance of the second balanced terminal Rx. In this case, for example, even when the impedance on the Rx side and the impedance on the Tx side of the RF circuit to be connected are different, the laminated balun 100 can be connected as it is. Furthermore, the impedance of the first balanced terminal Tx and the impedance of the second balanced terminal Rx can be designed independently of each other.
 不平衡端子UBと第1平衡端子Txとの間に形成される通過帯域の周波数と、不平衡端子UBと第2平衡端子Rxとの間に形成される通過帯域の周波数とは、異なっていても良い。 The frequency of the pass band formed between the unbalanced terminal UB and the first balanced terminal Tx is different from the frequency of the pass band formed between the unbalanced terminal UB and the second balanced terminal Rx. Also good.
 あるいは、不平衡端子UBと第1平衡端子Txとの間に形成される通過帯域の周波数と、不平衡端子UBと第2平衡端子Rxとの間に形成される通過帯域の周波数とは、同じであっても良い。この場合には、たとえば、TDD(Time Division Duplex)方式の通信に積層バラン100を使用することができる。 Alternatively, the frequency of the pass band formed between the unbalanced terminal UB and the first balanced terminal Tx is the same as the frequency of the pass band formed between the unbalanced terminal UB and the second balanced terminal Rx. It may be. In this case, for example, the laminated balun 100 can be used for TDD (Time Division Duplex) communication.
 積層バラン100は、複数の誘電体層が積層された積層体1と、誘電体層の層間に積層された複数のインダクタ電極と、誘電体層を貫通して形成された複数のビア電極とを備える。インダクタ電極により、または、インダクタ電極とビア電極とにより、不平衡側インダクタL2、第1平衡側インダクタ、第2平衡側インダクタがそれぞれ形成されたものとして構成することが好ましい。 The laminated balun 100 includes a laminated body 1 in which a plurality of dielectric layers are laminated, a plurality of inductor electrodes laminated between the dielectric layers, and a plurality of via electrodes formed through the dielectric layers. Prepare. It is preferable that the unbalanced-side inductor L2, the first balanced-side inductor, and the second balanced-side inductor are respectively formed by the inductor electrode or by the inductor electrode and the via electrode.
 積層バラン100は、更に、誘電体層の層間に積層された複数のキャパシタ電極を備え、複数のキャパシタ電極間に形成される容量により、第1キャパシタC1、第2キャパシタC2、第3キャパシタC3、第4キャパシタC4、第5キャパシタC5の少なくとも1つが形成されたものとして構成することが好ましい。 The multilayer balun 100 further includes a plurality of capacitor electrodes stacked between the dielectric layers, and the first capacitor C1, the second capacitor C2, the third capacitor C3, It is preferable that at least one of the fourth capacitor C4 and the fifth capacitor C5 is formed.
 積層体1内において、不平衡側インダクタL2を形成するインダクタ電極が、少なくとも、インダクタ電極(下側インダクタ電極)4dと、インダクタ電極(上側インダクタ電極)4jとに分割して形成され、インダクタ電極4dとインダクタ電極4jとが、ビア電極5iにより接続されたものとすることが好ましい。この場合において、更に、誘電体層の積層方向において、第1平衡側インダクタの第2インダクタ部L32を形成するインダクタ電極4gと、第2平衡側インダクタの第2インダクタ部L42を形成するインダクタ電極4hとが、不平衡側インダクタL2のインダクタ電極4dとインダクタ電極4jとの間に挟み込まれて配置される。これにより、不平衡側インダクタL2と第1平衡側インダクタとを電磁界結合させ、同時に、不平衡側インダクタL2と第2平衡側インダクタとを電磁界結合させることができる。インダクタ電極4dの下側、および/または、インダクタ電極4jの上側に、更に、不平衡側インダクタL2を構成するインダクタ電極を追加することにより、これらの電磁界結合の強さを高めることができる。 In the multilayer body 1, an inductor electrode forming the unbalanced inductor L2 is divided into at least an inductor electrode (lower inductor electrode) 4d and an inductor electrode (upper inductor electrode) 4j, and the inductor electrode 4d. The inductor electrode 4j is preferably connected to the via electrode 5i. In this case, further, in the stacking direction of the dielectric layers, an inductor electrode 4g that forms the second inductor portion L32 of the first balanced-side inductor and an inductor electrode 4h that forms the second inductor portion L42 of the second balanced-side inductor. Is sandwiched between the inductor electrode 4d and the inductor electrode 4j of the unbalanced inductor L2. As a result, the unbalanced inductor L2 and the first balanced inductor can be electromagnetically coupled, and at the same time, the unbalanced inductor L2 and the second balanced inductor can be electromagnetically coupled. By further adding an inductor electrode constituting the unbalanced inductor L2 below the inductor electrode 4d and / or above the inductor electrode 4j, the strength of these electromagnetic field couplings can be increased.
 上記構成において、第1平衡側インダクタを構成するインダクタ電極4gと、第2平衡側インダクタを構成するインダクタ電極4hとは、それぞれ環状に形成される。不平衡側インダクタL2のインダクタ電極4dとインダクタ電極4jとを接続するビア電極5iは、第1平衡側インダクタの第2インダクタ部L32のインダクタ電極4gの環状部分の内側を貫通して配置されたものとすることが好ましい。この場合には、不平衡側インダクタのインダクタ電極4dとインダクタ電極4jとを接続するビア電極5iが形成する磁束と、第1平衡側インダクタの第2インダクタ部L32のインダクタ電極4gが形成する磁束とが、相互に直交し、両者の干渉が抑制されるため、不平衡側インダクタL2および第1平衡側インダクタの双方においてQの低下を抑制することができる。 In the above configuration, the inductor electrode 4g constituting the first balanced-side inductor and the inductor electrode 4h constituting the second balanced-side inductor are each formed in an annular shape. The via electrode 5i that connects the inductor electrode 4d and the inductor electrode 4j of the unbalanced inductor L2 is disposed so as to penetrate the inside of the annular portion of the inductor electrode 4g of the second inductor portion L32 of the first balanced inductor. It is preferable that In this case, the magnetic flux formed by the via electrode 5i connecting the inductor electrode 4d of the unbalanced inductor and the inductor electrode 4j, and the magnetic flux formed by the inductor electrode 4g of the second inductor portion L32 of the first balanced inductor. However, since they are orthogonal to each other and their interference is suppressed, it is possible to suppress a decrease in Q in both the unbalanced inductor L2 and the first balanced inductor.
 今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は、上記した説明ではなく、請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
 1 積層体、1a~1u 誘電体層、2a~2q キャパシタ電極、3a 接続電極、4a~4u インダクタ電極、4s1,4s2 環状部分、5a~5p ビア電極、100 積層バラン、Rx1,Tx1 第1端子、Rx2,Tx2 第2端子、C1 第1キャパシタ、C2 第2キャパシタ、C3 第3キャパシタ、C4 第4キャパシタ、C5 第5キャパシタ、DCfeed DCフィード端子、F1 第1浮遊端子、F2 第2浮遊端子、G1 第1グランド端子、G2 第2グランド端子、L1 第1インダクタ、L2 不平衡側インダクタ、L31,L41 第1インダクタ部、L32,L42 第2インダクタ部、L33,L43 第3インダクタ部、Rx 第2平衡端子、Tx 第1平衡端子、UB 不平衡端子。 1 laminated body, 1a to 1u dielectric layer, 2a to 2q capacitor electrode, 3a connection electrode, 4a to 4u inductor electrode, 4s1, 4s2 annular part, 5a to 5p via electrode, 100 laminated balun, Rx1, Tx1, first terminal, Rx2, Tx2 second terminal, C1 first capacitor, C2 second capacitor, C3 third capacitor, C4 fourth capacitor, C5 fifth capacitor, DCfeed DC feed terminal, F1 first floating terminal, F2 second floating terminal, G1 1st ground terminal, G2 2nd ground terminal, L1 1st inductor, L2 unbalanced inductor, L31, L41 1st inductor part, L32, L42 2nd inductor part, L33, L43 3rd inductor part, Rx 2nd balanced Terminal, Tx first balanced terminal, UB unbalanced terminal.

Claims (4)

  1.  複数の誘電体層が積層された積層体と、
     前記積層体の層間に形成された複数のインダクタ導体パターンと、
     前記積層体の表面に形成された複数の端子とを備えた積層バランであって、
     前記複数の端子は、不平衡端子と、第1平衡端子と、第2平衡端子と、グランド端子とを含み、
     前記第1平衡端子と前記第2平衡端子との各々は、第1端子と第2端子とを有し、
     前記複数のインダクタ導体パターンは、
     前記不平衡端子と前記グランド端子との間に電気的に接続された少なくとも1つの不平衡側インダクタ導体パターンと、
     前記第1平衡端子の前記第1端子と前記第1平衡端子の前記第2端子との間に電気的に接続された第1平衡側インダクタ導体パターンと、
     前記第2平衡端子の前記第1端子と前記第2平衡端子の前記第2端子との間に電気的に接続された第2平衡側インダクタ導体パターンとを含み、
     前記複数の誘電体層の積層方向から見たとき、前記第1平衡側インダクタ導体パターンによって囲まれた領域の少なくとも一部分は、前記少なくとも1つの不平衡側インダクタ導体パターンによって囲まれた領域と重なり、かつ前記第2平衡側インダクタ導体パターンによって囲まれた領域の少なくとも一部分は、前記少なくとも1つの不平衡側インダクタ導体パターンによって囲まれた領域と重なり、
     前記第1平衡側インダクタ導体パターンと前記第2平衡側インダクタ導体パターンとは、前記積層体の同一の層間に形成される、積層バラン。
    A laminate in which a plurality of dielectric layers are laminated;
    A plurality of inductor conductor patterns formed between the layers of the laminate;
    A laminated balun comprising a plurality of terminals formed on the surface of the laminated body,
    The plurality of terminals include an unbalanced terminal, a first balanced terminal, a second balanced terminal, and a ground terminal,
    Each of the first balanced terminal and the second balanced terminal has a first terminal and a second terminal;
    The plurality of inductor conductor patterns are:
    At least one unbalanced inductor conductor pattern electrically connected between the unbalanced terminal and the ground terminal;
    A first balanced-side inductor conductor pattern electrically connected between the first terminal of the first balanced terminal and the second terminal of the first balanced terminal;
    A second balanced-side inductor conductor pattern electrically connected between the first terminal of the second balanced terminal and the second terminal of the second balanced terminal;
    When viewed from the stacking direction of the plurality of dielectric layers, at least a part of the region surrounded by the first balanced inductor conductor pattern overlaps the region surrounded by the at least one unbalanced inductor conductor pattern, And at least a part of a region surrounded by the second balanced-side inductor conductor pattern overlaps with a region surrounded by the at least one unbalanced-side inductor conductive pattern;
    The first balanced-side inductor conductor pattern and the second balanced-side inductor conductor pattern are multilayer baluns formed between the same layers of the multilayer body.
  2.  前記複数の誘電体層は、連続して順に積層された第1~第3誘電体層を含み、
     前記少なくとも1つの不平衡側インダクタ導体パターンは、前記第1誘電体層と前記第2誘電体層との間に形成された第1不平衡側インダクタ導体パターンを含み、
     前記第1平衡側インダクタ導体パターンと前記第2平衡側インダクタ導体パターンとは、前記第2誘電体層と前記第3誘電体層との間に形成される、請求項1に記載の積層バラン。
    The plurality of dielectric layers include first to third dielectric layers stacked sequentially in sequence,
    The at least one unbalanced inductor conductor pattern includes a first unbalanced inductor conductor pattern formed between the first dielectric layer and the second dielectric layer;
    The multilayer balun according to claim 1, wherein the first balanced-side inductor conductor pattern and the second balanced-side inductor conductor pattern are formed between the second dielectric layer and the third dielectric layer.
  3.  前記複数の誘電体層は、前記第3誘電体層の前記第2誘電体層とは反対側に積層された第4誘電体層を含み、
     前記少なくとも1つの不平衡側インダクタ導体パターンは、前記第3誘電体層と前記第4誘電体層との間に形成される第2不平衡側インダクタ導体パターンをさらに含む、請求項2に記載の積層バラン。
    The plurality of dielectric layers include a fourth dielectric layer stacked on the opposite side of the third dielectric layer from the second dielectric layer,
    The at least one unbalanced inductor conductor pattern further includes a second unbalanced inductor conductor pattern formed between the third dielectric layer and the fourth dielectric layer. Laminated balun.
  4.  前記少なくとも1つの不平衡側インダクタ導体パターンは、2つの開いた環状部分を連結させた形状を有し、
     前記第1平衡側インダクタ導体パターンによって囲まれた領域の少なくとも一部分は、前記少なくとも1つの不平衡側インダクタ導体パターンの一方の環状部分によって囲まれた領域と重なり、かつ前記第2平衡側インダクタ導体パターンによって囲まれた領域の少なくとも一部分は、前記少なくとも1つの不平衡側インダクタ導体パターンの他方の環状部分によって囲まれた領域と重なる、請求項1から3のいずれか1項に記載の積層バラン。
    The at least one unbalanced inductor conductor pattern has a shape formed by connecting two open annular portions;
    At least a part of a region surrounded by the first balanced inductor conductor pattern overlaps a region surrounded by one annular portion of the at least one unbalanced inductor conductor pattern, and the second balanced inductor conductor pattern 4. The multilayer balun according to claim 1, wherein at least a part of a region surrounded by the second region overlaps a region surrounded by the other annular portion of the at least one unbalanced inductor conductor pattern.
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JP2012109950A (en) * 2010-10-21 2012-06-07 Murata Mfg Co Ltd Laminated filter

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WO2022244601A1 (en) * 2021-05-18 2022-11-24 株式会社村田製作所 Coil part

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