WO2018198501A1

WO2018198501A1 - Information processing device, information processing method and program

Info

Publication number: WO2018198501A1
Application number: PCT/JP2018/006036
Authority: WO
Inventors: 博信山崎
Original assignee: 富士通株式会社
Priority date: 2017-04-26
Filing date: 2018-02-20
Publication date: 2018-11-01
Also published as: JP6810356B2; JP2018185691A

Abstract

[Problem] To provide an information processing device capable of determining whether a circuit scheduled to be added to a reconfigurable circuit can be configured. [Solution] The information processing device includes: at least one reconfigurable circuit (134a); and control units (413, 417, 419) which control a circuit configuration of the reconfigurable circuit, wherein the control units stores a threshold value for each reconfigurable circuit, and determines whether a circuit scheduled to be added is configurable for each reconfigurable circuit on the basis of information which indicates consumption power of a circuit currently being executed, consumption power information based on information which indicates consumption power of the circuit scheduled to be added, and the threshold value.

Description

Information processing apparatus, information processing method, and program

The present invention relates to an information processing apparatus, an information processing method, and a program.

An information processing apparatus having a reconfigurable device, a configuration code memory, and a reconfigurable device controller is known (see Patent Document 1). The reconfigurable device realizes the circuit for executing a desired task in accordance with the configuration code so that the circuit can be changed. The configuration code memory stores configuration codes for realizing a plurality of circuits having different characteristics for each task executed by the reconfigurable device. The reconfiguration device controller controls loading of the configuration code to the reconfiguration device, selecting an appropriate circuit to be executed by the reconfiguration device according to the operating state of the system from among a plurality of circuits having different characteristics.

Also known is a server load distribution method having a plurality of server devices that provide services in response to service requests and a load distribution device that transfers the service requests to any of the server devices (see Patent Document 2). . Each server device has means for detecting the server load, and means for comparing the server load with a threshold and notifying the comparison result to the load distribution device. The load distribution apparatus includes means for managing the load status of each server apparatus based on the comparison result notified from each server apparatus, and means for selecting a server apparatus having a low load and transferring a service request.

JP 2007-179358 A JP 2012-88797 A

∙ When the reconstructed device becomes hot, there is a possibility of performance degradation and failure rate increase. However, the reconfigurable device can change the circuit, and the power consumption and the heat generation amount change depending on the changed circuit. Therefore, it is difficult to manage the temperature of the reconfigurable device.

In one aspect, an object of the present invention is to provide an information processing apparatus, an information processing method, and a program capable of determining whether a circuit scheduled to be added to a reconfigurable circuit can be configured.

The information processing apparatus includes at least one reconfigurable circuit and a control unit that controls a circuit configuration of the reconfigurable circuit, and the control unit stores a threshold value for each of the reconfigurable circuits, For each reconfigurable circuit, the circuit to be added can be configured based on the power consumption information based on the information indicating the power consumption of the currently executing circuit, the power consumption of the circuit to be added, and the threshold value. Determine whether or not.

In one aspect, it can be determined whether or not a circuit to be added to the reconfigurable circuit can be configured.

FIG. 1 is a diagram illustrating a configuration example of an information processing apparatus according to the first embodiment. FIG. 2 is a diagram illustrating a configuration example of the first FPGA server. 3A to 3C are diagrams showing examples of task assignment to FPGAs. FIG. 4 is a diagram illustrating a functional configuration example of the information processing apparatus. FIG. 5 is a sequence diagram illustrating an example of an information processing method of the information processing apparatus. 6A is a time chart showing the threshold values of the FPGAs of the first to fifth FPGA servers, and FIG. 6B is a time chart showing the power consumption of the FPGAs of the first to fifth FPGA servers. FIG. 6C is a time chart showing the average power consumption of the FPGAs of the first to fifth FPGA servers, and FIG. 6D is the total power consumption of the whole FPGA of the first to fifth FPGA servers. 4 is a time chart showing the maximum power consumption of one FPGA. FIG. 7A is a time chart showing an example of the threshold value of the FPGA of the first to fifth FPGA servers according to the second embodiment, and FIG. 7B is a diagram of the FPGA of the first to fifth FPGA servers. It is a time chart which shows power consumption.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration example of an information processing apparatus according to the first embodiment. In order to realize a cloud service, the information processing apparatus includes a client 100, a management server 110, a network 120, and first to fifth field programmable gate array (FPGA) servers 1.
30a to 130e. Note that the number of FPGA servers 130a to 130e is not limited to five.

The client 100 is a computer, and includes a central processing unit (CPU) 101, a random access memory (RAM) 102, and a hard disk drive (HDD) unit 103. The CPU 101 reads a program from the HDD unit 103, expands the read program in the RAM 102, and executes the program expanded in the RAM 102. The client 100 can request the management server 110 to execute the task, and obtain the task execution result from the management server 110.

The management server 110 is a computer and includes a CPU 111, a RAM 112, and an HDD unit 113. The CPU 111 reads a program from the HDD unit 113, expands the read program in the RAM 112, and executes the program expanded in the RAM 112. The management server 110 assigns tasks to the first to fifth FPGA servers 130a to 130e via the network 120, acquires task execution results from the first to fifth FPGA servers 130a to 130e, and executes the execution results. Is output to the client 100.

The first FPGA server 130a is a computer, and includes a CPU 131a, a RAM 132a, an HDD unit 133a, and an FPGA 134a. Similarly, the second to fifth FPGA servers 130b to 130e are computers, and include CPUs 131b to 131e, RAMs 132b to 132e, HDD units 133b to 133e, and FPGAs 134b to 134e, respectively. The CPUs 131a to 131e read the programs from the HDD units 133a to 133e, respectively, expand the read programs in the RAMs 132a to 132e, and execute the programs expanded in the RAMs 132a to 132e. The FPGAs 134a to 134e are reconfigurable circuits whose circuits can be changed. Each of the first to fifth FPGA servers 130a to 130e configures a circuit corresponding to the task requested from the management server 110 in the FPGAs 134a to 134e, executes the circuit, and transmits the execution result data to the network 120. To the management server 110.

FIG. 2 is a diagram illustrating a configuration example of the first FPGA server 130a. The configuration of the first FPGA server 130a will be described as an example, but the configurations of the second to fifth FPGA servers 130b to 130e are the same as the configuration of the first FPGA server 130a.

The first FPGA server 130a includes a CPU 131a, a RAM 132a, an HDD unit 133a, and an FPGA 134a. The HDD unit 133a stores circuit information (configuration codes) 201 to 208 and circuit attached information 211 to 218 for configuring the task circuit in the FPGA 134a.

The circuit information 201 is circuit information for configuring the task A circuit on the top of the FPGA 134a. The circuit information 202 is circuit information for configuring the task A circuit second from the top of the FPGA 134a. The circuit information 203 is circuit information for configuring the task A circuit third from the top of the FPGA 134a. The circuit information 204 is circuit information for configuring the task A circuit at the bottom of the FPGA 134a.

The circuit information 205 is circuit information for configuring the task B circuit at the upper left of the FPGA 134a. The circuit information 206 is circuit information for configuring the task B circuit on the upper right side of the FPGA 134a.

The circuit information 207 is circuit information for configuring the task C circuit under the FPGA 134a. The circuit information 208 is circuit information for configuring the task C circuit on the FPGA 134a.

The circuit attached information 211 to 218 is information attached to the circuit information 201 to 208, respectively. The circuit ancillary information 211 to 218 includes a circuit size 221 and an operating frequency 222, respectively. The circuit ancillary information 211 to 214 includes a circuit size 221 and an operating frequency 222 of the circuit of task A, respectively. The circuit

ancillary information

215 and 216 include the circuit size 221 and the operating frequency 222 of the task B circuit, respectively. The circuit

ancillary information

217 and 218 include the circuit size 221 and the operating frequency 222 of the task C circuit, respectively.

The management server 110 generates circuit information 201 to 208 and circuit attached information 211 to 128, and outputs the circuit information 201 to 208 and circuit attached information 211 to 128 to the first to fifth FPGA servers 130a to 130e. In the first to fifth FPGA servers 130a to 130e, the CPUs 131a to 131e respectively write circuit information 201 to 208 and circuit attached information 211 to 128 in the HDD units 133a to 133e.

FIG. 3A shows an example of FPGAs 134a to 134c before task C is assigned. The first FPGA 134a includes four task A circuits and one task B circuit. In the second FPGA 134b, two task B circuits are configured. No circuit is configured in the third FPGA 134c. The management server 110 can add the circuit of task C to the

FPGA

134b or 134c using the

circuit information

207 or 208 of task C.

FIG. 3B is a diagram illustrating an example in which the management server 110 assigns a task C circuit to the FPGA 134b. The management server 110 assigns task C to the second FPGA server 130b. Then, the second FPGA server 130b writes the circuit information 207 in the HDD unit 133b to the FPGA 134b. Then, a task C circuit is additionally configured in the FPGA 134b.

FIG. 3C is a diagram showing an example in which the management server 110 assigns two task C circuits to the FPGA 134c. The management server 110 assigns two tasks C to the third FPGA server 130c. Then, the third FPGA server 130c writes the

circuit information

207 and 208 in the HDD unit 133c to the FPGA 134c. Then, two tasks C circuits are additionally configured in the FPGA 134c.

If the FPGAs 134a to 134e become too high in temperature, there is a possibility of performance degradation and failure rate increase due to thermal noise. The FPGAs 134a to 134e have power consumption (heat generation amount) greatly different depending on a circuit to be written, so that temperature management is difficult. If the temperature management of the FPGAs 134a to 134e is not performed, the FPGAs 134a to 134e may ignite. When tasks concentrate on a part of the plurality of FPGAs 134a to 134e, the part of the FPGA becomes very hot. Therefore, the management server 110 efficiently operates the first to fifth FPGA servers 130a to 130e by appropriately assigning tasks to the first to fifth FPGA servers 130a to 130e. Specifically, the management server 110 suppresses the overall power consumption of the FPGAs 134a to 134e of the first to fifth FPGA servers 130a to 130e, and the task concentrates on one FPGA, resulting in an abnormally high temperature. Assign tasks to avoid.

FIG. 4 is a diagram illustrating a functional configuration example of the information processing apparatus. The information processing apparatus includes a client 100, a management server 110, and first to fifth FPGA servers 130a to 130e. The management server 110 has a module 400. The module 400 is a program module executed by the CPU 111. The module 400 includes an FPGA execution management unit 401, an execution FPGA server selection unit 402, an execution availability inquiry unit 403, a task reception unit 404, and a threshold control unit 405.

The first FPGA server 130a includes a RAM 132a, an HDD unit 133a, an FPGA 134a, and a module 410. The RAM 132a has a threshold storage unit 413. The HDD unit 133 a includes a circuit information storage unit 411 and a circuit attached information storage unit 412. The circuit information storage unit 411 stores the circuit information 201 to 208 in FIG. The circuit attached information storage unit 412 stores circuit attached information 211 to 218 shown in FIG.

The module 410 is a module of a program executed by the CPU 131a. The module 410 includes an execution result processing unit 414, an execution control unit 415, a circuit information management unit 416, a circuit information writing unit 417, a power consumption calculation unit 418, and an execution availability determination unit 419. The circuit information writing unit 417 is a control unit, and can control the circuit configuration of the FPGA 134a by writing circuit information to the FPGA 134a.

The second to fifth FPGA servers 130b to 130e have the same configuration as that of the first FPGA server 130a.

FIG. 5 is a sequence diagram illustrating an example of an information processing method of the information processing apparatus. Here, a case will be described as an example where the first to fifth FPGA servers 130a to 130e are in operation and the sixth FPGA server is inactive. The sixth FPGA server has the same configuration as the first to fifth FPGA servers 130a to 130e.

As shown in FIG. 6A, the management server 110 instructs the first to fifth FPGA servers 130a to 130e to set initial values (maximum values) of the threshold values 601a to 601e in order by the threshold control unit 405. To do. The first FPGA server 130 a writes the initial value of the threshold 601 a in the threshold storage unit 413 by the execution availability determination unit 419. Similarly, each of the second to fifth FPGA servers 130b to 130e causes the threshold storage unit 41 to execute the execution determination unit 419.
3 is written with initial values of threshold values 601b to 601e. Thereafter, the management server 110 causes the threshold value control unit 405 to decrease the threshold values 601a to 601e with respect to the first to fifth FPGA servers 130a to 130e at regular intervals as shown in FIG. 6A. Next, the thresholds 601a to 601e are instructed to be updated in order. This update instruction corresponds to steps S507 and S509. Details thereof will be described later. Each of the first to fifth FPGA servers 130a to 130e receives an update instruction, and updates the threshold value 601a to 601e of the threshold value storage unit 413 so that the threshold value 601a to 601e decreases by the execution availability determination unit 419. As shown in FIG. 6A, the management server 110 instructs the threshold values 601a to 601e to be set to initial values (maximum values) in order when the threshold values 601a to 601e become 0, as shown in FIG. 6A. The threshold values 601a to 601e of the FPGAs 134a to 134e of the first to fifth FPGA servers 130a to 130e periodically change as shown in FIG.

In step S501, the client 100 outputs a task C execution request to the management server 110. Then, the management server 110 receives an execution request for the task C by the task receiving unit 404.

Next, in step S502, the management server 110 causes the execution availability inquiry unit 403 to output an inquiry about whether task C can be executed to the first to fifth FPGA servers 130a to 130e in operation.

Next, in step S503, each of the first to fifth FPGA servers 130a to 130e causes the power consumption calculation unit 418 to add information indicating the power consumption of the circuit currently being executed for each FPGA 134a to 134e, and to be added. Information indicating the power consumption of the circuit of task C is added to obtain information indicating the overall power consumption.

For example, an example of the FPGA 134b in FIG. The execution control unit 415 outputs information on the two tasks B currently being executed to the circuit information management unit 416. The circuit attachment information storage unit 412 outputs the

circuit attachment information

215 and 216 of the two tasks B to the power consumption calculation unit 418 under the control of the circuit information management unit 416. The power consumption calculation unit 418 calculates power consumption by multiplying the circuit size 221 and the operating frequency 222 for each of the circuit attached

information

215 and 216, and adds the power consumption to obtain the two currently executed. The power consumption of the circuit of task B is obtained. Next, the power consumption calculation unit 418 obtains the power consumption of the circuit of the task C to be added by multiplying the circuit size 221 of the circuit ancillary information 217 of the task C to be added by the operating frequency 222. Next, the power consumption calculation unit 418 adds the power consumption of the circuits of the two tasks B that are currently being executed and the power consumption of the circuit of the task C that is scheduled to be added, and determines whether or not the entire power consumption can be executed. Output to.

Although the example of the second FPGA server 130b has been described, the

other FPGA servers

130a and 130c to 130e similarly calculate the overall power consumption.

Next, in step S504, the first to fifth FPGA servers 130a to 130e output the power consumption calculation unit 418 from the threshold values 601a to 601e stored in the threshold value storage unit 413 by the execution determination unit 419, respectively. The total power consumption is subtracted, and the result of the subtraction is output to the execution FPGA server selection unit 402 of the management server 110 as an execution propriety answer.

When the overall power consumption is smaller than the threshold value, the subtraction result is a positive value, indicating that the FPGA can execute the circuit of the additional task C. When the overall power consumption is larger than the threshold value, the subtraction result is a negative value, indicating that the FPGA cannot execute the circuit of the additional task C.

The execution determination unit 419 of each of the first to fifth FPGA servers 130a to 130e is a determination unit, and information indicating the power consumption of the circuit of the task currently being executed and the task to be added for each of the FPGAs 134a to 134e. Whether or not the circuit to be added can be configured is determined based on the power consumption information based on the information indicating the power consumption of the circuit and the threshold values 601a to 601e.

In step S505, the management server 110 causes the execution FPGA server selection unit 402 to have the largest value among the subtraction results of the first to fifth FPGA servers 130a to 130e, and the subtraction result is a positive value. The task C execution request is output to the execution control unit 415 of the FPGA server 130b. That is, the management server 110 instructs the circuit 134 of the task C to be added to the FPGA 134b of the second FPGA server 130b.

When all of the subtraction results of the first to fifth FPGA servers 130a to 130e that are in operation are negative values, the management server 110 uses the execution FPGA server selection unit 402 to change to the sixth FPGA server that is suspended. On the other hand, an execution request for task C is output, and the circuit configuration of task C is instructed to the FPGA of the sixth FPGA server. At that time, the management server 110 sets an initial value of the threshold for the suspended sixth FPGA server by the threshold control unit 405. Note that the sixth FPGA server being suspended can reduce the overall power consumption by not assigning tasks as much as possible.

Next, in step S506, the second FPGA server 130b instructs the execution control unit 415 to start executing task C. The circuit information writing unit 417 reads the circuit information 207 of task C from the circuit information storage unit 411, and writes the circuit information 207 to the FPGA 134b. As a result, as shown in FIG. 3B, a circuit for task C is added to the FPGA 134b. The FPGA 134b starts executing the circuits of two tasks B and one task C.

If the two task C circuits are to be processed in parallel as in the FPGA 134c of FIG. 3C, the process returns to step S502, and the management server 110 again outputs a task C execution possibility inquiry. That's fine. That is, the management server 110 may repeat the execution availability inquiry process by the number of parallel processes.

Next, in step S507, the management server 110 uses the threshold control unit 405 to set threshold values for the first to fifth FPGA servers 130a to 130e after a predetermined time has elapsed since the initial setting of the threshold values 601a to 601e. An update instruction for decreasing 601a to 601e is output.

Next, in step S508, the first to fifth FPGA servers 130a to 130e in operation are updated by the execution availability determination unit 419 so that the threshold value of the threshold value storage unit 413 decreases. Then, each of the first to fifth FPGA servers 130a to 130e calculates the power consumption of the circuit of the task currently being executed by the power consumption calculation unit 418 and outputs the calculated power consumption to the execution determination unit 419. To do. Then, the first to fifth FPGA servers 130a to 130e respectively subtract the power consumption output from the power consumption calculation unit 418 from the threshold values 601a to 601e stored in the threshold value storage unit 413 by the execution availability determination unit 419. If the subtraction result is a positive value, execution of the task circuits of the FPGAs 134a to 134e is continued.

Next, in step S509, the management server 110 causes the threshold control unit 405 to respectively perform the first to fifth FPGA servers 130a to 130e after a predetermined time has elapsed since the update of the thresholds 601a to 601e in step S507. An update instruction for decreasing the threshold values 601a to 601e is output.

Next, in step S510, the first to fifth FPGA servers 130a to 130 in operation.
As in step S508, e is updated so that the threshold value of the threshold value storage unit 413 decreases. Then, the first to fifth FPGA servers 130a to 130e respectively subtract the power consumption output from the power consumption calculation unit 418 from the threshold values 601a to 601e stored in the threshold value storage unit 413 by the execution availability determination unit 419. To do. The first, third to

fifth FPGA servers

130a and 130c to 130e respectively execute the task circuits of the

FPGAs

134a and 134c to 134e when the subtraction result is a positive value by the execution determination unit 419. Let it continue.

In step S511, the second FPGA server 130b compares the power consumption with the threshold value 601b by the execution determination unit 419, and determines that the power consumption is larger than the threshold value 601b and the subtraction result is a negative value. In this case, in step S512, the second FPGA server 130b causes the execution availability determination unit 419 to reduce the power consumption from the threshold value 601b in order from the task circuit with the largest power consumption among the circuits of the task being executed. Until execution is stopped. In the second FPGA server 130b, the execution result processing unit 414 writes the intermediate result data of the task circuit of the stopped FPGA 134b and the recovery point indicating the stop point in the RAM 132b.

Next, in step S513, the second FPGA server 130b causes the execution result processing unit 414 to output a task execution request including the intermediate result data and the recovery point to the FPGA execution management unit 401 of the management server 110.

At this time, the second FPGA server 130b changes the threshold value of the threshold value storage unit 132a to 0 as shown by the threshold value 610 in FIG. 6A by the execution determination unit 419 and completes the execution of the task circuit. The threshold value of the threshold value storage unit 132a is set to the initial value. The threshold value 610 in FIG. 6A indicates the threshold value of the FPGA 134c of the third FPGA server 130c, but the threshold value of the FPGA 134b of the second FPGA server 130b is the same.

Next, in step S514, the FPGA execution management unit 401 outputs the task execution request to the task reception unit 404. The task reception unit 404 outputs a task execution request to the execution availability inquiry unit 403. The management server 110 outputs a task execution permission inquiry to the first, third to

fifth FPGA servers

130a and 130c to 130e by the execution permission inquiry section 403.

Next, in step S515, the first, third to

fifth FPGA servers

130a, 130c to 130e are currently being executed for each of the

FPGAs

134a, 134c to 134e by the execution determination unit 419 in the same manner as in step S503. Information indicating the power consumption of the circuit and the information indicating the power consumption of the circuit of the task to be added are added to obtain information indicating the overall power consumption.

Next, in step S516, the first, third to

fifth FPGA servers

130a, 130c to 130e are caused to execute the threshold value 601a stored in the threshold value storage unit 413 by the execution availability determination unit 419, similarly to step S504. The total power consumption output from the power consumption calculation unit 418 is subtracted from 601c to 601e, and the subtraction result is output to the execution FPGA server selection unit 402 of the management server 110 as an execution availability answer.

Next, in step S517, the management server 110 has the largest value among the subtraction results of the first, third to

fifth FPGA servers

130a, 130c to 130e by the execution FPGA server selection unit 402, and performs subtraction. A task execution request is output to the execution control unit 415 of the first FPGA server 130a whose result is a positive value. The execution request includes the intermediate result data and the recovery point.

If all of the subtraction results of the first, third to

fifth FPGA servers

130a, 130c to 130e are negative values, the management server 110 causes the execution FPGA server selection unit 402 to execute the suspended sixth FPGA. The task execution request is output to the server. At that time, the management server 110 sets an initial value of the threshold for the suspended sixth FPGA server by the threshold control unit 405.

Next, in step S518, the first FPGA server 130a reads the circuit information of the task from the circuit information storage unit 411 by the circuit information writing unit 417, and writes the circuit information in the FPGA 134a. Then, the first FPGA server 130a causes the execution control unit 415 to input the intermediate result data to the FPGA 134a and instruct to resume execution from the recovery point of the task. Thereby, a task circuit is added to the FPGA 134a. The FPGA 134a resumes execution of the task circuit.

When the execution of the task circuit of the FPGA 134 a is completed, the first FPGA server 130 a outputs the execution result data of the FPGA 134 a to the FPGA execution management unit 401 of the management server 110 by the execution result processing unit 414. The FPGA execution management unit 401 outputs execution result data to the client 100 via the task reception unit 404.

FIG. 6A is a time chart showing threshold values 601a to 601e of the FPGAs 134a to 134e of the first to fifth FPGA servers 130a to 130e. FIG. 6B corresponds to FIG. 6A and is a time chart showing power consumption 602a to 602e of the FPGAs 134a to 134e of the first to fifth FPGA servers 130a to 130e. The management server 110 updates the threshold values 601a to 601e of the FPGAs 134a to 134e of the first to fifth FPGA servers 130a to 130e by rotation. As a result, the management server 110 can, on average, make a task execution request to the first to fifth FPGA servers 130a to 130e by rotation. As shown in FIG. 6B, the power consumptions 602a to 602e of the FPGAs 134a to 134e of the first to fifth FPGA servers 130a to 130e are not biased and are compared with the first to fifth FPGA servers 130a to 130e. It can be seen that the tasks are distributed almost evenly.

FIG. 6C is a time chart showing average power consumption of the FPGAs 134a to 134e of the first to fifth FPGA servers 130a to 130e. The FPGAs 134a to 134e of the first to fifth FPGA servers 130a to 130e have substantially the same average power consumption and the same amount of heat generation. The management server 110 can prevent the task from being concentrated on some of the first to fifth FPGA servers 130a to 130e and resulting in an abnormally high temperature. The FPGAs 134a to 134e can prevent performance degradation and failure rate increase due to high temperatures.

FIG. 6D is a time chart showing the total power consumption 604 of the entire FPGAs 134a to 134e of the first to fifth FPGA servers 130a to 130e and the maximum power consumption 605 of one FPGA. It can be seen that the management server 110 reduces the total power consumption 604 of the entire FPGAs 134a to 134e of the first to fifth FPGA servers 130a to 130e, and reduces the maximum power consumption 605 of one FPGA. . As a result, it is possible to prevent the task from being concentrated on the FPGAs of some of the FPGA servers and causing an abnormally high temperature.

It is also conceivable to provide a fan for cooling the FPGAs 134a to 134e. However, providing a fan increases power consumption. In this embodiment, since no fan is provided, it is possible to prevent abnormally high temperatures of the FPGAs 134a to 134e with low power consumption.

Also, each of the first to fifth FPGA servers 130a to 130e compares the power consumption with the threshold value by the execution determination unit 419 to determine whether or not the circuits of tasks scheduled to be added to the FPGAs 134a to 134e can be configured. Can be judged.

In steps S502 and S514, the management server 110 can output an execution feasibility inquiry only to the FPGA server to which tasks can be added, according to the free space of the FPGAs 134a to 134e. The management server 110 grasps the circuit of the task being executed by the FPGAs 134a to 134e of the FPGA servers 130a to 130e. For example, the FPGA 134a of the first FPGA server 130a in FIG. 3A has a small empty space and cannot add a task C circuit. In this case, the management server 110 outputs an execution availability inquiry to an FPGA server other than the first FPGA server 130a.

In the above description, the case where the plurality of FPGA servers 130a to 130e have the plurality of FPGAs 134a to 134e has been described as an example. However, one FPGA server may have the plurality of FPGAs 134a to 134e. Further, each of the FPGA servers 130a to 130e may have a plurality of FPGAs.

(Second Embodiment)
FIG. 7A is a time chart showing an example of threshold values 701a to 701e of the FPGAs 134a to 134e of the first to fifth FPGA servers 130a to 130e according to the second embodiment. This embodiment differs from the first embodiment in the threshold control method of the management server 110. Hereinafter, the difference of the present embodiment from the first embodiment will be described with reference to FIGS. 4 and 5.

In the first embodiment, in step S505, when all the subtraction results of the first to fifth FPGA servers 130a to 130e in operation are negative values, the management server 110 uses the execution FPGA server selection unit 402 to An execution request for task C is output to the suspended sixth FPGA server.

On the other hand, in this embodiment, when all the subtraction results of the operating first to fifth FPGA servers 130a to 130e are negative values in step S505, the management server 110 uses the threshold control unit 405 to When the sum of the threshold values 701a to 701e of the FPGAs 134a to 134e of the first to fifth FPGA servers 130a to 130e in operation is smaller than the first value, as shown in FIG. An instruction to increase the smallest threshold value 701a among the threshold values 701a to 701e of the FPGAs 134a to 134e of the first to fifth FPGA servers 130a to 130e to the threshold value 702 is output to the first FPGA server 130a. Here, the threshold control unit 405 sets the threshold 701a to the threshold 702 within a range where the sum of the thresholds 701a to 701e of the FPGAs 134a to 134e of the first to fifth FPGA servers 130a to 130e in operation does not exceed the first value. The instruction to increase is output.

Then, the first FPGA server 130a increases the threshold value of the threshold value storage unit 413 by the execution possibility determination unit 419. Next, the first FPGA server 130a causes the execution determination unit 419 to subtract the overall power consumption output from the power consumption calculation unit 418 from the threshold value 702 stored in the threshold value storage unit 413, and the subtraction result is obtained. The data is output to the execution FPGA server selection unit 402 of the management server 110.

When the subtraction result of the first FPGA server 130a is a positive value, the management server 110 outputs an execution request for task C to the execution control unit 415 of the first FPGA server 130a. To do. Thereafter, the first FPGA server 130a starts executing the circuit of the task C as in step S506.

In step S517, if all of the subtraction results of the first, third to

fifth FPGA servers

130a, 130c to 130e are negative values, the management server 110 causes the threshold control unit 405 to execute the first, third, If the sum of the threshold values 701a and 701c to 701e of the

FPGAs

134a and 134c to 134e of the

fifth FPGA servers

130a and 130c to 130e is smaller than the first value, the first, third to fifth FPGA servers 130a, An instruction to increase the threshold value 701a of the FPGA 134a of the first FPGA server 130a among the threshold values 701a and 701c to 701e of the

FPGAs

134a and 130c to 134e of 130c to 130e is output to the first FPGA server 130a. Here, the threshold control unit 405 increases the threshold 701a in a range where the sum of the thresholds 701a to 701e of the FPGAs 134a to 134e of the first to fifth FPGA servers 130a to 130e in operation does not exceed the first value. Output instructions.

When the subtraction result of the first FPGA server 130a is a positive value, the management server 110 outputs a task execution request to the execution control unit 415 of the first FPGA server 130a. . Thereafter, in step S508, the first FPGA server 130a resumes execution of the task circuit.

FIG. 7B corresponds to FIG. 7A and is a time chart showing power consumption 703a to 703e of the FPGAs 134a to 134e of the first to fifth FPGA servers 130a to 130e. The management server 110 temporarily increases the threshold 702 in order to be able to cope with temporary task concentration. As a result, the power consumption 704 temporarily increases. However, other than that time, in this embodiment, as in the first embodiment, the power consumption 703a to 703e of the FPGAs 134a to 134e of the first to fifth FPGA servers 130a to 130e is not biased, and Tasks are distributed almost uniformly to the FPGAs 134a to 134e of the fifth FPGA servers 130a to 130e.

This embodiment can be realized by a computer executing a program. Further, a computer-readable recording medium in which the above program is recorded and a computer program product such as the above program can also be applied as an embodiment of the present invention. As the recording medium, for example, a flexible disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

It should be noted that each of the above-described embodiments is merely a specific example for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

100

Client

101, 111, 131a to 131e CPU
102, 112, 132a to 132e RAM
103, 113, 133a to 133e HDD unit 110 Management server 120 Network 130a to 130e FPGA server 134a to 134e FPGA

Claims

At least one reconfigurable circuit;
A control unit for controlling the circuit configuration of the reconfigurable circuit,
The control unit stores a threshold value for each of the reconfigurable circuits, and for each of the reconfigurable circuits, consumption based on information indicating power consumption of a currently executing circuit and information indicating power consumption of a circuit to be added An information processing apparatus that determines whether or not a circuit to be added can be configured based on power information and the threshold value.
Furthermore, according to the determination result for each of the reconfigurable circuits, a selection unit that instructs the configuration of the circuit to be added to one of the at least one reconfigurable circuit. The information processing apparatus according to claim 1.
3. The information processing apparatus according to claim 1, wherein the threshold value is updated so as to decrease at regular time intervals.
When the threshold is updated, the control unit compares information indicating the power consumption of the currently executing circuit with the threshold for the reconfigurable circuit with the updated threshold, and the currently executing circuit. If the information indicating the power consumption is greater than the threshold, execution of at least one of the currently executing circuits is stopped,
4. The information processing apparatus according to claim 1, further comprising an execution management unit that causes another reconfigurable circuit to resume execution of the stopped circuit.
The selection unit instructs the reconfigurable circuit having the smallest value obtained by subtracting the power consumption information from the threshold among the at least one reconfigurable circuit to configure the circuit to be added. The information processing apparatus according to claim 2.
The selection unit is configured to configure the circuit to be added to the reconfigurable circuit that is in a suspended state when there is no reconfigurable circuit whose power consumption information is smaller than the threshold among the reconfigurable circuits that are in operation. The information processing apparatus according to claim 2, wherein
Furthermore, if there is no reconfigurable circuit whose power consumption information is smaller than the threshold among the reconfigurable circuits in operation, and the total threshold of the at least one reconfigurable circuit is smaller than a first value 6. The information processing apparatus according to claim 2, further comprising a threshold control unit configured to increase a smallest threshold among the thresholds of the at least one reconfigurable circuit.
The information processing apparatus according to any one of claims 1 to 7, wherein the control unit obtains information indicating the power consumption by multiplying a circuit size and an operating frequency.
An information processing method for an information processing apparatus having at least one reconfigurable circuit,
The storage unit of the information processing apparatus stores a threshold value for each reconfigurable circuit,
The determination unit included in the information processing apparatus includes, for each reconfigurable circuit, power consumption information based on information indicating power consumption of a currently executing circuit, information indicating power consumption of a circuit to be added, and the threshold value. And determining whether or not a circuit to be added can be configured based on the information processing method.
Set a threshold for at least one reconfigurable circuit;
For each reconfigurable circuit, a circuit to be added is configured based on power consumption information based on information indicating the power consumption of the currently executing circuit, information indicating the power consumption of the circuit to be added, and the threshold value. Determine whether it is possible,
A program that causes a computer to execute processing.