WO2018198325A1 - Système de stockage - Google Patents

Système de stockage Download PDF

Info

Publication number
WO2018198325A1
WO2018198325A1 PCT/JP2017/016951 JP2017016951W WO2018198325A1 WO 2018198325 A1 WO2018198325 A1 WO 2018198325A1 JP 2017016951 W JP2017016951 W JP 2017016951W WO 2018198325 A1 WO2018198325 A1 WO 2018198325A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
processor
memory
storage
address
Prior art date
Application number
PCT/JP2017/016951
Other languages
English (en)
Japanese (ja)
Inventor
健太郎 島田
山本　彰
定広 杉本
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to PCT/JP2017/016951 priority Critical patent/WO2018198325A1/fr
Priority to JP2017170379A priority patent/JP6734824B2/ja
Priority to US15/959,675 priority patent/US10402361B2/en
Priority to CN201810390254.7A priority patent/CN108804030B/zh
Publication of WO2018198325A1 publication Critical patent/WO2018198325A1/fr
Priority to US16/524,375 priority patent/US10789196B2/en

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers

Definitions

  • the present invention relates to a storage system.
  • a storage system generally has a storage controller and a plurality of randomly accessible non-volatile storage devices.
  • the nonvolatile storage device is, for example, a hard disk drive (HDD) or a solid state drive (SSD). There is also an example where both are mixed.
  • Patent Document 1 discloses a storage system having a back-end switch.
  • the storage system is provided with, for example, two storage control units, so that even if one of them stops operating, the remaining one can continue the operation as a storage system to maintain availability.
  • the two storage control units are connected via a special communication path different from the back-end switch, and exchange various control information.
  • Patent Document 1 discloses a configuration having two storage control units and a bus different from the back-end switch between them.
  • the communication path between the two storage control units uses a communication standard that is easy to connect directly to the processor included in the storage control unit in order to suppress overhead related to communication.
  • a communication standard that can be directly connected to such a processor is PCI Express, which is a communication standard between a processor and an input / output device.
  • SCSI Serial Computer System Interface
  • Fiber Channel or SAS (Serial Attached SCSI) is generally used as the communication standard between the storage control unit and the storage device that is aggregated by the back-end switch. .
  • the communication standard communication path between these storage control units and storage devices cannot be directly connected to the processor provided in the storage control unit, and a dedicated interface is required to use for communication between the storage control units.
  • Patent Document 2 discloses a technique for performing communication between different storage control units via a back-end switch.
  • the technology disclosed in Patent Document 2 enables communication between different storage control units by using a shared storage area included in the back-end switch.
  • NVM Express compatible with PCI Express has been newly used as a communication standard between the storage control unit and the storage device.
  • a storage system configured using the conventional technology uses a communication standard that can be easily connected to a processor of a storage control unit such as PCI Express for communication between two storage control units. For this reason, the conventional storage system requires a special communication path exclusively between the storage control units.
  • PCI Express is a communication standard between a processor and an input / output device, and does not stipulate communication between two processors of two storage control units. Therefore, by simply using PCI Express, even if a physical communication path can be directly connected to the processor, the communication procedure between the two processors cannot be determined, so communication between the two processors cannot be performed.
  • the communication standard between the storage control unit and the storage device aggregated by the back-end switch is not compatible with the communication standard between such storage control units. Communication between storage control units via the back-end switch is difficult.
  • the technique disclosed in Patent Document 2 requires periodic inspection of the shared storage area of the back-end switch and the shared area for communication detection by the storage control unit.
  • the communication between the storage control units via the back-end switch requires special means and causes a performance overhead.
  • NVM Express which is compatible with PCI Express, is a communication standard between one storage control unit and a storage device, and does not stipulate any communication between the two storage control units. For this reason, communication between the two storage control units cannot be performed by NVM Express.
  • An example of the present invention includes a first storage control unit including a first processor and a first memory, a second storage control unit including a second processor and a second memory, and one or more storage devices.
  • One or more back-end switches connecting the first processor, the second processor, and the one or more storage devices, each of the one or more back-end switches being the first processor
  • a destination of the frame is identified with reference to the frame received from the first processor, and when the destination of the frame is the second processor, the second processor includes the second processor in the address space of the first processor.
  • a first address that identifies a location on the second memory and a first address that identifies the location on the second memory in the address space of the second processor.
  • the frame including the second address is sent to the second storage control unit, and the destination of the frame is the first storage device in the one or more storage devices
  • a storage system for transmitting the frame to the first storage device without converting a third address included in the frame and identifying the first storage device in the address space of the first processor It is.
  • Another example of the present invention includes a first storage control unit including a first processor and a first memory, a second storage control unit including a second processor and a second memory, and one or more memories.
  • a data transfer instruction including an address of 5 and a data length to be transferred is received from the first processor, and the fifth address is an address of the second processor.
  • converting to a sixth address that identifies the second location on the second memory The storage system transfers the first data having the data length to the storage system.
  • efficient communication between storage control units is enabled via a back-end switch that connects between the storage control unit and the storage device.
  • FIG. 1 is a configuration example of a storage system.
  • FIG. 2 shows another configuration example of the storage system.
  • FIG. 3A shows an example of data request, data return, and data transmission frames communicated between storage control units.
  • FIG. 3B is an example of a switching information table for determining a switching operation for an address given to a frame sent from the processor in the back-end switch.
  • FIG. 3C is a diagram illustrating an example of a flowchart illustrating a processing procedure when the back-end switch receives data transmission or a data request from the processor.
  • FIG. 4A shows an example of a switching information table.
  • FIG. 4B is a diagram illustrating an example of a flowchart illustrating a processing procedure when the back-end switch receives data transmission or a data request from the storage device.
  • FIG. 5A is a diagram illustrating an example of a sequence of processing in which the first storage control unit transmits data to the second storage control unit.
  • FIG. 5B is a diagram illustrating an example of a sequence of processing in which the first storage control unit acquires data from the second storage control unit.
  • FIG. 6A is a diagram illustrating an example of a sequence of processing in which the storage control unit transmits data to the storage device.
  • FIG. 6B is a diagram illustrating an example of a sequence of processing in which the storage control unit acquires data from the storage device.
  • FIG. 7A is a diagram illustrating an example of a sequence of processing in which the storage device transmits data to the storage control unit.
  • FIG. 7B is a diagram illustrating an example of a sequence of processing in which the storage device acquires data from the storage control unit.
  • FIG. 8A is a frame format example of a data transfer instruction that can be used in the storage system.
  • FIG. 8B is a flowchart illustrating an example of a processing procedure when the back-end switch receives a data transfer instruction from the storage control unit.
  • FIG. 9A is a diagram illustrating another example of a processing sequence in which the first storage control unit transmits data to the second storage control unit.
  • FIG. 9B is a diagram illustrating another example of a sequence of processing in which the first storage control unit acquires data from the second storage control unit.
  • FIG. 10 is a diagram illustrating another example of a flowchart illustrating a processing procedure when the back-end switch receives data transmission or a data request from the processor.
  • FIG. 11 is a diagram illustrating another example of a processing sequence in which the first storage control unit transmits data to the second storage control unit.
  • FIG. 12 is a diagram illustrating another example of a flowchart illustrating a processing procedure when the back-end switch receives a data transfer instruction from the storage control unit.
  • FIG. 13A is a diagram illustrating another example of a processing sequence in which the first storage control unit transmits data to the second storage control unit.
  • FIG. 13B is a diagram illustrating another example of a processing sequence in which the first storage control unit acquires data from the second storage control unit.
  • FIG. 14 is a diagram illustrating another example of a flowchart illustrating a processing procedure when the back-end switch receives a data transfer instruction from the storage control unit.
  • FIG. 15 is a diagram showing still another example of a flowchart showing a processing procedure when the back-end switch receives a data transfer instruction from the storage control unit.
  • FIG. 16 is a diagram illustrating another example of a processing sequence in which the first storage control unit transmits data to the second storage control unit.
  • FIG. 17 is a configuration example for connecting a storage system and another storage system.
  • FIG. 18 shows another configuration example for connecting a storage system and another storage system.
  • FIG. 19 is a diagram illustrating an example of a flowchart illustrating a processing procedure when one storage control unit of a storage system receives a request from a higher-level device.
  • FIG. 20 is a diagram illustrating an example of a processing sequence when the storage control unit receives a data write request from a higher-level device.
  • FIG. 21 is a diagram illustrating another example of a flowchart illustrating a processing procedure when one storage control unit of a storage system receives a request from a higher-level device.
  • FIG. 22 is a diagram illustrating another example of a processing sequence when the storage control unit receives a data write request from a higher-level device.
  • FIG. 23 is a diagram illustrating another example of a flowchart illustrating a processing procedure when one storage control unit of a storage system receives a request from a higher-level device.
  • FIG. 24 is a diagram illustrating another example of a processing sequence when the storage control unit receives a data write request from a higher-level device.
  • FIG. 25 is a diagram illustrating another example of a flowchart illustrating a processing procedure when one storage control unit of a storage system receives a request from a higher-level device.
  • FIG. 26 is a diagram illustrating another example of a processing sequence when the storage control unit receives a data write request from a higher-level device.
  • FIG. 27 is a diagram illustrating another example of a flowchart illustrating a processing procedure when the back-end switch receives data transmission or a data request from the processor.
  • FIG. 28 is a diagram illustrating another example of a flowchart illustrating a processing procedure when the back-end switch receives data transmission or a data request from the processor.
  • FIG. 29 is a diagram illustrating another example of a processing sequence in which the first storage control unit transmits data to the second storage control unit.
  • FIG. 1 is a configuration example of a storage system according to the first embodiment.
  • the storage system includes two storage control units 103A and 103B.
  • the storage control unit 103A includes a processor 101A and a memory 102A
  • the storage control unit 103B includes a processor 101B and a memory 102B.
  • Processors 101A and 101B are connected to backend switch 104 by paths 106A and 106B, respectively.
  • the storage system according to the first embodiment includes storage devices 105A to 105F, and the storage devices 105A to 105F are connected to the back-end switch 104 through paths 107A to 107F, respectively.
  • FIG. 1 shows six storage devices 105A to 105F, but the number of storage devices is arbitrary.
  • Some or all of the functions of the back-end switch 104 may be realized by hardware, for example, by designing with an integrated circuit, or software by interpreting and executing a program that realizes each function by the processor. It may be realized with.
  • FIG. 3A shows an example of data request, data return, and data transmission frames communicated between the storage control units. Each frame may be sent as one unit or may be sent divided into packets.
  • FIG. 3B shows an example of a frame format, and other formats, for example, a packet format used in PCI Express may be used.
  • the data request frame 331 indicates a number indicating a data request (“0” in the example of FIG. 3A) in the head field.
  • the next field indicates a tag number (t) that distinguishes a plurality of data request frames. In general, the tag number allows the next data request to be sent before data is returned for one data request.
  • the next field indicates the data length.
  • the data length is represented by, for example, a byte unit or the number of data blocks of a predetermined size.
  • the next field indicates the requested address.
  • the request destination address indicates an address of an address space used by the processor in the request destination storage control unit.
  • the request destination address is converted by the back-end switch 104 from an address in the address space used by the processor in the request source storage control unit to an address used by the processor in the request destination storage control unit.
  • the data return frame 332 indicates a number indicating data return (“1” in the example of FIG. 3A) in the first field.
  • the next field indicates the tag number attached to the frame of the data request and identifies which data request is to be returned.
  • the next field indicates the data length.
  • the last field stores the data to be returned.
  • the data transmission frame 333 indicates a number indicating data transmission (“2” in the example of FIG. 3B) in the head field.
  • the next field indicates the data length.
  • the next field indicates the destination address.
  • the destination address indicates an address of an address space used by the processor in the destination storage control unit.
  • the destination address is converted by the back-end switch 104 from an address in the address space used by the processor in the source storage control unit to an address used by the processor in the destination storage control unit.
  • the last field stores the data to be sent.
  • FIG. 3B shows an example of the switching information table 350 for determining the switching operation for the address given to the frame sent from the processor 101A in the back-end switch 104.
  • the address is expressed in hexadecimal.
  • addresses 0000 to 00ff are addresses assigned to the memory 102A by the processor 101A.
  • a frame having an address in this address area is not sent from the processor 101A to the back-end switch 104.
  • the processor 101A directly accesses the memory 102A.
  • a frame to which an address after address 0100 is assigned arrives at the back-end switch 104 from the processor 101A.
  • the destination of the address 0180 is the processor 101B (memory 102B), and is sent to the path 106B.
  • the back-end switch 104 converts the destination address of the frame to the processor 101B (memory 102B).
  • the address 0180 of the processor 101A is converted to the address 0080 of the processor 101B.
  • the destination is determined to be the storage device 105C, and the frame is sent toward the path 107c connected to the storage device 105c. As will be described later, the frame to the storage device is not subjected to address translation by the back-end switch 104.
  • the switching of the frame received from the processor 101B also refers to the switching information table having the same configuration.
  • a frame whose destination is the processor 101A (memory 102A) is subjected to the address conversion, and a frame to the storage device is not subjected to the address conversion.
  • the back-end switch 104 receives a data transfer instruction from the processor 101A or 101B and performs address conversion, a switching information table holding address conversion information and destination information having the same configuration is used.
  • FIG. 3C is an example of a flowchart illustrating a processing procedure when the back-end switch 104 receives data transmission or a data request from the processor 101A.
  • the processing procedure when the back-end switch 104 receives data transmission or data request from the processor 101B is the same. In that case, the processor 101A and the processor 101B in FIG. 3C are interchanged.
  • step 300 the back-end switch 104 receives data transmission or data request from the processor 101A.
  • step 301 the back-end switch 104 refers to the destination address or request destination address (destination address) and the switching information table 350, and determines the destination of the data transmission or data request. If the destination is the processor 101B (301: processor 101B), the back-end switch 104 proceeds to step 302. In step 302, the backend switch 104 selects a path to the processor 101B. This route corresponds to the path 106B in FIG.
  • step 303 the back-end switch 104 converts the destination address of the received data transmission or data request with reference to the switching information table 350.
  • the address before conversion is an address in the address space used by the processor 101A
  • the address after conversion is an address in the address space used by the processor 101B.
  • the processor 101A and the processor 101B are independent from each other, and the address space used by each processor and the address specifying the location in the memory are determined independently. For this reason, it is possible to transfer data between processors (memory) by converting each other's address according to a predetermined rule defined by the switching information table 350.
  • step 304 the back-end switch 104 sends the data or data request to the processor 101B and ends.
  • step 301 if the destination is any of the storage devices 105A to 105F (301: storage devices 105A to 105F), the back-end switch 104 proceeds to step 305.
  • step 305 the back-end switch 104 selects any one of the paths 107A to 107F to the storage devices 105A to 105F.
  • step 306 the back-end switch 104 sends the data transmission or data request to the storage device and ends.
  • the storage devices 105A to 105F receive frames from the processor 101A or 101B and read / write specified data. Further, the storage devices 105A to 105F receive a special data pattern in which a command code for instructing a specific operation is encoded, and perform the instructed operation.
  • Storage devices 105A to F105 send frames to back-end switch 104.
  • the destinations of the frames received from the storage devices 105A to 105F are predetermined for the storage devices 105A to 105F in the back-end switch 104.
  • the destination is, for example, the processor 101A or the processor 101B.
  • the backend switch 104 performs switching so as to send the data frame received from the storage devices 105A to 105F toward the path 106A to the processor 101A or the path 106B to the processor 101B according to a predetermined setting.
  • the back-end switch 104 may perform a switching operation based on the address given to the data frame received from the storage devices 105A to 105F using the switching information table.
  • FIG. 4A shows an example of the switching information table 450.
  • the switching information table 450 defines the relationship between the address range in the address space of the storage device, the destination, and the address range in the processor address space.
  • the back end switch 104 receives a data frame to which, for example, an address 0440 is given from the storage device.
  • the back-end switch 104 performs switching so as to send the data frame toward the path 106A.
  • the backend switch 104 converts the address 0440 into an address 0040 that the processor 101A uses to access the memory 102A. As a result, the processor 101A can correctly access the memory 102A.
  • the back-end switch 104 when the back-end switch 104 receives a data frame assigned with the address 0560 from the storage device, the back-end switch 104 performs switching so as to send the data frame toward the path 106B.
  • the back-end switch 104 converts the address 0560 into the address 0060.
  • FIG. 4B is an example of a flowchart showing a processing procedure when the back-end switch 104 receives data transmission or data request from the storage devices 105A to 105F.
  • the backend switch receives a data transmission or data request from one of the storage devices 105A-105F.
  • step 401 the back-end switch 104 determines the destination of the data transmission or data request. The determination method is as described above. If the destination is the processor 101A (401: processor 101A), the back-end switch proceeds to step 402. In step 402, the backend switch 104 selects a path to the processor 101A. This route corresponds to the path 106A in FIG.
  • step 403 sends the data transmission or data request to the processor 101A using the selected route, and ends the processing.
  • step 401 if the destination is the processor 101B (401: processor 101B), the back-end switch 104 proceeds to step 404.
  • step 404 the backend switch 104 selects a path to the processor 101B. This route corresponds to the path 106B in FIG.
  • step 403 sends the data transmission or data request to the processor 101B using the selected route, and ends the processing.
  • 5A and 5B respectively show a sequence example of processing in which the storage control unit 103A transmits data to the storage control unit 103B, and a sequence example of processing in which the storage control unit 103A acquires data from the storage control unit 103B.
  • the sequence of processing in which the storage control unit 103B transmits data to the storage control unit 103A or acquires data from the storage control unit 103A is the same. 5A and 5B, the storage control unit 103A and the storage control unit 103B are replaced, the processor 101A and the processor 101B are replaced, and the memory 102A and the memory 102B are replaced.
  • step 501 the processor 101A acquires data from the memory 102A.
  • step 502 the processor 101A assigns an address A that identifies the location on the memory 102B to the acquired data, and sends the acquired data to the back-end switch 104.
  • the address A identifies a specific location on the memory 102B in the address space of the processor 101A.
  • steps 501 and 502 may be executed by software operating on the processor 101A, and all or part of them is performed by functional hardware (circuits) installed in the processor 101 that operates according to software instructions. May be executed.
  • the software specifies an address for identifying the location of data on the memory 102A, an address A for identifying a location on the memory 102B, and the length of data to be sent.
  • the functional hardware reads data having a specified length from the address on the specified memory 102A, generates a frame including the data and the specified destination address, and sends the frame to the back-end switch 104.
  • the back-end switch 104 refers to the switching information table 350, converts the address A into an address B used by the processor 101B to identify a location on the memory 102B, and sends the address B to the processor 101B.
  • the reason for converting address A to address B is as described in step 303 of FIG. 3C.
  • the processor 101B receives the frame to which the address B is assigned from the back-end switch 104.
  • the processor 101B stores data in the memory 102B according to the address B.
  • Step 504 may be performed by software running on processor 101B.
  • Functional hardware circuit that automatically stores data in the memory 102B according to the address B when the data to which the address B is assigned is received from the back-end switch 104 may be installed in the processor 101B.
  • processor 101A assigns address C for identifying a location on memory 102B in the address space of processor 101A, and sends a data request to backend switch 104.
  • Step 511 may be executed by software operating on the processor 101A, or may be executed by functional hardware (circuit) installed in the processor 101A.
  • the software operating on the processor 101A specifies the address C for identifying the location on the memory 102B, the location on the memory 102A for storing the acquired data, and the length of the acquired data.
  • the functional hardware generates and sends a data request that includes the specified information.
  • the back end switch 104 receives the data request to which the address C is given from the processor 101A.
  • the backend switch 104 converts the address C to an address D that the processor 101B uses to identify a location on the memory 102B and sends a data request to the processor 101B.
  • the reason for converting the address C to the address D is as described in step 303 of FIG. 3C.
  • the processor 101B receives the data request to which the address D is assigned from the back-end switch 104. In step 513, the processor 101B acquires data from the memory 102B according to the address D. In step 514, the processor 101B returns the data acquired from the memory 102B to the back-end switch 104.
  • Steps 513 and 514 may be executed by software operating on the processor 101B, or may be executed by functional hardware (circuit) mounted on the processor 101B.
  • the functional hardware When receiving the data request to which the address D is assigned from the back-end switch 104, the functional hardware automatically acquires data from the memory 102B according to the address D and returns it to the back-end switch 104, for example.
  • the back end switch 104 receives the data returned from the processor 101B in response to the data request sent in step 512. In step 515, the back-end switch 104 returns the returned data to the processor 101A.
  • the processor 101A receives a data return in response to the data request sent in step 511 from the back-end switch 104.
  • the processor 101A stores the returned data in the memory 102A.
  • Step 516 may be executed by software operating on the processor 101A, or may be executed by functional hardware (circuit) implemented in the processor 101A. For example, when the functional hardware receives a data return from the back-end switch 104, it automatically stores it in the memory 102A.
  • FIG. 6A shows an example of a processing sequence in which the storage control unit 103A transmits data to the storage devices 105A to 105F.
  • the storage control unit 103B can be applied to the following description. In this case, the storage control unit 103A, the processor 101A, and the memory 102A are replaced with the storage control unit 103B, the processor 101B, and the memory 102B, respectively. This is the same for the description of FIG. 6B.
  • step 601 the processor 101A acquires data from the memory 102A.
  • step 602 the processor 101A assigns designation to which of the storage devices 105A to 105F the acquired data is to be sent, and sends it to the back-end switch 104.
  • Steps 601 and 602 may be executed by software operating on the processor 101A, and all or part of them may be executed by functional hardware (circuit) mounted on the processor 101A.
  • the software designates the data acquisition location on the memory 102A, the destination storage device, and the data length to send, and the functional hardware operates according to the designated information.
  • the backend switch 104 receives data sent from the processor 101A to the storage device. In step 603, the back-end switch 104 sends the data to one of the storage devices 105A to 105F in accordance with the designation of the destination storage device given to the received data.
  • FIG. 6B is an example of a processing sequence in which the storage control unit 103A acquires data from the storage devices 105A to 105F.
  • the processor 101A gives designation of which of the storage devices 105A to 105F obtains data and sends a data request to the back-end switch 104.
  • Step 611 may be executed by software operating on the processor 101A, or may be executed by functional hardware (circuit) installed in the processor 101A.
  • the software designates from which storage device the data is acquired, the location on the memory 102A where the acquired data is stored, and the data length to be acquired.
  • the functional hardware operates according to the specified information.
  • the back-end switch 104 receives a data request to which designation of which storage device from which data is acquired is given from the processor 101A. In step 612, the backend switch 104 sends the data request to the designated storage device.
  • the storage device When the storage device receives the data request from the backend switch 104, the storage device returns the requested data to the backend switch 104 in step 613.
  • the data is returned from the storage device to the back-end switch 104.
  • the back-end switch 104 further returns the data returned to the processor 101A that is the data request sending source.
  • Step 615 the processor 101A stores the returned data in the memory 102A.
  • Step 615 may be executed by software operating on the processor 101A, or may be executed by functional hardware (circuit) implemented in the processor 101A.
  • the functional hardware receives a data return from the back-end switch 104, it automatically stores it in the memory 102A.
  • FIG. 7A shows an example of a processing sequence in which one of the storage devices 105A to 105F sends data to the memory 102A.
  • the following description can also be applied to the memory 102B.
  • the processor 101A and the memory 102A are replaced with the processor 101B and the memory 102B, respectively. This point is similar to the description of FIG. 7B.
  • one of the storage devices 105A to 105F designates a location on the memory 102A and sends the data to the back-end switch 104 in step 701.
  • the data transmission frame 333 shown in FIG. 3A is used.
  • the back-end switch 104 When the back-end switch 104 receives data from one of the storage devices 105A to 105F, in step 702, according to whether the specified memory is the memory 102A or the memory 102B, the back-end switch 104 specifies the location on the memory 102A or 102B. At the same time, it is sent to the processor 101A or 101B. In this example, the designated memory is 102A.
  • the back-end switch 104 may make a determination based on the address given to the data frame received from the storage devices 105A to 105F using the switching information table 450 shown in FIG. 4A. In this case, as described with reference to FIG. 4A, the back-end switch 104 uses the information in the switching information table 450 to specify the destination address included in the data transmission frame received from the storage devices 105A to 105F. Convert to the address space to be used.
  • Step 703 When the processor 101A receives data from the back-end switch 104, in step 703, the processor 101A stores the received data in a designated location on the memory 102A.
  • Step 703 may be executed by software operating on the processor 101A, may perform processing, or automatically receives data from the back-end switch 104 in the processor 101A or 101B and automatically stores it in the memory 102A or 102B. You may provide the function of the hardware to store.
  • FIG. 7B is an example of a processing sequence in which one of the storage devices 105A to 105F acquires data from the memory 102A.
  • one of the storage devices 105A to 105F specifies a location on the memory 102A from which data is acquired, and sends a data request to the back-end switch 104.
  • the data request frame 331 shown in FIG. 3A is used.
  • step 712 the back-end switch 104 sends the received data request to the processor 101A or 101B together with the designation of the location on the memory 102A or 102B according to whether the designated memory is the memory 102A or the memory 102B.
  • the memory 102A is designated.
  • the back-end switch 104 may make a determination based on the address given to the data frame received from the storage devices 105A to 105F using the switching information table 450 shown in FIG. 4A. In this case, as described with reference to FIG. 4A, the back-end switch 104 uses the information in the switching information table 450 to specify the destination address included in the data transmission frame received from the storage devices 105A to 105F. Convert to the address space to be used.
  • the processor 101A When the processor 101A receives the data request from the back-end switch 104, in step 713, the processor 101A acquires the data from the designated location on the memory 102A. Further, in step 714, the processor 101A returns the data acquired from the memory 102A to the back-end switch 104.
  • Steps 713 and 714 may be executed by software operating on the processor 101A, or may be executed by functional hardware (circuit) mounted on the processor 101A.
  • the functional hardware when receiving a data request from the back-end switch 104, the functional hardware automatically obtains data from the memory 102A according to the designated location on the memory 102A and returns it to the back-end switch 104.
  • the back-end switch 104 When the data is sent back from the processor 101A in response to the data request sent in step 712, the back-end switch 104 further sends the data in step 715 to the storage device 105A-105 that sent the data request in step 711. Return to one of 105F.
  • compatible communication standards are applied to communication between storage control units and communication between storage control units and storage devices.
  • the storage control units 103 ⁇ / b> A and 103 ⁇ / b> B can communicate with each other using the back-end switch 104.
  • the storage control units 103A and 103B can duplicate the data via the back-end switch 104. Since sufficient reliability and availability can be ensured even if writing to the storage devices 105A to 105F is not completed, it is possible to notify the host device of the completion of writing before writing to the storage devices 105A to 105F. Further, the back-end switch 104 does not require a shared storage area.
  • FIG. 2 is a configuration example of the storage system according to the second embodiment.
  • the storage system includes two storage control units 203A and 203B.
  • the storage control unit 203A includes a processor 201A and a memory 202A.
  • the storage control unit 203B includes a processor 201B and a memory 202B.
  • the storage system according to the second embodiment includes two mutually independent back-end switches 204A and 204B.
  • the processor 201A is connected to the back-end switches 204A and 204B by paths 206A and 208A, respectively.
  • Processor 201B is connected to backend switches 204A and 204B by paths 206B and 208B, respectively.
  • the storage system according to the second embodiment includes storage devices 205A to 205F.
  • the storage devices 205A to 205F are connected to the back end switch 204A by paths 207A to 207F, respectively.
  • the storage devices 205A to 205F are connected to the back end switch 204B by paths 209A to 209F, respectively.
  • the processors 201A and 201B are connected to all the storage devices 205A to 205F and the other processors 201B and 201A even if only one of the back-end switches 204A and 204B is used.
  • FIG. 2 shows six storage devices 205A to 205F, but the number of storage devices is arbitrary.
  • 3A to 7B in the first embodiment can be applied to the storage system according to the second embodiment.
  • the storage controllers 103A and 103B, the processors 101A and 101B, and the memories 102A and 102B are replaced with storage controllers 203A and 203B, processors 201A and 201B, and memories 202A and 202B, respectively.
  • the back-end switch 104 is replaced with the back-end switch 204A or 204B, and the storage devices 105A to 105F are replaced with the storage devices 205A to 205F.
  • the storage controllers 203A and 203B can communicate with each other using the back-end switch 204A or 204B. For example, when data for writing to the storage devices 205A to 205F is received from a host device not shown in FIG. 2, the storage control units 203A and 203B can duplicate the data via the back-end switch 204A or 204B.
  • Example 3 will be described with reference to FIGS. 1, 4A, 4B, 6A to 9B, and 27.
  • FIG. in the third embodiment the description of FIGS. 1, 4A, 4B, and 6A to 7B is the same as that of the first embodiment.
  • FIG. 27 is an example of a flowchart showing a processing procedure when the back-end switch 104 receives data transmission or a data request from the processor 101A.
  • the processing procedure when the back-end switch 104 receives data transmission or data request from the processor 101B is the same. In that case, the processor 101A in FIG. 27 is replaced with the processor 101B.
  • step 2700 the back end switch 104 receives data or a data request from the processor 101A.
  • step 2701 the back-end switch 104 selects one of the paths 107A to 107F to the storage devices 105A to 105F.
  • step 2702 the back-end switch 104 sends the data transmission or data request to the storage device, and ends the process.
  • FIG. 8A is a frame format example of a data transfer instruction that can be used in the storage system according to the third embodiment.
  • a data transfer instruction 851 in the first format is a data transfer instruction from the processor 101A to the back-end switch 104.
  • the data transfer instruction 851 specifies the data transfer direction.
  • the first field specifies the transfer direction.
  • the transfer direction is represented by 0 or 1, for example. For example, 0 indicates that data is transferred from the processor 101A to the processor 101B. 1 indicates that data is transferred from the processor 101B to the processor 101A.
  • the next field indicates the data length to be transferred.
  • the next field indicates an address on the memory 102A in the address space of the processor 101A.
  • the last field indicates an address on the memory 102B of the processor 101B set in the address space of the processor 101A.
  • the data transfer instruction 851 needs to include information for specifying the data transfer direction. For example, the address conversion is always performed on the memory 102 of the processor 101B set by the last processor 101A. An address conversion function can be easily provided in the end switch 104.
  • the data transfer instruction 852 of the second format indicates the transfer direction by designating the transfer source address and the transfer destination address.
  • the transfer direction field is not required.
  • the first field indicates the data length.
  • the next field indicates the transfer source address.
  • the last field indicates the transfer destination address.
  • FIG. 8B is an example of a flowchart showing a processing procedure when the back-end switch 104 receives a data transfer instruction from the processor 101A.
  • the processing procedure when the back-end switch 104 receives a data transfer instruction from the processor 101B is the same. In that case, in the following description, the processor 101A and the processor 101B are interchanged, and the memory 102A and the memory 102B are interchanged.
  • back-end switch 104 receives a data transfer instruction from processor 101A in step 800.
  • the back-end switch 104 determines the transfer direction of the received data transfer instruction. If the transfer direction is transfer from the memory 102A to the memory 102B (801: transfer from the memory 102A to the memory 102B), the process proceeds to step 802.
  • step 802 the back-end switch 104 acquires data to be transferred from the memory 102A.
  • step 803 the back-end switch 104 converts the transfer destination address designated by the processor 101A in the data transfer instruction into an address used by the processor 101B.
  • the switching information table 350 is referred to.
  • the processor 101A and the processor 101B are processors independent from each other, and addresses specifying the memory locations used by the processors 101A and 101B are determined independently. For this reason, this embodiment also converts each other's address according to a predetermined rule.
  • step 804 the back-end switch 104 writes the data acquired from the memory 102A in the memory 102B according to the converted address, and ends the process.
  • step 801 if the transfer direction is transfer from the memory 102B to the memory 102A (801: transfer from the memory 102B to the memory 102A), the process proceeds to step 805.
  • step 805 as in step 803, the back-end switch 104 converts the transfer source address designated by the processor 101A into an address used by the processor 101B.
  • step 806 the back-end switch 104 acquires data from the memory 102B according to the converted address.
  • step 807 the back-end switch 104 writes the data acquired from the memory 102B to the memory 102A, and ends the process.
  • FIG. 9A is an example of a sequence of processing in which the storage control unit 103A sends data to the storage control unit 103B according to the processing procedure shown in the flowchart of FIG. 8B.
  • FIG. 9B is an example of a processing sequence in which the storage control unit 103A acquires data from the storage control unit 103B.
  • the processing sequence in which the storage control unit 103B sends data to the storage control unit 103A or acquires data from the storage control unit 103A is the same.
  • the storage control unit 103A, the processor 101A, and the memory 102A are replaced with the storage control unit 103B, the processor 101B, and the memory 102B, respectively.
  • processor 101A transfers data including an address A for identifying a location on transfer destination memory 102B, an address for identifying a location on transfer source memory 102A, and the length of data to be transferred.
  • An instruction is sent to the backend switch 104.
  • the two specified addresses are addresses in the address space of the processor 101A.
  • step 902 the back-end switch 104 sends a request for acquiring transfer source data from the designated data transfer source address in the memory 102A to the processor 101A.
  • step 903 the processor 101A acquires data from the requested address on the memory 102A.
  • step 904 the processor 101A returns the data acquired from the memory 102A to the back-end switch 104.
  • Steps 903 and 904 may be executed by software operating on the processor 101A, or may be executed by functional hardware (circuit) implemented in the processor 101A.
  • the functional hardware automatically acquires data from the memory 102A according to the designated address and returns it to the back-end switch 104.
  • the back end switch 104 receives the data of the transfer source from the processor 101A.
  • the back-end switch 104 uses the address A in the data transfer instruction sent from the processor 101A to identify the location on the memory 102B to which the processor 101A is to transfer on the memory 102B used by the processor 101B. Convert to address B.
  • the switching information table 350 is referred to.
  • the back-end switch 104 gives an address B and sends the data returned from the processor 101A to the processor 101B.
  • the reason for converting address A to address B is as described in step 803 of FIG. 8B.
  • the processor 101B receives data to which the address B is assigned from the back-end switch 104.
  • the processor 101B stores the data sent to the memory 102B according to the address B.
  • Step 906 may be executed by software operating on the processor 101B, or may be executed by functional hardware (circuit) implemented in the processor 101B.
  • the functional hardware When the functional hardware receives the data with the address B from the back-end switch 104, the functional hardware automatically stores the data in the memory 102B according to the address B.
  • processor 101A sends a data transfer instruction to back-end switch 104.
  • the data transfer instruction includes an address C for identifying the location on the transfer source memory 102B by the processor 101A, an address for identifying the location on the transfer destination memory 102A, and the data length to be transferred.
  • the back-end switch 104 converts the address C included in the data transfer instruction sent by the processor 101A into an address D used by the processor 101B to identify a location on the memory 102B.
  • the switching information table 350 is referred to.
  • the back-end switch 104 gives an address D and sends a data acquisition request to the processor 101B.
  • the reason for converting the address C to the address D is as described in step 803 of FIG. 8B.
  • the processor 101B receives the data request to which the address D is assigned from the backend switch 104. In step 913, the processor 101B acquires data from the memory 102B according to the address D. Next, in step 914, the processor 101B returns the data acquired from the memory 102B to the back-end switch 104.
  • Steps 913 and 914 may be executed by software operating on the processor 101B, or may be executed by functional hardware (circuit) mounted on the processor 101B.
  • the functional hardware When receiving the data request to which the address D is assigned from the back-end switch 104, the functional hardware automatically acquires the data from the memory 102B according to the address D and returns it to the back-end switch 104.
  • the back end switch 104 receives the data acquired from the memory 102B from the processor 101B in response to the data request sent to the processor 101B in step 912. In step 915, the back-end switch 104 assigns the received data to the processor 101A with an address on the transfer destination memory 102A indicated in the transfer instruction.
  • Step 916 may be executed by software operating on the processor 101A, or may be executed by functional hardware (circuit) implemented in the processor 101A.
  • the functional hardware automatically stores the data in the memory 102A according to the assigned address.
  • the storage control units 103A and 103B can communicate with each other using the back-end switch 104.
  • the storage control units 103A and 103B can duplicate the data via the back-end switch 104.
  • the back-end switch 104 does not require a shared storage area. Further, in this embodiment, the processing hardware of the processor can be reduced by the functional hardware of the back-end switch and the processor executing data transfer between the transfer source address and the transfer destination address.
  • the storage system configuration shown in FIG. 2 may be adopted.
  • the storage control unit 103A is replaced with the storage control unit 203A
  • the storage control unit 103B is replaced with the storage control unit 203B.
  • the processor 101A is replaced with the processor 201A
  • the processor 101B is replaced with the processor 201B
  • the memory 102A is replaced with the memory 202A
  • the memory 102B is replaced with the memory 202B.
  • the back-end switch 104 is replaced with the back-end switch 204A or 204B
  • the storage devices 105A to 105F are replaced with the storage devices 205A to 205F.
  • Embodiment 4 will be described with reference to FIG. 1 or FIG. 2 and FIGS. 4A, 4B, 6A to 7B, FIG. 10, and FIG.
  • the description of FIGS. 1, 4A, 4B, and 6A to 7B is the same as that of the first embodiment.
  • FIG. 10 is an example of a flowchart showing a processing procedure when the back-end switch 104 receives data transmission or data request from the processor 101A in this embodiment.
  • the processing procedure when the back-end switch 104 receives data transmission or data request from the processor 101B is the same. In that case, the processor 101A and the processor 101B are interchanged in FIG.
  • step 300 to step 306 in FIG. 3C in the first embodiment can be applied to the processing from step 1000 to step 1006.
  • step 1007 the back-end switch 104 determines whether the frame sent from the processor 101A is sending data for storage in the memory 102B or a request for obtaining data in the memory 102B. If the determined result is data transmission for storage in the memory 102B (1007: data transmission), the back-end switch 104 proceeds to step 1008.
  • the back-end switch 104 notifies the processor 101B that data has been sent for storage in the memory 102B.
  • the notification to the processor 101B is performed by, for example, sending a predetermined specific signal from the back-end switch 104 to the processor 101B.
  • the notification is performed by sending predetermined specific data to a specific address of the processor 101B.
  • an interrupt signal may be sent from the back-end switch 104 to the processor 101B.
  • step 1007 if the determined result is a request for acquisition of data in the memory 102B (1007: data request), the back-end switch 104 ends the process.
  • FIG. 11 is an example of a processing sequence for transmitting data from the storage control unit 103A to the storage control unit 103B when the back-end switch 104 performs processing according to the processing procedure shown in FIG.
  • the processing sequence in which the storage control unit 103B transmits data to the storage control unit 103A is the same.
  • the storage control unit 103A and the storage control unit 103B are interchanged, the processor 101A and the processor 101B are interchanged, and the memory 102A and the memory 102B are interchanged.
  • step 1105 the back-end switch 104 notifies the processor 101B that data has been sent.
  • This notification method is the same as that described in step 1008 of FIG.
  • the present embodiment notifies the data transmission from the back-end switch to the processor.
  • the processor 101B can know that data has been sent from the processor 101A without periodically checking the contents of the memory 102B. Since it is not necessary to periodically inspect the contents of the memory 102B, performance overhead can be reduced and the efficiency of the processor 101B can be improved.
  • the configuration shown in FIG. 2 can be adopted instead of the configuration shown in FIG.
  • the description regarding FIGS. 2, 4A, 4B, and 6A to 7B is the same as that of the second embodiment. 10 and 11, the storage control unit 103A is replaced with a storage control unit 203A, and the storage control unit 103B is replaced with a storage control unit 203B.
  • the processor 101A is replaced with the processor 201A
  • the processor 101B is replaced with the processor 201B
  • the memory 102A is replaced with the memory 202A
  • the memory 102B is replaced with the memory 202B.
  • the back-end switch 104 is replaced with the back-end switch 204A or 204B
  • the storage devices 105A to 105F are replaced with the storage devices 205A to 205F.
  • Example 5 will be described with reference to FIG. 1 or 2, FIG. 4A, FIG. 4B, FIG. 6A to FIG. 7B, FIG. 12, FIG. 13A, FIG.
  • the description of FIGS. 1, 2, 4A, 4B, 6A to 7B, and 27 is the same as that of the third embodiment.
  • FIG. 12 is an example of a flowchart illustrating a processing procedure when the back-end switch 104 receives a data transfer instruction from the processor 101A.
  • the processing procedure when the back-end switch 104 receives data or a data request from the processor 101B is the same. In that case, in FIG. 12, the processor 101A and the processor 101B are interchanged, and the memory 102A and the memory 102B are interchanged.
  • Step 800 to Step 807 in FIG. 8B of Embodiment 3 can be applied to Step 1200 to Step 1207.
  • step 1208 the back-end switch 104 notifies the processor 101B that the data has been written to the memory 102B.
  • the notification to the processor 101B is performed by, for example, sending a predetermined specific signal from the back-end switch 104 to the processor 101B.
  • the notification is performed by sending predetermined specific data to a specific address of the processor 101B.
  • an interrupt signal may be sent from the back-end switch 104 to the processor 101B.
  • the back end switch 104 proceeds to step 1209 after step 1207.
  • the back-end switch 104 notifies the processor 101A that the data acquired from the memory 102B has been written to the memory 102A.
  • the notification to the processor 101A is performed, for example, by sending a predetermined signal from the back-end switch 104 to the processor 101A.
  • the notification is performed by sending predetermined specific data to a specific address of the processor 101A.
  • an interrupt signal may be sent from the back-end switch 104 to the processor 101A.
  • FIG. 13A is an example of a processing sequence in which the storage control unit 103A transmits data to the storage control unit 103B when the back-end switch 104 performs processing according to the processing procedure shown in FIG.
  • FIG. 13B is an example of a processing sequence in which the storage control unit 103A acquires data from the storage control unit 103B.
  • the processing sequence in which the storage control unit 103B transmits data to the storage control unit 103A or acquires data of the storage control unit 103A is the same.
  • the storage control unit 103A and the storage control unit 103B are interchanged, the processor 101A and the processor 101B are interchanged, and the memory 102A and the memory 102B are interchanged.
  • step 1305 the back-end switch 104 notifies the processor 101B that the data has been sent in step 1307. This notification method is as described in step 1208 of FIG.
  • step 911 to step 916 in FIG. 9B of the third embodiment can be applied to step 1311 to step 1316.
  • the back-end switch 104 after step 1315, notifies the processor 101A that the data has been sent in step 1317. This notification method is as described in step 1209 of FIG.
  • this embodiment notifies the processor of data transmission from the back-end switch.
  • the configuration shown in FIG. 2 can be adopted instead of the configuration shown in FIG.
  • the processor 101A is replaced with the processor 201A
  • the processor 101B is replaced with the processor 201B
  • the memory 102A is replaced with the memory 202A
  • the memory 102B is replaced with the memory 202B.
  • the back-end switch 104 is replaced with the back-end switch 204A or 204B
  • the storage devices 105A to 105F are replaced with the storage devices 205A to 205F.
  • Example 6 will be described with reference to FIG. 1 or FIG. 2, FIG. 4A, FIG. 4B, FIG. 6A to FIG. 7B, FIG. In this embodiment, the description of FIGS. 1, 2, 4A, 4B, 6A to 7B, and 27 is the same as that of the third embodiment.
  • FIG. 14 will be described in the case where the configuration shown in FIG.
  • FIG. 14 is an example of a flowchart showing a processing procedure when the back-end switch 104 receives a data transfer instruction from the processor 101A.
  • the processing procedure when the back-end switch 104 receives a data transfer instruction from the processor 101B is the same. In that case, the processor 101A and the processor 101B are interchanged in FIG. 14, and the memory 102A and the memory 102B are interchanged.
  • step 800 to step 807 in FIG. 8B of the third embodiment can be applied to step 1400 to step 1407.
  • the data transfer instruction received from the processor 101A in step 1400 includes a data check code that can check whether there is an error in the data to be transferred.
  • the data check code may be a standard data check code called T10DIF, for example.
  • a data protection code that can be collated with the data check code may be attached to the data to be checked, or may be supplied to the back-end switch 104 separately from the check target.
  • step 1408 the process proceeds to step 1408 after step 1402.
  • step 1408 the back-end switch 104 checks whether there is an error in the data acquired from the memory 102A in step 1402 based on the data check code included in the data transfer instruction received from the processor 101A.
  • step 1409 the back-end switch 104 determines whether there is an error as a result of the check. If there is no error (1409: OK), the process proceeds to step 1403. If there is an error (1409: NG), the backend switch 104 proceeds to Step 1412 without writing the data in the memory 102B. The back end switch 104 proceeds to step 1412 even after step 1404.
  • step 1410 the back-end switch 104 checks whether there is an error in the data acquired from the memory 102B in step 1406 based on the data check code included in the data transfer instruction received from the processor 101A.
  • the backend switch 104 proceeds to step 1411 and determines whether there is an error as a result of the check. If there is no error (1411: OK), the back-end switch 104 proceeds to Step 1407. If there is an error (1411: NG), the back-end switch 104 proceeds to Step 1412 without writing the data in the memory 102A. The back end switch 104 proceeds to step 1412 even after step 1403.
  • step 1412 the back-end switch 104 reports the check result checked in step 1408 or step 1410 to the processor 101A, and ends the process.
  • this embodiment can check the back-end switch 104 to determine whether there is an error in the data to be transferred. Therefore, it is possible to increase the legitimacy of the data to be transferred, and further, there is no performance overhead for data error check in the processor 101A or 101B.
  • the configuration shown in FIG. 2 can be adopted instead of the configuration shown in FIG.
  • the processor 101A is replaced with the processor 201A
  • the processor 101B is replaced with the processor 201B
  • the memory 102A is replaced with the memory 202A
  • the memory 102B is replaced with the memory 202B.
  • the back-end switch 104 is replaced with the back-end switch 204A or 204B
  • the storage devices 105A to 105F are replaced with the storage devices 205A to 205F.
  • Example 7 will be described with reference to FIG. 1 or FIG. 2, FIG. 4A, FIG. 4B, FIG. 6A to FIG. 7B, FIG.
  • the description of FIGS. 1, 2, 4A, 4B, 6A to 7B, and 27 is the same as that of the third embodiment.
  • the case where the configuration shown in FIG. 1 is adopted as the configuration of the storage system of this embodiment will be described with reference to FIGS.
  • FIG. 15 is an example of a flowchart showing a processing procedure when the back-end switch 104 receives a data transfer instruction from the processor 101A.
  • the processing procedure when the back-end switch 104 receives a data transfer instruction from the processor 101B is the same. In that case, in FIG. 15, the processor 101A and the processor 101B are interchanged, and the memory 102A and the memory 102B are interchanged.
  • step 800 to step 807 in FIG. 8 of the third embodiment can be applied to step 1500 to step 1507.
  • the back-end switch 104 proceeds to step 1508 after step 1504.
  • step 1508 the back-end switch 104 reads the data written in the memory 102B again. By this step, it can be assured that the processing for reliably writing the data in the memory 102B in step 1504 is completed.
  • the length of the data read in step 1508 may be equal to the length of the data written in step 1504, or may be the length of a part of the data written in step 1504.
  • the back end switch 104 may read the last part of the data written in step 1504.
  • step 1509 the back-end switch 104 notifies the processor 101A that the data has been read.
  • the notification may be performed, for example, by sending all or part of the data read in step 1508 to the processor 101A, or by sending a predetermined specific signal to the processor 101A.
  • the notification may be performed by sending specific predetermined data to a specific address in the address space of the processor 101A, or by sending an interrupt signal from the back-end switch 104 to the processor 101A. Also good. In this way, it is possible to notify the processor 101A that the process of writing to the memory 102B has been completed.
  • FIG. 16 is an example of a processing sequence for transmitting data from the storage control unit 103A to the storage control unit 103B when the back-end switch 104 performs processing according to the processing procedure shown in FIG.
  • the flow of processing in which the storage control unit 103B transmits data to the storage control unit 103A is the same.
  • the storage control unit 103A and the storage control unit 103B are replaced, the processor 101A and the processor 101B are replaced, and the memory 102A and the memory 102B are replaced.
  • steps 901 to 906 in FIG. 9A of the third embodiment can be applied to steps 1601 to 1606.
  • the back-end switch 104 uses the address B used in step 1605 again in step 1607 to send a request to acquire the data from the memory 102B to the processor 101B.
  • the length of the data to be acquired may be equal to the length of the data sent with the address B given in step 1605, or may be the length of a part of the data sent with the address B given in step 1605. Good. This is as described in step 1508 of FIG.
  • the back end switch 104 may change the length of the data to be acquired and the address B so as to acquire the last part of the data sent in step 1605.
  • the processor 101B When the processor 101B receives the data request to which the address B is assigned from the back-end switch 104, the processor 101B acquires data from the memory 102B according to the address B in step 1608. Next, in step 1609, the processor 101B returns the data acquired from the memory 102B to the back-end switch 104.
  • Steps 1608 and 1609 may be executed by software operating on the processor 101B, or may be executed by functional hardware (circuit) mounted on the processor 101B.
  • the functional hardware When the functional hardware receives a data request to which the address B is assigned from the back-end switch 104, the functional hardware automatically acquires data from the memory 102B according to the address B and returns it to the back-end switch 104.
  • the back-end switch 104 When the back-end switch 104 receives the data at the address B from the processor 101B, in step 1610, the back-end switch 104 notifies the processor 101A that the data has been read from the memory 102B.
  • the notification method is as described in step 1509 in FIG.
  • this embodiment can guarantee that the data can be stored in the memory 102B when the data is transferred from the storage control unit 103A to the storage control unit 103B. .
  • this embodiment can guarantee that the data can be stored in the memory 102B when the data is transferred from the storage control unit 103A to the storage control unit 103B.
  • the storage control units 103A and 103B can duplicate the data.
  • the host device is notified of the completion of the data writing. Is possible. In the present embodiment, the data duplication can be reliably ensured as compared with the third embodiment.
  • the configuration shown in FIG. 2 can be adopted instead of the configuration shown in FIG.
  • the descriptions regarding FIG. 2, FIG. 4A, FIG. 4B, FIG. 6A to FIG. 7B, and FIG. 15 and 16 the storage control unit 103A is replaced with a storage control unit 203A, and the storage control unit 103B is replaced with a storage control unit 203B.
  • the processor 101A is replaced with the processor 201A
  • the processor 101B is replaced with the processor 201B
  • the memory 102A is replaced with the memory 202A
  • the memory 102B is replaced with the memory 202B.
  • the back-end switch 104 is replaced with the back-end switch 204A or 204B
  • the storage devices 105A to 105F are replaced with the storage devices 205A to 205F.
  • FIG. 17 is a diagram illustrating an example of the configuration of a storage system according to the eighth embodiment.
  • the storage system 1700 includes two storage control units 1703A and 1703B.
  • the storage control unit 1703A includes a processor 1701A, a memory 1702A, a host IF 1710A connected to the host device 1714A, and an interconnect IF 1711A.
  • the storage control unit 1703B includes a processor 1701B, a memory 1702B, a host IF 1710B connected to the host device 1714B, and an interconnect IF 1711B.
  • Interconnect IFs 1711A and 1711B are connected to other storage systems 1713A to 1713E through interconnect switches 1712A and 1712B different from the back-end switch 1704, respectively.
  • the storage system 1700 includes storage devices 1705A to 1705F.
  • the storage devices 1705A to 1705F are connected to the back-end switch 1704 through paths 1707A to 1707F, respectively.
  • FIG. 17 shows six storage devices 1705A to 1705F, but the number of storage devices is arbitrary.
  • FIG. 17 shows five other storage systems 1713A to 1713E, but the number of other storage systems is arbitrary.
  • the other storage systems 1713A to 1713E may have the same configuration as the storage system 1700, respectively.
  • Each of the higher-level devices 1714A and 1714B may be a virtual device realized by software operating on the processors 1701A and 1701B or other processors in the storage control unit 1703A or 1703B.
  • the software exchanges requests and responses with the storage system 1700 via a software driver instead of the upper IF 1710A or 1710B.
  • FIG. 18 is a diagram showing an example of the configuration of a storage system using two back-end switches instead of FIG.
  • the storage system 1800 includes two storage control units 1803A and 1803B.
  • the storage control unit 1803A includes a processor 1801A, a memory 1802A, a host IF 1810A connected to the host device 1814A, and an interconnect IF 1811A.
  • the storage control unit 1803B includes a processor 1801B, a memory 1802B, a host IF 1810B connected to the host device 1814B, and an interconnect IF 1811B.
  • the storage system 1800 includes two mutually independent back-end switches 1804A and 1804B.
  • Processor 1801A is connected to backend switches 1804A and 1804B by path 1806A and path 1808A, respectively.
  • Processor 1801B is connected to backend switches 1804A and 1804B by path 1806B and path 1808B, respectively.
  • the storage system 1800 includes storage devices 1805A to 1805F.
  • the storage devices 1805A to 1805F are connected to the back-end switch 1804A through paths 1807A to 1807F, respectively.
  • the storage devices 1805A to 1805F are connected to the back-end switch 1804B by paths 1809A to 1809F, respectively.
  • the processors 1801A and 1801B are connected to all the storage devices 1805A to 1805F and the other processors 1801B and 1801A using only one of the back-end switches 1804A and 1804B. Even if one of the back-end switches 1804A or 1804B stops operating, or the path connected to one of the back-end switches 1804A or 1804B is disconnected, the storage system 1800 communicates with the processors 1801A and 1801B and the processor 1801A or 1801B. All communications between the storage devices 1805A-1805F can be continued. Thereby, the availability of the system can be increased.
  • Interconnect IFs 1811A and 1811B are connected to other storage systems 1813A to 1813E through interconnect switches 1812A and 1812B different from back-end switches 1804A and 1804B, respectively.
  • FIG. 18 shows six storage devices 1805A to 1805F, but the number of storage devices is arbitrary in this embodiment.
  • FIG. 18 shows five other storage systems 1813A to 1813E, but the number of other storage systems is arbitrary in this embodiment.
  • Other storage systems 1813A to 1813E may have the same configuration as the storage system 1800.
  • the host devices 1814A and 1814B may be virtual devices like the host devices 1714A and 1714B in FIG.
  • FIG. 19 is an example of a flowchart showing a processing procedure by the storage control units 1703A, 1703B, 1803A, or 1803B according to the present embodiment.
  • the storage control unit receives a data read request or a data write request from the host device.
  • the storage control unit determines whether the received request is a request for data stored in the storage device of the storage system including the storage control unit. For example, the storage control unit makes a determination with reference to information for managing the relationship between the address indicated by the request from the host device and the storage device.
  • step 1902 the storage control unit determines whether the request received from the higher-level device is data reading or writing. If the request is a write (1902: write), the storage controller proceeds to step 1903.
  • step 1903 the storage control unit receives write data from the host device.
  • step 1904 the storage control unit stores the received write data in the memory of the storage control unit.
  • step 1905 the storage control unit transfers the data stored in the memory of the storage control unit to the memory of the other storage control unit through the back-end switch in the same storage system.
  • step 1906 the storage control unit reads again the write data transferred to the memory of the other storage control unit, and confirms that it has been stored in the memory of the other storage control unit.
  • the length of the data read again in step 1906 may be equal to the length of the data transferred in step 1905 or may be the length of a part of the data transferred in step 1905.
  • the storage control unit may read the last part of the data transferred in step 1905.
  • step 1907 the storage control unit notifies the host device of the completion of writing.
  • step 1902 if the request received from the host device is data read (1902: read), the storage control unit proceeds to step 1908.
  • step 1908 the storage control unit reads the data from the storage device in the same storage system.
  • step 1909 the storage control unit proceeds to step 1909 and returns the data read from the storage device to the host device.
  • the storage control unit may store the read data in the memory of the storage control unit. In response to the next read request for the same data, the storage control unit returns the data stored in the memory without reading the data from the storage device.
  • step 1901 if the request received from the host device is not a request for data stored in the storage device of the storage system including the storage control unit (1901: NO), the storage control unit proceeds to step 1910.
  • step 1910 the storage control unit sends the read or write request received from the host device to another storage system via the interconnect IF and the interconnect switch.
  • FIG. 20 is an example of a sequence when the processing procedure in the storage control unit 1703A or 1803A is performed according to the flowchart shown in FIG. FIG. 20 shows an example of processing for a data write request from the host device to the storage devices 1705A to 1705F of the storage system 1700 or the storage devices 1805A to 1805F of the storage system 1800.
  • the processing sequence when the storage control unit 1703B or 1803B receives a data write request from the higher-level device to the storage devices 1705A to 1705F of the storage system 1700 or the storage devices 1805A to 1805F of the storage system 1800 is the same. .
  • the storage control unit 1703A or 1803A and the storage control unit 1703B or 1803B are interchanged.
  • the processor 1701A or 1801A and the processor 1701B or 1801B are interchanged.
  • Memory 1702A or 1802A and memory 1702B or 1802B are interchanged.
  • step 2001 when the storage control unit 1703A or 1803A receives a data write request from a host device, in step 2001, the storage control unit 1703A or 1803A receives write data.
  • step 2002 the processor 1701A or 1801A stores the received write data in the memory 1702A or 1802A.
  • step 2003 the processor 1701A or 1801A obtains the data stored in the memory 1702A or 1802A again.
  • the processor 1701A or 1801A assigns an address A that identifies the location on the memory 1702B or 1802B to the acquired data and sends it to the back-end switch 1704, 1804A, or 1804B.
  • the data transmission frame 333 shown in FIG. 3A is used.
  • Steps 2003 and 2004 may be executed by software operating on the processor 1701A or 1801A, or may be executed by functional hardware (circuit) mounted on the processor 1701A or 1801A.
  • the functional hardware operates by designating a location for acquiring data on the memory 1702A or 1802A, an address A for identifying a location on the memory 1702B or 1802B, and a data length to be sent by software.
  • the back end switch 1704 or the back end switch 1804A or 1804B receives data transmission from the processor 1701A or 1801A.
  • the back-end switch 1704 or the back-end switch 1804A or 1804B converts the assigned address A into an address B that identifies the location on the memory 1702B or 1802B by the processor 1701B or 1801B.
  • Data transmission including the converted address B is sent to the processor 1701B or 1801B.
  • the processor 1701B or 1801B receives the data to which the address B is assigned from the back-end switch 1704, 1804A or 1804B. In step 2006, the processor 1701B or 1801B stores the received data in the memory 1702B or 1802B based on the address B.
  • Step 2006 may be executed by software operating on the processor 1701B or 1801B, or may be executed by functional hardware (circuit) mounted on the processor 1701B or 1801B.
  • the functional hardware When the functional hardware receives the data with the address B from the back-end switch, the functional hardware automatically stores the data in the memory 1702B or 1802B according to the address B.
  • step 2007, the processor 1701A or 1801A again sends a request for acquiring the data stored in the memory 1702B or 1802B using the address A to the back-end switch 1704 or back-end switch 1804A or 1804B.
  • the data request frame 331 shown in FIG. 3A is used.
  • the length of the data to be acquired may be equal to the length of the data sent with the address A given in step 2004, or the length of the part of the data sent with the address A given in step 2004. There may be. For example, the length of the data to be acquired and the address A may be changed so that the last part of the data sent in step 2004 is acquired. This point is as described in step 1906 of FIG.
  • Step 2007 may be executed by software operating on the processor 1701A or 1801A, or may be executed by functional hardware (circuit) mounted on the processor 1701A or 1801A.
  • the functional hardware operates by designating the address A for identifying the location on the memory 1702B or 1802B and the length of data to be acquired by software.
  • step 2008 the back end switch 1704 or the back end switch 1804A or 1804B converts the address A into the address B again, and sends a request to acquire data to the processor 1701B or 1801B.
  • the processor 1701B or 1801B receives a data acquisition request from the back-end switch 1704 or the back-end switch 1804A or 1804B. In step 2009, the processor 1701B or 1801B acquires data from the memory 1702B or 1802B according to the assigned address B.
  • step 2010 the processor 1701B or 1801B returns the acquired data to the back-end switch 1704 or the end switch 1804A or 1804B.
  • Steps 2009 and 2010 may be executed by software operating on the processor 1701B or 1801B, or may be executed by functional hardware (circuit) implemented in the processor 1701B or 1801B.
  • the functional hardware When the functional hardware receives the data request to which the address B is given from the back-end switch 1704 or the back-end switch 1804A or 1804B, the functional hardware automatically acquires the data from the memory 1702B or 1802B according to the address B, and the back-end switch 1704 Alternatively, the data is returned to the back-end switch 1804A or 1804B.
  • the back end switch 1704 or the back end switch 1804A or 1804B receives return data from the processor 1701B or 1801B. In step 2011, the back end switch 1704 or the back end switch 1804A or 1804B returns the data to the processor 1701A or 1801A.
  • the processor 1701A or 1801A receives the returned data from the back-end switch 1704 or the back-end switch 1804A or 1804B. In step 2012, the processor 1701A or 1801A reports the completion of data writing to the host device.
  • the storage system 1700 or 1800 can provide an effect called scale-out that adds capacity and performance to other storage systems.
  • the storage system 1800 according to the present embodiment is particularly highly available, it is not necessary to have redundant data with other storage systems when providing the effect of scale-out. Therefore, there is no performance overhead and the use efficiency of the storage capacity of each storage system does not decrease.
  • the first storage control unit includes a first interconnect unit
  • the second storage control unit includes a second interconnect unit.
  • the first and second interconnects are connected to one or more interconnect switches different from the backend switch.
  • the interconnect switch is further connected to the second storage system.
  • the first or second storage control unit receives a data read or write request from the host device, and determines whether the requested data is stored in the storage device in the received data read or write request. When it is determined that the data is not stored in the storage device, the first or second storage control unit uses the first or second interconnect unit and the interconnect switch to issue a data read or write request to the second To the storage system.
  • Example 9 will be described with reference to FIGS.
  • the configuration example of the storage system in the ninth embodiment is the configuration shown in FIGS.
  • FIG. 21 is an example of a flowchart illustrating a processing procedure in the storage control unit 1703A or 1703B of the storage system 1700 illustrated in FIG. 17 and the storage control unit 1803A or 1803B of the storage system 1800 illustrated in FIG.
  • step 2105 the storage control unit sends an instruction to transfer write data from the memory to the memory of the other storage control unit in the storage system to the back-end switch.
  • the back-end switch When receiving the instruction, the back-end switch transfers the specified write data from the memory of the storage control unit to the memory of the other storage control unit.
  • the back-end switch reads back the memory of the other storage control unit, confirms that the transfer is complete, and notifies the storage control unit of the completion of data transfer.
  • step 2106 the storage control unit receives a data transfer completion notification from the back-end switch.
  • step 2107 the storage control unit notifies the host device of the completion of writing.
  • FIG. 22 is an example of a sequence when the processing procedure in the storage control unit 1703A or 1803A is performed according to the flowchart shown in FIG. More specifically, FIG. 22 shows an example of a processing sequence when a write request is received for data stored in the storage devices 1705A to 1705F of the storage system 1700 or the storage devices 17051805A to 1805F of the storage system 1800 from the host device. It is.
  • the processing sequence when the storage control unit 1703B or 1803B receives a write request for data stored in the storage devices 1705A to 1705F of the storage system 1700 or the storage devices 1805A to 1805F of the storage system 1800 from the host device is also shown. It becomes the same.
  • the storage control unit 1703A or 1803A and the storage control unit 1703B or 1803B are interchanged.
  • the processor 1701A or 1801A and the processor 1701B or 1801B are interchanged.
  • Memory 1702A or 1802A and memory 1702B or 1802B are interchanged.
  • step 2201 when the storage control unit 1703A or 1803A receives a data write request from a host device, in step 2201, the storage control unit 1703A or 1803A receives write data.
  • step 2202 the processor 1701A or 1801A stores the received write data in the memory 1702A or 1802A.
  • steps 1601 to 1610 in FIG. 16 of the seventh embodiment can be applied to steps 2203 to 2212.
  • the storage control unit 103A or 203A is replaced with a storage control unit 1703A or 1803A.
  • the storage control unit 103B or 203B is replaced with a storage control unit 1703B or 1803B.
  • the processor 101A or 201A is replaced with the processor 1701A or 1801A.
  • the processor 101B or 201B is replaced with a processor 1701B or 1801B.
  • the memory 102A or 202A is replaced with the memory 1702A or 1802A.
  • the memory 102B or 202B is replaced with the memory 1702B or 1802B.
  • back end switch 104 or the back end switch 204A or 204B is replaced with the back end switch 1704 or the back end switch 1804A or 1804B.
  • the transfer source data is replaced with the write data received from the host device.
  • step 2212 the processor 1701 ⁇ / b> A or 1801 ⁇ / b> A receives a data storage completion notification from the back-end switch 1704 or the back-end switch 1804 ⁇ / b> A or 1804 ⁇ / b> B.
  • the processor 1701A or 1801A reports the completion of data writing to the host device.
  • Example 9 can achieve the same effects as those described in Example 8.
  • Example 10 will be described with reference to FIGS.
  • the configuration example of the storage system in the tenth embodiment is the configuration shown in FIGS.
  • FIG. 23 is an example of a flowchart showing a processing procedure in the storage control unit 1703A or 1703B of the storage system 1700 shown in FIG. 17 and the storage control unit 1803A or 1803B of the storage system 1800 shown in FIG.
  • steps 2100 to 2104, 2107, 2108 to 2110 in FIG. 21 shown in the ninth embodiment can be applied to steps 2300 to 2304, 2307, 2308 to 2310.
  • the storage control unit stores the write data received from the higher-level device in step 2304 in the memory of the storage control unit.
  • the storage control unit sends an instruction to transfer the write data from the memory to the memory of the other storage control unit in the same storage system to the back-end switch.
  • step 2306 the storage control unit receives the data error check result from the back-end switch.
  • step 2307 the storage control unit notifies the upper level apparatus of the check result. If the received check result indicates a data error, the higher-level device determines that the data has not been correctly written and, for example, sends the previous data write request to the storage system again.
  • FIG. 24 is an example of a sequence when the processing procedure in the storage control unit 1703A or 1803A is performed according to the flowchart shown in FIG. More specifically, FIG. 24 shows an example of a sequence of processing when a write request for data stored in the storage devices 1705A to 1705F of the storage system 1700 or the storage devices 1805A to 1805F of the storage system 1800 is received from the host device. is there.
  • the processing sequence when the storage control unit 1703B or 1803B receives a write request for data stored in the storage devices 1705A to 1705F of the storage system 1700 or the storage devices 1805A to 1805F of the storage system 1800 from the host device is also shown. It becomes the same.
  • the storage control unit 1703A or 1803A and the storage control unit 1703B or 1803B are interchanged.
  • the processor 1701A or 1801A and the processor 1701B or 1801B are interchanged.
  • Memory 1702A or 1802A and memory 1702B or 1802B are interchanged.
  • steps 2201 to 2208 in FIG. 22 of the ninth embodiment can be applied to steps 2401 to 2408.
  • the back-end switch 1704 or the back-end switch 1804A or 1804B notifies the processor 1701B or 1801B that the write data has been sent.
  • the processor 1701B or 1801B acquires the write data from the memory 1702B or 1802B in processing 2410. Next, the processor 1701B or 1801B checks whether there is a data error in step 2411 for the write data acquired from the memory 1702B or 1802B.
  • the data check code is given in advance to the processor 1701B or 1801B.
  • the processor 1701B or 1801B may generate a data check code based on a predetermined rule.
  • the processor 1701A or 1801A may supply the data check code to the processor 1701B or 1801B via the back-end switch 1704 or the back-end switch 1804A or 1804B.
  • the processor 1701B or 1801B After step 2411, the processor 1701B or 1801B notifies the back end switch 1704 or the back end switch 1804A or 1804B of the result of the data error check in step 2412. In step 2413, the back-end switch 1704 or the back-end switch 1804A or 1804B notifies the processor 1701A or 1801A of the notified result.
  • step 2414 the processor 1701A or 1801A notifies the host device of the data error check result notified from the back-end switch 1704 or back-end switch 1804A or 1804B.
  • the storage system 1700 or 1800 according to the tenth embodiment can confirm that the data is stored in the memory without error, and can increase the validity of the data.
  • the data stored in the memory 1702A or 1802A can also be checked for errors.
  • Example 11 will be described with reference to FIGS.
  • the configuration example of the storage system according to the eleventh embodiment is the configuration shown in FIGS.
  • FIG. 25 is an example of a flowchart showing a processing procedure in the storage control unit 1703A or 1703B of the storage system 1700 shown in FIG. 17 and the storage control unit 1803A or 1803B of the storage system 1800 shown in FIG.
  • steps 1900 to 1905 and 1908 to 1910 in FIG. 19 shown in the eighth embodiment can be applied to steps 2500 to 2505 and 2508 to 2510.
  • the storage control unit transfers write data from the memory of the storage control unit to the memory of the other storage control unit in the storage system in step 2505, and then proceeds to step 2520.
  • the storage control unit notifies the other storage control unit that the write data has been transferred to the memory of the other storage control unit.
  • predetermined specific data may be sent to a specific address in the other storage control unit.
  • the notification may be special data including information for identifying the write data and information on whether or not the write data is written in the memory in the other storage control unit.
  • the notification may include an interrupt signal.
  • the other storage control unit When the other storage control unit is notified that the write data has been transferred, the other storage control unit performs a data error check on the transferred data and notifies the storage control unit of the result. This notification is similar to the method of notifying the other storage control unit that the write data has been transferred to the memory of the other storage control unit.
  • step 2521 the storage control unit receives the data error result notified from the other storage control unit.
  • step 2522 the storage control unit notifies the host device of the data error check result. If there is a data error, the host device determines that the data could not be written correctly, and sends the previous data write request to the storage system again, for example. This is the same as the description of step 2307 in FIG.
  • FIG. 26 shows an example of a sequence when the processing procedure in the storage control unit 1703A or 1803A is performed according to the flowchart shown in FIG. More specifically, it is an example of a processing sequence when a write request for data stored in the storage devices 1705A to 1705F of the storage system 1700 or the storage devices 1805A to 1805F of the storage system 1800 is received from the host device.
  • the processing sequence when the storage control unit 1703B or 1803B receives a write request for data stored in the storage devices 1705A to 1705F or the storage devices 17051805A to 1805F from the host device is the same.
  • the storage control unit 1703A or 1803A and the storage control unit 1703B or 1803B are interchanged.
  • the processor 1701A or 1801A and the processor 1701B or 1801B are interchanged.
  • the memory 1702A or 1802A and the memory 1702B or 1802B are interchanged.
  • steps 2001 to 2006 in FIG. 20 in the eighth embodiment can be applied to steps 2601 to 2606.
  • step 2604 the processor 1701A or 1801A reads the write data received from the host device from the memory 1702A or the memory 1802A and sends it to the back-end switch 1704 or the back-end switch 1804A or 1804B.
  • step 2607 the processor 1701A or 1801A notifies the back-end switch 1704 or the back-end switch 1804A or 1804B that the write data has been sent.
  • the back-end switch 1704 or the back-end switch 1804A or 1804B Upon receiving the notification, the back-end switch 1704 or the back-end switch 1804A or 1804B sends a similar notification to the processor 1701B or 1801B in step 2608.
  • the notification method performed in steps 2607 and 2608 is as described for step 2520 in FIG.
  • the processor 1701B or 1801B is notified from the back-end switch 1704 or the back-end switch 1804A or 1804B that the write data has been sent.
  • the processor 1701B or 1801B acquires the write data from the memory 1702B or 1802B.
  • the processor 1701B or 1801B checks whether there is a data error in step 2610 for the write data acquired from the memory 1702A or 1802A.
  • the data error check in step 2610 is the same as the data error check in step 2411 of FIG.
  • steps 2412 to 2414 in FIG. 24 of the tenth embodiment can be applied to subsequent steps 2611 to 2613.
  • Example 11 can achieve the same effect as the effect described in Example 10.
  • Example 12 will be described with reference to FIG. 1 or FIG. 2 and FIGS. 4A, 4B, 6A to 7B, FIG. 28, and FIG.
  • the configuration of the storage system of the twelfth embodiment is the configuration shown in FIG. 1, the descriptions of FIGS. 1, 4A, 4B, and 6A to 7B are the same as those of the first embodiment.
  • FIG. 28 is an example of a flowchart illustrating a processing procedure when the back-end switch 104 receives data or a data request from the processor 101A in the twelfth embodiment.
  • the processing procedure when the back-end switch 104 receives data or a data request from the processor 101B is the same.
  • the processor 101A in FIG. 28 may be read as the processor 101B.
  • the part having the processor 101B is read as the processor 101A.
  • step 2807 the description from step 300 to step 306 in FIG. 3 in the first embodiment can be applied to step 2800 to step 2806.
  • step 2804 the processing in the backend switch 104 proceeds to step 2807.
  • step 2807 the back-end switch 104 determines whether the frame sent from the processor 101A is data sending for storage in the memory 102B or a data acquisition request for the memory 102B. If the determined result is data transmission to the memory 102B (2807: data transmission), the back-end switch 104 proceeds to step 2808.
  • step 2808 the back-end switch 104 sends a request to obtain again the data stored in the memory 102B to the processor 101B.
  • the length of the data requested again may be equal to the length of the data sent in step 2804, or may be the length of a part of the data sent in step 2804.
  • the back end switch 104 may read the last part of the data sent in step 2804.
  • step 2809 the back-end switch 104 receives the data from the processor 101B.
  • step 2810 the back-end switch 104 notifies the processor 101A that the data has been received from the processor 101B, and ends the processing.
  • the notification to the processor 101A may be performed, for example, by sending all or a part of the data received from the processor 101B to the processor 101A, or by sending a predetermined specific signal to the processor 101A. .
  • the processor 101A discards all or part of the received data.
  • the notification may be performed by sending predetermined specific data to a specific address in the address space of the processor 101A.
  • the notification may be performed by sending an interrupt signal to the processor 101A. In this way, it is possible to notify the processor 101A that the data has been reliably written to the memory 102B. If it is determined in step 2807 that the determination result is a data acquisition request for the memory 102B (2807: data request), the back-end switch 104 ends the process.
  • FIG. 29 shows an example of a processing sequence for transmitting data from the storage control unit 103A to the storage control unit 103B when the back-end switch 104 performs processing according to the processing procedure shown in FIG.
  • the sequence of processing in which the storage control unit 103B transmits data to the storage control unit 103A is the same.
  • the storage control unit 103A and the storage control unit 103B are interchanged.
  • the processor 101A and the processor 101B are interchanged.
  • the memory 102A and the memory 102B are interchanged.
  • step 2905 the back-end switch 104 sends a data acquisition request for re-designating the address B sent in step 2903 to the processor 101B.
  • the length of the data to be acquired may be equal to the length of the data sent with the address B given in step 2905, or the length of the part of the data sent with the address B given in step 2905.
  • the back end switch 104 may change the data length and the address B so as to obtain the last part of the data sent in Step 2905. This is the same as the description of step 2808 in FIG.
  • the processor 101B When the processor 101B receives the data request to which the address B is assigned from the back-end switch 104, the processor 101B acquires data from the memory 102B according to the address B in step 2906. Next, in step 2907, the processor 101B returns the data acquired from the memory 102B to the back-end switch 104.
  • Steps 2906 and 2907 may be executed by software operating on the processor 101B, or may be executed by functional hardware (circuit) mounted on the processor 101B.
  • the functional hardware When the functional hardware receives a data request to which the address B is assigned from the back-end switch 104, the functional hardware automatically acquires data from the memory 102B according to the address B and returns it to the back-end switch 104.
  • the back-end switch 104 When the back-end switch 104 receives the return of the data at the address B from the processor 101B, in step 2908, the back-end switch 104 notifies the processor 101A that the data has been sent. This notification method is as described in step 2810 of FIG.
  • the processor 101A can be notified that the data sent to the storage control unit 103B has been reliably stored in the memory 102B.
  • the storage control units 103A and 103B can duplicate the data.
  • FIG. 2 As the configuration of the storage system of the present embodiment, the configuration shown in FIG. 2 can be adopted instead of the configuration shown in FIG. In this case, the description regarding FIGS. 2, 4A, 4B, and 6A to 7B is the same as that of the second embodiment.
  • the storage control unit 103A is replaced with a storage control unit 203A.
  • the storage control unit 103B is replaced with a storage control unit 203B.
  • the processor 101A is replaced with a processor 201A.
  • the processor 101B is replaced with a processor 201B.
  • the memory 102A is replaced with the memory 202A.
  • the memory 102B is replaced with the memory 202B.
  • the back end switch 104 is replaced with a back end switch 204A or 204B.
  • the storage devices 105A to 105F are replaced with storage devices 205A to 205F.
  • this invention is not limited to the above-mentioned Example, Various modifications are included.
  • the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described.
  • a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment.
  • each of the above-described configurations, functions, processing units, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit.
  • Each of the above-described configurations, functions, and the like may be realized by software by interpreting and executing a program that realizes each function by the processor.
  • Information such as programs, tables, and files for realizing each function can be stored in a memory, a hard disk, a recording device such as an SSD (Solid State Drive), or a recording medium such as an IC card or an SD card.
  • control lines and information lines indicate what is considered necessary for the explanation, and not all control lines and information lines on the product are necessarily shown. In practice, it may be considered that almost all the components are connected to each other.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Multi Processors (AREA)

Abstract

La présente invention concerne un système de stockage comprend un premier processeur, un deuxième processeur et un ou plusieurs commutateurs dorsaux qui connectent un ou plusieurs dispositifs de stockage. Chacun des commutateurs dorsaux se réfère à une trame reçue du premier processeur pour identifier une destination de transmission de la trame. Dans le cas où la destination de transmission de la trame est le deuxième processeur, chacun des commutateurs dorsaux convertit une première adresse qui est incluse dans la trame et identifie un emplacement dans une deuxième mémoire dans un espace d'adresses du premier processeur en une deuxième adresse qui identifie l'emplacement dans la deuxième mémoire dans un espace d'adresses du deuxième processeur, et transmet la trame contenant la deuxième adresse à une deuxième unité de commande de stockage.
PCT/JP2017/016951 2017-04-28 2017-04-28 Système de stockage WO2018198325A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
PCT/JP2017/016951 WO2018198325A1 (fr) 2017-04-28 2017-04-28 Système de stockage
JP2017170379A JP6734824B2 (ja) 2017-04-28 2017-09-05 ストレージシステム
US15/959,675 US10402361B2 (en) 2017-04-28 2018-04-23 Storage system
CN201810390254.7A CN108804030B (zh) 2017-04-28 2018-04-27 存储系统
US16/524,375 US10789196B2 (en) 2017-04-28 2019-07-29 Storage system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2017/016951 WO2018198325A1 (fr) 2017-04-28 2017-04-28 Système de stockage

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US15/959,675 Continuation-In-Part US10402361B2 (en) 2017-04-28 2018-04-23 Storage system
US15/959,675 Continuation US10402361B2 (en) 2017-04-28 2018-04-23 Storage system

Publications (1)

Publication Number Publication Date
WO2018198325A1 true WO2018198325A1 (fr) 2018-11-01

Family

ID=63920196

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2017/016951 WO2018198325A1 (fr) 2017-04-28 2017-04-28 Système de stockage

Country Status (2)

Country Link
JP (1) JP6734824B2 (fr)
WO (1) WO2018198325A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020077137A (ja) * 2018-11-07 2020-05-21 株式会社日立製作所 ストレージシステム

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6899852B2 (ja) * 2019-01-15 2021-07-07 株式会社日立製作所 ストレージ装置
JP7315753B2 (ja) * 2019-08-02 2023-07-26 株式会社日立製作所 ストレージ装置
JP7080863B2 (ja) * 2019-08-02 2022-06-06 株式会社日立製作所 ストレージ装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007128175A (ja) * 2005-11-01 2007-05-24 Hitachi Ltd ストレージシステム
WO2014027416A1 (fr) * 2012-08-17 2014-02-20 富士通株式会社 Dispositif de traitement d'informations et procédé pour la commande d'un dispositif de traitement d'informations

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7062591B2 (en) * 2001-09-28 2006-06-13 Dot Hill Systems Corp. Controller data sharing using a modular DMA architecture
JP4391954B2 (ja) * 2005-02-18 2009-12-24 富士通株式会社 ファイル制御システムおよびファイル制御装置
US8250254B2 (en) * 2007-07-31 2012-08-21 Intel Corporation Offloading input/output (I/O) virtualization operations to a processor
JP2009053946A (ja) * 2007-08-27 2009-03-12 Toshiba Corp 二重化コントーラ構成ブロックデバイス制御装置
US8700856B2 (en) * 2012-03-23 2014-04-15 Hitachi, Ltd. Method for accessing mirrored shared memories and storage subsystem using method for accessing mirrored shared memories

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007128175A (ja) * 2005-11-01 2007-05-24 Hitachi Ltd ストレージシステム
WO2014027416A1 (fr) * 2012-08-17 2014-02-20 富士通株式会社 Dispositif de traitement d'informations et procédé pour la commande d'un dispositif de traitement d'informations

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020077137A (ja) * 2018-11-07 2020-05-21 株式会社日立製作所 ストレージシステム

Also Published As

Publication number Publication date
JP6734824B2 (ja) 2020-08-05
JP2018190368A (ja) 2018-11-29

Similar Documents

Publication Publication Date Title
CN108804030B (zh) 存储系统
WO2018198325A1 (fr) Système de stockage
US7899945B2 (en) Interface device and method for command processing
US8332542B2 (en) Communication with input/output system devices
US20050108476A1 (en) Storage device and controlling method thereof
US8527725B2 (en) Active-active remote configuration of a storage system
US20050262390A1 (en) Method and apparatus for constructing redundant array of independent disks system using disk drives
US7460531B2 (en) Method, system, and program for constructing a packet
CN110609659A (zh) 用于执行读取命令的NVMeoF RAID实现方法
JP5102917B2 (ja) ストレージ装置及びアクセス命令送信方法
CN113767360A (zh) 在驱动器级别处对非易失性存储器联网消息的终止
US10275388B2 (en) Simultaneous inbound multi-packet processing
US20150067235A1 (en) Memory system and data writing method
US20060277326A1 (en) Data transfer system and method
JP5728088B2 (ja) 入出力制御装置及び入出力制御装置のフレーム処理方法
US10719391B2 (en) Storage system and storage control apparatus
US8856404B2 (en) Primitive group data encoding in a data storage fabric
US11842083B2 (en) Storage system architecture with dual storage virtualization controllers and the data access method thereof
US11474751B2 (en) Storage apparatus and data processing method therefor
US11836386B2 (en) Storage system and method of controlling storage system that set ports associated with a logical unit
US20240232099A9 (en) Storage system
JP2024060523A (ja) ストレージシステム
JP4497940B2 (ja) データ保証制御装置
JP2023038548A (ja) ストレージシステム
JP2022039501A (ja) ストレージ制御装置、送達状況判定プログラムおよびストレージシステム

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17907982

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17907982

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP