WO2018188166A1 - 一种屏蔽式均压电路 - Google Patents

一种屏蔽式均压电路 Download PDF

Info

Publication number
WO2018188166A1
WO2018188166A1 PCT/CN2017/085347 CN2017085347W WO2018188166A1 WO 2018188166 A1 WO2018188166 A1 WO 2018188166A1 CN 2017085347 W CN2017085347 W CN 2017085347W WO 2018188166 A1 WO2018188166 A1 WO 2018188166A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
capacitance
thyristor
branch
series
Prior art date
Application number
PCT/CN2017/085347
Other languages
English (en)
French (fr)
Inventor
汤广福
高冲
贺之渊
查鲲鹏
周建辉
盛财旺
Original Assignee
全球能源互联网研究院有限公司
国家电网公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 全球能源互联网研究院有限公司, 国家电网公司 filed Critical 全球能源互联网研究院有限公司
Publication of WO2018188166A1 publication Critical patent/WO2018188166A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion

Definitions

  • the invention relates to the technical field of ultra-high voltage direct current transmission, in particular to a shielded voltage equalization circuit.
  • the converter valve is the core equipment for AC/DC conversion of electric energy. It is the "heart" of DC engineering, and it is essential to be able to operate reliably for a long time. There are many metal parts in the converter valve, various shapes and complicated layouts. There are a lot of stray capacitance between the metal parts and the ground, and the frequency change effect is remarkable. The thyristors and the saturable reactors in the converter valve are strongly nonlinear. Under the action of 1200kV/ ⁇ s steep wave impulse voltage, the stray capacitance of the shield will cause the voltage distribution in the wide frequency range of the hundreds of series thyristors and their components in the converter valve to be unbalanced, and the unevenness will exceed 40%. In order to solve the problem of series electrical stress equalization of more than 100 series thyristors and their components under the impact voltage, domestic and foreign scholars have carried out a lot of research work, and each proposed their own voltage equalization circuit.
  • ABB's converter valve uses the averaging circuit schematic shown in Figure 1.
  • C s(in) and C g(in) respectively indicate the mutual capacitance between the metal terminals in the converter valve and the capacitance of the metal terminal to ground
  • C s (out) and C g (out) respectively indicate the mutual capacitance between the shields in the converter valve and the capacitance of the shield to the ground.
  • the grading circuit shown in Figure 1 adopts the split shielding method, in which the shield is divided into several sections, and there is a coupling relationship between the shields of each section, which is equivalent to a large capacitance between each thyristor, and each shield pair
  • the ground capacitance acts on different potential points, and the shunting action is dispersed, which also weakens the uneven pressure effect.
  • the saturable reactor in the converter valve is arranged centrally in the middle of the valve assembly, and the surge voltage is not limited by the saturation reactor, directly invading the first-end thyristor, thereby increasing the voltage and steepness of the thyristor of the stage; and for the voltage level higher ⁇ In 1100kV DC project, the number of thyristor series connected in series with single valve will increase, which will increase the influence of the capacitance of the shield cover on the voltage distribution, increase the voltage and steepness of the first-level thyristor, and eventually increase the voltage unevenness of the thyristor. This can cause damage to the device.
  • FIG. 2 Another schematic diagram of the voltage equalization circuit of the existing converter valve is shown in Fig. 2.
  • the circuit increases the longitudinal stray capacitance C e based on the split shield voltage equalization method, so that the ratio of the capacitance to the mutual capacitance is When reduced, the thyristor unevenness is reduced.
  • the venting effect of the shield to ground capacitance increases, resulting in increased thyristor non-uniformity. Therefore, the method of increasing the vertical stray capacitance can not meet the requirements, and a new equalization measure is required.
  • the original circuit diagram of the voltage equalization circuit adopted by the Siemens converter valve is shown in Figure 3.
  • the circuit is equalized by the method of integral shielding plus component capacitance.
  • the potential of each layer of the shield is fixed at the intermediate potential of the converter valve module.
  • the voltage of the thyristor in each module is consistent, and the voltage of the thyristor in the upper and lower modules of the single valve is not uniform, mainly due to the commutation in Figure 3.
  • the capacitance of the inner shield of the valve to the ground C g (out) is large, which increases the leakage current of the main circuit to the ground.
  • Siemens parallels the component capacitor C t in each converter valve module, which is equivalent to equalizing by increasing the mutual capacitance.
  • the component capacitor will assume a converter valve assembly. Voltage. Increasing the component capacitor voltage equalization scheme will increase the total capacitance of the single valve. Under the non-periodic triggering condition, the opening current stress of the thyristor will increase, and the loss of the converter valve under various operating conditions will be increased.
  • the thyristor voltage unevenness is less than 1%, and the maximum voltage steepness is reduced to 6.8kV/ ⁇ s can realize the distortion of the key components of the converter valve in the wide frequency domain, improve the reliability and insulation tolerance of components, and has strong engineering application value.
  • the present invention provides a shielded voltage equalizing circuit, the shielded voltage equalizing circuit comprising a main circuit and an auxiliary circuit in parallel with the main circuit;
  • the main circuit includes a thyristor-level equivalent circuit, a metal terminal-to-ground capacitance, and a saturable reactor equivalent circuit;
  • the auxiliary circuit includes M ⁇ -type circuits connected in series.
  • the thyristor-level equivalent circuit is provided with 2N, wherein N thyristor-level equivalent circuits are sequentially connected in series to form a first thyristor assembly circuit, and the remaining N thyristor-level equivalent circuits are sequentially connected in series to form a second thyristor assembly circuit.
  • the saturation reactor equivalent circuit includes a first saturable reactor equivalent circuit, a second saturable reactor equivalent circuit, a third saturable reactor equivalent circuit, and a fourth saturable reactor equivalent circuit.
  • the first saturated reactor equivalent circuit, the first thyristor component circuit, the second saturated reactor equivalent circuit, the third saturated reactor equivalent circuit, the second thyristor component circuit, and the fourth saturated reactor equivalent circuit are sequentially In series.
  • the thyristor-level equivalent circuit includes a damping resistor R d , a parasitic inductance L Rd , a damping capacitor C d , a thyristor junction capacitance C i , and a mutual capacitance C j between the heat sinks;
  • the damping resistor R d , the parasitic inductance L Rd and the damping capacitor C d are connected in series to form a R d -L Rd -C d branch;
  • the thyristor junction capacitance C i and the heat sink mutual capacitance C j are connected in parallel to form a C i //C j branch;
  • the R d -L Rd -C d branch is connected in parallel with the C i //C j branch.
  • the first saturated reactor equivalent circuit, the second saturated reactor equivalent circuit, the third saturated reactor equivalent circuit and the fourth saturated reactor equivalent circuit both include an in-and-out line busbar mutual capacitance Cb , copper
  • the loss equivalent resistance R Cu , the hollow inductor L leak , the mutual capacitance C gr between the turns and the core, the eddy current loss equivalent resistance R Fe , the nonlinear inductance inductance L m , and the turn-to-turn capacitance C sl both include an in-and-out line busbar mutual capacitance Cb , copper
  • the copper loss equivalent resistance R Cu is connected in series with the hollow inductor L leak to form a R Cu -L leak branch;
  • the R Cu -L leak branch is connected in parallel with the mutual capacitance C gr between the coil and the core to form a (R Cu -L leak )//C gr branch;
  • the eddy current loss equivalent resistance R Fe , the nonlinear inductor inductance L m and the interturn capacitance C sl are connected in parallel to form an R Fe //L m //C sl branch;
  • the ⁇ -type circuit includes a shield-to-ground capacitance C g1 (out) , a shield-to-ground capacitance C g2 (out) , a shield-to-earth capacitance C s , and a component capacitance C m .
  • the shield-to-ground capacitance C g1(out) is connected in series with the C s //C m branch to form a C g1(out) -(C s //C m ) branch, the C g1(out) -( C s // C m) branch connected to ground and the other end connected to one end of the shield cover earth capacitance C g2 (out), the other end of the shield the earth capacitance C g2 (out) is.
  • the metal terminal has a capacitance of 2N to the ground, and one end of the metal terminal to the ground is connected between two adjacent thyristor-level equivalent circuits, and the other end is grounded.
  • the shielded voltage equalizing circuit provided by the invention is provided with a main circuit and an auxiliary circuit connected in parallel with the main circuit, and the main circuit comprises a thyristor-level equivalent circuit, a metal terminal-to-ground capacitance and a saturable reactor equivalent circuit, and the auxiliary circuit includes M
  • the ⁇ -type circuit connected in series realizes the shielded equalization of the thyristor in the converter valve;
  • the first and last ends of the ⁇ -type circuit in the shielded voltage equalizing circuit provided by the invention are connected to the first end of the main circuit, and the potential point of the shielding cover is fixed on the capacitors of the respective stages, which can completely block the flow of the stray capacitance of the main circuit through the shielding cover to the ground or Leakage current flowing out;
  • the shielding type voltage equalizing circuit provided by the invention does not have any electrical connection between the main circuit and the shielding cover and the component capacitor, so that the capacitance current of the shielding cover to the ground is provided by the component capacitance of the auxiliary circuit, and does not pass through the main circuit, so that the commutation is performed.
  • the key components of the valve are completely shielded, so as to ensure the uniform distribution of the thyristor voltage in the converter valve under high frequency impact. Under the low frequency domain of the converter valve, the capacitor of the component is equivalent to the open circuit state, which ensures the safety of the main circuit. Reliable operation; under high frequency impact, the voltage distribution of the component capacitor can be adjusted by the parameter selection of the capacitor to ensure the voltage distribution of the capacitor voltage of each component;
  • the invention can realize that the thyristor voltage non-uniformity is reduced to 0.17%, the maximum voltage steepness reaches 6.8kV/ ⁇ s, the interlayer voltage unevenness reaches 0.8%, the voltage harmonization distribution of the series thyristor is realized, and the thyristor is greatly reduced due to voltage distribution. Risk of damage;
  • the invention utilizes parasitic capacitance or component capacitance to reduce the influence of stray capacitance on the voltage distribution of the series thyristor in the converter valve, and increases the mutual capacitance and shields the leakage effect of the capacitance to the main circuit, so that the capacitance to the ground and the mutual The ratio of the capacitances approaches zero, achieving a voltage-balanced distribution of the thyristors.
  • FIG. 1 is a schematic diagram of a company's converter valve grading circuit in the prior art
  • FIG. 2 is a schematic diagram of a conventional converter valve equalizing circuit in the prior art
  • FIG. 3 is a schematic diagram of a commutation valve grading circuit of Siemens in the prior art
  • FIG. 4 is a schematic diagram of a shielded voltage equalizing circuit in an embodiment of the present invention.
  • Figure 5 is a structural diagram of a shielded voltage equalizing circuit in an embodiment of the present invention.
  • the shielded equalizing circuit applied to the converter valve with zero distortion and high reliability provided by the embodiment of the invention mainly adopts two technical solutions of the surge valve surge voltage analysis and the capacitor shielded equalizing voltage.
  • the technical solutions are described as follows:
  • the thyristor in the converter valve adopts a chain-type series structure, and its structure size can be compared with the wavelength of the high-frequency surge voltage. It cannot be regarded as a centralized parameter circuit. It is necessary to adopt the transmission line theory to establish a distributed parameter mode analysis wave process.
  • the converter valve When the converter valve is excited by high-frequency voltage, the saturable reactor as the inductance component has a large impedance and the current cannot be abrupt, so there is no current flowing temporarily, which is equivalent to the direct opening of the inductor.
  • the converter valve can be simplified to T.
  • the calculation formula is as follows:
  • the auxiliary circuit includes a plurality of ⁇ -type circuits.
  • the first end of the ⁇ -type circuit is connected to the first end of the main circuit, and the potential of the shield cover is fixed on the capacitors of the respective stages, which can completely block the flow or the outflow of the main circuit through the shield cover to the ground stray capacitance. Leakage current. There is no electrical connection between the main circuit and the shield and component capacitors.
  • the insulated slot beam maintains good insulation between the main circuit and the shield and component capacitors.
  • the capacitance current of the shield to the ground is provided by the auxiliary circuit component capacitor, and does not pass through the main circuit, so that the key components of the converter valve are completely shielded, thereby ensuring uniform distribution of the thyristor voltage in the converter valve under high frequency impact.
  • the auxiliary circuit impedance is equivalent to the open circuit state, which ensures the safe and reliable operation of the main circuit; under high frequency impact, the voltage distribution of the component capacitor can be adjusted by the parameter selection of the capacitor. Ensure the voltage distribution of the capacitor voltage of each component.
  • the embodiment of the present invention provides a shielded voltage equalizing circuit applied to the converter valve, and the schematic diagram of the shielded voltage equalizing circuit is as shown in FIG. 4 .
  • C s (in) and C g (in) respectively indicate the mutual capacitance between the metal terminals in the converter valve and the capacitance of the metal terminal to the ground
  • C s (out) and C g (out) respectively represent the inside of the converter valve.
  • C m represents the parasitic capacitance or component capacitance of the components in the converter valve. It can be seen from Fig. 4 that the C g(out) and the single-valve main circuit are only connected end to end, and the intermediate stray capacitance has no electrical connection relationship with the main circuit, so the voltage distribution of each module of the main circuit is not affected.
  • FIG. 5 The specific structure of the shielded voltage equalizing circuit is shown in FIG. 5, which includes a main circuit and an auxiliary circuit in parallel with the main circuit; the main circuit and the auxiliary circuit are respectively described in detail below.
  • the above main circuit includes a thyristor-level equivalent circuit, a saturable reactor equivalent circuit, and a metal terminal-to-ground capacitance;
  • the thyristor-level equivalent circuit is provided with 2N, wherein N thyristor-level equivalent circuits are sequentially connected in series to form a first thyristor assembly circuit, and the remaining N thyristor-level equivalent circuits are sequentially connected in series to form a second thyristor assembly circuit.
  • the thyristor-level equivalent circuit in the first thyristor assembly circuit and the second thyristor assembly circuit includes a damper resistor R d , a parasitic inductance L Rd , a damper capacitor C d , a thyristor junction capacitance C i , and a mutual capacitance C j between the heat sinks.
  • the series-parallel relationship between them is as follows:
  • the damping resistor R d , the parasitic inductance L Rd and the damping capacitor C d are connected in series to form a R d -L Rd -C d branch; the thyristor junction capacitance C i and the heat sink mutual capacitance C j are connected in parallel to form C i //C
  • the j branch, the above R d -L Rd -C d branch is connected in parallel with the C i //C j branch.
  • the capacitor is composed of a thyristor junction capacitance C i and a heat sink capacitor C j at both ends.
  • the thyristor ends the thyristor to turn off the overshoot voltage through a parallel RC circuit.
  • the equivalent circuit of the saturable reactor includes four saturated reactor equivalent circuits, which are the first saturated reactor equivalent circuit, the second saturated reactor equivalent circuit, the third saturated reactor equivalent circuit and the fourth saturation. Reactor equivalent circuit.
  • the first saturated reactor equivalent circuit, the second saturated reactor equivalent circuit, the third saturated reactor equivalent circuit and the fourth saturated reactor equivalent circuit all include mutual capacitance C b between the input and output busbars, copper loss, etc.
  • the effective resistance R Cu , the hollow inductor L leak , the mutual capacitance C gr between the turns and the core, the eddy current loss equivalent resistance R Fe , the nonlinear inductance inductance L m and the turn-to-turn capacitance C sl , the series-parallel relationship between them is as follows :
  • the copper loss equivalent resistance R Cu is connected in series with the hollow inductor L leak to form a R Cu -L leak branch, and the R Cu -L leak branch is connected in parallel with the mutual capacitance C gr between the coil and the core to form (R Cu -L Leak ) / / C gr branch, eddy current loss equivalent resistance R Fe , nonlinear inductance inductance L m and turn-to-turn capacitance C sl in parallel, forming R Fe / / L m / C sl branch, (R Cu - L
  • the leak )//C gr branch is connected in series with the R Fe //L m //C sl branch, and is connected in parallel with the mutual capacitance C b between the incoming and outgoing busbars.
  • the shielding cover Since the shielding cover is installed on the periphery, the first saturated reactor equivalent circuit, the second saturated reactor equivalent circuit, the third saturated reactor equivalent circuit, and the fourth saturation reactor equivalent circuit
  • the mutual capacitance C b is shielded and therefore negligible.
  • the first saturated reactor equivalent circuit, the second saturated reactor equivalent circuit, the third saturated reactor equivalent circuit, the fourth saturated reactor equivalent circuit, the first thyristor module circuit, and the second thyristor module circuit The order of tandem is:
  • the first saturated reactor equivalent circuit, the first thyristor assembly circuit, the second saturated reactor equivalent circuit, the third saturated reactor equivalent circuit, the second thyristor assembly circuit, and the fourth saturated reactor equivalent circuit are sequentially connected in series.
  • the number of capacitors of the metal terminal to the ground is the same as the equivalent circuit of the thyristor stage, that is, the capacitance of the metal terminal to the ground is also set to 2N, and one end of the metal terminal to the ground is connected between the adjacent two thyristor-level equivalent circuits, The other end is grounded.
  • the auxiliary circuit includes M ⁇ -type circuits connected in series, each ⁇ -type circuit including a shield-to-ground capacitance C g1 (out) , a shield-to-ground capacitance C g2 (out) , and a mutual capacitance C s between the shields.
  • the component capacitance C m the series-parallel relationship between them is as follows:
  • the mutual capacitance C s between the shielding cover and the component capacitance C m are connected in parallel to form a C s //C m branch;
  • the shield-to-ground capacitance C g1(out) is connected in series with the above-mentioned C s //C m branch to form C g1 (out) -(C s //C m ) branch, the C g1(out) -(C s //C m ) branch is grounded at one end, and the other end is connected to one end of the shield to ground capacitance C g2 (out)
  • the shield is grounded to the other end of the ground capacitor C g2 (out) .
  • the voltage distribution of the converter valve using the shielded voltage equalizing voltage circuit is shown in Table 1.
  • the voltage distribution trend of the thyristors at each level is basically the same regardless of the variability of the thyristor parameters at all levels, and the difference between the maximum and minimum values is only the same. 0.004kV, the unevenness is 0.17%, which greatly reduces the non-uniformity of the converter valve; the maximum voltage steepness of the thyristor is 6.8kV/ ⁇ s, which greatly improves the reliability of the device; the voltage distribution between the layers of the converter valve Very uniform pressure, uneven pressure is 0.03%.
  • the shielded voltage equalizing circuit applied to the converter valve provided by the embodiment of the present invention has a thyristor voltage, a maximum voltage steepness and a voltage of a key component of the converter valve under high frequency impact during the working process. All important indicators such as unevenness are significantly better than the electrical balancing effect of the converter valve in the prior art.
  • the circuit can be applied to equipments with modular and large-scale series unit voltage equalization, such as CVT, flexible DC converter valves, DC circuit breakers and other high-voltage equipment, and has broad market application prospects.
  • the embodiment of the present invention adopts the impulse voltage analysis technology
  • the voltage distribution of each component of the main circuit of the converter valve is mainly determined by the stray capacitance to the ground, and the discharge capacity of the main circuit is increased by increasing the mutual capacitance and shielding the capacitance to the ground. Therefore, the ratio of capacitance to mutual capacitance approaches zero, and the voltage distribution of the thyristor is balanced.
  • the technology can simplify the complicated circuit of the converter valve and improve the calculation efficiency of the voltage distribution of the thyristor under high frequency impact;
  • the shielded voltage equalizing circuit provided by the embodiment of the present invention can utilize parasitic capacitance or component capacitance to reduce the influence of the ground stray capacitance on the voltage distribution of the series thyristor in the converter valve, and realize the voltage distribution of the thyristor voltage;
  • the shielded voltage equalizing circuit provided by the embodiment of the invention can realize the following three functions: 1) the fixed position of the shield cover potential has no electrical connection relationship with the main circuit of the converter valve; 2) the potential of the single valve head end and the first end shield cover have The potential connection relationship; 3) The other potential points of the shield can be fixed on the component or capacitor component of the converter valve and shielded from the main circuit of the converter valve.
  • the embodiment of the invention can also realize that the thyristor voltage non-uniformity is reduced to 0.17%, the maximum voltage steepness reaches 6.8kV/ ⁇ s, and the interlayer voltage unevenness reaches 0.8%, thereby realizing the balanced distribution of the series thyristor voltage and greatly reducing the voltage.
  • UHV converter valves have entered the overseas market, and cross-regional energy interconnection can be realized in engineering applications in Brazil, Canada, Pakistan and other regions in the future.
  • Foreign ABB and Siemens converter valves may apply this technology, and this technical solution can be applied to
  • embodiments of the present application can be provided as a method, system, or computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • These computer program instructions can also be stored in a computer or other programmable data processing device.
  • the computer readable memory that operates in a fixed manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device implemented in a block or a block and/or a block diagram of a flowchart or The functions specified in multiple boxes.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Power Conversion In General (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

一种屏蔽式均压电路，其包括主电路和与主电路并联的辅助电路；主电路包括晶闸管级等效电路、金属端子对地电容和饱和电抗器等效电路；辅助电路包括M个依次串联的π型电路。将屏蔽罩电位固定点与主电路电气隔离，仅让换流阀首末端与屏蔽罩有电气连接，屏蔽了换流阀内对地杂散电容的泄流效应，实现了宽频域规模化串联晶闸管的电压均衡分布，在陡波冲击下，晶闸管电压不均匀度低于1％，最大电压陡度降低至6.8kV/μs，能够实现宽频域下换流阀关键元器件电压无畸变，提高了元器件的可靠性及绝缘耐受度。

Description

一种屏蔽式均压电路 技术领域
本发明涉及特高压直流输电技术领域，具体涉及一种屏蔽式均压电路。
背景技术
换流阀是实现电能交直流转换的核心装备，是直流工程的“心脏”，能否长期可靠运行至关重要。换流阀内金属部件众多、形状各异、布局复杂，各金属部件间和对地存在大量杂散电容，频变效应显著，换流阀中的晶闸管和饱和电抗器等部件呈现强非线性。在1200kV/μs陡波冲击电压作用下，屏蔽罩杂散电容将导致换流阀内百余支串联晶闸管及其组件宽频范围内电压分布不均衡，不均匀度将超过40％。为解决冲击电压作用下，百余支串联晶闸管及其组件串联电气应力均衡难题，国内外学者开展了大量研究工作，各自提出了自身的均压电路。
ABB公司的换流阀采用图1所示的均压电路原理图，图中Cs(in)和Cg(in)分别表示换流阀内金属端子间互电容和金属端子对地电容，Cs(out)和Cg(out)分别表示换流阀内屏蔽罩间互电容和屏蔽罩对地电容。
如图1所示的均压电路采用分体式屏蔽法，其中将屏蔽罩分成几段，各段屏蔽罩之间存在着耦合关系，等效至每级晶闸管间的电容较大，各屏蔽罩对地电容作用于不同的电位点，其分流作用被分散，也相应削弱了不均压作用。换流阀中的饱和电抗器集中布置于阀组件中间，冲击电压未通过饱和电抗器予以限压，直接侵入首端晶闸管，提高了该级晶闸管电压和陡度；而对于电压等级更高的±1100kV直流工程，单阀串联的晶闸管级数将增加，将会增大屏蔽罩对地电容对电压分布的影响，增大首级晶闸管电压和陡度，最终会加大晶闸管电压不均匀度，严重时会造成器件的损坏。
再一现有换流阀其均压电路原理图如图2所示，该电路在分体式屏蔽均压方法的基础之上增加了纵向杂散电容Ce，使得对地电容与互电容之比减小，则晶闸管不均匀度降低。随着阀模块层数的增加，屏蔽罩对地电容的泄流效应增强，使得晶闸管不均匀度增大。因此，通过增加纵向杂散电容的方法已不能满足要求，需采取新型均压措施。
西门子换流阀所采取的均压电路原路图如图3所示，该电路采用整体式屏蔽加组件电容的方法进行均压。其中每层屏蔽罩电位都固定在换流阀模块中间电位点，每个模块内晶闸管电压是一致的，而单阀上下层模块内晶闸管电压不均匀度较大，主要是 由于图3中换流阀内屏蔽罩对地电容Cg(out)较大，增大了主电路对地泄露电流。为保证换流阀模块电压均压分布，西门子公司在每个换流阀模块当中并联组件电容Ct，相当于通过增加互电容的方法进行均压，该组件电容将承担一个换流阀组件的电压。增加组件电容均压的方案会增大单阀总电容值，在非周期触发工况下，会增大晶闸管的开通电流应力；同时会增加换流阀在多种运行工况下的损耗。
发明内容
为了克服国内外换流阀中串联晶闸管及其组件电气应力均衡实施方案存在不均匀性带来的换流阀中关键器件可靠性降低的问题，本发明从冲击电压下串联晶闸管电压分布的电气原理出发，基于换流阀冲击电压分布机理，提供一种屏蔽式均压电路，通过将屏蔽罩电位固定点与主电路的电气隔离，仅让换流阀首末端与屏蔽罩有电气连接，屏蔽了换流阀内对地杂散电容的泄流效应，最终实现了宽频域规模化串联晶闸管的电压均衡分布，在陡波冲击下，晶闸管电压不均匀度低于1％，最大电压陡度降低至6.8kV/μs，能够实现宽频域下换流阀关键元器件电压无畸变，提高了元器件的可靠性及绝缘耐受度，具有很强的工程应用价值。
为了实现上述发明目的，本发明采取如下技术方案：
本发明提供一种屏蔽式均压电路，所述屏蔽式均压电路包括主电路和与主电路并联的辅助电路；
所述主电路包括晶闸管级等效电路、金属端子对地电容和饱和电抗器等效电路；
所述辅助电路包括M个依次串联的π型电路。
所述晶闸管级等效电路设有2N个，其中N个晶闸管级等效电路依次串联形成第一晶闸管组件电路，其余N个晶闸管级等效电路依次串联形成第二晶闸管组件电路。
所述饱和电抗器等效电路包括第一饱和电抗器等效电路、第二饱和电抗器等效电路、第三饱和电抗器等效电路和第四饱和电抗器等效电路。
所述第一饱和电抗器等效电路、第一晶闸管组件电路、第二饱和电抗器等效电路、第三饱和电抗器等效电路、第二晶闸管组件电路和第四饱和电抗器等效电路依次串联。
所述晶闸管级等效电路包括阻尼电阻Rd、寄生电感LRd、阻尼电容Cd、晶闸管结电容Ci和散热器间互电容Cj；
所述阻尼电阻Rd、寄生电感LRd和阻尼电容Cd串联，组成Rd-LRd-Cd支路；
所述晶闸管结电容Ci和散热器间互电容Cj并联，组成Ci//Cj支路；
所述Rd-LRd-Cd支路与Ci//Cj支路并联。
所述第一饱和电抗器等效电路、第二饱和电抗器等效电路、第三饱和电抗器等效电路和第四饱和电抗器等效电路均包括进出线母排间互电容Cb、铜损等效电阻RCu、空心电感Lleak、线匝和铁芯间互电容Cgr、涡流损耗等效电阻RFe、非线性电感电感Lm以及匝间电容Csl。
所述铜损等效电阻RCu与空心电感Lleak串联，形成RCu-Lleak支路；
所述RCu-Lleak支路与线匝和铁芯间互电容Cgr并联，形成(RCu-Lleak)//Cgr支路；
所述涡流损耗等效电阻RFe、非线性电感电感Lm以及匝间电容Csl并联，形成RFe//Lm//Csl支路；
所述(RCu-Lleak)//Cgr支路与RFe//Lm//Csl支路串联后，与进出线母排间互电容Cb并
联。
所述π型电路包括屏蔽罩对地电容Cg1(out)、屏蔽罩对地电容Cg2(out)、屏蔽罩间互电容Cs和组件电容Cm。
所述屏蔽罩间互电容Cs和组件电容Cm并联，组成Cs//Cm支路；
所述屏蔽罩对地电容Cg1(out)与Cs//Cm支路串联，形成Cg1(out)-(Cs//Cm)支路，所述Cg1(out)-(Cs//Cm)支路一端接地，另一端连接屏蔽罩对地电容Cg2(out)的一端，所述屏蔽罩对地电容Cg2(out)的另一端接地。
所述金属端子对地电容设有2N个，所述金属端子对地电容一端连接在相邻两个晶闸管级等效电路之间，其另一端接地。
与最接近的现有技术相比，本发明提供的技术方案具有以下有益效果：
本发明提供的屏蔽式均压电路设有主电路和与主电路并联的辅助电路，且主电路包括晶闸管级等效电路、金属端子对地电容和饱和电抗器等效电路，辅助电路包括M个依次串联的π型电路，实现了换流阀中晶闸管的屏蔽式均压；
本发明提供的屏蔽式均压电路中的π型电路首尾端与主电路首末端相连，屏蔽罩电位点固定在各级电容上，可完全阻断主电路通过屏蔽罩对地杂散电容流入或流出的泄漏电流；
本发明提供的屏蔽式均压电路中主电路与屏蔽罩及组件电容之间没有任何电气连接，这样屏蔽罩对地的电容电流均由辅助电路的组件电容提供，不经过主电路，使得换流阀关键元部件处于完全的屏蔽状态，从而保证高频冲击下换流阀内晶闸管电压均匀分布，在换流阀低频域运行下，该组件电容相当于开路状态，保证了主电路安全 可靠运行；在高频冲击下，组件电容的电压分布可以用电容器的参数选择加以调节，保证各组件电容电压均压分布；
本发明可实现晶闸管电压不均匀度降低到0.17％，最大电压陡度达到6.8kV/μs；层间电压不均匀度达到0.8％，实现了串联晶闸管电压均衡分布，大幅度降低晶闸管由于电压分配不均导致损坏的风险；
本发明利用寄生电容或组件电容，降低杂散电容对换流阀中串联晶闸管电压分布的影响，且通过增大互电容并且屏蔽对地电容对主电路的泄流效应，使得对地电容与互电容之比趋近于零，实现晶闸管的电压均衡分布。
附图说明
图1是现有技术中ABB的公司换流阀均压电路原理图；
图2是现有技术中中国的换流阀均压电路原理图；
图3是现有技术中西门子的换流阀均压电路原理图；
图4是本发明实施例中屏蔽式均压电路原理图；
图5是本发明实施例中屏蔽式均压电路结构图。
具体实施方式
下面结合附图对本发明作进一步详细说明。
本发明实施例提供的零畸变度、高可靠性的应用于换流阀的屏蔽式均压电路主要采用换流阀冲击电压分析和电容屏蔽式均压这两种技术方案，下面对这两种技术方案分别作如下介绍：
(1)换流阀冲击电压分析：
换流阀中的晶闸管采用链式串联结构，其结构尺寸与高频冲击电压波长可以比拟，不能视为集中参数电路，需要采用传输线理论，建立分布参数模式分析波过程。当换流阀在高频电压激励下，饱和电抗器作为电感元件其阻抗较大，电流不能突变，故暂时不会有电流流过，相当于电感直接开路，这时换流阀可简化为T型电容链网络形式的晶闸管级等效电路。根据电路传输方程可求得换流阀各级晶闸管连接点的电压，其计算公式如下：
Figure PCTCN2017085347-appb-000001
其中，uk表示换流阀内第k级晶闸管节点电压，中间量
Figure PCTCN2017085347-appb-000002
Cg表示金属端子对地电容，Cs表示金属端子间互电容，则当Cg<<Cs，即b→0时，有：
Figure PCTCN2017085347-appb-000003
由上式可以得出，当对地电容与互电容之比趋近于零时，各节点电压分布均匀。
(2)电容屏蔽式均压：
辅助回路包括多个π型电路，π型电路首尾端与主电路首末端相连，屏蔽罩电位点固定在各级电容上，可完全阻断主电路通过屏蔽罩对地杂散电容流入或流出的泄漏电流。主电路与屏蔽罩及组件电容之间没有任何电气连接，通过绝缘槽梁保持主电路与屏蔽罩及组件电容之间的良好绝缘。这样屏蔽罩对地的电容电流均由辅助电路组件电容提供，不经过主电路，使得换流阀关键元部件处于完全的屏蔽状态，从而保证高频冲击下换流阀内晶闸管电压均匀分布。同时，在换流阀低频域运行下，该辅助电路阻抗较大相当于开路状态，保证了主电路安全可靠运行；在高频冲击下，组件电容的电压分布可以用电容器的参数选择加以调节，保证各组件电容电压均压分布。
基于以上换流阀冲击电压分析和电容屏蔽式均压这两种技术方案，本发明实施例提供应用于换流阀的屏蔽式均压电路，该屏蔽式均压电路的原理图如图4所示，图中Cs(in)和Cg(in)分别表示换流阀内金属端子间互电容和金属端子对地电容，Cs(out)和Cg(out)分别表示换流阀内屏蔽罩间互电容和屏蔽罩对地电容，Cm表示换流阀内元器件寄生电容或组件电容。由图4可得，Cg(out)与单阀主电路只是首尾相连，而中间杂散电容与主电路无电气连接关系，因此不会影响主电路各模块电压分布不均匀。
屏蔽式均压电路的具体结构如图5所示，其包括主电路和与主电路并联的辅助电路；以下分别对主电路和辅助电路进行详细说明。
上述的主电路包括晶闸管级等效电路、饱和电抗器等效电路和金属端子对地电容；
其中，晶闸管级等效电路设有2N个，其中N个晶闸管级等效电路依次串联形成第一晶闸管组件电路，其余N个晶闸管级等效电路依次串联形成第二晶闸管组件电路。
上述的第一晶闸管组件电路、第二晶闸管组件电路中的晶闸管级等效电路包括阻 尼电阻Rd、寄生电感LRd、阻尼电容Cd、晶闸管结电容Ci和散热器间互电容Cj，它们之间的串并联关系具体如下：
其中阻尼电阻Rd、寄生电感LRd和阻尼电容Cd串联，组成Rd-LRd-Cd支路；晶闸管结电容Ci和散热器间互电容Cj并联，组成Ci//Cj支路，上述的Rd-LRd-Cd支路与Ci//Cj支路并联。
晶闸管两端有两散热器压装，该部分电容由晶闸管结电容Ci和两端散热器间电容Cj构成；晶闸管两端通过并联阻容回路限制晶闸管关断过冲电压。
其中，饱和电抗器等效电路包括四个饱和电抗器等效电路，分别为第一饱和电抗器等效电路、第二饱和电抗器等效电路、第三饱和电抗器等效电路和第四饱和电抗器等效电路。
第一饱和电抗器等效电路、第二饱和电抗器等效电路、第三饱和电抗器等效电路和第四饱和电抗器等效电路均包括进出线母排间互电容Cb、铜损等效电阻RCu、空心电感Lleak、线匝和铁芯间互电容Cgr、涡流损耗等效电阻RFe、非线性电感电感Lm以及匝间电容Csl，它们之间的串并联关系如下：
铜损等效电阻RCu与空心电感Lleak串联，形成RCu-Lleak支路，该RCu-Lleak支路与线匝和铁芯间互电容Cgr并联，形成(RCu-Lleak)//Cgr支路，涡流损耗等效电阻RFe、非线性电感电感Lm以及匝间电容Csl并联，形成RFe//Lm//Csl支路，(RCu-Lleak)//Cgr支路与RFe//Lm//Csl支路串联后，与进出线母排间互电容Cb并联。
由于外围安装了屏蔽罩，所以上述第一饱和电抗器等效电路、第二饱和电抗器等效电路、第三饱和电抗器等效电路和第四饱和电抗器等效电路中的进出线母排间互电容Cb被屏蔽，所以可忽略不计。
上述的第一饱和电抗器等效电路、第二饱和电抗器等效电路、第三饱和电抗器等效电路、第四饱和电抗器等效电路、第一晶闸管组件电路、第二晶闸管组件电路之间的串联顺序为：
第一饱和电抗器等效电路、第一晶闸管组件电路、第二饱和电抗器等效电路、第三饱和电抗器等效电路、第二晶闸管组件电路和第四饱和电抗器等效电路依次串联。
其中，金属端子对地电容个数与晶闸管级等效电路相同，即金属端子对地电容同样设有2N个，金属端子对地电容一端连接在相邻两个晶闸管级等效电路之间，其另一端接地。
上述的辅助电路包括M个依次串联的π型电路，每个π型电路包括屏蔽罩对地 电容Cg1(out)、屏蔽罩对地电容Cg2(out)、屏蔽罩间互电容Cs和组件电容Cm，它们之间的串并联关系具体如下：
屏蔽罩间互电容Cs和组件电容Cm并联，组成Cs//Cm支路；屏蔽罩对地电容Cg1(out)与上述的Cs//Cm支路串联，形成Cg1(out)-(Cs//Cm)支路，该Cg1(out)-(Cs//Cm)支路一端接地，另一端连接屏蔽罩对地电容Cg2(out)的一端，屏蔽罩对地电容Cg2(out)的另一端接地。
采用屏蔽式均压电压电路的换流阀电压分布如表1所示，在不考虑各级晶闸管参数差异性的情况下，各级晶闸管电压分布趋势基本一致，最大值和最小值之间只差0.004kV，不均度为0.17％，大大降低了换流阀不均匀系数；晶闸管最大电压陡度为6.8kV/μs，大幅度提高了器件的可靠性；换流阀各层间之间电压分布很均压，不均压度为0.03％。
表1
Figure PCTCN2017085347-appb-000004
本发明技术与现有技术中的换流阀均压技术对比结果如下表2，在冲击电压下换流阀关键元器件晶闸管电压、最大电压陡度、电压不均匀度等各项重要指标均显著优于现有技术中换流阀电气均衡的效果。
表2
Figure PCTCN2017085347-appb-000005
经过以上表2的对比，可知本发明实施例提供的应用于换流阀的屏蔽式均压电路在工作的过程中，高频冲击下换流阀关键元器件晶闸管电压、最大电压陡度、电压不均匀度等各项重要指标均显著优于现有技术中的换流阀电气均衡效果。该电路可推广应用于模块化、规模化串联组件均压的设备中，如CVT、柔性直流换流阀、直流断路器等高压设备，市场应用前景广阔。
由于本发明实施例采用了冲击电压分析技术，所以换流阀主电路各元器件电压分布主要由对地杂散电容决定的，通过增大互电容并且屏蔽对地电容对主电路的泄流效应，使得对地电容与互电容之比趋近于零，实现晶闸管电压均衡分布；同时该技术可实现了换流阀复杂电路的简化，提高了高频冲击下晶闸管电压分布计算效率；
另外，本发明实施例提供的屏蔽式均压电路可利用寄生电容或组件电容，降低对地杂散电容对换流阀中串联晶闸管电压分布的影响，实现晶闸管电压均压分布；
采用本发明实施例提供的屏蔽式均压电路可以实现以下三种功能：1)屏蔽罩电位固定点与换流阀主电路没有电气连接关系；2)单阀首末端电位与首末端屏蔽罩有电位连接关系；3)屏蔽罩其他电位点可固定在换流阀内元器件或电容器组件上与换流阀主电路屏蔽隔离。
另外，本发明实施例还可实现晶闸管电压不均匀度降低到0.17％，最大电压陡度达到6.8kV/μs；层间电压不均匀度达到0.8％，实现了串联晶闸管电压均衡分布，大幅度降低晶闸管由于电压分配不均导致损坏的风险；
特高压换流阀已进入海外市场，未来可在巴西、加拿大、巴基斯坦等地区工程应用实现跨区域能源互联，国外ABB和西门子换流阀可能会应用此项技术，同时本技术方案可推广应用于元器件串级结构的高压电气设备均压，如CVT、避雷器、柔性直流换流阀和直流断路器等设备，市场应用前景广阔。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特 定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
最后应当说明的是：以上实施例仅用以说明本发明的技术方案而非对其限制，所属领域的普通技术人员参照上述实施例依然可以对本发明的具体实施方式进行修改或者等同替换，这些未脱离本发明精神和范围的任何修改或者等同替换，均在申请待批的本发明的权利要求保护范围之内。

Claims (10)

  1. 一种屏蔽式均压电路，其特征在于，所述屏蔽式均压电路包括主电路和与主电路并联的辅助电路；
    所述主电路包括晶闸管级等效电路、金属端子对地电容和饱和电抗器等效电路；
    所述辅助电路包括M个依次串联的π型电路。
  2. 根据权利要求1所述的屏蔽式均压电路，其特征在于，所述晶闸管级等效电路设有2N个，其中N个晶闸管级等效电路依次串联形成第一晶闸管组件电路，其余N个晶闸管级等效电路依次串联形成第二晶闸管组件电路。
  3. 根据权利要求2所述的屏蔽式均压电路，其特征在于，所述饱和电抗器等效电路包括第一饱和电抗器等效电路、第二饱和电抗器等效电路、第三饱和电抗器等效电路和第四饱和电抗器等效电路。
  4. 根据权利要求3所述的屏蔽式均压电路，其特征在于，所述第一饱和电抗器等效电路、第一晶闸管组件电路、第二饱和电抗器等效电路、第三饱和电抗器等效电路、第二晶闸管组件电路和第四饱和电抗器等效电路依次串联。
  5. 根据权利要求1或2所述的屏蔽式均压电路，其特征在于，所述晶闸管级等效电路包括阻尼电阻Rd、寄生电感LRd、阻尼电容Cd、晶闸管结电容Ci和散热器间互电容Cj；
    所述阻尼电阻Rd、寄生电感LRd和阻尼电容Cd串联，组成Rd-LRd-Cd支路；
    所述晶闸管结电容Ci和散热器间互电容Cj并联，组成Ci//Cj支路；
    所述Rd-LRd-Cd支路与Ci//Cj支路并联。
  6. 根据权利要求3或4所述的屏蔽式均压电路，其特征在于，所述第一饱和电抗器等效电路、第二饱和电抗器等效电路、第三饱和电抗器等效电路和第四饱和电抗器等效电路均包括进出线母排间互电容Cb、铜损等效电阻RCu、空心电感Lleak、线匝和铁芯间互电容Cgr、涡流损耗等效电阻RFe、非线性电感电感Lm以及匝间电容Csl。
  7. 根据权利要求6所述的屏蔽式均压电路，其特征在于，所述铜损等效电阻RCu与空心电感Lleak串联，形成RCu-Lleak支路；
    所述RCu-Lleak支路与线匝和铁芯间互电容Cgr并联，形成(RCu-Lleak)//Cgr支路；
    所述涡流损耗等效电阻RFe、非线性电感电感Lm以及匝间电容Csl并联，形成RFe//Lm//Csl支路；
    所述(RCu-Lleak)//Cgr支路与RFe//Lm//Csl支路串联后，与进出线母排间互电容Cb并联。
  8. 根据权利要求1所述的屏蔽式均压电路，其特征在于，所述π型电路包括屏蔽罩对地电容Cg1(out)、屏蔽罩对地电容Cg2(out)、屏蔽罩间互电容Cs和组件电容Cm。
  9. 根据权利要求8所述的屏蔽式均压电路，其特征在于，所述屏蔽罩间互电容Cs和组件电容Cm并联，组成Cs//Cm支路；
    所述屏蔽罩对地电容Cg1(out)与Cs//Cm支路串联，形成Cg1(out)-(Cs//Cm)支路，所述Cg1(out)-(Cs//Cm)支路一端接地，另一端连接屏蔽罩对地电容Cg2(out)的一端，所述屏蔽罩对地电容Cg2(out)的另一端接地。
  10. 根据权利要求1所述的屏蔽式均压电路，其特征在于，所述金属端子对地电容设有2N个，所述金属端子对地电容一端连接在相邻两个晶闸管级等效电路之间，其另一端接地。
PCT/CN2017/085347 2017-04-12 2017-06-12 一种屏蔽式均压电路 WO2018188166A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710236708.0A CN108712058B (zh) 2017-04-12 2017-04-12 一种屏蔽式均压电路
CN201710236708.0 2017-04-12

Publications (1)

Publication Number Publication Date
WO2018188166A1 true WO2018188166A1 (zh) 2018-10-18

Family

ID=63792204

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/085347 WO2018188166A1 (zh) 2017-04-12 2017-06-12 一种屏蔽式均压电路

Country Status (2)

Country Link
CN (1) CN108712058B (zh)
WO (1) WO2018188166A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111324971A (zh) * 2020-03-12 2020-06-23 全球能源互联网研究院有限公司 一种饱和电抗器铁心损耗优化方法
CN112269066A (zh) * 2020-09-14 2021-01-26 中国南方电网有限责任公司超高压输电公司广州局 一种换流阀均压电容电路核心器件不拆线参数测量方法
CN114552619A (zh) * 2022-01-18 2022-05-27 华中科技大学 一种串联二极管器件并联均压电路及参数设计方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19850840A1 (de) * 1998-11-04 2000-05-18 Siemens Ag Vorrichtung zur Symmetrierung der Spannungsverteilung bei einem Stromrichterventil mit einer Reihenschaltzahl Zwei und größer
CN101923593A (zh) * 2010-08-23 2010-12-22 中国电力科学研究院 一种换流阀用饱和电抗器在晶闸管阻态下的性能分析方法
CN101937484A (zh) * 2010-09-10 2011-01-05 中国电力科学研究院 一种换流阀用饱和电抗器的电气分析模型的建模方法
CN102723879A (zh) * 2012-06-15 2012-10-10 中电普瑞电力工程有限公司 一种换流阀组件均压电容设计方法
CN103048595A (zh) * 2012-12-13 2013-04-17 国网智能电网研究院 一种晶闸管开通应力测试方法和装置
CN106526446A (zh) * 2016-12-14 2017-03-22 云南电网有限责任公司电力科学研究院 一种高压直流换流阀组件中晶闸管级的试验电路

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101975892B (zh) * 2010-09-10 2014-02-12 中国电力科学研究院 一种换流阀用饱和电抗器的损耗计算方法
JP6394401B2 (ja) * 2015-01-14 2018-09-26 株式会社明電舎 ５レベル電力変換器および制御方法
CN106547990B (zh) * 2016-11-24 2019-06-18 华北电力大学 特高压直流换流阀塔阀层集成宽频等效电路模型的建模方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19850840A1 (de) * 1998-11-04 2000-05-18 Siemens Ag Vorrichtung zur Symmetrierung der Spannungsverteilung bei einem Stromrichterventil mit einer Reihenschaltzahl Zwei und größer
CN101923593A (zh) * 2010-08-23 2010-12-22 中国电力科学研究院 一种换流阀用饱和电抗器在晶闸管阻态下的性能分析方法
CN101937484A (zh) * 2010-09-10 2011-01-05 中国电力科学研究院 一种换流阀用饱和电抗器的电气分析模型的建模方法
CN102723879A (zh) * 2012-06-15 2012-10-10 中电普瑞电力工程有限公司 一种换流阀组件均压电容设计方法
CN103048595A (zh) * 2012-12-13 2013-04-17 国网智能电网研究院 一种晶闸管开通应力测试方法和装置
CN106526446A (zh) * 2016-12-14 2017-03-22 云南电网有限责任公司电力科学研究院 一种高压直流换流阀组件中晶闸管级的试验电路

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111324971A (zh) * 2020-03-12 2020-06-23 全球能源互联网研究院有限公司 一种饱和电抗器铁心损耗优化方法
CN111324971B (zh) * 2020-03-12 2023-05-30 全球能源互联网研究院有限公司 一种饱和电抗器铁心损耗优化方法
CN112269066A (zh) * 2020-09-14 2021-01-26 中国南方电网有限责任公司超高压输电公司广州局 一种换流阀均压电容电路核心器件不拆线参数测量方法
CN112269066B (zh) * 2020-09-14 2022-05-13 中国南方电网有限责任公司超高压输电公司广州局 一种换流阀均压电容电路核心器件不拆线参数测量方法
CN114552619A (zh) * 2022-01-18 2022-05-27 华中科技大学 一种串联二极管器件并联均压电路及参数设计方法
CN114552619B (zh) * 2022-01-18 2024-05-24 华中科技大学 一种串联二极管器件并联均压电路及参数设计方法

Also Published As

Publication number Publication date
CN108712058B (zh) 2021-10-01
CN108712058A (zh) 2018-10-26

Similar Documents

Publication Publication Date Title
Zhang et al. Common-mode EMI noise modeling and reduction with balance technique for three-level neutral point clamped topology
WO2018188166A1 (zh) 一种屏蔽式均压电路
Bucher Transient fault currents in HVDC VSC networks during pole-to-ground faults
Baitha et al. A comparative analysis of passive filters for power quality improvement
CN105470963B (zh) 一种有源电力滤波器及其控制方法
US9667063B1 (en) Harmonic filter for multipulse converter systems
Sekar et al. A review and study of harmonic mitigation techniques
Bagheri et al. A technique to mitigate zero-sequence harmonics in power distribution systems
Cui et al. High‐frequency resonance suppression of high‐speed railways in China
Heidary et al. Compound ferroresonance overvoltage and fault current limiter for power system protection
Abbas et al. Comprehensive parametric analysis of single tuned filter in distribution systems
CN108667006B (zh) 用于提升换流阀可靠性的单阀数字宽频故障风险分析方法
CN107679285B (zh) 特高压直流换流阀二端口电路
CN111446708A (zh) 一种分级可调串电阻抑制电网gic装置与方法
CN206497826U (zh) 一种能提高阻抗的变压器
Hu et al. Electric field optimization of cast resin dry-type transformer under lightning impulse
KR101146885B1 (ko) Ｈｖｄｃ 송전 시스템의 귀로 측의 절연 레벨 설계 방법
Shariatinasab et al. Harmonic analysis of power systems in order to network conversion
Liang et al. A new method highly integrated with converter transformer for harmonic suppression and reactive power compensation
Yang et al. Stress analysis and reliability calculation of saturable reactor of HVDC converter valve in HEMP environment
Zhang et al. HVDC converter transformer saturation in hybrid AC/DC system caused by coupled transmission lines
WO2020234044A1 (en) Dc current damper for a medium voltage or high voltage transformer
Saied Effect of transformer sizes and neutral treatments on the electromagnetic transients in transformer substations
US9973001B2 (en) Zero sequence, fifth harmonic filter for five-phase power distribution system
Chernyshov et al. Hybrid power quality conditioner for three-phase four-wire power systems

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17905799

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17905799

Country of ref document: EP

Kind code of ref document: A1