WO2018184292A1 - 保护电路 - Google Patents

保护电路 Download PDF

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Publication number
WO2018184292A1
WO2018184292A1 PCT/CN2017/088337 CN2017088337W WO2018184292A1 WO 2018184292 A1 WO2018184292 A1 WO 2018184292A1 CN 2017088337 W CN2017088337 W CN 2017088337W WO 2018184292 A1 WO2018184292 A1 WO 2018184292A1
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WO
WIPO (PCT)
Prior art keywords
circuit
input
power
output
power supply
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PCT/CN2017/088337
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English (en)
French (fr)
Inventor
易铭国
邓任钦
陈涛
Original Assignee
深圳市大疆创新科技有限公司
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Application filed by 深圳市大疆创新科技有限公司 filed Critical 深圳市大疆创新科技有限公司
Priority to CN201780060678.0A priority Critical patent/CN109792392B/zh
Publication of WO2018184292A1 publication Critical patent/WO2018184292A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/52—Circuit arrangements for protecting such amplifiers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/10—Current supply arrangements

Definitions

  • the present invention relates to the field of power failure protection, and more particularly to a protection circuit.
  • PA is the abbreviation of Power Amplifier, the Chinese name is power amplifier, referred to as "power amplifier”, which refers to the amplifier that can produce the maximum power output to drive a certain load under the given distortion rate.
  • the power of the power supply is converted to the current that varies according to the input signal by the current control action of the triode or the voltage control of the FET.
  • GaN gallium nitride
  • the application of power amplifiers is more and more extensive, and power amplifiers are more sensitive to power-down timing.
  • GaN gallium nitride
  • power-down GaN power amplifiers need to maintain their bases under negative voltage, the gates are turned off and then turned off to ensure GaN. The power amplifier is not damaged.
  • the base and drain of the GaN power amplifier are simultaneously powered down, the likelihood of damage to the GaN power amplifier is greatly increased.
  • the present invention provides a protection circuit.
  • a protection circuit for protecting a power amplifier including an input power source, a storage capacitor, a power supply output circuit, a power failure detection circuit, and a processor;
  • the input power source is connected to the storage capacitor, the storage capacitor is connected to the power supply output circuit, and the input power source is used for charging the storage capacitor and supplying power to the power supply output circuit, the energy storage
  • the capacitor is configured to supply power to the power supply output circuit after the input power source is powered off, and the voltage outputted by the power supply output circuit is respectively input to a base and a drain of the power amplifier;
  • the power failure detecting circuit is connected to the input power source, and after detecting that the input power source is powered down, sending power down information to the processor, and the processor outputs a base input for controlling the power amplifier. After the signal having a voltage less than or equal to zero is applied to the power supply circuit, a signal for controlling the drain input voltage of the power amplifier to be zero is output to the power supply output circuit.
  • the input power source includes two paths, wherein an output voltage of one path is greater than an output voltage of the other path;
  • the output terminals of the two input power sources are respectively connected to the storage capacitor through respective anti-reverse connection and reverse irrigation circuits.
  • an anti-surge circuit is further included, an input end of the anti-surge circuit is connected to an output end of the anti-reverse connection and a reverse circuit, and an output end of the anti-surge circuit is connected to the storage capacitor.
  • one of the two input power sources includes a battery
  • the other circuit includes an adapter
  • the voltage output by the adapter is greater than a voltage output by the battery
  • the power failure detecting circuit includes a voltage dividing circuit and a comparator, and the input power An output of the source is coupled to an input of the voltage divider circuit, an output of the voltage divider circuit is coupled to an input of the comparator, and an output of the comparator is coupled to an input of the processor.
  • the output of the comparator is further connected to a filter circuit.
  • the filter circuit is an RC filter circuit.
  • a linear power supply is further included, the input end of the linear power supply is connected to the storage capacitor, and the output end of the linear power supply is connected to the power supply end of the comparator.
  • the storage capacitor is an aluminum electrolytic capacitor.
  • the power supply output circuit is a BUCK-BOOST circuit.
  • the input power supply of the present invention supplies power to the power amplifier during normal operation, and charges the storage capacitor, thereby causing the input power to be powered down (normal power failure or abnormal power failure).
  • the power amplifier can be powered by the storage capacitor, so that the processor has enough time to process the power amplifier's power-down sequence (first controlling the power amplifier's base input voltage to be negative or zero, and the power amplifier's drain is powered down) to Ensure that the power amplifier is not damaged.
  • FIG. 1 is a schematic structural diagram of a protection circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of another protection circuit according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of still another protection circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of an unmanned aircraft interference grab according to an embodiment of the present invention.
  • 100 power amplifier; 200: protection circuit; C: storage capacitor;
  • first, second, third, etc. may be used to describe various information in the present invention, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other.
  • first information may also be referred to as the second information without departing from the scope of the invention.
  • second information may also be referred to as the first information.
  • word "if” as used herein may be interpreted as "when” or “when” or “in response to a determination.”
  • FIG. 1 is a schematic structural diagram of a protection circuit 200 for protecting a power amplifier 100, such as a GaN power amplifier 100, according to an embodiment of the present invention.
  • the protection circuit 200 includes an input power source 1, a storage capacitor C, a power supply output circuit 2, a power failure detection circuit 3, and a processor 4.
  • the input power source 1 is connected to the storage capacitor C, and the storage capacitor C is connected to the power supply output circuit 2, and the input power source 1 is used to charge the storage capacitor C and the power supply output circuit 2, the storage capacitor C is used to supply power to the power supply output circuit 2 after the input power source 1 is powered off, and the voltage outputted by the power supply output circuit 2 is input to the base of the power amplifier 100 and Drain.
  • the power failure detecting circuit 3 is connected to the input power source 1, and after detecting that the input power source 1 is powered down, sends power down information to the processor 4, and is output by the processor 4. After controlling the signal that the base input voltage of the power amplifier 100 is less than or equal to zero to the power supply circuit, a signal for controlling the drain input voltage of the power amplifier 100 to be zero is output to the power supply output circuit 2.
  • the input power source 1 of the embodiment supplies power to the power amplifier 100 during normal operation, and charges the storage capacitor C, so that after the input power source 1 is powered off (normal power failure or abnormal power failure), the power can be stored by the storage capacitor C.
  • the amplifier 100 is powered, so that the processor 4 has enough time to process the power-down sequence of the power amplifier 100 (first controlling the base input voltage of the power amplifier 100 to be negative or zero, and the drain of the power amplifier 100 is powered down again) to ensure The power amplifier 100 is not damaged.
  • the power failure of the input power source 1 may include normal power failure, such as the normal shutdown of the user, and the power failure of the input power source 1 may also include abnormal power failure.
  • the input power source 1 is connected in parallel with the storage capacitor C.
  • the two ends of the storage capacitor C are respectively connected to two input ends of the power supply output circuit 2, and the output of the power supply output circuit 2 is output. Voltages are input to the base and drain of the power amplifier 100, respectively.
  • An input end of the power failure detecting circuit 3 is connected to an output end of the input power source 1, an output end of the power failure detecting circuit 3 is connected to an input end of the processor 4, and an output end of the processor 4 is connected to the output end.
  • the power failure detecting circuit 3 detects that the input power source 1 is powered off, the voltage across the storage capacitor C is input to the input end of the power supply output circuit 2, and the processor 4 outputs the power output.
  • the circuit 2 inputs a signal whose voltage to the base is less than or equal to zero to the enable end of the power supply circuit, and then outputs the power supply output.
  • the circuit 2 inputs a signal having a voltage of zero to the drain to an enable terminal of the power supply circuit, thereby implementing timing control of power-down of the power amplifier 100, and protecting the power amplifier 100 from damage.
  • the power amplifier 100 is a GaN power amplifier 100.
  • the base input voltage of the GaN power amplifier 100 is first maintained at -5 V, and then the drain of the GaN power amplifier 100 is powered down to ensure that the GaN power amplifier 100 is not damaged.
  • the power failure detecting circuit 3 detects that the input power source 1 is powered off, the voltage across the storage capacitor C is input to the input end of the power supply output circuit 2, and the GaN power amplifier 100 is still working normally.
  • the power failure detecting circuit 3 sends a signal that the input power source 1 is powered down to the processor 4, and the processor 4 outputs a voltage such that the power supply output circuit 2 is input to the base voltage is -5V.
  • the signal is to the enable end of the power supply circuit. And, after the processor 4 outputs a signal that causes the power supply output circuit 2 to input the voltage of the base to be -5V to the enable end of the power supply circuit, the processor 4 further outputs the power supply.
  • the output circuit 2 inputs a signal of 0 V to the drain to the enable terminal of the power supply circuit, thereby controlling the power-down timing of the GaN power amplifier 100 after the input power source 1 is abnormally powered down, so that the GaN power amplifier 100 is After the input power supply 1 is powered down, it can be safely turned off.
  • the storage capacitor C is an aluminum electrolytic capacitor, which has large capacity and low cost.
  • the processor 4 can be an FPGA (Advanced RISC Machines, RISC Microprocessor 4), an AVR (RISC Reduced Instruction Set High Speed 8-bit Microcontroller), and the like, and can also be an ASIC (Application Specific Integrated Circuit). Circuit) chip.
  • FPGA Advanced RISC Machines, RISC Microprocessor 4
  • AVR RISC Reduced Instruction Set High Speed 8-bit Microcontroller
  • ASIC Application Specific Integrated Circuit
  • the input power source 1 includes two paths, wherein an output voltage of one path is greater than an output voltage of the other circuit; and output ends of the two input power sources 1 are respectively connected through respective anti-reverse connection and reverse circuit 5 The storage capacitor C.
  • the anti-reverse and back-up circuit 5 is configured to select one of the two input power sources 1 to charge the subsequent storage capacitor C and supply power to the power supply output circuit 2. In this embodiment, the anti-reverse and reverse circuit 5 is selected. One of the two input power sources 1 having a larger output voltage charges the subsequent storage capacitor C and supplies power to the power supply output circuit 2.
  • the anti-reverse connection and back-up circuit 5 can also prevent the internal and external voltage difference of the input power source 1 from causing current backflow to damage the power supply.
  • the anti-reverse connection and reverse circuit 5 can cut off the input power supply 1 and the system. The path protects the energy of the storage capacitor C such that the processor 4 has sufficient time to process the power down sequence of the power amplifier 100.
  • dual power supply also makes the system more stable.
  • one of the two input power sources 1 includes a battery 11 and the other circuit includes an adapter 12 that outputs a voltage greater than a voltage output by the battery 11.
  • the storage capacitor C is charged by the adapter 12 and the power supply output circuit 2 is powered; when one of the two input power sources 1 is powered off, the other circuit is powered off (ie, the power is not turned off)
  • One input power source 1) charges the storage capacitor C and supplies power to the power supply output circuit 2.
  • the output voltage of the battery 11 can also be set to be greater than the output voltage of the adapter 12, so that when both the battery 11 and the adapter 12 are working normally, the storage capacitor C is charged by the battery 11 and the power supply output circuit 2 is powered. .
  • the battery 11 is a battery 11 to facilitate recycling and save resources.
  • the adapter 12 cooperates with the mains to output a voltage.
  • a slow start is provided for charging the storage capacitor C to prevent input power. 1
  • the output voltage exceeds the normal voltage in a short time, causing a spark when the user hot plugs, causing damage to the entire protection circuit 200.
  • the protection circuit 200 further includes an anti-surge circuit 6, the input of the anti-surge circuit 6.
  • the output terminal of the anti-reverse and reverse circuit 5 is connected to the end, and the output of the anti-surge circuit 6 is connected to the storage capacitor C.
  • the input power source 1 may also include three channels or more, and each input power source 1 is connected to the input end of the anti-surge circuit 6 via a respective anti-reverse connection and back-up circuit 5, and then the output of the anti-surge circuit 6.
  • the storage capacitor C is connected to the end.
  • each input power source 1 is connected to a power-down detection circuit 3, so as to know the power-down condition of each input power source 1 in time.
  • the detection point of the power failure detecting circuit 3 is as close as possible to the input interface of the input power source 1, so that the power failure detecting circuit 3 can detect the power failure at the fastest time, and notify the processor 4 in time.
  • the power failure detecting circuit 3 includes a voltage dividing circuit 31 and a comparator 32.
  • the output end of the input power source 1 is connected to the input end of the voltage dividing circuit 31, and the output terminal of the voltage dividing circuit 31 is connected.
  • the output of the comparator 32 is coupled to the input of the processor 4.
  • the voltage dividing circuit 31 can be selected as the voltage dividing circuit 31 which is conventional in the art.
  • those skilled in the art can select the resistance of the voltage dividing resistor according to the common sense of the technology, so that when the input power source 1 is powered down, the voltage input from the voltage dividing circuit 31 to the comparator 32 enables the comparator 32 to output the power-down information to the processor. 4, thereby recognizing that the input power source 1 is powered down.
  • the comparator 32 outputs a high-low level signal to the processor 4 in a positive feedback connection manner, that is, the power-down information sent by the comparator 32 to the processor 4 may be a high level or a low level.
  • the comparator 32 when the power failure detecting circuit 3 detects that the input power source 1 is powered down, The comparator 32 outputs a low level signal to the processor 4, that is, the processor 4 receives the power down information input by the comparator 32 to indicate that the input power source 1 is powered down.
  • the comparator 32 outputs a high level signal to the processor 4, that is, the processor 4 receives the input from the comparator 32.
  • a high level of electrical information indicates that the input power supply 1 is powered down.
  • the comparator 32 When the input power source 1 includes two paths, and the power-down detecting circuit 3 detects that the input power source 1 is powered down, the comparator 32 outputs a low-level signal to the processor 4 as an example to further explain the operation of the processor 4.
  • the processor 4 When the processor 4 receives the signals output by the two comparators 32 is low level, the output causes the power supply output circuit 2 to input a signal whose voltage to the base is less than or equal to zero to the enable end of the power supply circuit. And outputting a signal that causes the voltage input to the drain of the power supply output circuit 2 to be zero to an enable end of the power supply circuit to complete power-off processing of the power amplifier 100, thereby causing the power amplifier 100 The drain is powered down with its base input voltage being negative or zero, thereby protecting the power amplifier 100.
  • the power supply output circuit 2 is a BUCK-BOOST (buck-boost converter) circuit.
  • BUCK-BOOST buck-boost converter
  • the output of the comparator 32 is also connected to the filter circuit.
  • the filter circuit is an RC filter circuit.
  • the filtering time of the filtering circuit is 10 us (unit: microsecond).
  • the filter circuit can also be a grounded capacitor, and the output of the comparator 32 is grounded through a capacitor to prevent false alarms caused by jitter.
  • the comparator 32 of this embodiment needs to perform a hysteresis design to prevent the system from oscillating when the output voltage of the input power source 1 is changed within the hysteresis range.
  • the comparator 32 has a hysteresis of 2V.
  • the comparator 32 outputs a low level until the processor 4 represents the input power source 1 is powered down, and the voltage output by the voltage dividing circuit 31 is the voltage output by the input power source 1. 1/2, the voltage output from the voltage dividing circuit 31 is directly applied to the non-inverting input terminal of the comparator 32, and the negative phase input terminal of the comparator 32 is connected to the reference voltage.
  • the reference voltage is 6V.
  • the comparator 32 is designed to have a 2V hysteresis design, when the output voltage of the input power source 1 is ⁇ (12 + 2) V, the representative system can operate normally, and the reference voltage is 7V.
  • the protection circuit 200 further includes a linear power supply (not shown).
  • the input end of the linear power supply is connected to the storage capacitor C, and the output end of the linear power supply is connected to the power supply end of the comparator 32.
  • the storage capacitor C is also used after the input power source 1 is powered off.
  • the linear power supply is powered so that the power supply of the comparator 32 is maintained for a time not less than the power-off completion time of the power amplifier 100.
  • the linear power supply includes a TL431, and an input end of the TL431 is connected to the storage Capacitor C, the output end of the TL431 is connected to the power supply end of the comparator 32.
  • protection circuit 200 described above can be applied to a device including the power amplifier 100 such as a drone jammer, a base station, or a radar.
  • protection circuit 200 is further described by taking the protection circuit 200 as an unmanned aerial jammer as an example. Said
  • the UAV jammer is a UAV jammer, which includes a power amplifier 100 and a protection circuit 200 for protecting the power amplifier 100.
  • the UAV interference is used to transmit an interference signal to interfere with the normal operation of the UAV, forcing the UAV to return or land, thereby protecting the security sensitive area.
  • UAV interference There are many application scenarios for UAV interference, such as large-scale events, political meetings, security work, etc., which require high reliability. However, it is difficult to guarantee that there will be no sudden power failure. In addition, the price of drone interference is higher, the maintenance cost is higher, and the MTBF (mean time between failures) of the system is high.
  • the embodiment of the present invention improves the reliability of the system and reduces the failure rate of the product by providing the protection circuit 200 for protecting the power amplifier 100.
  • UAV of the present embodiment can be described as a multi-rotor drone, such description is not limiting, and those skilled in the art should understand that any type of drone is applicable.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

一种保护电路，包括输入电源(1)、储能电容(C)、供电输出电路(2)、掉电检测电路(3)以及处理器(4)；输入电源(1)与储能电容(C)相连，储能电容(C)连接供电输出电路(2)，输入电源(1)用于对储能电容(C)充电并对供电输出电路(2)供电，储能电容(C)用于在输入电源(1)掉电后对供电输出电路(2)供电，供电输出电路(2)输出的电压分别输入至功率放大器(100)的基极和漏极；掉电检测电路(3)连接输入电源(1)，并在检测到输入电源(1)掉电后，将掉电信息发送至处理器(4)，由处理器(4)输出控制功率放大器(100)的基极输入电压小于或者等于零的信号至供电电路后，再输出控制功率放大器(100)的漏极输入电压为零的信号至供电输出电路(2)，以保护功率放大器(100)在掉电后不受损坏。

Description

保护电路 技术领域
本发明涉及掉电保护领域，尤其涉及一种保护电路。
背景技术
PA是Power Amplifier的简称，中文名称为功率放大器，简称“功放”，指在给定失真率条件下，能产生最大功率输出以驱动某一负载的放大器。利用三极管的电流控制作用或场效应管的电压控制作用将电源的功率转换为按照输入信号变化的电流。
目前，功率放大器的应用越来越广泛，而功率放大器对掉电时序较为敏感。例如，GaN(氮化镓)功率放大器，其应用越来越成熟，GaN功率放大器在掉电时，需要将其基极维持在负压后，漏极(gate)再下电关闭，才能保证GaN功率放大器不受损坏。但是，如果GaN功率放大器的基极和漏极同时下电，GaN功率放大器受损的可能性则会大大增加。
发明内容
本发明提供一种保护电路。
具体地，本发明是通过如下技术方案实现的：
一种保护电路，用于保护功率放大器，包括输入电源、储能电容、供电输出电路、掉电检测电路以及处理器；
所述输入电源与所述储能电容相连，所述储能电容连接所述供电输出电路，所述输入电源用于对所述储能电容充电并对所述供电输出电路供电，所述储能电容用于在所述输入电源掉电后对所述供电输出电路供电，所述供电输出电路输出的电压分别输入至所述功率放大器的基极和漏极；
所述掉电检测电路连接所述输入电源，并在检测到所述输入电源掉电后，将掉电信息发送至所述处理器，由所述处理器输出控制所述功率放大器的基极输入电压小于或者等于零的信号至所述供电电路后，再输出控制所述功率放大器的漏极输入电压为零的信号至所述供电输出电路。
可选地，所述输入电源包括两路，其中一路的输出电压大于另一路的输出电压；
两路输入电源的输出端分别经各自的防反接和倒灌电路连接所述储能电容。
可选地，还包括防浪涌电路，所述防浪涌电路的输入端连接所述防反接和倒灌电路的输出端，且防浪涌电路的输出端连接所述储能电容。
可选地，所述两路输入电源中的一路包括电池，另一路包括适配器，所述适配器输出的电压大于所述电池输出的电压。
可选地，所述掉电检测电路包括分压电路和比较器，所述输入电 源的输出端连接所述分压电路的输入端，所述分压电路的输出端连接所述比较器的输入端，所述比较器的输出端连接所述处理器的输入端。
可选地，所述比较器的输出端还连接滤波电路。
可选地，所述滤波电路为RC滤波电路。
可选地，还包括线性电源，所述线性电源的输入端连接所述储能电容，所述线性电源的输出端连接所述比较器的供电端。
可选地，所述储能电容为铝电解电容。
可选地，所述供电输出电路为BUCK-BOOST电路。
由以上本发明实施例提供的技术方案可见，本发明的输入电源在正常工作时对功率放大器供电，并对储能电容充电，从而使得输入电源掉电(正常掉电或者异常掉电)后，可由储能电容对功率放大器供电，使得处理器有足够的时间处理功率放大器的掉电时序(先控制功率放大器的基极输入电压为负压或者零，功率放大器的漏极再下电)，以保证功率放大器不受损。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本发明。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例示出的一种保护电路的结构示意图；
图2是本发明实施例示出的另一种保护电路的结构示意图；
图3是本发明实施例示出的又一种保护电路的结构示意图；
图4是本发明实施例示出的一种无人机干扰抢的结构示意图。
附图标记：
100：功率放大器；200：保护电路；C：储能电容；
1：输入电源；11：电池；12：适配器；
2：供电输出电路；
3：掉电检测电路；31：分压电路；32：比较器；
4：处理器；
5：防反接和倒灌电路；
6：防浪涌电路。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本发明相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本发明的一些方面相一致的装置和方法的例子。
在本发明使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明。在本发明和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其 他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
应当理解，尽管在本发明可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本发明范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语“如果”可以被解释成为“在……时”或“当……时”或“响应于确定”。
下面结合附图，对本发明的保护电路200进行详细说明。在不冲突的情况下，下述的实施例及实施方式中的特征可以相互组合。
图1所示，本发明实施例提出的一种保护电路200的结构示意图，该保护电路200用于保护功率放大器100，例如，GaN功率放大器100。
参见图1，所述保护电路200包括输入电源1、储能电容C、供电输出电路2、掉电检测电路3以及处理器4。所述输入电源1与所述储能电容C相连，所述储能电容C连接所述供电输出电路2，所述输入电源1用于对所述储能电容C充电并对所述供电输出电路2供电，所述储能电容C用于在所述输入电源1掉电后对所述供电输出电路2供电，所述供电输出电路2输出的电压分别输入至所述功率放大器100的基极和漏极。
所述掉电检测电路3连接所述输入电源1，并在检测到所述输入电源1掉电后，将掉电信息发送至所述处理器4，由所述处理器4输 出控制所述功率放大器100的基极输入电压小于或者等于零的信号至所述供电电路后，再输出控制所述功率放大器100的漏极输入电压为零的信号至所述供电输出电路2。
本实施例的输入电源1在正常工作时对功率放大器100供电，并对储能电容C充电，从而使得输入电源1掉电(正常掉电或者异常掉电)后，可由储能电容C对功率放大器100供电，使得处理器4有足够的时间处理功率放大器100的掉电时序(先控制功率放大器100的基极输入电压为负压或者零，功率放大器100的漏极再下电)，以保证功率放大器100不受损。需要说明的是，本发明中，输入电源1掉电可包括正常掉电，如用户正常关机，输入电源1掉电还可包括异常掉电。
又参见图1，所述输入电源1与所述储能电容C并联连接，所述储能电容C的两端分别连接所述供电输出电路2的两输入端，所述供电输出电路2输出的电压分别输入至所述功率放大器100的基极和漏极。
所述掉电检测电路3的输入端连接所述输入电源1的输出端，所述掉电检测电路3的输出端连接所述处理器4的输入端，所述处理器4的输出端连接所述供电输出电路2的使能端。
其中，所述掉电检测电路3检测到输入电源1掉电后，所述储能电容C两端的电压输入至所述供电输出电路2的输入端，所述处理器4输出使得所述供电输出电路2输入至所述基极的电压小于或者等于零的信号至所述供电电路的使能端后，再输出使得所述供电输出 电路2输入至所述漏极的电压为零的信号至所述供电电路的使能端，从而实现对功率放大器100掉电的时序控制，保护功率放大器100不受损。
在一实施例中，所述功率放大器100为GaN功率放大器100。在输入电源1掉电时，先将GaN功率放大器100的基极输入电压维持在-5V，再使得GaN功率放大器100的漏极下电，才能保证GaN功率放大器100不受损。本实施例中，所述掉电检测电路3检测到输入电源1掉电后，所述储能电容C两端的电压输入至所述供电输出电路2的输入端，维持GaN功率放大器100仍然正常工作，同时，掉电检测电路3将所述输入电源1掉电的信号发送至所述处理器4，处理器4则会输出使得所述供电输出电路2输入至所述基极的电压为-5V的信号至所述供电电路的使能端。并且，在处理器4输出使得所述供电输出电路2输入至所述基极的电压为-5V的信号至所述供电电路的使能端之后，所述处理器4还会输出使得所述供电输出电路2输入至所述漏极的电压为0V的信号至所述供电电路的使能端，从而控制GaN功率放大器100在输入电源1异常掉电后的掉电时序，使得GaN功率放大器100在输入电源1掉电后，能够安全关闭。
可选地，所述储能电容C为铝电解电容，其容量大，成本低。
可选地，所述处理器4可为ARM(Advanced RISC Machines，RISC微处理器4)、AVR(RISC精简指令集高速8位单片机)等单片机，还可为ASIC(Application Specific Integrated Circuit，专用集成电路)芯片。
参见图2，本实施例中，所述输入电源1包括两路，其中一路的输出电压大于另一路的输出电压；两路输入电源1的输出端分别经各自的防反接和倒灌电路5连接所述储能电容C。所述防反接和倒灌电路5用于选择两路输入电源1中的一路对后续储能电容C充电并对供电输出电路2供电，本实施例中，所述防反接和倒灌电路5选择两路输入电源1中输出电压较大的一路对后续储能电容C充电并对供电输出电路2供电。同时，防反接和倒灌电路5还能够防止输入电源1内外压差导致电流倒灌而损坏电源，另外，在输入电源1异常短路时，防反接和倒灌电路5能够截断输入电源1与系统的通路，保护储能电容C的能量，使得处理器4有足够的时间处理功率放大器100的掉电时序。并且，双电源供电也使得系统的稳定性更强。
可选地，两路输入电源1中的一路包括电池11，另一路包括适配器12，所述适配器12输出的电压大于所述电池11输出的电压。当电池11和适配器12均正常工作时，由适配器12对储能电容C充电并对供电输出电路2供电；当两路输入电源1中的一路断电后，则由另一路(即未断电的一路输入电源1)对储能电容C充电并对供电输出电路2供电。当然，也可将所述电池11的输出电压设置成大于所述适配器12的输出电压，使得电池11和适配器12均正常工作时，由电池11对储能电容C充电并对供电输出电路2供电。
可选地，所述电池11为蓄电池11，便于循环利用，节省资源。可选地，所述适配器12与市电配合，从而输出电压。
又参见图2，为对储能电容C的充电提供缓启动，防止输入电源 1输出的电压在短时间内超出正常电压而导致用户热拔插时出现火花，造成整个保护电路200损坏，所述保护电路200还包括防浪涌电路6，所述防浪涌电路6的输入端连接所述防反接和倒灌电路5的输出端，且防浪涌电路6的输出端连接所述储能电容C。
另外，所述输入电源1也可包括三路及以上，每路输入电源1均经各自的防反接和倒灌电路5连接防浪涌电路6的输入端，再由防浪涌电路6的输出端连接所述储能电容C。
本实施例中，每路输入电源1的输出端均连接一路掉电检测电路3，以便及时获知每路输入电源1的掉电情况。其中，掉电检测电路3的检测点是尽量靠近输入电源1的输入接口的，以使得掉电检测电路3能够在最快的时间检测到掉电，并及时通知处理器4。
参见图3，所述掉电检测电路3包括分压电路31和比较器32，所述输入电源1的输出端连接所述分压电路31的输入端，所述分压电路31的输出端连接所述比较器32的输入端，所述比较器32的输出端连接所述处理器4的输入端。
其中，分压电路31可选择为本领域常规的分压电路31。另外，本领域技术人员可根据技术常识选取分压电阻的阻值，使得在输入电源1掉电时，分压电路31输入至比较器32的电压使得比较器32能够输出掉电信息至处理器4，从而识别出输入电源1掉电。
可选地，所述比较器32以正反馈连接方式输出高低电平信号至处理器4，即比较器32发送至处理器4的掉电信息可为高电平或低电平。在一些例子中，当掉电检测电路3检测到输入电源1掉电时， 所述比较器32输出低电平信号至处理器4，即处理器4接收到比较器32输入的掉电信息为低电平表示输入电源1掉电。当然，在其他一些例子中，当掉电检测电路3检测到输入电源1掉电时，所述比较器32输出高电平信号至处理器4，即处理器4接收到比较器32输入的掉电信息为高电平表示输入电源1掉电。
以输入电源1包括两路，并且掉电检测电路3检测到输入电源1掉电时，所述比较器32输出低电平信号至处理器4为例进一步说明处理器4的操作。
当处理器4接收到两个比较器32输出的信号均为低电平时，输出使得所述供电输出电路2输入至所述基极的电压小于或者等于零的信号至所述供电电路的使能端，再输出使得所述供电输出电路2输入至所述漏极的电压为零的信号至所述供电电路的使能端，以完成对功率放大器100的下电处理，从而使得所述功率放大器100的漏极下电是在其基极输入电压为负或者零的情况下进行，从而对功率放大器100进行保护。
本实施例中，所述供电输出电路2为BUCK-BOOST(即降压-升压变换器)电路。通过BUCK-BOOST拓扑转换，在接收到处理器4发送的控制基极的电压小于或者等于零的信号后，将输入至功率放大器100的基极的电压转换为负压或者零，并在接收到处理器4发送的控制漏极电压为零的信号后，将输入至功率放大器100的漏极的电压转换为零，以顺利完成功率放大器100的掉电，防止功率放大器100受损。
另外，为避免由于分压电路31与输入电源1的连接处抖动造成比较器32对处理器4的误报，所述比较器32的输出端还连接滤波电路。可选地，所述滤波电路为RC滤波电路。可选地，所述滤波电路的滤波时间为10us(单位：微秒)。当然，所述滤波电路也可以为接地的电容，所述比较器32的输出端通过电容接地，从而防止抖动造成的误报。
本实施例的比较器32需要进行回差设计，防止输入电源1的输出电压在回差范围内变化时，导致系统震荡。可选地，所述比较器32的回差为2V。例如，当输入电源1的输出电压≥12V时，系统能够正常工作，比较器32输出低电平至处理器4代表输入电源1掉电，分压电路31输出的电压为输入电源1输出的电压的1/2，分压电路31输出的电压直接加载在比较器32的正相输入端，所述比较器32的负相输入端连接基准电压。若不对比较器32做回差设计，所述基准电压为6V即可。对比较器32做2V的回差设计后，输入电源1的输出电压≥(12+2)V时，代表系统能够正常工作，所述基准电压为7V。
本实施例中，所述保护电路200还包括线性电源(图中未显示)。所述线性电源的输入端连接所述储能电容C，所述线性电源的输出端连接所述比较器32的供电端，所述储能电容C还用于在所述输入电源1掉电后，对所述线性电源进行供电，以使得比较器32的供电电源的保持时间不小于功率放大器100的下电完成时间。另外，所述输入电源1正常工作时，由所述输入电源1对所述线性电源进行供电。可选地，所述线性电源包括TL431，所述TL431的输入端连接所述储 能电容C，所述TL431的输出端连接所述比较器32的供电端。
需要说明的是，上述保护电路200可应用于无人机干扰器、基站、雷达等具备功率放大器100的设备中。
本实施例以保护电路200应用在无人机干扰器为例进一步进行阐述。所述
参见图4，所述无人机干扰器为无人机干扰抢，其包括功率放大器100和保护电路200，所述保护电路200用于保护所述功率放大器100。
所述无人机干扰抢用于发射干扰信号，以干扰无人机的正常工作，迫使无人机返航或者降落，从而对安防敏感区域进行保护。
无人机干扰抢的应用场景多种多样，例如，大型活动、政治会议、安保工作等，这些场合均需要很高的可靠性。然而，无人机干扰抢很难保证不会出现突然掉电的情况。另外，无人机干扰抢的价格较高，维修成本较高，系统的MTBF(mean time between failures,平均故障间隔)要求高。本发明实施例通过设置用于保护所述功率放大器100的保护电路200，从而提高系统的可靠性，减小产品的失效率。
需要说明的是，尽管本实施例的无人飞行器可被描述为多旋翼无人机，然而这样的描述并不是限制，本领域技术人员应该了解，任何类型的无人机都适用。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明保护的范围之内。

Claims (10)

  1. 一种保护电路，用于保护功率放大器，其特征在于，包括输入电源、储能电容、供电输出电路、掉电检测电路以及处理器；
    所述输入电源与所述储能电容相连，所述储能电容连接所述供电输出电路，所述输入电源用于对所述储能电容充电并对所述供电输出电路供电，所述储能电容用于在所述输入电源掉电后对所述供电输出电路供电，所述供电输出电路输出的电压分别输入至所述功率放大器的基极和漏极；
    所述掉电检测电路连接所述输入电源，并在检测到所述输入电源掉电后，将掉电信息发送至所述处理器，由所述处理器输出控制所述功率放大器的基极输入电压小于或者等于零的信号至所述供电电路后，再输出控制所述功率放大器的漏极输入电压为零的信号至所述供电输出电路。
  2. 如权利要求1所述的保护电路，其特征在于，所述输入电源包括两路，其中一路的输出电压大于另一路的输出电压；
    两路输入电源的输出端分别经各自的防反接和倒灌电路连接所述储能电容。
  3. 如权利要求2所述的保护电路，其特征在于，还包括防浪涌电路，所述防浪涌电路的输入端连接所述防反接和倒灌电路的输出端，且防浪涌电路的输出端连接所述储能电容。
  4. 如权利要求2所述的保护电路，其特征在于，所述两路输入 电源中的一路包括电池，另一路包括适配器，所述适配器输出的电压大于所述电池输出的电压。
  5. 如权利要求1所述的保护电路，其特征在于，所述掉电检测电路包括分压电路和比较器，所述输入电源的输出端连接所述分压电路的输入端，所述分压电路的输出端连接所述比较器的输入端，所述比较器的输出端连接所述处理器的输入端。
  6. 如权利要求5所述的保护电路，其特征在于，所述比较器的输出端还连接滤波电路。
  7. 如权利要求6所述的保护电路，其特征在于，所述滤波电路为RC滤波电路。
  8. 如权利要求5所述的保护电路，其特征在于，还包括线性电源，所述线性电源的输入端连接所述储能电容，所述线性电源的输出端连接所述比较器的供电端。
  9. 如权利要求1所述的保护电路，其特征在于，所述储能电容为铝电解电容。
  10. 如权利要求1所述的保护电路，其特征在于，所述供电输出电路为BUCK-BOOST电路。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN207117578U (zh) * 2017-04-07 2018-03-16 深圳市大疆创新科技有限公司 保护电路
CN109615833A (zh) * 2019-01-15 2019-04-12 安徽皖兴通信息技术有限公司 一种双电源供电设备掉电告警的方法
CN110086148A (zh) * 2019-05-31 2019-08-02 深圳市道通智能航空技术有限公司 一种电源保护电路及电源
WO2021102901A1 (zh) * 2019-11-29 2021-06-03 深圳市大疆创新科技有限公司 电池检测电路、方法及电池、电子设备、存储介质
CN113741252A (zh) * 2021-08-19 2021-12-03 武汉光迅科技股份有限公司 一种多电源系统的下电时序控制电路

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060022648A1 (en) * 2004-08-02 2006-02-02 Green Power Technologies Ltd. Method and control circuitry for improved-performance switch-mode converters
CN102412815A (zh) * 2011-06-28 2012-04-11 中兴通讯股份有限公司 一种控制功放上下电的方法和系统
CN102684615A (zh) * 2012-04-23 2012-09-19 烽火通信科技股份有限公司 实现功率放大器理想上下电时序的驱动装置
CN103368750A (zh) * 2013-06-24 2013-10-23 华为技术有限公司 一种电源时序电路及供电方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201336019Y (zh) * 2009-01-22 2009-10-28 无锡市中远工业自动化有限公司 可编程序控制器的掉电保护电路
CN102684240B (zh) * 2011-03-17 2015-01-28 上海中兴派能能源科技有限公司 应用于锂离子电池及锂离子电池组的管理系统
US9716477B2 (en) * 2012-12-28 2017-07-25 Peregrine Semiconductor Corporation Bias control for stacked transistor configuration
CN103280968B (zh) * 2013-05-09 2015-10-28 中国电子科技集团公司第二十四研究所 脉冲电源的时序控制电路
CN203572867U (zh) * 2013-11-25 2014-04-30 深圳市金威源科技股份有限公司 一种输入电源掉电检测电路
CN105048969B (zh) * 2015-07-15 2018-01-09 京信通信系统（中国）有限公司 GaN HEMT偏置电路
CN207117578U (zh) * 2017-04-07 2018-03-16 深圳市大疆创新科技有限公司 保护电路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060022648A1 (en) * 2004-08-02 2006-02-02 Green Power Technologies Ltd. Method and control circuitry for improved-performance switch-mode converters
CN102412815A (zh) * 2011-06-28 2012-04-11 中兴通讯股份有限公司 一种控制功放上下电的方法和系统
CN102684615A (zh) * 2012-04-23 2012-09-19 烽火通信科技股份有限公司 实现功率放大器理想上下电时序的驱动装置
CN103368750A (zh) * 2013-06-24 2013-10-23 华为技术有限公司 一种电源时序电路及供电方法

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