WO2018182697A1

WO2018182697A1 - Magnetic tunnel junction (mtj) devices with a sidewall passivation layer and methods to for the same

Info

Publication number: WO2018182697A1
Application number: PCT/US2017/025436
Authority: WO
Inventors: Sarah ATANASOV; Satyarth Suri; Kevin P. O'brien; Kaan OGUZ; Brian S. Doyle; Mark L. Doczy; Charles C. Kuo
Original assignee: Intel Corporation
Priority date: 2017-03-31
Filing date: 2017-03-31
Publication date: 2018-10-04

Abstract

A magnetic tunnel junction (MTJ) device, includes an MTJ material layer stack having an uppermost surface, a lowermost surface, and a sidewall ending from the uppermost surface to the lowermost surface. The MTJ material stack includes a fixed magnet, a tunnel barrier disposed above the fixed magnet, a free magnet disposed on the tunnel barrier and a passivation layer disposed laterally adjacent to the sidewall of the MTJ material stack. The passivation layer extends only partially along the sidewall between the uppermost surface of the MTJ material layer stack and the lowermost surface of the MTJ material stack.

Description

MAGNETIC TUNNEL JUNCTION (MTJ) DEVICES WITH A SIDEWALL PASSIVATION LAYER AND

METHODS TO FOR THE SAME

TECHNICAL FIELD

Embodiments of the invention are in the field of integrated circuit fabrication and, in particular, related to magnetic tunnel junction (MTJ) devices with a sidewall passivation layer and methods to form the same.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

Non-volatile embedded memory with MTJ devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. However, the technical challenges of patterning an MTJ stack to form functional MTJ devices present formidable roadblocks to commercialization of this technology today. Specifically, challenges of patterning an MTJ stack involves etching a large number of layers of magnetic and non-magnetic materials that do not form volatile byproducts. During the etching process the non-volatile etch byproducts are re-sputtered back onto exposed sidewalls of an already patterned portion of the MTJ stack. These non-volatile etch byproducts are predominantly metallic and provide a current path that is alternative to the current path through the MTJ device. This lead to potential shorting and renders the MTJ device functionless. Removal of the etch byproducts is cumbersome and can lead to damage of the MTJ device.

As such, significant innovations are still needed in the areas of MTJ stack patterning process that overcome limitations in etch by product removal.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1A illustrates a cross-sectional view of a magnetic tunnel junction (MTJ) device including a passivation layer disposed on sidewalls of the MTJ device, in accordance with an embodiment of the present invention.

Figure IB illustrates a plan view of Figure 1A.

Figure 1C illustrates a cross-sectional view of a magnetic tunnel junction (MTJ) device including a passivation layer disposed on a sidewall of the MTJ device, in accordance with an embodiment of the present invention.

Figure ID illustrates a cross sectional view of a synthetic antiferromagnetic layer, in accordance with an embodiment of the present invention.

Figure IE illustrates a cross-sectional view of a magnetic tunnel junction (MTJ) device including a passivation layer disposed on a sidewall of the MTJ device, in accordance with an embodiment of the present invention.

Figure IF illustrates a cross-sectional view of a magnetic tunnel junction (MTJ) device including a passivation layer disposed on a sidewall of the MTJ device, in accordance with an embodiment of the present invention.

Figure 1G illustrates a cross-sectional view of a magnetic tunnel junction (MTJ) device including a first passivation layer disposed on a sidewall of a first layer of the MTJ device and a second passivation disposed on a sidewall of a second layer of the MTJ device, in accordance with an embodiment of the present invention.

Figure 1H illustrates a cross-sectional view of a magnetic tunnel junction (MTJ) device including a passivation layer disposed on sidewalls of the MTJ device, and a dielectric spacer disposed on sidewalls of the passivation layer and on sidewalls of the MTJ device, in accordance with an embodiment of the present invention.

Figure 2A illustrates a cross-sectional view of a magnetic tunnel junction (MTJ) device including a first passivation layer disposed laterally adjacent to a tunnel barrier and a second passivation layer disposed laterally adjacent to an oxide barrier, in accordance with an embodiment of the present invention.

Figure 2B illustrates a cross-sectional view of a magnetic tunnel junction (MTJ) device including a first passivation layer and a second passivation layer disposed on sidewalls of the MTJ device, in accordance with an embodiment of the present invention.

Figure 2C illustrates a cross-sectional view of a magnetic tunnel junction (MTJ) device including a first passivation layer and a second passivation layer with merged portions disposed on a sidewall of the MTJ device, in accordance with an embodiment of the present invention.

Figure 3 illustrates a cross-sectional view of a magnetic tunnel junction (MTJ) device including a first and a second passivation layer disposed on a sidewall of the MTJ device, and a dielectric spacer disposed on sidewalls of the first and the second passivation layers, in accordance with an embodiment of the present invention. Figure 4A-4H illustrate cross-sectional views representing various operations in a method of fabricating an MTJ device with a first and a second passivation layer in accordance with embodiments of the present invention.

Figure 4A illustrates a cross-sectional view of the formation of a bottom electrode formed on a conductive interconnect structure formed above a substrate.

Figure 4B illustrates a cross-sectional view of the structure in Figure 4A following the formation of various layers in an MTJ material layer stack for an MTJ device, in an accordance with an embodiment of the present invention.

Figure 4C illustrates a cross-sectional view of the structure in Figure 4B following an etch process to pattern various layers of the material layer stack.

Figure 4D illustrates a cross-sectional view of the structure in Figure 4C following the formation of a first passivation layer and a second passivation layer on sidewalls of different layers of the patterned material layer stack.

Figure 4E illustrates a cross-sectional view of the structure in Figure 4D following an etch process to pattern various layers of the material layer stack to form an MTJ device and the formation of etch residue on sidewall of the first and second passivation layers and on sidewall of the MTJ device

Figure 4F illustrates a cross-sectional view of the structure in Figure 4E following a cleanup etch process to remove etch residue from sidewalls of the MTJ device and from sidewalls of the first and the second passivation layers.

Figure 4G illustrates a cross-sectional view of the structure in Figure 4F following the formation of a dielectric spacer around the MTJ device, around the first passivation layer and around the second passivation layer.

4H illustrates a cross-sectional view of the structure in Figure 4B following a partial etch of the MTJ material layer stack followed by the formation of a passivation layer around a protective layer and another passivation layer surrounding and covering any exposed metallic surfaces of the MTJ material layer stack.

Figure 5 illustrates a cross-sectional view of an MTJ device on a conductive interconnect coupled to a transistor.

Figure 6 illustrates a computing device in accordance with embodiments of the present invention.

DESCRIPTION OF THE EMBODIMENTS

Magnetic tunnel junction (MTJ) devices with a sidewall passivation layer and their methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as switching operations associated with embedded memory and transistor operations, are described in lesser detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

A magnetic tunnel junction (MTJ) includes a free magnet, a fixed magnet and a tunnel barrier disposed between the free magnet and the fixed magnet. The MTJ device functions as a variable resistor where a resistance of the MTJ device may switch between a high resistance state and a low resistance state. The resistance state of an MTJ device is defined by the relative orientation of magnetization between the fixed magnet and the free magnet. When the magnetization of the free and fixed magnets have orientations that are parallel to each other the MTJ device is said to be in a low resistance state. Conversely, when the magnetization of the free and fixed magnets have orientations that are anti parallel to each other the MTJ device is said to be in a high resistance state. In an embodiment, resistance switching is brought about by passing a critical amount of spin polarized current through the MTJ device to influence the orientation of the magnetization in the free magnet relative to the magnetization in the fixed magnet. By changing the direction of the spin polarized current flow through the MTJ device, the resistance state of the MTJ device can be changed from high to low or vice versa. Since the free magnetic layer does not need power to retain relative orientation of magnetization, the resistance state of the MTJ device is retained even when there is no power applied to the MTJ device. For this reason, MTJ device belongs to a class of memory known as non-volatile memory.

Integrating a non-volatile memory device such as an MTJ device onto an access transistor enables the formation of embedded memory for system on chip or for other applications. However, integrating a new memory device onto an access transistor while decreasing memory cell footprint presents its own set of challenges. In this regard, a class of MTJ devices known as perpendicular MTJ or pMTJ is sought after for its potential to scale down to dimensions of 30nm or less. Perpendicular MTJ devices have attractive device features such as high thermal stability for a small memory device size, high tunneling magnetoresistance ratios and freedom on the shape of device formed. However, pMTJ stacks can include a multitude of interlaced magnetic and non-magnetic layers which poses challenges from the perspective of device fabrication. Examples of such challenges include etching a pMTJ stack without damaging any of the layers, minimizing etch residue from accumulating on sidewalls of the pMTJ stack during patterning and removal of etch residue from sidewalls without adversely impacting the pMTJ device. Any or all of the above mentioned challenges can adversely impact the advantages offered by a pMTJ device in the first place. However, with innovative fabrication techniques, practical challenges such as patterning of complex multilayered pMTJ stacks can also be overcome.

In accordance with embodiments of the present invention, a magnetic tunnel junction (MTJ) device, includes an MTJ material layer stack having an uppermost surface, a lowermost surface, and a sidewall ending from the uppermost surface to the lowermost surface. The MTJ material layer stack includes a fixed magnet, a tunnel barrier disposed above the fixed magnet and a free magnet disposed on the tunnel barrier. In an embodiment a passivation layer is disposed laterally adjacent to the sidewall of the MTJ material layer stack. The passivation layer extends only partially along the sidewall between the uppermost surface of the MTJ material layer stack and the lowermost surface of the MTJ material layer stack. The presence of a passivation layer can help preserve MTJ device parameters such as switching current (Jc) and tunnel magnetoresi stance ratio (TMR). The critical switching current, Jc, is the current required to switch the magnetization of the free magnet relative to the fixed magnet from an antiparallel state to a parallel state and depends partially on the quality of the tunnel barrier. If edges of the tunnel barrier become damaged during a fabrication process, the effective area of the tunnel barrier becomes smaller and the amount of current that can flow between the fixed and the free magnetic layer is reduced. In an embodiment, the passivation layer is disposed laterally adjacent to specific layers of the material layer stack such as the tunnel barrier to mitigate damage to the tunnel barrier during the formation of the MTJ device.

The TMR of the MTJ device is proportional to the difference between the magnitude of the high resistance state and the low resistance state of the MTJ device. During MTJ device fabrication, shorting structures extending from the fixed magnet to the free magnet may be formed from the plasma etch residue. These shorting structures provide an alternative path for current to flow preventing any spin polarized current to tunnel through the tunnel barrier. The presence of passivation layer adjacent to the tunnel barrier facilitates removal of the shorting structures without adversely damaging the tunnel barrier during MTJ device formation.

In another embodiment, the passivation layer is partially disposed laterally adjacent to the fixed and free magnets as well as laterally adjacent to the tunnel barrier to provide encapsulation to the interface between the tunnel barrier and the fixed magnet and the tunnel barrier and the free magnet. Encapsulation of the interfaces on either side of the tunnel barrier can help to optimize the tunneling effect and optimize TMR. In an embodiment, a dielectric spacer is also disposed laterally adjacent to the passivation layer and extends along the sidewall from the uppermost surface to the lower most surface of the MTJ material layer stack. The dielectric spacer enables a hermetical seal for the MTJ device and prevents moisture from degrading the tunnel barrier.

Figure 1 A is an illustration of a cross-sectional view of a magnetic tunnel junction

(MTJ) device 100A disposed above a conductive interconnect structure 101, in accordance with an embodiment of the present invention. MTJ device 100 A includes an MTJ material layer stack 102 having an uppermost surface 103, a lowermost surface 104, and a sidewall ending from the uppermost surface 103 to the lowermost surface 104. The MTJ device 100A includes a fixed magnet 106, a tunnel barrier 108 such as an MgO disposed above the fixed magnet 106 and a free magnet 110 disposed on the tunnel barrier 108. A passivation layer 112 is disposed laterally on the sidewalls of the MTJ device 100A and extends only partially along the sidewall between the uppermost surface 103 of the MTJ material layer stack 102 and the lowermost surface 104 of the MTJ material layer stack 102. The MTJ device further includes a top electrode 120 disposed above the free magnet 110 and a bottom electrode 130 disposed directly below the fixed magnet 106.

In an embodiment, the passivation layer 112, is disposed laterally adjacent to the sidewalls of the tunnel barrier 108. The passivation layer 112, has an intermediate portion 112A, an upper portion 112B and a lower portion 112C as is illustrated in the enhanced cross sectional illustration of Figure 1 A. The lower portion 112C of the passivation layer 112 does not extend over an interface 122 between an uppermost surface of the fixed magnet 106 and a lowermost surface of the tunnel barrier 108. Likewise, the upper portion 112B of the passivation layer 112 does not extend over an interface 124 between an uppermost surface of the tunnel barrier 108 and a lowermost surface of the free magnet 110. In an embodiment, the passivation layer 112, is disposed only laterally adjacent to the sidewalls of the tunnel barrier 108.

In an embodiment, the passivation layer 112 is an insulator and includes an oxide of an element selected from the group consisting of Al, Ta, Ni, Zr and Ti and Si. In an embodiment, the passivation layer 112 is an oxide of Ti, such as T1O2. In an embodiment, the shape of the passivation layer 112 is hemispherical as shown in the enhanced cross sectional illustration of Figure 1 A. In an embodiment, the intermediate portion 112A of the passivation layer 112 has a peak lateral thickness, WA, that is located approximately midway along a height, HTB, of the tunnel barrier 108. In an embodiment, the intermediate portion 112A of the passivation layer 112 has a peak lateral thickness, WA, that is greater than a mean lateral thickness, WB, of the upper portion 112B of the passivation layer 112. In an embodiment, the intermediate portion 112A of the passivation layer 112 has a peak lateral thickness, WA, that is greater than the mean lateral thickness, Wc, of the lower portion 112C of the passivation layer 112.

In an embodiment, the intermediate portion 112A of the passivation layer 112 has a peak lateral thickness, WA, that is (a) at least 50% greater than the mean lateral thickness, WB, of the upper portion 112B of the passivation layer 112 and (b) that is at least 50% greater than the mean lateral thickness, Wc, of the lower portion 112C of the passivation layer 112.

In an embodiment, the intermediate portion 112A of the passivation layer 112 has a peak lateral thickness, WA, between lnm-3nm. Figure IB illustrates the plan view of the MTJ material layer stack 102 taken along a horizontal line A- A' approximately midway along the height, HTB, of the tunnel barrier 108. In an embodiment, the peak lateral thickness of the intermediate portion 112A of the passivation layer 112 is uniform around the tunnel barrier 108 as seen in the plan view illustration of Figure IB.

In another embodiment, the shape of the passivation layer 112 is oval. In an embodiment, the mean lateral thickness, WB, of the upper portion 112B of the passivation layer 112 is greater than the mean lateral thickness, Wc, of the lower portion 112C of the passivation layer 112 or vice versa. When the shape of the passivation layer 112 is oval, the location of the peak lateral thickness, WA, of the intermediate portion 112A of the passivation layer 112 shifts towards the interface 124 or towards the interface 122.

In an embodiment, an MTJ device 100B includes a passivation layer such as a passivation layer 140 that is laterally disposed beyond the sidewall of the tunnel barrier 108. As illustrated in Figure 1C, the passivation layer 140 is also disposed on a portion of a sidewall of the fixed magnet 106 and on a portion of a sidewall of the free magnet 110 of the MTJ material layer stack 102. The passivation layer 140 has an intermediate portion 140A, an upper portion 140B and a lower portion 140C as illustrated in the enhanced cross sectional illustration of Figure 1C. In one such embodiment, the lower portion 140C of the passivation layer 140 is laterally disposed over an interface 146 between an uppermost surface of the fixed magnet 106 and a lowermost surface of the tunnel barrier 108. In an embodiment, the lower portion 140C of the passivation layer 140 extends a distance, Dx, from the interface 146 along a sidewall of the fixed magnet 106. Likewise, the upper portion 140B of the passivation layer 140 is also laterally disposed over an interface 148 between an uppermost surface of the tunnel barrier 108 and a lowermost surface of the free magnet 110. Encapsulation of the interfaces 146 and 148 provide numerous process and device reliability advantages that will be described further below.

In an embodiment, the upper portion 140B of the passivation layer 140 extends a distance, DR, from the interface 148 along a sidewall of the free magnet 110. In an embodiment, the distances Dx and DR are approximately equal. In another embodiment the distance Dx is greater than the distance DR. And in yet another embodiment, the distance Dxis less than the distance DR. In an embodiment, the distances Dx and DR are at least 0. lnm. Unlike a homogenous ring of passivation layer 140 disposed laterally adjacent to the tunnel barrier 108, the upper and lower portions 140B and 140C of the passivation layer 140 are not uniformly disposed laterally on the free magnet 110 and fixed magnet 106. In an embodiment, the distances Dx and DR vary around the sidewall from 0. lnm-0.3nm.

In an embodiment, the shape and thickness characteristics of the passivation layer 140 is similar to the shape and thickness characteristics of the passivation layer 112. In an

embodiment, the passivation layer 140 has a material composition similar to the material composition of the passivation layer 112. In an embodiment, the shape of the passivation layer 140 is hemispherical as shown in the enhanced cross sectional illustration of Figure 1 A. In an embodiment, the intermediate portion 140 A of the passivation layer 140 has a peak lateral thickness, WD, that is located approximately midway along a vertical extent of the tunnel barrier 108. In an embodiment, the intermediate portion 140 A of the passivation layer 140 has a peak lateral thickness, WD, that is greater than a mean lateral thickness, WE, of the upper portion 140B of the passivation layer 140. In an embodiment, the intermediate portion 140A of the passivation layer 140 has a peak lateral thickness, WD, that is greater than the mean lateral thickness, WF, of the lower portion 140C of the passivation layer 140.

Referring again to Figure 1 A, in an embodiment, the fixed magnet 106 is composed of materials and has a thickness suitable for maintaining a fixed magnetization. In an embodiment, the fixed magnet 106 includes an alloy such as CoFe and CoFeB. In an embodiment, fixed magnet 106 includes a Coi-x-yFe_xBy, where X is between from 0.5-0.8 and Y is between 0.2-0.4. In one specific embodiment, X is 0.8 and Y is 0.3. In one specific embodiment, X is 0.6 and Y is 0.2. In an embodiment the fixed magnet 106 has a thickness that is between 2nm- 3nm.

Referring again to Figure 1 A, in an embodiment, the tunnel barrier 108 is composed of a material suitable for allowing electron current having a majority spin to pass through the tunnel barrier 108, while impeding at least to some extent electron current having a minority spin from passing through the tunnel barrier 108. Thus, the tunnel barrier 108 (or spin filter layer) may also be referred to as a tunneling layer for electron current of a particular spin orientation. In one embodiment, the tunnel barrier 108 includes an oxide such as, but not limited to, magnesium oxide (MgO) or aluminum oxide (AI2O3). In one embodiment, the tunnel barrier 108 is MgO and has a thickness of approximately 1 to 2 nm.

Referring again to Figure 1 A, in an embodiment, the free magnet 110 is composed of materials and has a thickness relative to the fixed layer that is suitable to undergo magnetization flipping. In an embodiment, the free magnet 110 includes an alloy such as CoFe and CoFeB. In an embodiment, free magnet 110 includes a Coi-x-yFe_xBy, where X is between from 0.5-0.8 and Y is between 0.2-0.4. In one specific embodiment, X is 0.8 and Y is 0.3. In one specific embodiment, X is 0.6 and Y is 0.2. In an embodiment the free magnet 110 has a thickness that is between 2nm- 2.5nm. In an embodiment, the free magnet 110 has a thickness that is less than the thickness of the fixed magnet 106.

In an embodiment, the free magnet 110 and the fixed magnet 106 can have similar thicknesses and an injected electron spin current which changes the orientation of the

magnetization in the free magnet 110 can also affect the magnetization of the fixed magnet 106. In an embodiment, to make the fixed magnet 106 more resistant to accidental flipping a synthetic antiferromagnetic (SAF) structure is disposed between the bottom electrode 104 and the fixed magnet 106. In an embodiment, when the fixed magnet 106 has a thickness that is less than 1.5nm, the SAF structure is disposed on the bottom electrode 104 and below the fixed magnet 106 in order to prevent accidental flipping of the fixed magnet 106. The SAF structure is ferromagnetically coupled with the fixed magnet 106 and pins the direction of the magnetization in the fixed magnet 106.

Figure ID illustrates cross-sectional view of a synthetic antiferromagnetic (SAF) layer

150 in an accordance of an embodiment of the present invention. In an embodiment, the SAF structure 150 includes a non-magnetic layer 150B sandwiched between a first ferromagnetic layer 150A and a second ferromagnetic layer 150C as depicted in Figure ID. The first ferromagnetic layer 150A and the second ferromagnetic layer 150C are anti -ferromagnetically coupled to each other. In an embodiment, the first ferromagnetic layer 150 A includes a layer of a magnetic metal such as Co, Ni, Fe, alloys such as CoFe, CoFeB, or alloys of magnetic metals such as Co, Ni, Fe or a bilayer of a magnetic/non-magnetic metals such but not limited to Co/Pd or a Co/Pt. In an embodiment, the non-magnetic layer 150B includes a ruthenium or an iridium layer. In an embodiment, the second ferromagnetic layer 150C includes a layer of a magnetic metal such as Co, Ni, Fe, alloys such as CoFe, CoFeB, or alloys of magnetic metals such as Co, Ni, Fe or a bilayer of a magnetic/non-magnetic metals such but not limited to Co/Pd or a Co/Pt. In an embodiment, a ruthenium based non-magnetic layer 150B is limited to a thickness between 4-9 Angstroms to ensure that the coupling between the first ferromagnetic layer 150A and the second ferromagnetic layer 150C is anti -ferromagnetic in nature.

It is to be appreciated that an additional layer of non-magnetic spacer material may be disposed on the SAF structure 150. A non-magnetic spacer layer enables coupling between the SAF structure 150 and the fixed magnet 106 (depicted in Figure 1A). In an embodiment, the non-magnetic spacer layer may include metals such as Ta, Ru or Ir.

Referring again to Figure 1 A, in an embodiment, the bottom electrode layer 130 is composed of a material or stack of materials suitable for electrically contacting the fixed magnet 106 side of the MTJ material layer stack 102. In an embodiment, the bottom electrode 130 includes an amorphous conductive layer. In an embodiment, the bottom electrode layer 130 is a topographically smooth electrode. In a specific embodiment, the bottom electrode layer 130 is composed of Ru layers interleaved with Ta layers. In another embodiment, the bottom electrode layer 130 is TiN. In an embodiment, the bottom electrode layer 130 has a thickness between 20nm-50nm.

In an embodiment, the MTJ device 100A further includes a top electrode 120 disposed on the free magnet 110 as illustrated in Figure 1 A. In an embodiment, the top electrode 120 includes a material such as Ta or TiN. In an embodiment, the top electrode 120 includes a material suitable to minimize series resistance with the MTJ material layer stack 102. In an embodiment, top electrode 120 has a thickness between 30-70nm. In an embodiment, the top electrode and the bottom electrode include a same metal such as Ta or TiN.

Referring again to Figures 1 A and 1C, the bottom electrode 130 is disposed on a conductive interconnect structure 101. The conductive interconnect structure 101 includes a conductive interconnect 133 disposed in an interlayer dielectric 134 formed above a substrate 132. In an embodiment, the conductive interconnect 133 includes a barrier layer, such as tantalum nitride, and a fill metal, such as copper, tungsten or ruthenium. In an embodiment, the interlayer dielectric 134 includes a dielectric layer such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. As illustrated in Figure 1 A, the MTJ device lOOA has a width, WMTJ, and the conductive interconnect 133 has a width Wei. In an embodiment, the MTJ device 100A has a width, WMTJ, that is less that the width Wei, of the conductive interconnect 133. In an embodiment, the MTJ device lOOA has a width, WMTJ, that is greater that the width Wei, of the conductive interconnect 133. In another embodiment, the MTJ device lOOA has a width, WMTJ, that is similar to the width Wei, of the conductive interconnect 133. In an embodiment, the substrate 132 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials such as germanium, silicon germanium or a suitable group III-V compound. Logic devices such as MOSFET tranistors and access transistors and may be formed on the substrate 132. Access transistors may be integrated with MTJ devices such as MTJ device 100A, 100B, 100E or 100F.

Figure IE illustrates a cross-sectional view of a magnetic tunnel junction (MTJ) device 100E including a second passivation layer 160 disposed on a sidewall of the of the MTJ material layer stack 102, in accordance with an embodiment of the present invention. In an embodiment, the second passivation layer 160 is disposed laterally on the sidewall of the free magnet 110, and on a sidewall and on an uppermost surface of the top electrode 120. In an embodiment, the second passivation layer 160 has a lower portion 160 A that extends continuously from the sidewall of the free magnet 110, along the sidewall of the top electrode 120. In an embodiment, second passivation layer 160 has a second portion 160B disposed on the uppermost surface of the top electrode 120. In an embodiment, the lower portion 160A of the second passivation layer 160 and the second portion 160B of the second passivation layer 160 are continuous and connected. In an embodiment, the upper portion 160B of the second passivation layer 160 and the lower portion 160A of the second passivation layer 160 have hemispherical profiles as illustrated in Figure IE.

In an embodiment, the second passivation layer 160 is an insulator and is an oxide of W, such as W0₂. In an embodiment, the lower portion 160A of the second passivation layer 160 has a peak lateral thickness between l-3nm. In an embodiment, the second portion 160B of the second passivation layer 160B has a peak height between l-3nm.

Figure IF illustrates a cross-sectional view of a magnetic tunnel junction (MTJ) device 100F including a second passivation layer 160 and a third passivation layer 162 disposed on a sidewall of the MTJ material layer stack 102, in accordance with an embodiment of the present invention. In an embodiment, the second passivation layer 160 is disposed laterally on the sidewall of the free magnet 110, and on a sidewall and on the uppermost surface of the top electrode 120. In an embodiment, the third passivation layer 162 is disposed laterally on the sidewall of the fixed magnet 106. In an embodiment, the second passivation layer 160 is only disposed on the free magnet 110 and on the top electrode 120 and the third passivation layer 162 is only disposed on the 106 as illustrated in Figure IF.

In an embodiment, the third passivation layer 162 has a composition and a lateral thickness that is substantially similar to composition and the lateral thickness of the second passivation layer 160. In an embodiment, the second passivation layer 160 has a peak lateral thickness between l-3nm.

Figure 1G illustrates a cross-sectional view of a magnetic tunnel junction (MTJ) device 100G including the second passivation layer 160, and the passivation layer 112 disposed on the sidewall of the MTJ material layer stack 102, in accordance with an embodiment of the present invention. In an embodiment, the passivation layer 112 is disposed laterally only on the sidewall of the tunnel barrier 108 and second passivation layer 160 is only disposed on the sidewall of the free magnet 110, and on the sidewall and uppermost surface of the top electrode 120.

In an embodiment, the peak lateral thickness of the second passivation layer 160 is greater than the peak lateral thickness of the passivation layer 112. In an embodiment, the second passivation layer 160 and the passivation layer 112 are connected at the interface 124 between the free magnet 110 and the tunnel barrier 108. Figure 1H illustrates a cross sectional view of an MTJ device lOOC which includes a dielectric spacer 160 disposed on an MTJ device 100B (structure inside the dashed lines). In an embodiment, the dielectric spacer 180 extends along a sidewall of the MTJ device 100B from an uppermost surface 105 above the top electrode 120 to a surface 107 above the interlay er dielectric 134. In an embodiment, the dielectric spacer 180 is disposed conformally on a sidewall of the passivation layer 140. In an embodiment, the dielectric spacer 180 includes a dielectric material such as a silicon nitride, carbon doped silicon nitride or a silicon carbide. In an embodiment, the dielectric spacer 180 has a thickness that is between 10-30nm.

In an embodiment, an MTJ device also includes additional layers to improve perpendicular anisotropy of the MTJ device. In one such embodiment, when additional layers include an additional oxide layer, an additional passivation layer may be disposed laterally adjacent to the oxide layer.

Figure 2A illustrates a cross sectional view of an MTJ device 200A disposed above a conductive interconnect structure 201, in accordance with an embodiment of the present invention. The MTJ device 200A includes an additional oxide barrier 212 that is disposed on a free magnet 210. MTJ device 200A includes an MTJ material layer stack 202 having an uppermost surface 203, a lowermost surface 204, and a sidewall extending from the uppermost surface 203 to the lowermost surface 204. The MTJ device 200A includes a fixed magnet 206, a tunnel barrier 208 such as an MgO disposed above the fixed magnet 206 and a free magnet 210 disposed on the tunnel barrier 208. The oxide barrier 212 such as an MgO is disposed on the free magnet 210 and a protective barrier 214 is disposed on the oxide barrier 212. A first passivation layer 216 is disposed laterally adjacent to a sidewall of the tunnel barrier 208 and a second passivation layer 218 is disposed laterally adjacent to a sidewall of the oxide barrier 212.

The first passivation layer 216 is compositionally and structurally similar to the passivation layer 1 12 disposed laterally adj acent to the tunnel barrier 108. The first passivation layer 216, has an intermediate portion 216A having a peak lateral thickness, WPIA, an upper portion 216B having a mean lateral thickness, WPIB, and a lower portion 216C having a mean lateral thickness, Wpic, as illustrated in the enhanced cross sectional illustration of Figure 2 A. In an embodiment, the intermediate portion of the first passivation layer 216 has a peak lateral thickness between lnm-3nm.

In an embodiment, the intermediate portion 216A of the first passivation layer 216 has a peak lateral thickness, WPIA, that is (a) at least 50% greater than the mean lateral thickness, WPIB, of the upper portion 216B of the first passivation layer 216 and (b) at least 50% greater than the mean lateral thickness, Wpic, of the lower portion 216C of the passivation layer 216. In an embodiment, the intermediate portion of the first passivation layer 216 has a lateral thickness between lnm-3nm.

In an embodiment, the second passivation layer 218 is disposed laterally adjacent to the sidewall of the oxide barrier 212. In an embodiment, the second passivation layer 218 is compositionally and structurally similar to the passivation layer 216 disposed laterally adjacent to the tunnel barrier 208. The second passivation layer 218 has an intermediate portion 218 A, an upper portion 218B and a lower portion 218C as illustrated in the enhanced cross sectional illustration of Figure 2 A. The intermediate portion 218A of the second passivation layer 218, has a peak lateral thickness, WP₂A, the upper portion 218B of the second passivation layer 218 has a mean lateral thickness, WP₂B, and the lower portion 218C of the second passivation layer 218 has a peak lateral thickness, Wp₂c, as illustrated in the enhanced cross sectional illustration of Figure 2 A.

In an embodiment, the intermediate portion 218A of the second passivation layer 218 has a peak lateral thickness, WP₂A, that is (a) at least 50% greater than the mean lateral thickness, WP2B, of the upper portion 218B of the passivation layer 218 and (b) at least 50% greater than the mean lateral thickness, Wp2c, of the lower portion 218C of the passivation layer 218. In an embodiment, the intermediate portion of the second passivation layer 218 has a peak lateral thickness, Wp2A, between lnm-3nm.

It is to be appreciated that the first passivation layer 216 and the second passivation layer 218 can be compositionally and/or structurally different from each other in various respects. In an embodiment, the second passivation layer 218 is an insulator and includes an oxide of an element selected from the group consisting of Al, Ta, Ni, Zr and Ti and Si. In an embodiment, the passivation layer 112 is an oxide of Ti, such as T1O2. In an embodiment, the first passivation layer 216 includes an oxide of a first metal and the second passivation layer 218 includes an oxide of a second metal, where the second metal is different from the first metal. In one such embodiment, the first passivation layer 216 is an oxide of Ti and the second passivation layer 218 is an oxide of Al.

In an embodiment, the first passivation layer 216 and the second passivation layer 218 have a layer height, Hpi and Hp2, respectively. In an embodiment, the height, Hpi, of the first passivation layer 216 is greater than the height, Hp2, of the second passivation layer 218. In an embodiment, difference in thickness between the tunnel barrier 208 and the oxide barrier 212 leads to differences in heights between the first passivation layer 216 and the second passivation layer 218, respectively. In an embodiment, the first passivation layer 216, has a height, Hpi, that is at least 10% greater than the height, Hp2, of the second passivation layer 218.

In an embodiment, the peak lateral thickness of the intermediate portion 216A of the first passivation layer 216, WPIA, is greater than the peak thickness, WP2A, of the intermediate portion 218A of the second passivation layer 218. In an embodiment, the peak lateral thickness of the intermediate portion 216A of the first passivation layer 216, WPIA, is at least 10% greater than the peak thickness, WP₂A, of the intermediate portion 218A of the second passivation layer 218.

Figure 2B illustrates an MTJ device 200B that includes a first passivation layer 240 that is laterally disposed beyond the sidewall of the tunnel barrier 208 and a second passivation layer 242 that is laterally disposed beyond the sidewall of the oxide barrier 212.

As illustrated in Figure 2B, the first passivation layer 240 is further disposed on a portion of a sidewall of the fixed magnet 206 and on a portion of a sidewall of the free magnet 210 of the MTJ material layer stack 202. In an embodiment, the first passivation layer 240 is compositionally and structurally similar to the passivation layer 216 disposed laterally adjacent to the tunnel barrier 208 as is depicted in Figure 2A. The first passivation layer 240, has (a) an intermediate portion 240A having a peak lateral thickness, W'PIA, (b) an upper portion 240B having a mean lateral thickness, W'PIB, and (c) a lower portion 240C having a peak lateral thickness, W'pic, as illustrated in the enhanced cross sectional illustration of Figure 2B.

The lower portion 240C of the passivation layer 240 is laterally disposed over an interface 250 between an uppermost surface of the fixed magnet 206 and a lowermost surface of the tunnel barrier 208. In an embodiment, the lower portion 240C of the passivation layer 240 extends a distance, Dxi, below the interface 250 along the sidewall of the fixed magnet 206. The upper portion 240B of the passivation layer 240 is also laterally disposed over an interface 252 between an uppermost surface of the tunnel barrier 208 and a lowermost surface of the free magnet 210. In an embodiment, the upper portion 240B of the passivation layer 240 extends a distance, DRI, above the interface 252 along a sidewall of the free magnet 210. In an

embodiment, the distances Dxi and DRI are approximately equal. In another embodiment the distance Dxi is greater than the distance DRI. And in yet another embodiment, the distance Dxi is less than the distance DRI. In an embodiment, the distances Dxi and DRI are at least 0. lnm.

Referring again to Figure 2B, the second passivation layer 242 is further disposed on a portion of a sidewall of the free magnet 210 and on a portion of a sidewall of the protective barrier 214 of the MTJ material layer stack 202. In an embodiment, the second passivation layer 242 is compositionally and structurally similar to the second passivation layer 218 disposed laterally adjacent to the oxide barrier 212. The second passivation layer 242, has an intermediate portion 242A having a peak lateral thickness, W'P2A, an upper portion 242B having a mean lateral thickness, W'P2B, and a lower portion 242C having a peak lateral thickness, W'p2c, as illustrated in the enhanced cross sectional illustration of Figure 2 A. The lower portion 242C of the second passivation layer 242 is laterally disposed over an interface 254 between an uppermost surface of the free magnet 210 and a lowermost surface of the oxide barrier 212. In an embodiment, the lower portion 242C of the second passivation layer 242 extends a distance, Dx2, below the interface 254 along the sidewall of the fixed magnet 206. The upper portion 242B of the second passivation layer 242 is also laterally disposed over an interface 256 between an uppermost surface of the oxide barrier 212 and a lowermost surface of the protective barrier 214. In an embodiment, the upper portion 242B of the second passivation layer 242 extends a distance, DR₂, above the interface 256 along a sidewall of the protective barrier 214. In an embodiment, the distances Dx₂ and DR₂ are approximately equal. In another embodiment the distance Dx₂ is greater than the distance DR₂. And in yet another embodiment, the distance Dx₂ is less than the distance DR₂. In an embodiment, the distances Dx₂ and DR₂ are at least 0. lnm.

It is to be appreciated that the first passivation layer 240 and the second passivation layer 242 can be compositionally and/or structurally different from each other in various respects. In an embodiment, the first passivation layer 240 is an oxide of Al and the second passivation layer 242 is an oxide of Ta.

In an embodiment, the peak lateral thickness of the intermediate portion 240A of the first passivation layer 240, W'PIA, is greater than the peak thickness, W'P₂A, of the intermediate portion 242A of the second passivation layer 242. In an embodiment, the peak lateral thickness of the intermediate portion 240A of the first passivation layer 240, W'PIA, is at least 10% greater than the peak thickness, W'P₂A, of the intermediate portion 242A of the second passivation layer 242.

In an embodiment, the first passivation layer 240 and the second passivation layer 242 have a layer height, H'pi and H'p₂, respectively. In an embodiment, the height, H'pi, of the first passivation layer 240 is greater than the height, Hp₂, of the second passivation layer. In an embodiment, differences in relative thickness between the tunnel barrier 208 and the oxide barrier 212 leads to differences in heights, H'pi and H'p₂, between the first passivation layer 240 and the second passivation layer 242, respectively. In an embodiment, the first passivation layer 240, has a height, H'pi, that is at least 10% greater than the height, H'p₂, of the second passivation layer.

Referring again to Figure 2A, in an embodiment, the fixed magnet 206, tunnel barrier 208, free magnet 210, bottom electrode 230 and top electrode 220 each have a material composition and a thickness that is substantially similar to fixed magnet 106, tunnel barrier 108, free magnet 1 10, bottom electrode 130 and top electrode 120 described in association with Figure 1A.

In an embodiment, the oxide barrier 212 includes an MgO. In an embodiment, the oxide barrier 212 has a thickness that is between 0.3nm-l . barrier 5nm. The oxide barrier 212 provides a source of oxygen that enables oxygen-iron hybridization at the interface 254 located between an uppermost surface of the free magnet 210 including iron and a lowermost surface of the oxide layer 212. The oxygen-iron hybridization in the interface 254 enables interfacial perpendicular magnetic anisotropy in the free magnet 210. Interfacial perpendicular magnetic anisotropy is a component of the total perpendicular magnetic anisotropy of a free or a fixed magnet in an MTJ device such as an MTJ device 200A.

Referring again to Figure 2A, a protective barrier 214 is disposed on the oxide barrier 212. The protective barrier 214 acts as a protective barrier for the oxide barrier 212 against direct physical sputter damage during the formation of a subsequent layer such as a top electrode 220. In an embodiment, the protective barrier 214 has a thickness between 0.3nm - 1.5nm. In an embodiment, the protective barrier 214 is composed of a single layer of cobalt, iron and boron (CoFeB), but has a thickness such that the layer is essentially non-magnetic or weakly magnetic.

The conductive interconnect structure 201 is substantially similar to the conductive interconnect structure 101 described in association with Figure 1A. The conductive interconnect 233, the dielectric layer 234 and the substrate 232 have material compositions that are substantially similar to the material compositions of the conductive interconnect 133, the dielectric layer 134 and the substrate 132, respectively, described in association with Figure 1 A.

Figure 2C illustrates a cross-sectional view of a magnetic tunnel junction (MTJ) device 200C including a first passivation layer 260, a second passivation layer 262 and a merged portion 263 including the first passivation layer 260 and the second passivation layer 262 disposed on sidewall of the MTJ material layer stack 202, in accordance with an embodiment of the present invention. The merged portion 263 completely encapsulates the sidewall of the free magnet 210 and interfaces 254 and 252. Encapsulated interfaces offer numerous advantages such as damage free sidewalls and oxidation barriers which ultimately translates to an MTJ device 200C with enhanced performance.

As illustrated in Figure 2C, the first passivation layer 260 is disposed laterally on the tunnel barrier 208, on a portion of the sidewall of the fixed magnet 206 and on a portion of the sidewall of the free magnet 210 of the MTJ material layer stack 202. In an embodiment, the first passivation layer 260 is compositionally and structurally similar to the passivation layer 240 disposed laterally adjacent to the tunnel barrier 208 as is depicted in Figure 2B. The first passivation layer 260 has an upper portion 260A having a mean lateral thickness, WPMI as illustrated in the enhanced cross sectional illustration of Figure 2C. In an embodiment, WPMI is at least lnm.

The second passivation layer 262 is disposed laterally on the oxide barrier 212, on a portion of the sidewall of the free magnet 210 and on a portion of the sidewall of the protective barrier 214 of the MTJ material layer stack 202. In an embodiment, the second passivation layer 262 is compositionally and structurally similar to the second passivation layer 242 disposed laterally adjacent to the oxide barrier 212 as is depicted in Figure 2B. The second passivation layer 262 has a lower portion 262A having a mean lateral thickness, WPM2, as illustrated in the enhanced cross sectional illustration of Figure 2C. In an embodiment, WpM2 is at least lnm.

A merged portion 263 including the upper portion 260A of the first passivation layer 260 and the lower portion 262A of the second passivation layer 262 is disposed laterally on the sidewall of the free magnet 210. In an embodiment, the merged portion 263 includes a material composition that is different from the individual compositions of the first passivation layer 260 and the second passivation layer 262. In an embodiment, when the first passivation layer 260 and the second passivation layer 262 include a same material the merged portion 263 includes a material that is homogenous in composition.

In an embodiment, the merged portion 263 has a center of merge, M, that is located a distance, DM, away from the interface 252 disposed between the tunnel barrier 208 and the free magnet 210. In an embodiment, the distance, DM has a value that is at least half the thickness, EM, of the free magnet 210 is sufficient to ensure that the interface 252 is encapsulated. In an embodiment, the distance, DM extends at least 50% of the sidewall of the free magnet 210. In an embodiment, the merged portion 263 has a minimum lateral thickness, WM, that is at least 0.5nm. In an embodiment, the merged portion 263 having a minimum lateral thickness WM, of at least 0.5nm offers protection to the free magnet 210 during fabrication of MTJ device 200C.

Figure 3 illustrates a cross sectional view of an MTJ device 300A which includes a dielectric spacer 302 disposed on an MTJ device 200A (structure inside the dashed lines). In an embodiment, the dielectric spacer 302 extends along a sidewall of the MTJ device 300A from an uppermost surface 305 above the top electrode 220 to a surface 307 above the interlay er dielectric 204. In an embodiment, the dielectric spacer 302 is disposed laterally adjacent to the free magnet 210 and the fixed magnet 206. The dielectric spacer 302 is disposed conformally on a sidewall of the first passivation layer 240 and second passivation layer 242. In an embodiment, the dielectric spacer includes a dielectric material such as a silicon nitride, carbon doped silicon nitride or a silicon carbide. The dielectric spacer 302 acts as a hermetic seal for the MTJ device 300A and prevents moisture from attacking the tunnel barrier 208. In an embodiment, the dielectric spacer 302 has a thickness that is between 10-30nm.

Figure 4A-4G illustrate cross-sectional views representing various operations in a method of fabricating an MTJ device in accordance with embodiments of the present invention.

Figure 4A illustrates a cross-sectional view of the formation of a bottom electrode layer 403 on a conductive interconnect structure 400 formed above a substrate 450. In an embodiment, the conductive interconnect structure 400 includes a conductive interconnect 401 formed in a dielectric layer 402 by a dual damascene process that is well known in the art. In an embodiment, the conductive interconnect 401 includes a barrier layer, such as tantalum nitride, and a fill metal, such as copper, tungsten or ruthenium. In an embodiment, the dielectric layer 402 includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the bottom electrode layer 403 includes an alloy such as TiN or TaN. In an embodiment, the bottom electrode layer 403 is deposited using a physical vapor deposition (PVD) process or a plasma enhanced chemical vapor deposition (PECVD) process. In an embodiment the bottom electrode layer 403 is first blanket deposited onto an upper most surface of the dielectric layer 402 and on an uppermost surface of the conductive interconnect 401 and subsequently planarized. In an embodiment, the planarization process includes a chemical mechanical polish to form a topographically smooth uppermost surface having a surface roughness that is less than lnm. A surface roughness of less than 1 nm is sufficient to enable various layers of an MTJ material layer stack that will be subsequently deposited to have well-defined crystal planes.

Figure 4B illustrates a cross-sectional view of the structure in Figure 4A following the formation of various layers in an MTJ material layer stack 490 for an MTJ device, in an accordance with an embodiment of the present invention. In an embodiment, the individual layers in the MTJ material layer stack 490 are deposited without an air break. In an embodiment, when the deposition process is carried without an air break, the individual layers are blanket deposited using a variety of deposition processes in a cluster tool. In an embodiment, some layers are deposited using a physical vapor deposition (PVD) process. In an embodiment, a reactive sputtering process is utilized to deposit one or more layers of the MTJ material layer stack 490.

A fixed magnetic layer 405 is deposited on the bottom electrode layer 403. In an embodiment, the fixed magnetic layer 405 is blanket deposited using a physical vapor deposition (PVD) process. In an embodiment, the PVD process forms a fixed magnetic layer 405 that is amorphous in nature. In an embodiment, the fixed magnetic layer 405 includes an alloy such as CoFe and CoFeB. In an embodiment, fixed magnetic layer 405 includes a Coi-x-yFe_xBy, where X is between from 0.5-0.8 and Y is between 0.2-0.4. In one specific embodiment, X is 0.8 and Y is 0.3. In one specific embodiment, X is 0.6 and Y is 0.2. In an embodiment, the fixed magnetic layer 405 is blanket deposited to a thickness between 2-3nm. The PVD deposition process ensures that the thickness uniformity of the fixed magnetic layer 405 is uniform to within 1% of the film thickness across an entire substrate. Typically, the fixed magnetic layer 405 is the thickest single magnetic layer in the MTJ material layer stack 490. A tunnel barrier layer 407 is then blanket deposited on the fixed magnetic layer 405. In an embodiment, the tunnel barrier layer 407 includes a material such as MgO or AI2O3. In an embodiment, the tunnel barrier layer 407 is an MgO and is deposited using a reactive sputter process. In an embodiment, the reactive sputter process is carried out at room temperature. In an embodiment, the MgO is deposited to a thickness between 0.8 to lnm. In an embodiment, the deposition process is carried out in a manner that yields a tunnel barrier layer 407 having a mostly crystalline structure. In an embodiment, the tunnel barrier layer 407 becomes highly crystalline after an anneal process.

A free magnetic layer 409 is then deposited on the uppermost surface of the tunnel barrier layer 407. In an embodiment, the free magnetic layer 409 is blanket deposited using a PVD process. In an embodiment, the PVD process forms a free magnetic layer 409 that is amorphous. In an embodiment, the free magnetic layer 409 includes an alloy such as CoFe and CoFeB. In an embodiment, free magnetic layer 409 includes a Coi-x-yFe_xBy, where X is between from 0.5-0.8 and Y is between 0.2-0.4. In an embodiment, the free magnetic layer 409 is blanket deposited with a boron content of at least 20% to ensure lattice matching with the tunnel barrier layer 407.

The deposition process continues with the formation of an oxide layer 411 on the uppermost surface of the free magnetic layer 409, the formation of a protective layer 413 on the oxide layer 411, and finally the formation of a top electrode layer 419 on the protective layer 413, in an accordance with an embodiment of the present invention.

The oxide layer 411 is deposited on the free magnetic layer 409 to increase the interfacial perpendicular magnetic anisotropy of the MTJ material layer stack 490. In an embodiment, the oxide layer 411 is deposited using a room temperature reactive sputter deposition process. In an embodiment, the oxide 411 is deposited using an atomic layer deposition (ALD) process. In an embodiment, the oxide layer 411 includes a material such as

MgO. In an embodiment, the oxide layer 411 is deposited to a thickness between 0.3nm - 0.8nm to minimize the resistance of the MTJ material layer stack 490. Unlike the tunnel barrier layer 407, the oxide layer 411 does not act as a spin filter.

In an embodiment, the protective layer 413 is deposited on the oxide layer 411. In an embodiment, the protective layer 413 includes a magnetic material such as CoFe or CoFeB and is blanket deposited using a PVD deposition process. In an embodiment, the protective layer 413 is deposited to a thickness of 0.3-0.6nm. In an embodiment, the protective layer 413 becomes essentially non-magnetic or very weakly magnetic after subsequent deposition of the top electrode layer 419.

In an embodiment, the top electrode layer 419 is blanket deposited on the surface of the protective layer 413 using a PVD deposition process. In an embodiment, the top electrode layer 419 includes a material such as Ta or an alloy such as TaN. In an embodiment, the thickness of the top electrode layer 419 ranges from 30nm-70nm. The thickness is chosen to provide etch resistivity during etching of the MTJ material layer stack 490. In an embodiment, the process of PVD deposition using a heavy metal such as Ta causes damage to the underlying protective layer 413 causing it to lose its magnetism. In an embodiment, at least 0.3nm of the protective layer 413 becomes nonmagnetic in the process.

In an embodiment, after all the layers in the MTJ material layer stack 490 are deposited, an anneal is performed under conditions well known in the art to promote solid phase epitaxy of the free magnetic layer 409 following a template of a crystalline layer of the tunnel barrier layer 407. A post-deposition anneal of the MTJ material layer stack 490 is carried out in a furnace at a temperature between 300-400 degrees C. In an embodiment, the anneal is performed

immediately post deposition but before patterning of the material layer stack to enable boron diffusion away from an interface 453 between the tunnel barrier layer 407 and the free magnetic layer 409. The process of diffusing boron away from the interface 453 enables lattice matching between the free magnetic layer 409 and the tunnel barrier layer 407.

In an embodiment, the annealing process is also performed in the presence of a magnetic field which sets the magnetization direction of the fixed magnetic layer 405 and the free magnetic layer 409. An applied magnetic field that is directed parallel to the vertical axis of the pMTJ material layer stack 490, during the annealing process, enables a perpendicular anisotropy to be set in the fixed magnetic layer 405 and in the free magnetic layer 409. The annealing process initially aligns the magnetization of the fixed magnetic layer 405 and the free magnetic layer 409 to be parallel to each other.

It is to be appreciated that while not shown in Figure 4B, in an embodiment, a SAF structure such as a SAF structure 150 (described in association with Figure ID) is formed on the bottom electrode layer 403 by a PVD process prior to depositing the fixed magnetic layer 405. It is to be appreciated that an additional layer of non-magnetic spacer material may be deposited on the SAF structure 150 before depositing the fixed magnetic layer 405. The non-magnetic spacer layer enables coupling between the SAF structure 150 and the fixed magnetic layer 405. In an embodiment, the non-magnetic spacer layer may include metals such as Ta, Ru or Ir.

Figure 4C illustrates a cross-sectional view of the structure in Figure 4B following an etch process to pattern the top electrode layer 419 and various layers of the MTJ material layer stack 490. In an embodiment, a hardmask (not shown) is formed above the top electrode layer 419. In an embodiment, the hardmask is lithographically patterned and etched. The patterned hardmask is then used to subsequently pattern the MTJ material layer stack 490. In an embodiment, the plasma etch process etches a portion of the MTJ material layer stack 490 and forms a top electrode 420, a barrier layer 414, an oxide barrier 412, a free magnet 410 and stops on the unetched tunnel barrier layer 407 (indicated by the dashed line 460) in Figure 4C. In an embodiment, almost 30-50% of the top electrode 420 may be consumed during the partial etch process. In an embodiment, the plasma etch forms a tapered profile of the top electrode 420, the barrier layer 414, the oxide barrier 412 and the free magnet 410. In an embodiment, the sidewall of the etched portion of the MTJ material layer stack is tapered. While a highly energetic plasma etch can produce a vertical profile of the MTJ material layer stack 490, a tapered profile results when nonvolatile etch residue continues to adhere to freshly etched sidewalls of the MTJ material layer stack 490. Accumulation of residue acts as a micro mask during the etch process.

In an embodiment, the non-volatile byproducts contain magnetic and non-magnetic materials and are deposited on the sidewalls of the oxide barrier 414, the protective barrier 418 and the top electrode 420. In an embodiment, the residual non-volatile by products are metallic and can lead to shorting between the free magnet 410 and the protective barrier 418. The residual non-volatile by products is indicated by dashed line 461. In an embodiment, the nonvolatile residue is removed from the sidewall of the oxide barrier 414, the protective barrier 418 and the top electrode 420 by a second plasma etch based clean-up process. The clean-up process includes an isotropic etch to remove the residue from the sidewall of MTJ material layer stack 490. In an embodiment, the cleanup etch process can damage sidewalls of the oxide barrier 414. However, some damage of the sidewall of the oxide barrier 414 is acceptable for device functionality. The plasma etch process is then continued to etch the tunnel barrier layer 407 to form a tunnel barrier 408 and stops after it etches a small portion amount of the fixed magnetic layer 405 as illustrated in cross illustration of Figure 4C. The small amount of over etch into the fixed magnetic layer 405 enables a subsequent deposition of a passivation layer to extend below a lowermost surface of the tunnel barrier 408.

Figure 4D illustrates a cross-sectional view of the structure in Figure 4C following the formation of a first passivation layer 422 on sidewalls of the tunnel barrier 408 and a second passivation layer 424 on sidewalls of the oxide barrier 414.

In an embodiment, the first and second passivation layers 422 and 424, respectively include a same metal oxide. In one such embodiment the first and second passivation layers 422 and 424, respectively are formed at the same time. In an embodiment, the formation of the first passivation layer 422 is selectively deposited by a cyclical dual deposition process. In a first operation, a metal-alkoxide precursor is deposited on and reacted with the exposed sidewall of the tunnel barrier 408 to form a reactive surface. In an embodiment, the metal-alkoxide is deposited using an atomic layer deposition (ALD) process. In an embodiment, the metal- alkoxide includes an ethoxide or an isopropoxide such as but not limited to Ta(OEt)₅, Al(OEt)₃, Al(OPr)₃, Ti(OPr)4 or Ti(OEt)4. In an embodiment, the metal-alkoxide precursors are chosen to selectively react with the sidewall of the exposed tunnel barrier 408 and not with other exposed surfaces of the MTJ material layer stack 490. In a second operation, the reactive surface is exposed to a metal halide or an organic metal to form a metal oxide on the exposed sidewall of the tunnel barrier 408. In an embodiment, the metal halide includes a material such as but not limited to A1C1₃, ZrCl₄, HfCl₄ or TiCl₃ and the organic metal includes a material such as but not limited to AlMe₃. In an embodiment, the first passivation layer 422 includes a metal oxide such as an oxide of Ti, (e.g. T1O2), an oxide of Hf (e.g. Hf0₂), an oxide of Zr, (e.g. Zr0₂), or an oxide of Al, (e.g. A1₂0₃). In an embodiment, a silicon ethoxide such as for e.g. Si(OEt)₄ is used a precursor during the first operation and a SiCl₄ is used as a halide in the second operation. In one such embodiment, the first passivation layer 422 formed is an oxide of silicon (e.g. Si0₂.)

The ALD deposition process includes alternating between the first process and the second process (a cycle) to complete deposition of the first passivation layer 422. In an embodiment, the lateral thickness of the first passivation layer 422 is between l-3nm.

Depending on the choice of metal-alkoxide and the metal halide or organic metal, the ALD deposition process utilizes between 20-100 cycles to form a lnm laterally thick layer of the first passivation layer 422.

In an embodiment, as first few monolayers of the first passivation layer 422 begin to form via the ALD deposition process, further nucleation takes place on the passivation layer 422 formed near edges of uppermost and lower surfaces of the tunnel barrier 408. In one such embodiment, with subsequent ALD deposition cycles, the first passivation layer 422 is formed on portions of the fixed magnetic layer 405 immediately under the tunnel barrier 408 and on portions of the free magnet 410 immediately above the tunnel barrier 408 as illustrated in Figure 4D. In an embodiment, the first passivation layer 422 is deposited to a thickness so as to encapsulate an interface 452 between the tunnel barrier 408 and the fixed magnetic layer 405 and an interface 453 between the tunnel barrier 408 and the free magnet 410. In an embodiment, encapsulation of the interfaces 452 and 453 enables cleaning of patterned structures with wet chemical methods to remove residue formed by etching process. Typically wet chemicals can cause damage to an MgO tunnel barrier 408 that is not encapsulated by a passivation layer such as a passivation layer 422.

In an embodiment, the ALD process is carried out at a process temperature that is between 200-400 degrees C. A temperature of less than 400 degrees C is optimal to prevent damage to magnetic layers in the MTJ material layer stack 490.

In an embodiment, the process of forming the second passivation layer 424 is identical to the process of forming the first passivation layer 422. In an embodiment, the second passivation layer 424 is deposited to a thickness so as to encapsulate the interface 454 between the oxide barrier 414 and the free magnet 410 and the interface 455 between the oxide barrier 414 and the protective barrier 414. In an embodiment, the first and second passivation layers are formed at the same time.

In an embodiment, when the first and second passivation layers 422 and 424, respectively include different metal oxides, the first passivation layer 422 is formed on the sidewalls of the tunnel barrier 408 and then second passivation layer 424 is formed on the sidewall of the oxide barrier 412. In an embodiment, the passivation layer requiring a lower processing temperature is formed first, followed by the formation of the passivation layer that requires a higher process temperature.

In an embodiment, only the second passivation layer 424 can be formed on the sidewall of the MTJ material layer stack 490. In an embodiment, after etching to form the top electrode 420, the protective barrier 414 and the oxide barrier 412, the plasma etch process is paused upon etching a small portion (less than 10% of the thickness) of the free magnetic layer 409. In an embodiment, the second passivation layer 424 is then formed around the oxide barrier 412 by using the deposition method described above. In one such embodiment, after the formation of the second passivation layer 424, the plasma etching process is continued to form a free magnet 410, the tunnel barrier 408 and paused again after etching a small amount (less than 10% of the thickness) of the fixed magnetic layer 405. The first passivation layer 422 is subsequently formed around the tunnel barrier 408.

Figure 4E illustrates a cross-sectional view of the structure in Figure 4D following an etch process to complete patterning of the MTJ material layer stack 490 and the bottom electrode layer 403 to form MTJ device 492. In an embodiment, the plasma etch process utilized to pattern the free magnetic layer 409 is also utilized to complete patterning of the fixed magnetic layer 405 to form a fixed magnet 406. In an embodiment, the presence of the first and second passivation layers 422 and 424, respectively, causes shadowing during the plasma etch process and consequently leads to the formation of a step-feature 470 in the fixed magnet 406. A slight increase in the width of the fixed magnet 406 manifests as a result of the step-feature. However, the dimension of an MTJ device is partially determined by a width of the fixed magnet 406 at interface 452.

It is to be appreciated that portions of the first and second passivation layers 422 and 424, respectively may become slightly eroded during etching of the bottom electrode layer 403. In an embodiment, an uppermost portion of the second passivation layer 424 may become eroded more than other portions of the first passivation layer 422 because of the direct line of sight of the advancing ions during the plasma etch process.

As discussed above, etching of a magnetic layer such as the fixed magnetic layer 405 can also lead to the formation of non-volatile etch residue. In an embodiment, these non-volatile etch residue 472 can adhere on portions of the sidewall of the MTJ material layer stack 490 as well as on the first and second passivation layers 422 and 424, respectively as illustrated in Figure 4E. It is to be appreciated that the non-volatile etch residue 472 may or may not form conformally around the sidewalls of the first passivation layer 422 or the second passivation layer 424, or around the MTJ material layer stack 490.

Figure 4F illustrates a cross-sectional view of the structure in Figure 4E following a cleanup etch process to remove non-volatile etch residue 472 from portions of the sidewall of the MTJ material layer stack 490 and from sidewalls of the first and the second passivation layers 422 and 424, respectively. In an embodiment, the non-volatile etch residue 472 is removed by a cleanup process similar to the cleanup process described above. It is to be appreciated that the non-volatile etch residue 472 may not be deposited conformally over the tunnel barrier 408 or over the oxide barrier 414 as discussed above. In an embodiment, the clean-up process utilized to remove the non-volatile etch residue 472 can preferentially remove some of the first passivation layer 422 from the tunnel barrier 408 and also some of the second passivation layer 424 from the oxide barrier 414 as illustrated in the plan view illustration in Figure 4F. The process of removing the non-volatile etch residue 472 does not damage the tunnel barrier 408, the oxide layer 414. In an embodiment, when the first passivation layer 422 and second passivation layer 424, respectively, completely merge to cover the sidewall of the free magnet 410, then removal of any non-volatile etch residue formed on the merged region will not damage the free magnet 410 (not shown).

Figure 4G illustrates a cross-sectional view of the MTJ device 492 in Figure 4F following the formation of a dielectric spacer layer 480 on the top electrode 420, on the sidewalls of the MTJ material layer stack 490, on the surfaces of the first passivation layer 422 the second passivation layer 424 and on an uppermost surface of the dielectric layer 403. In an

embodiment, the dielectric spacer layer 480 is deposited without an air break following the plasma etch process. It is to be appreciated that the process of dielectric spacer 480 deposition can also potentially damage the tunnel barrier 408. In this regard the presence of the first passivation layer 422 formed adjacent to the tunnel barrier 408 can also protect the tunnel barrier 408 during the dielectric spacer 480 deposition process.

In an embodiment, the dielectric spacer layer 480 includes a material such as silicon nitride or carbon doped silicon nitride. The dielectric spacer layer 480 is chosen not to contain a material that includes oxygen to prevent oxidation of magnetic layers after the clean-up process. In an embodiment, the dielectric spacer 480 is deposited at a process temperature of less than 300 degrees C. In an embodiment, the dielectric spacer 480 is deposited to a thickness between 10-20nm. In an embodiment, the dielectric spacer layer 480 is plasma etched (not shown).

In an embodiment, a post process anneal of the MTJ device is carried out at process temperature of at least 300 degrees Celsius. In an embodiment, the post process anneal can help to recrystallize sidewalls of the fixed tunnel barrier 408 that may be potentially damaged during an initial etching process of forming the tunnel barrier 408.

In an alternative embodiment, a third passivation layer 464 is formed around the free magnet 410 as is illustrated in Figure 4H. Formation of the third passivation layer 464 can help to protect sidewalls of the free magnet 410 during etching of layer further below. In an embodiment, the top electrode 420, the protective barrier 414 and the oxide barrier 412 are first formed. In an embodiment, the second passivation layer 424 is then formed around the oxide barrier 412 by utilizing a deposition method described above. After forming the second passivation layer 424, the plasma etch process is continued to form the free magnet 410. In an embodiment, the plasma etch is stopped after forming the free magnet 410 but before etching the tunnel barrier layer 407. The third passivation layer 464 is then selectively formed on any exposed metallic surface of the MTJ material layer stack 490.

Referring to Figure 4H, in a first operation, a WF₆ precursor is deposited on and reacted with sidewalls of any exposed metallic surfaces such as sidewall surface of free magnet 410, sidewall and uppermost surfaces of top electrode 420 and sidewall surface of protective barrier 414 to form reactive surfaces. In a second operation, the reactive surfaces having WF_X, are then exposed to a S1H4 gas to form a third passivation layer 464 such as for e.g. W. The third passivation layer 464 has two portions, a first portion 464A formed around the fixed magnet 406 and a second portion 464B formed on the sidewall of the protective barrier 414 and on the sidewall and on the uppermost surface of the top electrode 420 as illustrated in Figure 4H. It is to be appreciated that the second passivation layer 424 may be formed before or after formation of the third passivation layer 464. In an embodiment, the second passivation layer 424 and the third passivation layer 464 may be formed during a single introduction into an ALD chamber.

In an embodiment, the plasma etch process is further continued after formation of passivation layers 464 and 424, and is utilized to pattern the tunnel barrier layer 407, fixed magnetic layer 405 and the bottom electrode layer 403, completing patterning of the MTJ material layer stack 490.

Figure 5 illustrates an MTJ memory device 500, formed on a conductive interconnect 502. In an embodiment, the conductive interconnect 502 is disposed on a contact structure 504 above a drain region 506 of an access transistor 508 disposed above a substrate 510. In an embodiment, the MTJ memory device 500 includes a first and a second passivation layer such as the first passivation layer 422 and second passivation layer 424, surrounded by a dielectric spacer layer 501. In an embodiment, the MTJ memory device 500 has a width that is greater than the width of the conductive interconnect 502. In one such embodiment, a portion of the bottom electrode 104 of MTJ memory device 500 is also disposed on a dielectric layer 503. In an embodiment, the MTJ memory device 500 has a width smaller than the width of the conductive interconnect 502. In an embodiment, the MTJ memory device 500 has a width equal to the width of the conductive interconnect 502.

In an embodiment, the underlying substrate 510 represents a surface used to

manufacture integrated circuits. Suitable substrate 510 includes a material such as single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The substrate 510 may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.

In an embodiment, the access transistor 508 associated with substrate 510 are metal - oxide- semi conductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate 510. In various implementations of the invention, the access transistor 508 may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

In an embodiment, the access transistor 508 of substrate 510 includes a gate stack formed of at least two layers, a gate dielectric layer 514 and a gate electrode layer 512. The gate dielectric layer 514 may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer 514 to improve its quality when a high-k material is used.

The gate electrode layer 512 of the access transistor 508 of substrate 510 is formed on the gate dielectric layer 514 and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer 512 may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer.

For a PMOS transistor, metals that may be used for the gate electrode layer 512 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an

MOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

In some implementations, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode 512 may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode 512 may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some implementations of the invention, a pair of sidewall spacers 516 may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers 516 may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source region 518 and drain region 506 are formed within the substrate adjacent to the gate stack of each MOS transistor. The source region 518 and drain region 506 are generally formed using either an implantation/diffusion process or an

etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source region 518 and drain region 506. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source region 518 and drain region 506. In some implementations, the source region 518 and drain region 506 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source region 518 and drain region 506 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source region 518 and drain region 506.

In an embodiment, a gate contact 520 and a source contact 522 are formed in a second dielectric layer 524 and in the dielectric layer 503 above the gate electrode 512 and source region 518, respectively.

Figure 6 illustrates a computing device 600 in accordance with one embodiment of the invention. The computing device 600 houses a motherboard 602. The motherboard 602 may include a number of components, including but not limited to a processor 604 and at least one communication chip 606. The processor 604 is physically and electrically coupled to the motherboard 602. In some implementations the at least one communication chip 606 is also physically and electrically coupled to the motherboard 602. In further implementations, the communication chip 606 is part of the processsor 604.

Depending on its applications, computing device 600 may include other components that may or may not be physically and electrically coupled to the motherboard 602. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 606 enables wireless communications for the transfer of data to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 606 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 600 may include a plurality of communication chips 606. For instance, a first communication chip 606 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 606 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 604 of the computing device 600 includes an integrated circuit die packaged within the processor 604. In some implementations of embodiments of the invention, the integrated circuit die of the processor includes one or more memory devices, such as an MTJ memory device 500, built with an MTJ material layer stack 202 in accordance with embodiments of the present invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 606 also includes an integrated circuit die packaged within the communication chip 606. In accordance with another implementation of an embodiment of the invention, the integrated circuit die of the communication chip includes MTJ memory elements integrated with access transistors, built in accordance with embodiments of the present invention.

In further implementations, another component housed within the computing device

600 may contain a stand-alone integrated circuit memory die that includes one or more memory elements, built in accordance with embodiments of the present invention.

In various implementations, the computing device 600 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 600 may be any other electronic device that processes data.

Accordingly, one or more embodiments of the present invention relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be nonvolatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present invention relate to the fabrication of an MTJ device 492. Such an MTJ device 492 may be used in an embedded non-volatile memory application.

Thus, embodiments of the present invention include magnetic tunnel junction (MTJ) devices with a sidewall passivation layer and methods to form the same. Specific embodiments are described herein with respect to magnetic tunnel junction (MTJ) devices. It is to be appreciated that embodiments described herein may also be applicable to other non-volatile memory devices. Such non-volatile memory devices may include, but are not limited to, magnetic random access memory (MRAM) devices, spin torque transfer memory (STTM) devices, perpendicular spin torque transfer memory (pSTTM) devices, spin orbit torque (SOT) memory devices and resistive random access memory (RRAM) devices.

Example 1 : A magnetic tunnel junction (MTJ) device, includes an MTJ material layer stack having an uppermost surface, a lowermost surface, and a sidewall ending from the uppermost surface to the lowermost surface. The MTJ material stack includes a fixed magnet, a tunnel barrier disposed above the fixed magnet, a free magnet disposed on the tunnel barrier and a passivation layer disposed laterally adjacent to the sidewall of the MTJ material stack. The passivation layer extends only partially along the sidewall between the uppermost surface of the MTJ material layer stack and the lowermost surface of the MTJ material stack.

Example 2: The MTJ device of example 1, wherein the passivation layer includes an oxide of an element selected from the group consisting of Al, Ta, Ni, Zr and Ti and Si.

Example 3 : The MTJ device of example 1 or 2, wherein the passivation layer is disposed laterally adjacent to the tunnel barrier.

Example 4: The MTJ device of example 1, 2 or 3, wherein the passivation layer has an upper portion, a lower portion and an intermediate portion disposed between the upper and the lower portions, and wherein the intermediate portion of the passivation layer has a lateral thickness that is greater than the lateral thicknesses of each of the upper and the lower portions of the passivation layer.

Example 5: The MTJ device of example 4, wherein the intermediate portion of the passivation layer has a lateral thickness that is at least 50% greater than the lateral thicknesses of each of the upper and the lower portions of the passivation layer.

Example 6: The MTJ device of example 5, wherein the intermediate portion of the passivation layer has a lateral thickness between lnm-3nm.

Example 7: The MTJ device of example 1, wherein a dielectric spacer is disposed laterally adjacent to the MTJ device and extends along the sidewall from the uppermost surface to the lower most surface of the MTJ device.

Example 8: The MTJ device of example 1 further includes a synthetic antiferromagnet disposed below the fixed magnet and in contact with the lowermost surface of the MTJ device, a bottom electrode disposed below the synthetic antiferromagnet, and a top electrode disposed on the free magnet.

Example 9: A magnetic tunnel junction (MTJ) device, includes an MTJ material layer stack having an uppermost surface, a lowermost surface, and a sidewall ending from the uppermost surface to the lowermost surface. The MTJ material stack includes a fixed magnet, a tunnel barrier disposed above the fixed magnet, a free magnet disposed on the tunnel barrier, an oxide barrier disposed on the free magnet, a protective barrier disposed on the oxide barrier, a first passivation layer disposed laterally adjacent to a sidewall of the tunnel barrier, and a second passivation layer disposed laterally adjacent to a sidewall of the oxide barrier.

Example 10: The MTJ device of example 9, wherein the first passivation layer includes an oxide of an element selected from the group consisting of Al, Ta, Ni, Zr and Ti and Si and the second passivation layer includes an oxide of an element selected from the group consisting of Al, Ta, Ni, Zr and Ti and Si.

Example 11 : The MTJ device of example 9 or 10, wherein the first passivation layer includes an oxide of a first metal and the second passivation layer includes an oxide of a second metal, where the second metal is different from the first metal.

Example 12: The MTJ device of example 9, 10 or 11, wherein the first passivation layer includes an upper portion, a lower portion and an intermediate portion disposed between the upper and the lower portions and wherein each of the upper portion and the lower portions of the passivation layer have a respective lateral thickness that is less than a lateral thickness of the intermediate portion of the first passivation layer.

Example 13 : The MTJ device of example 12, wherein the intermediate portion of the first passivation layer has a thickness that is at least 50% greater than the respective thicknesses of the upper and the lower portions of the first passivation layer.

Example 14: The MTJ device of example 13, wherein the intermediate portion of the first passivation layer has a lateral thickness between lnm-3nm

Example 15: The MTJ device of example 9, wherein the second passivation layer includes an upper portion, a lower portion and an intermediate portion disposed between the upper and the lower portions, wherein each of the upper portion and the lower portion of the second passivation layer have a respective lateral thickness that is less than a lateral thickness of the intermediate portion of the second passivation layer.

Example 16: The MTJ device of example 15, wherein the intermediate portion of the second passivation layer has a thickness that is at least 50% greater than the thicknesses of the upper and the lower portions of the second passivation layer.

Example 17: The MTJ device of example 15, wherein the intermediate portion of the second passivation layer has a lateral thickness between lnm-3nm

Example 18: The MTJ device of example 15, wherein the lower portion of the second passivation layer is connected to the upper portion of the first passivation layer along a sidewall of the free magnet.

Example 19: The MTJ device of example 9, wherein a dielectric spacer is disposed laterally adjacent to the MTJ device and extends along the sidewall from the uppermost surface to the lower most surface of the MTJ device.

Example 20: The MTJ device of example 9 further includes a synthetic

antiferromagnet disposed below the fixed magnet and in contact with the lowermost surface of the MTJ device, a bottom electrode disposed below the synthetic antiferromagnet and a top electrode disposed on the free magnet.

Example 21 : A method of fabricating a magnetic tunnel junction (MTJ) device includes forming a conductive interconnect above a substrate, forming a bottom electrode layer on the conductive interconnect and forming a material layer stack for the MTJ device. Forming the material layer stack for the MTJ device includes forming a fixed magnetic layer, forming a tunnel barrier layer on the fixed magnetic layer, forming a free magnetic layer on the tunnel barrier, forming a top electrode layer on the free magnetic layer, etching the top electrode layer by forming a mask above the top electrode, etching the material layer stack to form an MTJ device having sidewalls, wherein the MTJ device includes an oxide barrier and a tunnel barrier. The method further includes forming a passivation layer laterally adjacent to the tunnel barrier, etching the fixed magnetic layer to form a fixed magnet and the bottom electrode layer to form a bottom electrode, forming a dielectric spacer layer laterally adjacent to the bottom electrode, the MTJ device, the first and second passivation layers and the top electrode.

Example 22: The method of example 21, wherein forming the passivation layer includes forming with an atomic layer deposition (ALD) process and wherein forming the passivation layer includes depositing a metal-alkoxide on and reacting with an exposed sidewall of the tunnel barrier to form a reactive surface. The method further includes exposing the reactive surface to a metal halide or an organic metal to form a metal oxide on the exposed sidewall of the tunnel barrier.

Example 23 : The method of example 21 includes a process where the fixed magnetic layer is etched after forming the passivation layer.

Example 24: The method of example 20, wherein forming the dielectric spacer includes performing a cleanup etch to remove etch residue from the sidewall of the MTJ device and from sidewall of the first and second passivation layers and then depositing the dielectric spacer layer.

Claims

CLAIMS What is claimed is:

1. A magnetic tunnel junction (MTJ) device, comprising:

an MTJ material layer stack having an uppermost surface, a lowermost surface, and a sidewall ending from the uppermost surface to the lowermost surface, the MTJ material stack comprising:

a fixed magnet;

a tunnel barrier above the fixed magnet;

a free magnet on the tunnel barrier; and

a passivation layer laterally adjacent to the sidewall of the MTJ material stack,

wherein the passivation layer extends only partially along the sidewall between the uppermost surface of the MTJ material layer stack and the lowermost surface of the MTJ material stack.

2. The MTJ device of claim 1, wherein the passivation layer includes an oxide of an element selected from the group consisting of Al, Ta, Ni, Zr and Ti and Si.

3. The MTJ device of claim 1, wherein the passivation layer is laterally adjacent to the tunnel barrier.

4. The MTJ device of claim 1, wherein the passivation layer has an upper portion, a lower portion and an intermediate portion between the upper and the lower portions, and wherein the intermediate portion of the passivation layer has a lateral thickness that is greater than the lateral thicknesses of each of the upper and the lower portions of the passivation layer.

5. The MTJ device of claim 4, wherein the intermediate portion of the passivation layer has a lateral thickness that is at least 50% greater than the lateral thicknesses of each of the upper and the lower portions of the passivation layer.

6. The MTJ device of claim 5, wherein the intermediate portion of the passivation layer has a lateral thickness between lnm-3nm.

7. The MTJ device of claim 1, wherein a dielectric spacer is laterally adjacent to the MTJ device and extends along the sidewall from the uppermost surface to the lower most surface of the MTJ device.

8. The MTJ device of claim 1 further comprises:

a synthetic antiferromagnet below the fixed magnet;

a bottom electrode below the synthetic antiferromagnet; and

a top electrode on the free magnet.

9. A magnetic tunnel junction (MTJ) device, comprising:

a fixed magnet;

a tunnel barrier above the fixed magnet;

a free magnet on the tunnel barrier;

an oxide barrier on the free magnet;

a protective barrier on the oxide barrier;

a first passivation layer laterally adjacent to a sidewall of the tunnel barrier; and a second passivation layer laterally adjacent to a sidewall of the oxide barrier.

10. The MTJ device of claim 9, wherein the first passivation layer includes an oxide of an element selected from the group consisting of Al, Ta, Ni, Zr and Ti and Si and the second passivation layer includes an oxide of an element selected from the group consisting of Al, Ta, Ni, Zr and Ti and Si.

11. The MTJ device of claim 9, wherein the first passivation layer includes an oxide of a first metal and the second passivation layer includes an oxide of a second metal, the second metal different from the first metal.

12. The MTJ device of claim 9, wherein the first passivation layer includes an upper portion, a lower portion and an intermediate portion between the upper and the lower portions and wherein each of the upper portion and the lower portions of the passivation layer have a respective lateral thickness that is less than a lateral thickness of the intermediate portion of the first passivation layer.

13. The MTJ device of claim 12, wherein the intermediate portion of the first passivation layer has a thickness that is at least 50% greater than the respective thicknesses of the upper and the lower portions of the first passivation layer.

14. The MTJ device of claim 13, wherein the intermediate portion of the first passivation layer has a lateral thickness between lnm-3nm.

15. The MTJ device of claim 9, wherein the second passivation layer includes an upper portion, a lower portion and an intermediate portion between the upper and the lower portions, wherein each of the upper portion and the lower portion of the second passivation layer have a respective lateral thickness that is less than a lateral thickness of the intermediate portion of the second passivation layer.

16. The MTJ device of claim 15, wherein the intermediate portion of the second passivation layer has a thickness that is at least 50% greater than the thicknesses of the upper and the lower portions of the second passivation layer.

17. The MTJ device of claim 15, wherein the intermediate portion of the second passivation layer has a lateral thickness between lnm-3nm.

18. The MTJ device of claim 15, wherein the lower portion of the second passivation layer is connected to the upper portion of the first passivation layer along a sidewall of the free magnet.

19. The MTJ device of claim 9, wherein a dielectric spacer is laterally adjacent to the MTJ device and extends along the sidewall from the uppermost surface to the lower most surface of the MTJ device.

20. The MTJ device of claim 9 further comprises:

a synthetic antiferromagnet below the fixed magnet;

a bottom electrode below the synthetic antiferromagnet; and

a top electrode on the free magnet.

21. A method of fabricating a magnetic tunnel junction (MTJ) device, the method comprising: forming a conductive interconnect above a substrate;

forming a bottom electrode layer on the conductive interconnect; forming a material layer stack for the MTJ device, the forming comprising:

forming a fixed magnetic layer;

forming a tunnel barrier layer on the fixed magnetic layer;

forming a free magnetic layer on the tunnel barrier;

forming a top electrode layer on the free magnetic layer;

etching the top electrode layer by forming a mask above the top electrode;

etching the material layer stack to form an MTJ device having sidewalls, wherein the

MTJ device includes an oxide barrier and a tunnel barrier;

forming a passivation layer laterally adjacent to the tunnel barrier;

etching the fixed magnetic layer to form a fixed magnet and the bottom electrode layer to form a bottom electrode;

forming a dielectric spacer layer laterally adjacent to the bottom electrode, the MTJ device, the first and second passivation layers and the top electrode.

22. The method of claim 21, wherein forming the passivation layer comprises forming using an atomic layer deposition (ALD) process and wherein forming the passivation layer includes depositing a metal-alkoxide on and reacting with an exposed sidewall of the tunnel barrier to form a reactive surface, wherein the method further includes exposing the reactive surface to a metal halide or an organic metal to form a metal oxide on the exposed sidewall of the tunnel barrier.

23. The method of claim 21, wherein the fixed magnetic layer is etched after forming the passivation layer.

24. The method of claim 20, wherein forming the dielectric spacer includes performing a cleanup etch to remove etch residue from the sidewall of the MTJ device and from sidewall of the first and second passivation layers and then depositing the dielectric spacer layer laterally around and on the MTJ device.