WO2018182651A1

WO2018182651A1 - Perpendicular spin transfer torque memory (psttm) devices with enhanced anisotropy and methods to form the same

Info

Publication number: WO2018182651A1
Application number: PCT/US2017/025194
Authority: WO
Inventors: Tofizur RAHMAN; Mark L. Doczy; Satyarth Suri; Kaan OGUZ; Charles C. Kuo; Brian S. Doyle; Kevin P. O'brien; Christopher J. WIEGAND; Daniel G. OUELLETTE; Angeline K. SMITH
Original assignee: Intel Corporation
Priority date: 2017-03-30
Filing date: 2017-03-30
Publication date: 2018-10-04

Abstract

A magnetic tunnel junction (PSTTM) device includes a bottom electrode, a fixed magnet above the bottom electrode, a tunnel barrier disposed above the fixed magnet, a free magnet disposed on the tunnel barrier, an oxide layer disposed above the free magnet and a top electrode disposed above the oxide layer. In an embodiment, the oxide layer includes a stack of metal oxides, wherein the stack of metal oxides comprises a first metal oxide and a second metal oxide disposed on the first metal oxide, and wherein the first metal oxide comprises a metal different from a metal of the second metal oxide.

Description

PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (PSTTM) DEVICES WITH ENHANCED

ANISOTROPY AND METHODS TO FORM THE SAME

TECHNICAL FIELD

[0001] Embodiments of the invention are in the field of integrated circuit fabrication and, in particular, perpendicular spin transfer torque memory (pSTTM) devices with enhanced perpendicular anisotropy and methods to form the same.

BACKGROUND

[0002] For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

[0003] Non-volatile embedded memory with pSTTM devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. However, the technical challenges of assembling a pSTTM stack to form functional devices present formidable roadblocks to commercialization of this technology today. Specifically, increasing thermal stability and reducing retention loss of pSTTM devices are some important areas of process development. As such, improvements are still needed in the areas of pSTTM stack development. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 A illustrates a cross-sectional view of a perpendicular STTM device, in accordance with an embodiment of the present invention.

[0005] Figure IB illustrates a cross sectional view of an oxide layer which includes a stack of bilayers of oxides capped by a metal layer.

[0006] Figures 1C illustrates a cross-sectional view of individual layers of a synthetic antiferromagnetic layer.

[0007] Figure 2 illustrates a cross-sectional view of a perpendicular STTM device, where a protective layer is inserted above an oxide layer to improve perpendicular anisotropy, in accordance with an embodiment of the present invention.

[0008] Figures 3 A illustrate a cross-sectional view of a perpendicular STTM device, where additional layers are inserted into the free magnet to improve perpendicular anisotropy. [0009] Figures 3B illustrate a cross-sectional view of a perpendicular STTM device, where additional layers are inserted above the free magnetic layer to improve perpendicular anisotropy.

[0010] Figure 4A-4F illustrate cross-sectional views representing various operations in a method of fabricating a pSTTM material layer stack.

[0011] Figure 4A illustrates a cross-sectional view of the formation of a conductive interconnect and a bottom electrode layer on the conductive interconnect.

[0012] Figure 4B illustrates a cross-sectional view of the structure in Figure 4A following the formation of various layers in a material layer stack for a pSTTM device on the conductive interconnect.

[0013] Figure 4C illustrates a cross-sectional view of the structure in Figure 4B following the formation of an oxide layer on a free magnet to complete the formation of a pSTTM material layer stack.

[0014] Figure 4D illustrates a cross-sectional view of the structure in Figure 4C following the formation of an adhesion layer on the oxide layer and the formation of a top electrode layer on the adhesion layer.

[0015] Figure 4E illustrates a cross-sectional view of the structure in Figure 4D following patterning of the pSTTM material layer stack to form a pSTTM device.

[0016] Figure 4F illustrates a cross-sectional view of the structure in Figure 4E following the formation of a dielectric spacer surrounding the pSTTM device.

[0017] Figure 5 illustrates a cross-sectional view of a pSTTM device formed on a conductive interconnect coupled to a transistor.

[0018] Figure 6 illustrates a computing device in accordance with embodiments of the present invention.

[0019] Figure 7 illustrates an interposer that includes one or more embodiments of the invention.

DESCRIPTION OF THE EMBODIMENTS

[0020] Perpendicular-spin transfer torque memory (pSTTM) devices with enhanced stability and methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as transistor operations and switching operations associated with embedded memory, are described in lesser detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

[0021] Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

[0022] A pSTTM device functions as a variable resistor where the resistance of the device may switch between a high resistance state and a low resistance state. The resistance state of a pSTTM device is defined by the relative orientation of magnetization of two magnetic layers (fixed and free) that are separated by a tunnel barrier. When the magnetization of the two magnetic layers have orientations that are in the same direction the pSTTM device is said to be in a low resistance state. Conversely, when the magnetization of the two magnetic layers have orientations that in opposite directions, the pSTTM device is said to be in a high resistance state. In an embodiment, resistance switching is brought about by passing a critical amount of spin polarized current through the pSTTM device so as to influence orientation of the magnetization of the free magnetic layer to align with the magnetization of the fixed magnetic layer. By changing the direction of the current, the magnetization in the free magnetic layer may be reversed relative to that of the fixed magnetic layer. Since the free magnetic layer does not need power to retain relative orientation of magnetization, the resistance state of the pSTTM device is retained even when there is no power applied to the pSTTM device. For this reason, pSTTM belongs to a class of memory known as non-volatile memory.

[0023] Integrating a non-volatile memory device such as an STTM device onto an access transistor enables the formation of embedded memory for system on chip or for other applications. However, approaches to integrate an STTM device onto an access transistor presents challenges that have become far more formidable with scaling. Examples of such challenges range from improving thermal stability of STTM devices against perturbing forces, reducing retention loss and enabling patterning of STTM devices at less than 40nm feature sizes. As scaling continues, the need for smaller memory devices to fit into a scaled cell size has driven the industry in the direction of "perpendicular" STTM or pSTTM. The word "perpendicular" in pSTTM devices refers to fact that magnetic dipoles in the free and fixed magnets are directed perpendicular to the plane of the substrate. Fortunately, while pSTTM devices have higher stability for small memory device sizes, maintaining stability along with improving other device parameters continues to be a challenge. Stability of a pSTTM device refers to the ease with which the pSTTM device can be unintendedly perturbed from a high or low resistance state and is related to the strength or anisotropy of the free magnetic layer.

[0024] A pSTTM device includes a fixed or reference magnetic layer, a tunnel barrier disposed on the fixed magnetic layer and a free magnetic layer, including iron disposed on the tunnel barrier. An oxide layer is generally provided above the free magnetic layer to improve the perpendicularity anisotropy of the free magnetic layer by enhancing the interfacial perpendicular magnetic anisotropy at the interface between the oxide layer and the free magnetic layer. The interfacial perpendicular magnetic anisotropy in the free magnetic layer has a contribution from the bond hybridization between iron in the free magnetic layer and oxygen in the oxide layer. However, pinhole defects in the oxide layer can allow oxygen scavenging materials above the oxide layer to diffuse and break the Fe-0 bond-hybridization which gives rise to interfacial perpendicular magnetic anisotropy. Fabricating a pSTTM device further requires metallic layers to be deposited on the oxide layer. Deposition of metals having high atomic mass such as Ta or Ru on the oxide layer can damage an already defective oxide layer and also lead to damage of the free magnetic layer below. Damage of the surface of the free magnetic layer leads to degradation in the interfacial perpendicular magnetic anisotropy. Thus, by forming an oxide that is free of defects and resistant to damage during a subsequent deposition process, the iron- oxygen hybridization at the interface may be preserved.

[0025] In accordance with embodiments of the present invention, a material layer stack for a pSTTM memory device includes a fixed magnetic layer, a tunnel barrier such as but not limited to MgO disposed above the fixed magnetic layer, a free magnetic layer disposed on the tunnel barrier and an oxide layer including at least two different metals disposed on the free magnetic layer. In an embodiment, the oxide layer includes a bilayer stack of metal oxides. In an embodiment, the oxide layer includes a bilayer stack of metal oxides, where the bilayer stack of metal oxides includes a first metal oxide having magnesium and a second metal oxide having aluminum disposed on the first metal oxide. The oxides of Mg and the Al behave differently when subjected to a high temperature anneal process. The oxide of magnesium contracts developing pinhole defects, while the oxide of aluminum expands to fill the gap left by the pinholes. Through the contraction of one metal oxide and expansion of the other, the bilayer stack becomes a more robust oxide compared to an oxide of MgO alone, and offers protection against subsequent downstream deposition processes. In an embodiment, the oxide layer includes two or more bilayers to make the oxide layer even more physically robust. In an embodiment, a layer of metal such as Mg is disposed on the oxide layer.

[0026] In another embodiment, the oxide layer includes single layer having a first metal such as magnesium, a second metal such as aluminum, and oxygen. By combining magnesium and aluminum in various proportions, the oxide layer can be preferentially rich in one metal or another. In an embodiment, the oxide layer is magnesium rich to help increase the interfacial perpendicular magnetic anisotropy of the free magnetic layer. Unlike the bilayer stack of oxides, the single layer of metal oxide does not undergo the same level of contraction and expansion due to the chemical composition of the mixture and remains relatively free of defects. The oxide layer also offers protection against further damage during subsequent layer deposition.

[0027] Figure 1 A illustrates a cross-sectional illustration of a pSTTM device 100 in accordance with an embodiment of the present invention. The pSTTM device 100 includes a bottom electrode 104 disposed above a substrate 101, a fixed magnet 106 disposed above the bottom electrode 104, a tunnel barrier 108 including an MgO disposed on the fixed magnet 106, a free magnet 110 including iron disposed on the tunnel barrier 108, an oxide layer 112 disposed on the free magnet 110 and a top electrode 120 disposed above the oxide layer 112. The oxide layer 112 provides a source of oxygen that enables oxygen-iron hybridization at an interface 105 located between an uppermost surface of the free magnet 110 and a lowermost surface of the oxide layer 112. The oxygen-iron hybridization in the interface 105 enables interfacial perpendicular magnetic anisotropy in the free magnet 110. Preservation of interfacial perpendicular magnetic anisotropy relies upon (1) successfully preventing damage of the oxide layer 112 and the free magnet 110 during deposition of subsequent layers on the oxide layer and (2) preventing diffusion of oxygen gettering elements from reaching the interface 105. It is to be appreciated that oxygen gettering elements such as Ta can diffuse toward interface 105 and destroy the Fe-0 hybridization by forming an oxide.

[0028] In an embodiment, the oxide layer 112 includes a bilayer stack of metal oxides.

In an embodiment, the oxide layer 112 includes at least two bilayer stacks of metal oxides such as is shown in the cross-sectional illustration of Figure IB. In an embodiment, each bilayer stack of metal oxide includes a first metal oxide 112A and a second metal oxide 112B, disposed on the first metal oxide 112A. In an embodiment, the first metal oxide 112A is MgO and the second metal oxide 112B is AI2O3. In another embodiment, the first metal oxide 112A is AI2O3 and the second metal oxide 112B is MgO. By stacking the second metal oxide 112B such as AI2O3 on the first metal oxide 112A such as MgO, defectivity in the MgO is reduced as will be discussed below. In other embodiments, the oxide layer 112 has anywhere between 3-6 bilayer stacks of metal oxides.

[0029] In an embodiment, when the oxide layer 112 includes a bilayer stack of metal oxide bilayers such as the first metal oxide 112A and the second metal oxide 112B, the metal oxide layer 112 is capped by a layer of capping metal 114, as illustrated in Figure IB. In an embodiment, the capping metal 114 includes a metal such as the metal of the first metal oxide 112A. In an embodiment, the capping metal 114 is composed of magnesium when the first oxide layer 112 is MgO.

[0030] In an embodiment, the oxide layer 112 has a combined total thickness that is between 0.3nm-0.9nm. In an embodiment, each of the first and the second metal oxides 112A and 112B, respectively, has a thickness that is between 0.15nm-0.3nm. In an embodiment, the thickness of the first metal oxide 112A is greater than the thickness of the second metal oxide 112B. In another embodiment, the thickness of the second metal oxide 112B is greater than the thickness of the first metal oxide 112 A. In an embodiment, the thickness of the capping layer 114 is between 0.15-0.3nm. In an embodiment, the first metal oxide 112A has a thickness of 0.6nm, the second metal oxide 112B has a thickness of 0.2nm and the capping layer 114 has thickness of 0.2nm.

[0031] The oxide layer 112 can also be material composed of a bimetal oxide including first metal, a second metal and oxygen. In an embodiment, the oxide layer 112 is material composed of a bimetal oxide of a first metal such as Mg, a second metal such as Al, and oxygen. In an embodiment, the bimetal oxide is a magnesium aluminum oxide. In an embodiment, the bimetal oxide is a compound such as (Mg, Al) O. In an embodiment, bimetal oxide including magnesium aluminum oxide has a crystal structure. In an embodiment, the bimetal oxide including magnesium aluminum oxide has a <001> crystal structure that is templated from a <001> crystal structure of the underlying free magnet 110. In another embodiment, the bimetal oxide including magnesium aluminum oxide has a polycrystalline structure. An important property of the oxide layer 112 with a bimetal oxide including magnesium aluminum oxide is the absence of pinhole defects that can potentially lead to damage of the underlying free magnet 110.

[0032] By mixing various amounts of Mg and Al in the bimetal oxide, the oxide layer

112 can be preferentially rich in one metal or another. In an embodiment, the bimetal oxide includes a higher concentration of Mg to help increase the perpendicularity of pSTTM material layer stack. In an embodiment, the ratio of the Mg to Al in the bimetal oxide is at least 1.5: 1 but can be as high as 3 : 1. An Mg: Al ratio of 1.5 : 1 is sufficiently strong to form MgO bonds that will help maintain interfacial anisotropy at the interface 105 between the oxide layer 112 and the free magnet 110. In an embodiment, the ratio of the Mg to Al in the bimetal oxide is 2: 1. A strong MgO bond at the interface 105 can help to maintain the Fe-0 hybridization at the interface 105, important for maintaining interfacial perpendicular magnetic anisotropy in the free magnet 110. In another embodiment, the ratio of the Al to Mg in the bimetal oxide is at least 1.5: 1 but can be as high as 3 : 1.

[0033] Referring again to Figure 1 A, in an embodiment, the fixed magnet 106 is composed of materials and has a thickness suitable for maintaining a fixed perpendicular magnetization. In an embodiment, the fixed magnet 106 includes an alloy such as CoFe and CoFeB. In an embodiment, fixed magnetic layer 1-6 includes a Coi-x-yFe_xBy, where X and Y each represent atomic percent, further where X is between 0.5-0.8 and Y is between 0.1-0.4, and further where the sum of X and Y is less than 1. In one specific embodiment, X is 0.6 and Y is 0.2. In an embodiment the fixed magnet 106 has a thickness that is between l-2nm.

[0034] Referring again to Figure 1 A, in an embodiment, the tunnel barrier 108 is composed of a material suitable for allowing electron current having a majority spin to pass through the tunnel barrier 108, while impeding at least to some extent electron current having a minority spin from passing through the tunnel barrier 108. Thus, the tunnel barrier 108 (or spin filter layer) may also be referred to as a tunneling layer for electron current of a particular spin orientation. In one embodiment, the tunnel barrier 108 includes an oxide such as, but not limited to, magnesium oxide (MgO) or aluminum oxide (AI2O3). In one embodiment, the tunnel barrier 108 is MgO and has a thickness of approximately 0.7 to 2 nm.

[0035] Referring again to Figure 1 A, in an embodiment, the free magnet 110 is composed of materials and has a thickness relative to the fixed layer that is suitable to undergo magnetization flipping. In an embodiment, the free magnet 110 includes an alloy such as CoFe and CoFeB. In an embodiment, free magnet 110 includes a Coi-x-yFe_xBy, where X and Y each represent atomic percent, further where X is between 0.5-0.8 and Y is between 0.1-0.4, and further where the sum of X and Y is less than 1. In one specific embodiment, X is 0.6 and Y is 0.2. In an embodiment the free magnet 110 has a thickness that is between lnm-1.6nm. In an embodiment, the free magnet 110 has a thickness that is less than the thickness of the fixed magnet 106. In another embodiment, the free magnet 110 has a thickness that is greater than the thickness of the fixed magnet 106. In another embodiment, the free magnet 110 has a thickness that is equal to the thickness of the fixed magnet 106.

[0036] In an embodiment, the free magnet 110 and the fixed magnet 106 can have similar thicknesses and an injected electron spin current which changes the orientation of the

magnetization in the free magnet 110 can also affect the magnetization of the fixed magnet 106. In an embodiment, to make the fixed magnet 106 more resistant to accidental flipping a synthetic antiferromagnetic (SAF) layer 150 is disposed between the bottom electrode 104 and the fixed magnet 106. In an embodiment, when the fixed magnet 106 has a thickness that is less than 1.5nm, a synthetic antiferromagnetic (SAF) layer is disposed on the bottom electrode 104 and below the fixed magnet 106 in order to prevent accidental flipping of the fixed magnet 106. The SAF layer 150 is ferromagnetically coupled with the fixed magnet 106 and pins the direction of the magnetization in the fixed magnet 106.

[0037] Figure 1C illustrates cross-sectional view of the synthetic antiferromagnetic

(SAF) layer 150 in an accordance of an embodiment of the present invention. In an embodiment, the SAF layer 150 includes a non-magnetic layer 150B sandwiched between a first ferromagnetic layer 150A and a second ferromagnetic layer 150C as depicted in Figure ID. The first ferromagnetic layer 150A and the second ferromagnetic layer 150C are anti -ferromagnetically coupled to each other. In an embodiment, the first ferromagnetic layer 150 A includes a layer of a magnetic metal such as Co, Ni, Fe, alloys such as CoFe, CoFeB, or alloys of magnetic metals such as Co, Ni, Fe or a bilayer of a magnetic/non-magnetic metals such but not limited to Co/Pd or a Co/Pt. In an embodiment, the non-magnetic layer 150B includes a ruthenium or an iridium layer. In an embodiment, the second ferromagnetic layer 150C includes a layer of a magnetic metal such as Co, Ni, Fe, alloys such as CoFe, CoFeB, or alloys of magnetic metals such as Co, Ni, Fe or a bilayer of a magnetic/non-magnetic metals such but not limited to Co/Pd or a Co/Pt. In an embodiment, a ruthenium based non-magnetic layer 150B is limited to a thickness between 4-9 Angstroms to ensure that the coupling between the first ferromagnetic layer 150A and the second ferromagnetic layer 150C is anti -ferromagnetic in nature.

[0038] It is to be appreciated that an additional layer of non-magnetic spacer material may be disposed on the SAF layer 150, below the fixed magnet 106. A non-magnetic spacer layer enables coupling between the SAF layer 150 and the fixed magnet 106. In an embodiment, a non-magnetic spacer layer may include metals such as Ta, Ru or Ir.

[0039] Referring again to Figure 1 A, an adhesion layer 116 is disposed on the oxide layer

112. The adhesion layer 116 prevents the top electrode 120 from delaminating during the formation of pSTTM device 100. The adhesion layer 116 includes a metal such as but not limited to Ta, Ru or Ti. In an embodiment, the adhesion layer 116 has a thickness between 1- 5nm.

[0040] Referring again to Figure 1 A, in an embodiment, the top electrode 120 includes a material such as Ta, TaN or TiN. In an embodiment, the top electrode 120 includes a material suitable to minimize series resistance. In an embodiment, top electrode 120 has a thickness between 20-100nm. In an embodiment, the top electrode 120 and the bottom electrode 104 include a same metal such as Ta or TiN.

[0041] Referring again to Figure 1 A, in an embodiment, the bottom electrode 104 is composed of a material or stack of materials suitable for electrically contacting the fixed magnet 106 side of the pSTTM device 100. In an embodiment, the bottom electrode 104 includes an amorphous conductive layer. In an embodiment, the bottom electrode 104 is a topographically smooth electrode. In a specific embodiment, the bottom electrode 104 is composed of Ru layers interleaved with Ta layers. In another embodiment, the bottom electrode 104 is TiN. In an embodiment, the bottom electrode 104 has a thickness between 20nm-50nm. Referring again to Figure 1 A, the bottom electrode 104 is disposed on a conductive interconnect structure 130. The conductive interconnect structure 130 includes a conductive interconnect 132 disposed in an interlayer dielectric 134 formed above the substrate 101. In an embodiment, the conductive interconnect 132 includes a barrier layer, such as tantalum nitride, and a fill metal, such as copper, tungsten or ruthenium. In an embodiment, the interlayer dielectric 134 includes a dielectric layer such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the substrate 101 includes a material such as single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials such as silicon germanium, germanium or III-V compounds. In an embodiment, active devices such as logic transistors are formed on the substrate 101 to form functional circuits such as microprocessors. In an embodiment, active devices such as access transistors are integrated with MTJ devices such as MTJ devices 100A with bilayer stack of oxides or bi-metal oxides to form embedded memory circuits.

[0042] Figure 2 illustrates a cross-sectional view of a perpendicular STTM device 200, where a protective layer 218 is disposed directly between the oxide layer 112 and the adhesion layer 116, in accordance with an embodiment of the present invention. The protective layer is a conductive layer. In an embodiment, the protective layer 218 is an alloy whose individual constituent atoms each have a lower atomic mass compared to the atomic mass of the metal included in the adhesion layer 116 such as Ta. In an embodiment, the protective layer 218 includes a magnetic material such as Co and Fe. In an embodiment, the protective layer 218 includes a magnetic alloy of Co, Fe and B such as Coo.4Feo.6B. By forming a magnetic layer on the oxide layer 112, the perpendicular interfacial anisotropy is further increased. In an embodiment, the protective layer 218 has a thickness sufficient to prevent sputter damage during a subsequent deposition of the adhesion layer 116. In an embodiment, the protective layer 218 has a thickness between 0.3nm - 1.5nm. In an embodiment, the protective layer 218 has a thickness of 0.6nm and is a magnetically dead layer, i.e., it does not participate in spin polarized switching. A thickness of 0.6nm is sufficiently thick to protect against the deposition of the adhesion layer 112 but not thick enough to increase electrical resistance in the pSTTM device 200.

[0043] Figures 3A illustrate cross-sectional view of a perpendicular STTM device 300A that includes a composite free magnet 302, which has a first free magnet 304 and a second free magnet 308 separated by a coupling layer 306 in between to improve the perpendicular anisotropy of the composite free magnet 302. Insertion of the coupling layer 306 and the second free magnet 308 increases the number of interfaces between an uppermost surface of the tunnel barrier 108 and a lower most surface of the oxide layer 112 from 2 to 4. The increase in the number of interfaces increases the overall interfacial perpendicular anisotropy in the pSTTM device 300 A.

[0044] In an embodiment, the first free magnet 304 and the second free magnet 308 include a CoFeB layer. In an embodiment, when the first free magnet 304 and the second free magnet 308 include a CoFeB layer, the first free magnet 304 has a thickness greater than the thickness of the second free magnet 308. In an embodiment the CoFeB first free magnet 304 has a thickness between 0.5nm - 1.5nm and the CoFeB second free magnet 308 has a thickness between 0.3nm - 1.0 nm. In an embodiment, the CoFeB first free magnet 304 and the second CoFeB free magnet 308 have a combined thickness that is between lnm-2.5nm. In an embodiment, the composite free magnet 302 has a thickness that is greater than or equal to the thickness of the fixed magnet 106 to facilitate spin polarized current switching and to maintain perpendicular anisotropy.

[0045] In an embodiment, the coupling layer 306 includes a non-magnetic transition metal such as, but not limited to, tungsten, molybdenum, vanadium, niobium iridium. In an embodiment, the coupling layer 306 has a thickness between 0. lnm-lnm. In an embodiment, the coupling layer 306 is tantalum.

[0046] Figures 3B illustrate cross-sectional view of a pSTTM device 300B that includes the composite free magnet 302 as well as a protective layer 318 to increase the perpendicular anisotropy of the pSTTM device 300B. In an embodiment, the protective layer 318 is substantially similar to the protective layer 218 described in connection with Figure 2.

[0047] It is to be appreciated that the synthetic antiferromagnetic (SAF) layer 150 described in association with Figure 1C may be inserted on the bottom electrode 104 and below the fixed magnet 106 in each of the pSTTM devices 200, 300A and 300B to pin the

magnetization of the fixed magnet 106. In one such embodiment the fixed magnet 106 is disposed above the SAF layer. It is to be appreciated that an additional layer of non-magnetic spacer material may be disposed on the SAF layer 150, below the fixed magnet 106. A non- magnetic spacer layer enables coupling between the SAF layer 150 and the fixed magnet 106. In an embodiment, a non-magnetic spacer layer may include metals such as Ta, Ru or Ir.

[0048] Figure 4A-4F illustrate cross-sectional views representing various operations in a method of fabricating a pSTTM material layer stack.

[0049] Figure 4A illustrates a conductive interconnect 402 surrounded by a dielectric layer 401 formed above a substrate 400 and the formation of a bottom electrode layer 403 on the conductive interconnect 402. In an embodiment, the conductive interconnect 402 is formed in a dielectric layer 401 by a damascene or a dual damascene process that is well known in the art. In an embodiment, the conductive interconnect 402 includes a barrier layer, such as tantalum nitride, and a fill metal, such as copper, tungsten or ruthenium. In an embodiment, the conductive interconnect 402 is fabricated using a subtractive etch process when materials other than copper are utilized. In an embodiment, the dielectric layer 401 includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the dielectric layer 401 has an uppermost surface substantially co-planar with an uppermost surface of the conductive interconnect 402. In an embodiment, the dielectric layer 401 has a total thickness between 1500A - 3000A. In an embodiment, conductive interconnect 402 is electrically connected to a circuit element such as a transistor (not shown).

[0050] In an embodiment, the bottom electrode layer 403 is blanket deposited onto an uppermost surface of the conductive interconnect 402 and on an upper most surface of the dielectric layer 401. In an embodiment, the bottom electrode layer 403 is deposited using a physical vapor deposition (PVD) process or a plasma enhanced chemical vapor deposition

(PECVD) process. In an embodiment, the bottom electrode layer 403 includes a metal such as but not limited to W, Ru, Ti or Ta or an alloy such as but not limited to WN, TiN or TaN. In an embodiment, the bottom electrode layer 403 is deposited to a thickness between 30nm to 50nm.

[0051] In an embodiment the bottom electrode layer 403 is first blanket deposited on an uppermost surface of the conductive interconnect 402 and on an upper most surface of the dielectric layer 401, and subsequently polished to achieve a surface roughness of 1 nm or less. In an embodiment, the planarization process includes a chemical mechanical polish (CMP) process to form a topographically smooth uppermost surface having a surface roughness of less than lnm. A surface roughness of less than 1 nm is sufficient to enable a subsequent fixed magnetic layer and a tunnel barrier layer to be formed with well-ordered crystal planes. The formation of a well ordered crystalline tunnel barrier layer 407 on a fixed magnetic layer 405 with a <001> orientation, with respect to the substrate, can help to preserve a quantity known as tunneling magneto-resistance ratio of the pSTTM material layer stack. The TMR of the pSTTM material layer stack is proportional to the difference between the magnitude of the high resistance state and the low resistance state of the pSTTM device.

[0052] In an embodiment, the substrate 400 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials such as germanium, silicon germanium or a suitable group III-V compound.

[0053] Figure 4B illustrates a cross-sectional view of the structure in Figure 4A following the formation of various layers of a pSTTM device, in an accordance with an embodiment of the present invention. A fixed magnetic layer 405 is deposited on the bottom electrode layer 403. In an embodiment, the fixed magnetic layer 405 is blanket deposited using a physical vapor deposition (PVD) process. In an embodiment, the PVD process forms a fixed magnetic layer 405 that is amorphous in nature. In an embodiment, the fixed magnetic layer 405 includes an alloy such as but not limited to CoFe, CoFeB and FeB. In an embodiment, fixed magnetic layer 405 includes a Coi-x-yFe_xBy, where X and Y each represent atomic percent, further where X is between 0.5-0.8 and Y is between 0.1-0.4, and further where the sum of X and Y is less than 1. In one specific embodiment, X is 0.6 and Y is 0.2. In an embodiment, the fixed magnetic layer 405 is blanket deposited to a thickness between l-2nm. The PVD deposition process ensures that the fixed magnetic layer 405 has thickness uniformity that is uniform to within 1% of the film thickness across an entire substrate.

[0054] A tunnel barrier layer 407 is then blanket deposited on the fixed magnetic layer

405. In an embodiment, the tunnel barrier layer 407 includes a material such as MgO or AI2O3. In an embodiment, the tunnel barrier layer 407 is an MgO and is deposited using a reactive sputter process. In an embodiment, the reactive sputter process is carried out at room

temperature. In an embodiment, the MgO is deposited to a thickness between 0.8 to lnm. In an embodiment, the deposition process is carried out in a manner that yields a tunnel barrier layer 407 having a mostly crystalline structure. In an embodiment, the tunnel barrier layer 407 becomes highly crystalline after an anneal process.

[0055] A free magnetic layer 409 is then deposited on the uppermost surface of the tunnel barrier 407. In an embodiment, the free magnetic layer 409 is blanket deposited using a PVD process. In an embodiment, the PVD process forms a free magnetic layer 409 that is amorphous. In an embodiment, the free magnetic layer 409 includes an alloy such as CoFe and CoFeB. In an embodiment, free magnetic layer 409 includes a Coi-x-yFe_xBy, where X and Y each represent atomic percent, further where X is between 0.5-0.8 and Y is between 0.1-0.4, and further where the sum of X and Y is less than 1. In one specific embodiment, X is 0.6 and Y is 0.2. In an embodiment, the free magnetic layer 409 is blanket deposited with a boron content of at least 20% to ensure lattice matching with the tunnel barrier 407. In an embodiment, free magnetic layer 409 is deposited to a thickness between 1.0-2.8nm. Exemplary thickness of the free magnetic layer is 1.5nm.

[0056] Figure 4C illustrates a cross-sectional view of the structure of Figure 4B following the formation of an oxide layer 411 to complete formation of a pSTTM material layer stack 440, in an embodiment of the present invention. The oxide layer 411 is formed on the uppermost surface of the free magnetic layer 409 to increase the interfacial perpendicular magnetic anisotropy of the pSTTM material layer stack 440. Unlike the tunnel barrier layer 405, the oxide layer 411 does not act as a spin filter. In an embodiment, the oxide layer 411 includes a first bilayer stack 411C of metal oxides and a second bilayer stack 41 ID of metal oxides as illustrated in Figure 4C.

[0057] The oxide deposition process includes forming a first metal oxide 411 A on the free magnetic layer 409. In an embodiment, a first metal is deposited onto an uppermost surface of the free magnetic layer 409 and then oxidized to form the first metal oxide 411 A. In an embodiment, the first metal such as magnesium is sputter deposited onto the surface of the free magnetic layer 409. In an embodiment, the process includes DC sputter deposition carried out at ambient temperatures of less than 300K. The relatively low atomic mass of Mg sufficiently prevents the underlying free magnetic layer 409 from becoming damaged during the sputter deposition process. In an embodiment, the first layer of a metal is deposited to a thickness of 0.15-0.6nm. The as-deposited layer of the metal is immediately oxidized to form a first metal oxide 411 A. In an embodiment, the oxidation process includes subjecting the first metal to a low pressure 02 gas operating at a pressure between 3-750mtorr. A combination of the relatively thin layer of metal, having a thickness less than lnm and a reactive oxygen gas results in the first metal oxide 411 A to become uniformly oxidized. The oxidation process takes place after blanket deposition of the layer of metal to avoid oxidation of the free magnetic layer 409. Thus, it is to be appreciated that depositing a uniform layer of metal on the surface of the free magnetic layer 409 is highly desirable to prevent any portion of the free magnetic layer 409 from becoming oxidized. Oxidation of the free magnetic layer 409 may destroy the interfacial perpendicular magnetic anisotropy of the free magnetic layer 409 and affect spin torque transfer switching characteristics of the pSTTM device that will ultimately be formed. For this reason, the lowest layer of metal deposited to form the bilayer stack of metal oxides, can be thicker than subsequent layer of metal that is deposited to form the second metal oxide to ensure that the layer of metal covers the surface of the free magnetic layer 409. In an embodiment, a second metal oxide 41 IB is formed on the first metal oxide 411 A using a similar process. In an embodiment, a second metal is deposited on the surface of the first metal oxide 411 A and then oxidized in a similar manner as the first metal, to form the second metal oxide 41 IB.

[0058] In an embodiment, the first metal deposited on the surface of the free magnetic layer 409 is Mg and the resulting first metal oxide 411 A is an MgO. In an embodiment, a second metal such as aluminum is deposited on the surface of the MgO-first metal oxide 411 A and then oxidized to form an Al₂03-second metal oxide 41 IB. The deposition of the Al₂0₃-second metal oxide 41 IB on the MgO-first metal oxide 411 A results in the formation of the first bilayer stack 411C of metal oxides. [0059] In an embodiment, the first metal deposited on the surface of the free magnetic layer 409 is aluminum and the resulting first metal oxide 411 A is an AI2O3. In an embodiment, a second metal such as magnesium is deposited on the surface of the AhCb-first metal oxide 411 A and then oxidized to form an MgO-second metal oxide 41 IB. The deposition of the MgO- second metal oxide 41 IB on the AhCb-first metal oxide 411 A results in the formation of the first bilayer stack 411C of metal oxides.

[0060] In an embodiment, the sputter deposition and oxidation process is subsequently repeated to form a second bilayer stack 41 ID of metal oxides, including the first metal oxide 411 A and the second metal oxide 41 IB as illustrated in Figure 4F. In an embodiment, the oxide layer 411 shown in Figure 4F includes alternating layers of MgO and Al₂Ox, where X is substantially close to 3. In one such embodiment, the layer of MgO is deposited on the surface of the free magnetic layer 409. In another embodiment, the oxide layer 411 shown in Figure 4F includes alternating layers of Al₂Ox (where X is substantially close to 3) and MgO. In one such embodiment, the layer of Al₂Ox is deposited on the uppermost surface of the free magnetic layer 409. In an embodiment, the oxide layer 411 can be formed by sequentially depositing anywhere from 3-6 bilayers of metal oxides although only two such stacks of bilayers are shown in Figure 4C.

[0061] In an embodiment, the oxide layer 411 is deposited to a thickness between 0.3nm-

1.8nm. In an embodiment, the oxide layer 411 is deposited to a total thickness of 0.9nm. In an embodiment, the thickness of the first metal oxide 411 A is greater than the thickness of the second metal oxide 41 IB. In an embodiment, the first metal oxide 411 A is deposited to a thickness between 0.3nm-0.6nm. and the second metal oxide 41 IB in the oxide layer 411 is deposited to a thickness between 0.15nm-0.3nm. In an embodiment, the first bilayer stack 411C has a first metal oxide 411 A that is greater than the thickness of the first metal oxide 411 A in the second bilayer stack 41 ID. In an embodiment, the first metal oxide 411 A in the first bilayer stack 411C includes a layer of magnesium and has a thickness of 0.6nm, and the first metal oxide 411 A in the second bilayer stack 41 ID includes a magnesium and has a thickness of 0.2nm. In an embodiment, the first bilayer stack 411C has a second metal oxide 41 IB that has a thickness that is equal to the thickness of the second metal oxide 41 IB in the second bilayer stack 41 ID. In an embodiment, the second metal oxide 41 IB in the first bilayer stack 411C includes a layer of aluminum and has a thickness of 0.2nm, and the second metal oxide 41 IB in the second bilayer stack 41 ID includes an aluminum and has a thickness of 0.2nm.

[0062] In an embodiment, a capping metal layer 413 is blanket deposited on the surface of the second metal oxide 41 IB to prevent damage of the second metal oxide during deposition of a subsequent adhesion layer. In an embodiment, the capping layer 413 includes a metal such as the metal of the first metal oxide 411 A. In an embodiment, the capping layer includes a layer of magnesium metal. In an embodiment, the capping layer 413 is deposited to a thickness of 0.15nm-0.3nm.

[0063] In a different embodiment, the oxide layer 411 is a bimetal oxide. In an embodiment, the bimetal oxide is formed by oxidizing a bimetal alloy. In an embodiment, the fabrication of the bimetal oxide begins by first reactively sputtering two different metals to form a metal alloy on the surface of the free magnetic layer 409. In an embodiment, embodiment, a DC sputter process is utilized to form a metal alloy on the surface of the free magnetic layer 409. In an embodiment, the metal includes magnesium and aluminum. The sputtered magnesium and aluminum form, Al-Al, Mg-Mg, and Mg-Al bonds on the surface of the free magnetic layer 409. Once formed on the free magnetic layer 409, the metal alloy containing Al and Mg is

subsequently oxidized by an oxygen containing plasma, similar to the oxygen plasma used to the form the single metal oxide layer 411 A and 41 IB, to oxidize the Al and Mg. The oxidation process results in formation of a magnesium aluminum oxide layer where the magnesium oxygen and the aluminum are stoichiometrically bound to form the metal oxide layer 411. In an embodiment, the ratio of the Mg to Al in the bimetal oxide is at least 1.5: 1 but can be as high as 3 : 1. In another embodiment, the ratio of the Al to Mg in the bimetal oxide is at least 1.5: 1 but can be as high as 3 : 1. In an embodiment, the oxide layer 411 includes bimetal oxide such as [0064] In an embodiment, the process of forming the bimetal oxide may be repeated anywhere from 3-5 times to form the oxide layer 411. In an embodiment, the oxide layer 411 is deposited to a total thickness between 0.3-1.8nm. In an embodiment, the magnesium aluminum oxide has an ordered crystal structure that templates from the underlying free magnetic layer 409. In an embodiment, the ordered crystal structure has a <001> orientation. In an

embodiment, a capping layer 413 can be formed on the bimetal oxide.

[0065] Figure 4D illustrates a cross-sectional view of the structure of Figure 4C following the formation of an adhesion layer 415 on the pSTTM material layer stack 440 and the formation of a top electrode layer 419 on the adhesion layer 415, in an embodiment of the present invention. The adhesion layer 415 is formed above the oxide layer 411. In an embodiment, the adhesion layer 415 is formed on the capping layer 413 as illustrated in Figure 4D. In other embodiments, the adhesion layer 415 is deposited on the bimetal oxide layer described above. In an embodiment, the adhesion layer 415 is deposited to a thickness between 2-5nm using a PVD deposition process. The adhesion layer 415 includes a layer of metal such as but not limited to Ta or Ti.

[0066] In an embodiment, the top electrode layer 419 is blanket deposited on the adhesion layer 415 using a PVD deposition process. In an embodiment, the top electrode layer 419 includes a material such as Ta or an alloy such as TaN. In an embodiment, the thickness of the top electrode layer 419 ranges from 30nm-70nm. The thickness is chosen to provide etch resistivity during etching of the pSTTM material layer stack 440.

[0067] In an embodiment, after all the layers in the pSTTM material layer stack 440 are deposited, an anneal is performed under conditions well known in the art to promote solid phase epitaxy of the free magnetic layer 409 following a template of a crystalline layer of the tunnel barrier layer 407. A post-deposition anneal of the pSTTM material layer stack 440 is carried out in a furnace at a temperature between 300-400 degrees C. In an embodiment, the anneal is performed immediately post deposition but before patterning of the pSTTM material layer stack 440 to enable crystalline MgO to be formed in the tunnel barrier layer 407. The annealing process also enables boron to diffuse away from an interface 453 between the tunnel barrier layer 407 and the free magnetic layer 409. The process of diffusing boron away from the interface 453 enables lattice matching between the free magnetic layer 409 and the tunnel barrier 407.

[0068] In an embodiment, the annealing process is also performed in the presence of a magnetic field which sets the magnetization direction of the fixed magnetic layer 405 and the free magnetic layer 409. An applied magnetic field that is directed parallel to the vertical axis of the pSTTM material layer stack 440, during the annealing process, enables a perpendicular anisotropy to be set in the fixed magnetic layer 405 and in the free magnetic layer 409. The annealing process initially aligns the magnetization of the fixed magnetic layer 405 and the free magnetic layer 409 to be parallel to each other.

[0069] In an embodiment, when the oxide layer 411 includes one or more bilayers of metal oxides including MgO and AI2O3, the annealing process shrinks the MgO material in the first metal oxide 411 A but expands the AI2O3 in the second metal oxide 41 IB. The shrinking of the MgO material in the first metal oxide 411 A leads to pinhole defects to be formed in the first metal oxide 411 A. However, the expansion of the AI2O3 in the second metal oxide 41 IB fills most of the pin hole defects that are formed in the MgO material in the oxide layer 411, leading to a relatively defect free oxide layer 411.

[0070] It is to be appreciated that, in an embodiment, an SAF layer such as a SAF layer 150 (described in association with Figure 1C) can be formed on the bottom electrode layer 403 by a PVD process. Additional layers of non-magnetic spacer materials may be deposited on the SAF layer 150 prior to deposition of the fixed magnetic layer 405. A non-magnetic spacer layer is deposited to enable coupling between the SAF and the fixed magnetic layer 405. In an embodiment, a non magnetic spacer layer may include metals such as Ta, Ru or Ir.

[0071] Figure 4E illustrates a cross-sectional view of the structure in Figure 4D following an etch process to pattern the pSTTM material layer stack 440 to form a pSTTM device 450. In an embodiment, a layer photoresist (not shown) is formed above the top electrode layer 419. In an embodiment, the photoresist is patterned using well known lithographic processes known in the art. The lithography process defines the shape and size of the pSTTM device and a location where the pSTTM device is to be formed with respect the conductive interconnect 402. The hardmask is then etched using the photoresist mask and the patterned hardmask is used to subsequently pattern the top electrode layer 419, the adhesion layer 415 and the pSTTM material layer stack 440 and the bottom electrode layer 403. In an embodiment, a plasma etch process is utilized to etch top electrode layer 419 to form a top electrode 420, the adhesion layer 415 to form an adhesion barrier 416, the pSTTM material layer stack 440 to form an oxide layer 412, a free magnet 410, a tunnel barrier 408, a fixed magnet 406. The plasma etch also forms a bottom electrode 404 as illustrated in Figure 4E. In an embodiment, almost 30-50% of the top electrode 420 may be consumed during the etch process. In an embodiment, the plasma etch forms a pSTTM device 450 with a tapered profile. While a highly energetic plasma etch can produce a vertical profile of the pSTTM material layer stack 440, a tapered profile (indicated by dashed lines 460) results when nonvolatile etch residue is deposited onto the sidewalls of the patterned material layer stack 440. In an embodiment, the nonvolatile etch residue extending from the fixed magnet 406 to the free magnet 410 may be conductive and can lead to electrical shorting between the fixed and the free magnets 406 and 410, respectively. In an embodiment, a second clean-up etch process is carried out to remove the etch residue from sidewalls of the tunnel barrier 408 to sufficiently electrically isolate the free magnet 406 from the fixed magnet 410.

[0072] Referring again to Figure 4E, the pSTTM device 450 has a width that is greater than the width of the conductive interconnect 402. However, the pSTTM device 450 can have a width that is less than the width of the conductive interconnect 402. In such an embodiment, the conductive interconnect 402 will be exposed while etching the bottom electrode layer 404. It is to be appreciated that the plasma etch process utilized to etch the bottom electrode 404, includes etch chemistry that does not react with or sputter the material of the conductive interconnect 402. When the conductive interconnect 402 includes copper, etch chemistry for patterning the bottom electrode layer 403 excludes corrosive etch gases such as chlorine.

[0073] Figure 4F illustrates a cross-sectional view of the pSTTM device 450 in Figure

4D following the formation of a dielectric spacer layer 480 on the top electrode 420, on the sidewalls of the pSTTM material layer stack 440, and on an uppermost surface of the dielectric layer 401. In an embodiment, the dielectric spacer layer 480 is in-situ deposited immediately following the plasma etch process utilized to form the pSTTM device 450. [0074] In an embodiment, the dielectric spacer layer 480 includes a material such as silicon nitride, silicon dioxide or carbon doped silicon nitride. In an embodiment, the dielectric spacer layer 480 is chosen to exclude oxygen containing material to prevent oxidation of magnetic layers after the clean-up etch process. In an embodiment, the dielectric spacer layer 480 is deposited at a process temperature of less than 300 degrees C. In an embodiment, the dielectric spacer layer 480 is deposited to a thickness between 10-20nm. In an embodiment, the dielectric spacer layer 480 is plasma etched (not shown).

[0075] In an embodiment, a second anneal process can be performed after formation of the PSTTM device 450. In an embodiment, the second anneal process is carried out at a process temperature of at least 300 degrees Celsius but less than 500 degrees Celsius. In an embodiment, the post process anneal can help to recrystallize sidewalls of the tunnel barrier 408 that may have become potentially damaged during the etching process utilized to form the pSTTM device 450.

[0076] Figure 5 illustrates an PSTTM memory device 500, formed on a conductive interconnect 502. In an embodiment, the conductive interconnect is disposed on a contact structure 504 above a drain region 506 of an access transistor 508 disposed above a substrate 510. In an embodiment, the pSTTM material layer stack 440 described in Figure 4C is blanket deposited on a conductive interconnect 502, lithographically patterned and then etched to form an PSTTM memory device 500 as is illustrated in Figure 5. In an embodiment, the PSTTM memory device 500 includes an oxide layer 112 disposed on the free magnet 110. The oxide layer 112 includes a first metal oxide 112A and a second metal oxide 112B, disposed on the first metal oxide 112A and a capping metal layer 116 disposed on the second metal oxide 112B. The pSTTM device 500 further includes a spacer layer 501 disposed laterally around the pSTTM device 500. In an embodiment, the pSTTM memory device 500 has a width that is greater than the width of the conductive interconnect 502. In one such embodiment, a portion of the bottom electrode 104 of pSTTM memory device 500 is also disposed on a dielectric layer 503. In an embodiment, the pSTTM memory device 500 has a width less than the width of the conductive interconnect 502. In an embodiment, the pSTTM memory device 500 has a width equal to the width of the conductive interconnect 502.

[0077] In an embodiment, the underlying substrate 510 represents a surface used to manufacture integrated circuits. Suitable substrate 510 includes a material such as single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The substrate 510 may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.

[0078] In an embodiment, the access transistor 508 associated with substrate 510 are metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate 510. In various implementations of the invention, the access transistor 508 may be planar transistors, nonplanar transistors, or a combination of both.

Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

[0079] In an embodiment, the access transistor 508 of substrate 510 includes a gate stack formed of at least two layers, a gate dielectric layer 514 and a gate electrode layer 512. The gate dielectric layer 514 may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer 514 to improve its quality when a high-k material is used.

[0080] The gate electrode layer 512 of the access transistor 508 of substrate 510 is formed on the gate dielectric layer 514 and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an

MOS transistor. In some implementations, the gate electrode layer 512 may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer.

[0081] For a PMOS transistor, metals that may be used for the gate electrode layer 512 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

[0082] In some implementations, the gate electrode may consist of a "U'-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode 512 may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may consist of a combination of U- shaped structures and planar, non-U-shaped structures. For example, the gate electrode 512 may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0083] In some implementations of the invention, a pair of sidewall spacers 516 may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers 516 may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0084] As is well known in the art, source region 518 and drain region 506 are formed within the substrate adjacent to the gate stack of each MOS transistor. The source region 518 and drain region 506 are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source region 518 and drain region 506. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source region 518 and drain region 506. In some implementations, the source region 518 and drain region 506 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source region 518 and drain region 506 may be formed using one or more alternate semiconductor materials such as germanium or a suitable group III-V compound. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source region 518 and drain region 506.

[0085] In an embodiment, a gate contact 520 and a source contact 522 are formed in a second dielectric layer 524 and in the dielectric layer 503 above the gate electrode 512 and source region 518, respectively. [0086] Figure 6 illustrates a computing device 600 in accordance with one embodiment of the invention. The computing device 600 houses a motherboard 602. The motherboard 602 may include a number of components, including but not limited to a processor 604 and at least one communication chip 606. The processor 604 is physically and electrically coupled to the motherboard 602. In some implementations the at least one communication chip 606 is also physically and electrically coupled to the motherboard 602. In further implementations, the communication chip 606 is part of the processsor 604.

[0087] Depending on its applications, computing device 600 may include other components that may or may not be physically and electrically coupled to the motherboard 602. These other components include, but are not limited to, volatile memory (e.g., DRAM), nonvolatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

[0088] The communication chip 606 enables wireless communications for the transfer of data to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 606 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 600 may include a plurality of communication chips 606. For instance, a first communication chip 606 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 606 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0089] The processor 604 of the computing device 600 includes an integrated circuit die packaged within the processor 604. In some implementations of embodiments of the invention, the integrated circuit die of the processor includes one or more memory devices, such as an PSTTM memory device 500, built with a PSTTM material layer stack 440 in accordance with embodiments of the present invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[0090] The communication chip 606 also includes an integrated circuit die packaged within the communication chip 606. In accordance with another implementation of an embodiment of the invention, the integrated circuit die of the communication chip includes PSTTM memory elements integrated with access transistors, built in accordance with

embodiments of the present invention.

[0091] In further implementations, another component housed within the computing device 600 may contain a stand-alone integrated circuit memory die that includes one or more memory elements, built in accordance with embodiments of the present invention.

[0092] In various implementations, the computing device 600 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 600 may be any other electronic device that processes data

[0093] Figure 7 illustrates an interposer 700 that includes one or more embodiments of the invention. The interposer 700 is an intervening substrate used to bridge a first substrate 702 to a second substrate 704. The first substrate 702 may be, for instance, an integrated circuit die. The second substrate 704 may be, for instance, a memory module, a computer mother, or another integrated circuit die. Generally, the purpose of an interposer 700 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 700 may couple an integrated circuit die to a ball grid array (BGA) 706 that can subsequently be coupled to the second substrate 704. In some embodiments, the first and second substrates

702/704 are attached to opposing sides of the interposer 700. In other embodiments, the first and second substrates 702/704 are attached to the same side of the interposer 700. And in further embodiments, three or more substrates are interconnected by way of the interposer 700.

[0094] The interposer 700 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further

implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

[0095] The interposer may include metal interconnects 708 and vias 999, including but not limited to through-silicon vias (TSVs) 999. The interposer 700 may further include embedded devices 714, including both passive and active devices. Such devices include, but are not limited to, capacity ors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, transistors, pSTTM devices, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 700. In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer 700.

[0096] Accordingly, one or more embodiments of the present invention relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be non-volatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present invention relate to the fabrication of a pSTTM device 450. A large array of consisting of pSTTM device 450 may be used in an embedded non-volatile memory application.

[0097] Thus, embodiments of the present invention include perpendicular spin transfer torque memory (pSTTM) devices with enhanced perpendicular anisotropy and methods to form the same.

[0098] Specific embodiments are described herein with respect to perpendicular spin transfer torque memory (pSTTM) devices. It is to be appreciated that embodiments described herein may also be applicable to other non-volatile memory devices. Such non-volatile memory devices may include, but are not limited to, magnetic random access memory (MRAM) devices, spin torque transfer memory (STTM) devices and spin orbit torque (SOT) memory devices.

[0099] Example 1 : A magnetic tunnel junction (pSTTM) device, includes a bottom electrode, a fixed magnet disposed above the bottom electrode, a tunnel barrier disposed above the fixed magnet, a free magnet disposed on the tunnel barrier, an oxide layer disposed above the free magnet. The oxide layer comprises a stack of metal oxides, wherein the stack of metal oxides comprises a first metal oxide and a second metal oxide disposed on the first metal oxide. The first metal oxide includes a metal different from a metal of the second metal oxide. A top electrode is disposed above the oxide layer.

[00100] Example 2: The pSTTM device of example 1, wherein the stack of metal oxides further includes a third metal oxide disposed on the second metal oxide.

[00101] Example 3 : The pSTTM device of example 2, wherein the stack of metal oxides further includes a fourth metal oxide disposed on the third metal oxide.

[00102] Example 4: The pSTTM device of example 3, wherein the third metal oxide has the same metal as the metal of the first metal oxide and the fourth metal oxide has the same metal as the metal of the second metal oxide. [00103] Example 5: The pSTTM device of example 1, 2 or 3 wherein the stack of metal oxides further includes a layer of metal disposed on the stack of metal oxides, of the layer of metal comprising a same metal as the metal of the first metal oxide.

[00104] Example 6: The pSTTM device of example 1, wherein the metal of the first metal oxide is Mg and wherein the metal of the second metal oxide is Al.

[00105] Example 7: The pSTTM device of example 5, wherein the metal of the first metal oxide is Mg and wherein the metal of the second metal oxide is Al and the layer of metal includes Mg.

[00106] Example 8: The pSTTM device of example 1, wherein the oxide layer has a thickness between 0.6-1.0nm.

[00107] Example 9: The pSTTM device of example 4, wherein the oxide layer has a thickness between 0.6-1.3nm.

[00108] Example 10: The pSTTM device of example 4, wherein the oxide layer has an electrical resistance less than an electrical resistance of the tunnel barrier.

[00109] Example 11 : The pSTTM device of example 4, wherein a capping layer is disposed above the oxide layer.

[00110] Example 12: A perpendicular spin transfer torque memory (pSTTM) device includes a bottom electrode, a fixed magnet disposed above the bottom electrode, a tunnel barrier disposed above the fixed magnet, a free magnet disposed on the tunnel barrier. An oxide layer is disposed above the free magnet, wherein the oxide layer comprises a first metal, a second metal, and oxygen, and wherein the second metal is different from the first metal. A top electrode is disposed above the oxide layer.

[00111] Example 13 : The pSTTM device of example 12, wherein the first metal is Mg, and the second metal is Al.

[00112] Example 14: The pSTTM device of example 12, wherein the oxide layer includes a bimetal oxide including Mg, Al and oxygen, and has a crystal structure.

[00113] Example 15: The pSTTM device of example 12 or 13, wherein the oxide layer includes a bimetal oxide including Mg, Al and oxygen, and has a polycrystalline structure.

[00114] Example 16: The pSTTM device of example 12, 13, or 14, wherein the ratio of the Mg to Al in the oxide layer is at least 1.5: 1.

[00115] Example 17: The pSTTM device of example 14, wherein the oxide layer is

MGA1₂0₄.

[00116] Example 18: A method of fabricating a material layer stack for a perpendicular spin transfer torque memory (pSTTM) device includes forming a conductive interconnect structure, forming a bottom electrode layer on the conductive interconnect structure, forming a fixed magnetic layer above the bottom electrode, forming a tunnel barrier on the fixed magnetic layer, forming a free magnetic layer on the tunnel barrier. The method further includes forming an oxide layer on the free magnetic layer, wherein the oxide layer includes at least two distinct metals. The method further includes forming an adhesion layer on the oxide layer and forming a top electrode layer on the adhesion layer. The method of etching the top electrode layer by forming a mask above the top electrode layer. The method further includes etching the material layer stack to form a pSTTM device having sidewalls and forming a dielectric spacer layer laterally surrounding the pSTTM device.

[00117] Example 19: The method of example 18, wherein forming the oxide layer includes forming a bilayer stack of metal oxides, wherein the forming includes forming a first metal oxide on the free layer. Forming the first metal oxide includes sputter depositing a first metal on the oxide layer and oxidizing the first metal. The method further includes forming a second metal oxide on the first metal oxide, wherein the forming includes sputter depositing a second metal on the first metal oxide and oxidizing the second metal.

[00118] Example 20: The method of example 19, wherein a metal layer is formed on the oxide layer and wherein the forming includes depositing a same metal as the metal of first metal oxide.

[00119] Example 21 : The method of example 19, wherein forming the oxide layer further includes forming a second bilayer stack of metal oxides on the bilayer stack of metal oxides. The method of forming the second bilayer stack of metal oxides includes forming the first metal oxide, wherein forming the first metal oxide includes sputter depositing the first metal on an uppermost surface of the bilayer stack of metal oxides and oxidizing the first metal. The method further includes forming the second metal oxide on the first metal oxide, wherein the forming the second metal oxide includes sputter depositing the second metal on the first metal oxide and oxidizing the second metal.

[00120] Example 22: The method of example 18, wherein forming the oxide layer includes forming a metal alloy, wherein forming the metal alloy includes sputter depositing a first metal along with a second metal to form the metal alloy on the free layer and oxidizing the metal alloy to form an oxidized metal alloy.

[00121] Example 23 : The method of example 22, further includes forming a second metal alloy on the oxidized metal alloy, wherein forming the second metal alloy includes sputter depositing the first metal along with the second metal to form the second metal alloy and oxidizing the second metal alloy to form an oxidized second metal alloy.

[00122] Example 24: The method of example 23, wherein forming the oxide layer includes repeating sputter deposition and oxidation of the metal alloy and deposition of and oxidation of the second metal alloy on the oxidized metal alloy between 2-5 times to form an oxide layer with uniform composition.

Claims

CLAIMS What is claimed is:

1. A perpendicular spin transfer torque memory (pSTTM) device, comprising:

a bottom electrode above a substrate;

a fixed magnet above the bottom electrode;

a tunnel barrier above the fixed magnet;

a free magnet on the tunnel barrier;

an oxide layer above the free magnet, wherein the oxide layer comprises a stack of metal oxides, wherein the stack of metal oxides comprises a first metal oxide and a second metal oxide on the first metal oxide, and wherein the first metal oxide comprises a metal different from a metal of the second metal oxide; and

a top electrode above the oxide layer.

2. The pSTTM device of claim 1, wherein the stack of metal oxides further includes a third metal oxide on the second metal oxide.

3. The pSTTM device of claim 2, wherein the stack of metal oxides further includes a fourth metal oxide on the third metal oxide.

4. The pSTTM device of claim 3, wherein the third metal oxide has the same metal as the metal of the first metal oxide and the fourth metal oxide has the same metal as the metal of the second metal oxide.

5. The pSTTM device of claim 1, wherein the stack of metal oxides further includes a layer of metal on the stack of metal oxides, of the layer of metal comprising a same metal as the metal of the first metal oxide.

6. The pSTTM device of claim 1, wherein the metal of the first metal oxide is Mg and wherein the metal of the second metal oxide is Al.

7. The pSTTM device of claim 5, wherein the metal of the first metal oxide is Mg and wherein the metal of the second metal oxide is Al and the layer of metal includes Mg.

8. The pSTTM device of claim 1, wherein the oxide layer has a thickness between 0.6-1.Onm.

9. The pSTTM device of claim 4, wherein the oxide layer has a thickness between 0.6-1.3nm.

10. The pSTTM device of claim 4, wherein the oxide layer has an electrical resistance less than an electrical resistance of the tunnel barrier.

11. The pSTTM device of claim 4, wherein a capping layer is above the oxide layer.

12. A perpendicular spin transfer torque memory (pSTTM) device, comprising:

a bottom electrode above a substrate;

a fixed magnet above the bottom electrode;

a tunnel barrier above the fixed magnet;

a free magnet on the tunnel barrier;

an oxide layer above the free magnet, wherein the oxide layer comprises a first metal, a second metal, and oxygen, and wherein the second metal is different from the first metal; and a top electrode above the oxide layer.

13. The pSTTM device of claim 12, wherein the first metal is Mg, and the second metal is Al.

14. The pSTTM device of claim 12, wherein the oxide layer includes a bimetal oxide including Mg, Al and oxygen, and has a crystal structure.

15. The pSTTM device of claim 12, wherein the oxide layer includes a bimetal oxide including Mg, Al and oxygen, and has a polycrystalline structure.

16. The pSTTM device of claim 14, wherein the ratio of the Mg to Al in the oxide layer is at least 1.5: 1.

17. The pSTTM device of claim 14, wherein the oxide layer is MGA1₂0₄.

18. A method of fabricating a material layer stack for a perpendicular spin transfer torque memory (pSTTM) device, the method comprising:

forming a conductive interconnect structure;

forming a bottom electrode layer on the conductive interconnect structure;

forming a fixed magnetic layer above the bottom electrode layer; forming a tunnel barrier on the fixed magnetic layer;

forming a free magnetic layer on the tunnel barrier;

forming an oxide layer on the coupling layer, wherein the oxide layer includes at least two distinct metals;

forming an adhesion layer on the oxide layer;

forming a top electrode layer on the adhesion layer;

etching the top electrode layer by forming a mask above the top electrode layer;

etching the material layer stack to form a pSTTM device having sidewalls; and forming a dielectric spacer layer laterally surrounding the pSTTM device.

19. The method of example 18, wherein forming the oxide layer includes forming a bilayer stack of metal oxides, wherein the forming includes:

forming a first metal oxide on the free layer, wherein the forming includes sputter depositing a first metal on the free magnetic layer and oxidizing the first metal; and

forming a second metal oxide on the first metal oxide, wherein the forming includes sputter depositing a second metal on the first metal oxide and oxidizing the second metal.

20. The method of claim 19, wherein a metal layer is formed on the oxide layer and wherein the forming includes depositing a same metal as the metal of first metal oxide.

21. The method of claim 19, wherein forming the oxide layer further includes forming a second bilayer stack of metal oxides on the bilayer stack of metal oxides, wherein forming the second bilayer stack of metal oxides includes:

forming the first metal oxide, wherein the forming includes sputter depositing the first metal on an uppermost surface of the second metal oxide and oxidizing the metal; and

forming the second metal oxide on the first metal oxide, wherein the forming includes sputter depositing the second metal on the first metal oxide and oxidizing the second metal.

The method of claim 18, wherein forming the oxide layer includes:

forming a metal alloy, wherein forming the metal alloy includes sputter depositing a first metal along with a second metal to form the metal alloy on the free magnetic layer; and

oxidizing the metal alloy to form an oxidized metal alloy.

The method of claim 22, further includes: forming a second metal alloy on the oxidized metal alloy, wherein forming the second metal alloy includes sputter depositing the first metal along with the second metal to form the second metal alloy; and

oxidizing the second metal alloy to form an oxidized second metal alloy.

24. The method of claim 23, wherein forming the oxide layer includes repeating sputter deposition and oxidation of the metal alloy and deposition of and oxidation of the second metal alloy on the oxidized metal alloy between 2-5 times to form an oxide layer with uniform composition.