WO2018182650A1

WO2018182650A1 - Perpendicular spin transfer torque memory (psttm) devices with enhanced stability and methods to form same

Info

Publication number: WO2018182650A1
Application number: PCT/US2017/025186
Authority: WO
Inventors: Tofizur RAHMAN; Christopher J. WIEGAND; Kaan OGUZ; Justin S. BROCKMAN; Daniel G. OUELLETTE; Kevin P. O'brien; Mark L. Doczy; Brian S. Doyle; Oleg Golonzka; Tahir Ghani
Original assignee: Intel Corporation
Priority date: 2017-03-30
Filing date: 2017-03-30
Publication date: 2018-10-04

Abstract

A material layer stack for a pSTTM memory device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. In an embodiment, the free magnetic layer includes a bilayer stack of magnetic layers. In an embodiment, the bilayer stack includes a layer consisting essentially of iron disposed on a layer of a magnetic alloy including boron and can help to increase thermal stability of the pSTTM memory device.

Description

PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (PSTTM) DEVICES WITH ENHANCED

STABILITY AND METHODS TO FORM SAME

TECHNICAL FIELD

[0001] Embodiments of the invention are in the field of integrated circuit fabrication and, in particular, related to perpendicular spin transfer torque memory (pSTTM) devices with enhanced stability and methods to form the same.

BACKGROUND

[0002] For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

[0003] Non-volatile embedded memory with pSTTM devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. However, the technical challenges of assembling a pSTTM stack to form functional devices present formidable roadblocks to commercialization of this technology today. Specifically, increasing thermal stability and minimizing retention loss of pSTTM devices are some important areas of process development. As such, improvements are still needed in the areas of pSTTM stack development. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 A illustrates a cross-sectional view of a material layer stack including a free magnetic layer having a bilayer stack for a perpendicular STTM device, in accordance with an embodiment of the present invention.

[0005] Figure IB, illustrates a cross-sectional view depicting the direction of

magnetization in a free magnetic layer relative to the direction of magnetization in a fixed magnetic layer, in accordance with an embodiment of the present invention.

[0006] Figure 1C, illustrates a cross-sectional view depicting the direction of

magnetization in a free magnetic layer relative to the direction of magnetization in a fixed magnetic layer, in accordance with an embodiment of the present invention. [0007] Figures ID illustrates a cross-sectional view of individual layers of a synthetic antiferromagnetic layer.

[0008] Figure 2A illustrates a cross-sectional view of a material layer stack having a storage layer that includes a first free magnetic layer, a coupling layer and a second free magnetic layer, wherein the second magnetic layer includes a bilayer stack, in an accordance with an embodiment of the present invention.

[0009] Figure 2B illustrates a cross-sectional view of a material layer stack having a storage layer that includes a first free magnetic layer, a coupling layer and a second free magnetic layer including a bilayer stack, in an accordance with an embodiment of the present invention.

[0010] Figure 2C illustrates a cross-sectional view of a material layer stack having a storage layer that includes a first free magnetic layer, wherein the first free layer includes a bilayer stack, a coupling layer and a second free magnetic layer, in an accordance with an embodiment of the present invention.

[0011] Figure 2D illustrates a cross-sectional view of a material layer stack having a storage layer that includes a first free magnetic layer, wherein the first free layer includes a bilayer stack, a coupling layer and a second free magnetic layer, in an accordance with an embodiment of the present invention.

[0012] Figure 3 A illustrates a cross-sectional view of a material layer stack having storage layer that includes a first free magnetic layer with a first bilayer stack, a coupling layer and a second free magnetic layer including a second bilayer stack, in an accordance with an embodiment of the present invention.

[0013] Figure 3B illustrates a cross-sectional view of a material layer stack having storage layer that includes a first free magnetic layer with a first bilayer stack, a coupling layer and a second free magnetic layer including a second bilayer stack, in an accordance with an embodiment of the present invention.

[0014] Figure 3C illustrates a cross-sectional view of a material layer stack having storage layer that includes a first free magnetic layer with a first bilayer stack, a coupling layer and a second free magnetic layer including a second bilayer stack, in an accordance with an embodiment of the present invention.

[0015] Figure 3D illustrates a cross-sectional view of a material layer stack having storage layer that includes a first free magnetic layer with a first bilayer stack, a coupling layer and a second free magnetic layer including a second bilayer stack, in an accordance with an embodiment of the present invention.

[0016] Figure 4A illustrates a cross-sectional view of a material layer stack having storage layer that includes a first free magnetic layer, a coupling layer and a second free magnetic layer consisting essentially of iron, in an accordance with an embodiment of the present invention.

[0017] Figure 4B illustrates a cross-sectional view of a material layer stack having storage layer that includes a first free magnetic layer with a bilayer stack, a coupling layer and a second free magnetic layer consisting essentially of iron, in an accordance with an embodiment of the present invention.

[0018] Figure 4C illustrates a cross-sectional view of a material layer stack having storage layer that includes a first free magnetic layer with a bilayer stack, a coupling layer and a second free magnetic layer including iron, in an accordance with an embodiment of the present invention.

[0019] Figure 5A-5D illustrate cross-sectional views representing various operations in a method of fabricating a pSTTM device in accordance with embodiments of the present invention.

[0020] Figure 5 A illustrates a cross-sectional view of the formation of a bottom electrode on a conductive interconnect structure formed above a substrate.

[0021] Figure 5B illustrates a cross-sectional view of the structure in Figure 5A following the formation of material stack for a pSTTM device, in accordance with an

embodiment of the present invention.

[0022] Figure 5C illustrates a cross-sectional view of the structure in Figure 5B following patterning of the top electrode layer.

[0023] Figure 5D illustrates a cross-sectional view of the structure in Figure 5C following patterning and etching of the pSTTM material layer stack to form a pSTTM device and the formation of a dielectric spacer adjacent to the pSTTM device.

[0024] Figure 6 illustrates a cross-sectional view of a pSTTM device on a conductive interconnect coupled to a transistor.

[0025] Figure 7 illustrates a computing device in accordance with embodiments of the present invention.

[0026] Figure 8 illustrates an interposer that includes one or more embodiments of the invention.

DESCRIPTION OF THE EMBODIMENTS

[0027] Perpendicular-spin transfer torque memory (pSTTM) devices with enhanced stability and methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as transistor operations and switching operations associated with embedded memory, are described in lesser detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

[0028] A pSTTM device functions as a variable resistor where the resistance of the device may switch between a high resistance state and a low resistance state. The resistance state of a pSTTM device is defined by the relative orientation of magnetization of two magnetic layers (fixed and free) that are separated by a tunnel barrier. When the magnetization of the two magnetic layers have orientations that are in the same direction the pSTTM device is said to be in a low resistance state. Conversely, when the magnetization of the two magnetic layers have orientations that in opposite directions the pSTTM device is said to be in a high resistance state. In an embodiment, the resistance switching is brought about by passing a critical amount of spin polarized current through the pSTTM so as to influence the orientation of the magnetization of the free magnetic layer to align with the magnetization of the fixed magnetic layer. By changing the direction of the current, the magnetization in the free magnetic layer may be reversed relative to that of the fixed magnetic layer. Since the free magnetic layer does not need power to retain relative orientation of magnetization, the resistance state of the pSTTM device is retained even when there is no power applied to the pSTTM device. For this reason, pSTTM belongs to a class of memory known as non-volatile memory.

[0029] Integrating a non-volatile memory device such as a STTM device onto an access transistor enables the formation of embedded memory for system on chip or for other

applications. However, approaches to integrate an STTM device onto an access transistor presents challenges that have become far more formidable with scaling. Examples of such challenges range from improving thermal stability of STTM devices against perturbing forces, minimizing retention loss and enabling patterning of STTM devices at less than 40nm feature sizes. As scaling continues, the need for smaller memory devices to fit into a scaled cell size has driven the industry in the direction of "perpendicular" STTM or pSTTM. Fortunately, while pSTTM devices have higher stability for small memory device sizes, maintaining stability along with improving other device parameters continues to be a challenge.

[0030] As the pSTTM device typically includes a multilayer stack of magnetic and nonmagnetic materials, the stack is engineered to exhibit thermal stability that allows the device to function as a memory device. To an extent, thermal stability of a pSTTM device depends on the strength of the perpendicular magnetic anisotropy of the free magnetic layer or layers in the pSTTM material layer stack. Strength of perpendicular magnetic anisotropy depends on the quality of the free magnetic layer. If there are more than one free magnetic layer, the strength of the perpendicular magnetic anisotropy depends to an extent on the number and quality of interfaces between magnetic and non-magnetic layers in the free magnetic layers. Hence, controlling the degree of thermal stability in such pSTTM devices is partly dictated by the increasing the number of magnetic layers and controlling the desired interfacial properties which give rise to perpendicular magnetic anisotropy in the first place. The magnetism arising from the interfacial properties of the free magnetic layer and the adjacent non-magnetic layer is called interfacial perpendicular magnetic anisotropy.

[0031] A pSTTM device includes a fixed or reference magnetic layer, a tunnel barrier disposed on the fixed magnetic layer and a free magnetic layer, including iron disposed on the tunnel barrier. An oxide layer is generally provided above the free magnetic layer to improve the perpendicularity anisotropy by preserving the interfacial perpendicular magnetic anisotropy at the interface between the oxide layer and the free magnetic layer. Moreover, retention in perpendicular STTM devices is also found to be improved by incorporating the oxide layer above the free magnetic layer. The interfacial perpendicular magnetic anisotropy arises due to bond hybridization between iron in the free magnetic layer and oxygen in the adjacent tunnel barrier below the free magnetic layer and also between iron in the free magnetic layer and oxygen in the adjacent oxide layer above the free magnetic layer. However, oxygen scavenging effects due to the presence of layers above the oxide layer can lead to degradation in interfacial perpendicular anisotropy. Preservation of iron-oxygen hybridization at the interface is enabled by inserting non-oxygen scavenging layers above the oxide layer.

[0032] In accordance with embodiments of the present invention, a material layer stack for a pSTTM memory device includes a fixed magnetic layer, a tunnel barrier such as but not limited to MgO, disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. In an embodiment, the free magnetic layer includes a bilayer stack of magnetic layers. In an embodiment, the bilayer stack includes a layer consisting essentially of iron and a layer of a magnetic alloy including boron. In an embodiment, the layer of magnetic alloy is disposed on the tunnel barrier and the layer of iron is disposed on the layer of magnetic alloy. The presence of boron in the magnetic alloy makes the magnetic alloy amorphous and helps the tunnel barrier to be textured in desired orientation. Boron can also form an oxide at an interface between the tunnel barrier and the magnetic alloy and adversely affect the tunnel barrier crystallinity. The layer of iron disposed on the magnetic alloy enables diffusion of boron away from the tunnel barrier /magnetic alloy interface, and preserves the tunnel barrier crystallinity as well as texture matching between free layer and tunnel barrier layer. Preserving tunneling barrier crystallinity and texture matching helps preserve tunneling magnetoresi stance ratio (TMR) of the pSTTM device. The TMR of a pSTTM device is the ratio of the difference between a high resistance value and a low resistance value divided by the low resistance value of the pSTTM device. Additionally, diffusion of boron away from the tunnel barrier-magnetic alloy interface preserves the interfacial perpendicular magnetic anisotropy at the interface. The interfacial perpendicular magnetic anisotropy at the tunnel barrier-magnetic alloy interface arises due to bond hybridization between iron in the free magnetic layer and oxygen in the tunnel barrier.

[0033] Furthermore, retention in perpendicular STTM devices is also found to be improved by incorporating the single magnetic layer consisting essentially of iron on the layer of magnetic alloy. Retention is inherently associated with thermal stability of a pSTTM device. Thermal stability is directly proportional to the product of the perpendicular magnetic anisotropy and the volume of the free magnetic layer - both of which are increased by the addition of the single magnetic layer consisting essentially of iron on the layer of magnetic alloy.

[0034] Figure 1 A is an illustration of a cross-sectional view of a material layer stack 100 for a pSTTM device in accordance with an embodiment of the present invention. The material layer stack 100 includes a fixed magnetic layer 102 having a perpendicular anisotropy, disposed on a bottom electrode layer 104. A tunnel barrier 106 such as a MgO is disposed on the fixed magnetic layer 102. The material layer stack 100 further includes a free magnetic layer 108 disposed on the tunnel barrier 106.

[0035] In an embodiment, the free magnetic layer 108 is a bilayer stack of magnetic layers. In an embodiment, the bilayer stack includes a first magnetic layer 108 A and a second magnetic layer 108B, consisting essentially of iron, disposed on the first magnetic layer 108A. In an embodiment, the first magnetic layer 108 A includes an alloy such as CoFe and CoFeB. In an embodiment, first magnetic layer 108 A comprises a Coi-x-yFe_xBy, where X is between from 0.5-0.8 and Y is between 0.1-0.4. In one specific embodiment, X is 0.8 and Y is 0.3. In one specific embodiment, X is 0.6 and Y is 0.2. In an embodiment, the second magnetic layer 108B includes at least 98% iron. In an embodiment, the second magnetic layer 108B includes 99% iron and a boron having a content of less than 1%. An iron content of 99% enables diffusion of boron away from an interface 107 between the tunnel barrier 106 and the first magnetic layer 108 A. Diffusion of boron away from the interface 107 can preserve the tunnel barrier crystallinity and enable a tunneling magnetoresi stance ratio (TMR) of at least 90% to be achieved. Additionally, boron out-diffusion from interface 107 preserves the interfacial perpendicular magnetic anisotropy at the interface 107. The interfacial perpendicular magnetic anisotropy arises due to bond hybridization between iron in the first magnetic layer 108 A and oxygen in the tunnel barrier 106.

[0036] In an embodiment, the first magnetic layer 108 A and the second magnetic layer

108B have a combined total thickness between l .Onm - 2.5nm. In an embodiment, the first magnetic layer 108 A of the bilayer stack has a thickness that is greater than the thickness of the second magnetic layer 108B of the bilayer stack. In an embodiment, the first magnetic layer 108 A has a thickness between 0.6nm - 2.4nm. In an embodiment, the second magnetic layer 108B has a thickness between 0. lnm - 0.9nm. In an embodiment, the first magnetic layer 108A has a thickness of 1.6nm and the second magnetic layer 108B has a thickness of 0.6nm.

[0037] Referring again to Figure 1 A, in an embodiment, the fixed magnetic layer 102 is composed of materials and has a thickness suitable for maintaining a fixed magnetization. In an embodiment, the fixed magnetic layer 102 is composed of a single layer of cobalt, iron and boron (CoFeB). In an embodiment the fixed magnetic layer 102 has a thickness that is between lnm- 3nm. In an embodiment, the fixed magnetic layer 102 has a thickness that is less than the thickness of the free magnetic bilayer 108.

[0038] The fixed magnetic layer 102 and the free magnetic layer 108 have perpendicular magnetic anisotropy with respect to a plane defining an uppermost surface of the bottom electrode layer 104 above which the fixed magnetic layer 102 is formed. As illustrated in Figure IB, the material layer stack 100 is in a high resistance state when direction of magnetization (denoted by the direction of the arrow) in the free magnetic layer 108 is opposite (anti-parallel) to the direction of magnetization in the fixed magnetic layer 102. Conversely, the material layer stack 100 is in a low resistance state when the direction of magnetization in the free magnetic layer 108 is parallel to the direction of magnetization in the fixed magnetic layer 102 as illustrated in Figure 1C. A change in resistance (high to low or low to high) in the material layer stack 100 results when a spin polarized electron current passing from the free magnetic layer 108 through the tunnel barrier 106 brings about a change in the direction of the magnetization in the free magnetic layer 108.

[0039] In an embodiment, the free magnetic layer 108 and the fixed magnetic layer 102 can have similar thicknesses and an injected electron spin current which changes the orientation of the magnetization in the free magnetic layer 108 can also affect the magnetization of the fixed magnetic layer 102. In an embodiment, to make the fixed magnetic layer 102 more resistant to accidental flipping the fixed magnetic layer 102 has higher PMA than free magnetic layer. In another embodiment, a synthetic antiferromagnetic (SAF) structure is disposed between the bottom electrode layer 104 and the fixed magnetic layer 102 in order to prevent accidental flipping of the fixed magnetic layer 102. The SAF structure 150 is ferromagnetically coupled with the fixed magnetic layer 102.

[0040] Figure ID illustrates cross-sectional view of the synthetic antiferromagnetic

(SAF) structure 150 in an accordance of an embodiment of the present invention. In an embodiment, the SAF structure 150 includes a non-magnetic layer 150B sandwiched between a first ferromagnetic layer 150A and a second ferromagnetic layer 150C as depicted in Figure ID. The first ferromagnetic layer 150A and the second ferromagnetic layer 150C are anti- ferromagnetically coupled to each other. In an embodiment, the first ferromagnetic layer 150A includes a layer of a magnetic metal such as Co, Ni, Fe, alloys such as CoFe, CoFeB, or alloys of magnetic metals such as Co, Ni, Fe or a bilayer of a magnetic/non-magnetic metals such but not limited to Co/Pd or a Co/Pt. In an embodiment, the non-magnetic layer 150B includes a ruthenium or an iridium layer. In an embodiment, the second ferromagnetic layer 150C includes a layer of a magnetic metal such as Co, Ni, Fe, alloys such as CoFe, CoFeB, or alloys of magnetic metals such as Co, Ni, Fe or a bilayer of a magnetic/non-magnetic metals such but not limited to Co/Pd or a Co/Pt. In an embodiment, a ruthenium based non-magnetic layer 150B is limited to a thickness between 4-9 Angstroms to ensure that the coupling between the first ferromagnetic layer 150A and the second ferromagnetic layer 150C is anti-ferromagnetic in nature.

[0041] It is to be appreciated that an additional layer of non-magnetic spacer material may be disposed on the SAF structure 150, below the fixed magnetic layer 102. A non-magnetic spacer layer enables coupling between the SAF structure 150 and the fixed magnetic layer 102. In an embodiment, a non-magnetic spacer layer may include metals such as Ta, Ru or Ir.

[0042] Referring again to Figure 1 A, in an embodiment, the tunnel barrier 106 is composed of a material suitable for allowing electron current having a majority spin to pass through the tunnel barrier 106, while impeding at least to some extent electron current having a minority spin from passing through the tunnel barrier 106. Thus, the tunnel barrier 106 (or spin filter layer) may also be referred to as a tunneling layer for electron current of a particular spin orientation. In one embodiment, the tunnel barrier 106 includes an oxide such as, but not limited to, magnesium oxide (MgO) or aluminum oxide (AI2O3). In one embodiment, the tunnel barrier 106 is MgO and has a thickness of approximately 1 to 2 nm.

[0043] Referring again to Figure 1 A, in an embodiment, the bottom electrode layer 104 is composed of a material or stack of materials suitable for electrically contacting the fixed magnetic layer 102 side of the material layer stack 100. In an embodiment, the bottom electrode includes an amorphous conductive layer. In an embodiment, the bottom electrode layer 104 is a topographically smooth electrode. In a specific embodiment, the bottom electrode layer 104 is composed of Ru layers interleaved with Ta layers. In another embodiment, the bottom electrode layer 104 is TiN. In an embodiment, the bottom electrode layer 104 has a thickness between 20nm-50nm.

[0044] In an embodiment, the material layer stack 100 further includes an oxide layer

114 disposed on the free magnetic layer 108 as illustrated in Figure 1 A. In an embodiment, the oxide layer 114 includes an MgO. In an embodiment, the oxide layer 114 has a thickness that is between 0.3nm-1.5nm. The oxide provides a source of oxygen that enables oxygen-iron hybridization at an interface 109 located between an uppermost surface of the second free magnetic layer 108B and a lowermost surface of the oxide layer 114. The oxygen-iron hybridization in the interface 109 enables interfacial perpendicular magnetic anisotropy in the free magnetic layer 108. Furthermore, lack of boron at the interface 109 enables a stronger iron- oxygen hybridization.

[0045] In an embodiment, material layer stack 100 further includes a protective layer 116 disposed on the oxide layer 114 as illustrated in Figure 1. The protective layer 116 acts as a protective barrier for the oxide layer 114 against direct physical sputter damage during the formation of a subsequent layer such as a capping layer 118. In an embodiment, the protective layer 116 has a thickness between 0.3nm - 1.5nm. In an embodiment, the protective layer 116 is composed of a single layer of cobalt, iron and boron (CoFeB), but has a thickness and a material composition such that the layer is essentially non-magnetic.

[0046] In an embodiment, the material layer stack 100 further includes a top electrode layer 120 disposed on the capping layer 118 as illustrated in Figure 1 A. In an embodiment, the top electrode layer 120 includes a material such as Ta or TiN. In an embodiment, the top electrode layer 120 includes a material suitable to minimize series resistance with the material layer stack 100. In an embodiment, the resistance of the top electrode layer 120 has a thickness between 30-70nm. In an embodiment, the top electrode and the bottom electrode include a same metal such as Ta or TiN.

[0047] In an embodiment, the storage layer 108 depicted in Figure 1A includes multiple free magnetic layers in order increase perpendicular magnetic anisotropy of the material layer stack 100.

[0048] Figure 2A illustrates a cross sectional view of a pSTTM device having a material layer stack 200A, in an accordance with an embodiment of the present invention. Material layer stack 200A has a storage layer 201 A which includes (a) a first free magnetic layer 202 (b) a coupling layer 204 disposed on first free magnetic layer 202 and (c) a second free magnetic layer 208 including a bilayer stack disposed on the coupling layer 204. In an embodiment, the bilayer stack includes a first magnetic layer 208A and a second magnetic layer 208B consisting essentially of iron disposed on the first magnetic layer 208A. The second magnetic layer 208B, consists essentially of iron and is in direct contact with the oxide layer 114 above it. An interface 209 between the second magnetic layer 208B and the oxide layer 114 has perpendicular interfacial magnetic anisotropy due to iron-oxygen hybridization. The iron-oxygen hybridization arises from oxygen from the oxide layer 114 and iron from second magnetic layer 208B consisting essentially of iron.

[0049] Insertion of the coupling layer 204 and the first free magnetic layer 202 in the material layer stack 100 of Figure 1A increases the number of interfaces between an uppermost surface of the tunnel barrier 106 and a lower most surface of the oxide layer 114 from 2 to 4. Increasing the number of interfaces increases the overall interfacial perpendicular magnetic anisotropy and thermal stability of material layer stack 200A.

[0050] In an embodiment, the first magnetic layer 208A and the second magnetic layer

208B are compositionally similar to the first magnetic layer 108 A and the second magnetic layer 108B, respectively, described in association with Figure 1 A.

[0051] In an embodiment, the first magnetic layer 208A and the second magnetic layer 208B of the second free magnetic layer 208 have a combined total thickness between 0.6nm - 1.Onm. In an embodiment, the first magnetic layer 208A has a thickness that is greater than the thickness of the second magnetic layer 208B. In an embodiment, the first magnetic layer 208 A has a thickness between 0.3nm - 0.6nm. In an embodiment, the second magnetic layer 208B has a thickness between O. lnm - 0.4nm.

[0052] In an embodiment, the first free magnetic layer 202 includes an alloy such as

CoFe. In an embodiment, first magnetic layer 208A comprises an alloy such as Coi-x-yFe_xBy. In an embodiment, X is between from 0.5-0.8 and Y is between 0.1-0.4. In an embodiment, X is 0.8 and Y is 0.3. In another embodiment, X is 0.6 and Y is 0.2.

[0053] In an embodiment, first free magnetic layer 202 has a thickness that is greater than the thickness of second free magnetic layer 208. In an embodiment, the second free magnetic layer 208 has a thickness between 0.3nm - 1.5nm and the first free magnetic layer has a thickness between lnm-2.5nm. The first free magnetic layer 202 is ferromagnetically coupled to the second free magnetic layer 208. In an embodiment, the second free magnetic layer 208 has a perpendicular magnetic anisotropy that is less than the perpendicular magnetic anisotropy of the first free magnetic layer 202.

[0054] In an embodiment, the first free magnetic layer 202 and the second free magnetic layer 208 in the storage layer 201 A have a combined total thickness that is greater than the thickness of the fixed magnetic layer 102. In an embodiment, the magnetic layers in the storage layer 201 A have a combined total thickness between 1.5-2.5nm and the fixed magnetic layer 102 has a thickness between 1-2 nm. [0055] In an embodiment, the coupling layer 204 includes a non-magnetic transition metal such as, but not limited to, tungsten, molybdenum, vanadium, niobium and iridium. In an embodiment, the coupling layer 204 has a thickness between 0. lnm-lnm. In an embodiment coupling layer 204, is a same metal as the capping layer 118. In an embodiment, the coupling layer 204 and the capping layer 118 are both tungsten. In an embodiment, the coupling layer 204 is tungsten and the capping layer 118 is tantalum.

[0056] Figure 2B illustrates a cross sectional view of a pSTTM device having a material layer stack 200B, in an accordance with an embodiment of the present invention. Material layer stack 200B has a storage layer 20 IB which includes (a) a first free magnetic layer 202 (b) a coupling layer 205 disposed on first free magnetic layer 202 and (c) a second free magnetic layer 210 including a bilayer stack disposed on the coupling layer 205.

[0057] In contrast to the second free magnetic layer 208 described in Figure 2A, the second free magnetic layer 210, includes a second magnetic layer 210B consisting essentially of iron disposed directly on the coupling layer 205. The first magnetic layer 21 OA is disposed between the second magnetic layer 210B and the oxide layer 114.

[0058] In an embodiment, the first magnetic layer 21 OA and the second magnetic layer

210B are compositionally similar to the first magnetic layer 108 A and second magnetic layer 108B, respectively, described in association with Figure 1 A. In an embodiment, the first magnetic layer 210A is a CoFeB and the second magnetic layer 210B consists essentially of iron. In an embodiment, the coupling layer 205 is compositionally similar to the coupling layer 204.

[0059] In an embodiment, the level of iron-oxygen hybridization and perpendicular interfacial magnetic anisotropy at interface 211 between the first magnetic layer 21 OA and the oxide layer 114 in material layer stack 200B is similar to the iron-oxygen hybridization and perpendicular interfacial magnetic anisotropy at interface 209 in the material layer stack 200A. In an embodiment, the level of iron-oxygen hybridization and perpendicular interfacial magnetic anisotropy at the interface 211 is less than the iron-oxygen hybridization and perpendicular interfacial magnetic anisotropy at interface 209 due the presence of boron at the interface 211.

[0060] In an embodiment, the second free magnetic layer 210 has a total thickness that is less than the thickness of the first free magnetic layer 202.

[0061] Figure 2C illustrates a cross sectional view of a pSTTM device having a material layer stack 200C, in an accordance with an embodiment of the present invention. Material layer stack 200C has a storage layer 201C which includes (a) a first free magnetic layer 212 including a bilayer stack, (b) a coupling layer 207 disposed on first free magnetic layer 212 and (c) a second free magnetic layer 206 disposed on the coupling layer 207.

[0062] The first magnetic layer 212A of the first free magnetic layer 212 is disposed directly on the tunnel barrier 106. The second magnetic layer 21B is disposed between the coupling layer 207 and the first magnetic layer 212A.

[0063] In an embodiment, the first magnetic layer 212A and the second magnetic layer

212B are compositionally similar to the first magnetic layer 108A and second magnetic layer 108B, respectively, described in association with Figure 1 A. In an embodiment, the second free magnetic layer 206 is compositionally similar to the first free magnetic layer 202 described in association with Figure 1 A. In an embodiment, the first magnetic layer 212A is a CoFeB and the second magnetic layer 212B consists essentially of iron. In an embodiment, the coupling layer 207 is compositionally similar to the coupling layer 204.

[0064] The second magnetic layer 212B consists essentially of iron. In an embodiment, boron can diffuse from an interface 213 between the first magnetic layer 212A and the tunnel barrier 106 into the second magnetic layer 212B. In an embodiment, diffusion of boron away from the interface 213 helps to increase iron-oxygen hybridization and consequently increase perpendicular magnetic anisotropy at the interface 213.

[0065] In an embodiment, the thickness of the first free magnetic layer 212 is greater than the thickness of the second free magnetic layer 206 in the storage layer 201C. In one such embodiment, the first free magnetic layer 212 has a thickness that is between 2-3nm and the first free magnetic layer 202 has a thickness between 0.6nm-1.5nm. In an embodiment, the first magnetic layer 212A has a thickness between 1.9nm-2.4nm and the second magnetic layer 212B has a thickness between 0. lnm and 0.6nm.

[0066] Figure 2D illustrates a cross sectional view of a pSTTM device having a material layer stack 200C, in an accordance with an embodiment of the present invention. Material layer stack 200D has a storage layer 201D which includes (a) a first free magnetic layer 214 including a bilayer stack, (b) a coupling layer 215 disposed on first free magnetic layer 214 and (c) a second free magnetic layer 206 disposed on the coupling layer.

[0067] In contrast to the first free magnetic layer 212 described in Figure 2C, the first free magnetic layer 214, includes a first magnetic layer 214A disposed directly below and in contact with the coupling layer 215. A second magnetic layer 214B consisting essentially of iron is disposed directly on the first magnetic layer 214A and the tunnel barrier 106.

[0068] In an embodiment, the first magnetic layer 214A and the second magnetic layer

214B are compositionally similar to the first magnetic layer 108 A and second magnetic layer 108B, respectively, described in association with Figure 1 A. In an embodiment, the second free magnetic layer 206 is compositionally similar to the first free magnetic layer 202 described in association with Figure 1 A.

[0069] In an embodiment, the presence of a boron free magnetic layer on the tunnel barrier 106 can impact the iron-oxygen hybridization at interface 216 between the tunnel barrier

106 and the second magnetic layer 214B. TMR of the material layer stack 200D can be lowered compared the TMR of the material layer stack 200C.

[0070] In an embodiment, the thickness of the first free magnetic layer 214 is greater than the thickness of the second free magnetic layer 206. In one such embodiment, the second free magnetic layer 214 has a thickness that is between 2-3nm and the first free magnetic layer 202 has a thickness between 0.6nm-1.5nm. In an embodiment, the first magnetic layer 214A has a thickness between 1.9nm-2.4nm and the second magnetic layer 214 has a thickness between O. lnm and 0.6nm.

[0071] Figure 3 A illustrates a cross sectional view of a pSTTM device having a material layer stack 300 A, in an accordance with an embodiment of the present invention. Material layer stack 300A has a storage layer 310A which includes (a) a first free magnetic layer 308 including a first bilayer stack (b) a coupling layer 304 disposed on first free magnetic layer 308 and (c) a second free magnetic layer 310 including a second bilayer stack disposed on the coupling layer 304.

[0072] In an embodiment, the first free magnetic layer 308 includes a first magnetic layer

308A and a second magnetic layer 308B consisting essentially of iron disposed on the first magnetic layer 308A. The first magnetic layer 308A is disposed on the tunnel barrier 106. In an embodiment, the first magnetic layer 308A is a CoFeB. The coupling layer 304 is disposed on the second magnetic layer 308B. In an embodiment, the second free magnetic layer 310, disposed above the coupling layer 304, includes a third magnetic layer 310A and a fourth magnetic layer 310B consisting essentially of iron disposed on the first magnetic layer 310A. The second magnetic layer 310B is in direct contact with the oxide layer 114 above it.

[0073] In an embodiment, the first magnetic layer 308 A and the third magnetic layer 310A are compositionally similar to the first magnetic layer 108 A described in association with Figure 1 A. In an embodiment, the second magnetic layer 308B and the fourth magnetic layer 310B consist essentially of iron. In an embodiment, the second magnetic layer 308B and the fourth magnetic layer 310B compositionally similar to the second magnetic layer 108B described in association with Figure 1 A. In an embodiment, the first magnetic layer 310A is a CoFeB. In an embodiment, the coupling layer 304 is compositionally similar to the coupling layer 204 described in association with Figure 2A.

[0074] An interface 305 between the first magnetic layer 308 A and the tunnel barrier 106 has perpendicular interfacial magnetic anisotropy due to iron-oxygen hybridization. An interface 307 between the second magnetic layer 310B and the oxide layer 114 has perpendicular interfacial magnetic anisotropy due to iron-oxygen hybridization. In an embodiment, the level of iron-oxygen hybridization and perpendicular interfacial magnetic anisotropy at interface 305 is similar to the iron-oxygen hybridization and perpendicular interfacial magnetic anisotropy at interface 307. In an embodiment, the level of iron-oxygen hybridization and perpendicular interfacial magnetic anisotropy at the interface 307 is less than the iron-oxygen hybridization and perpendicular interfacial magnetic anisotropy at interface 309 due the presence of boron at the interface 305.

[0075] In an embodiment, first free magnetic layer 308 has a thickness that is greater than the thickness of second free magnetic layer 310. The first free magnetic layer 308 is ferromagnetically coupled to the second free magnetic layer 310.

[0076] In an embodiment, the first magnetic layer 308 A and the second magnetic layer

308B of the first free magnetic layer 308 have a combined total thickness between lnm-1.5nm. In an embodiment, the first magnetic layer 308A has a thickness that is greater than the thickness of the second magnetic layer 308B. In an embodiment, the first magnetic layer 308A has a thickness between 0.3nm - lnm. In an embodiment, the second magnetic layer 308B has a thickness between 0. lnm - 0.5nm.

[0077] In an embodiment, the third magnetic layer 310A and the fourth magnetic layer

310B of the second free magnetic layer 310 have a combined total thickness between 0.6nm - 1.Onm. In an embodiment, the third magnetic layer 310A has a thickness that is greater than the thickness of the fourth magnetic layer 310B. In an embodiment, the third magnetic layer 310A has a thickness between 0.3nm - 0.6nm. In an embodiment, the fourth magnetic layer 310B has a thickness between O. lnm - 0.4nm.

[0078] In an embodiment, the first magnetic layer 308A has a thickness that is greater than the thickness of the third magnetic layer 310A. In an embodiment, the second magnetic layer 308B has a thickness that is greater than the thickness of the fourth magnetic layer 310B.

[0079] In an embodiment, the first free magnetic layer 308 and the second free magnetic layer 310 of the storage layer 301 A have a combined total thickness that is greater than the thickness of the fixed magnetic layer 102. In an embodiment, the magnetic layers in the storage layer 301 A have a combined total thickness between 1.5-2.5nm and the fixed magnetic layer 102 has a thickness between l-2nm. In another embodiment, the first free magnetic layer 308 and the second free magnetic layer 310 of the storage layer 301 A have a combined total thickness that is equal to the thickness of the fixed magnetic layer 102. In another embodiment, the first free magnetic layer 308 and the second free magnetic layer 310 of the storage layer 301 A have a combined total thickness that is less than the thickness of the fixed magnetic layer 102.

[0080] Figure 3B illustrates a cross sectional view of a pSTTM device having a material layer stack 300B, in an accordance with an embodiment of the present invention. Material layer stack 300B has a storage layer 30 IB which includes (a) a first free magnetic layer 312 including a first bilayer stack (b) a coupling layer 305 disposed on first free magnetic layer 312 and (c) a second free magnetic layer 314 including a bilayer stack disposed on the coupling layer 305.

[0081] In an embodiment, the first free magnetic layer 312 includes a first magnetic layer 312A and a second magnetic layer 312B consisting essentially of iron, disposed on the first magnetic layer 312A. The first magnetic layer 312A is disposed on the tunnel barrier 106. In an embodiment, the first magnetic layer 312A is a CoFeB. The coupling layer 305 disposed on the second magnetic layer 312B. In an embodiment, the second free magnetic layer 314, disposed above the coupling layer 305, includes a third magnetic layer 314A disposed on a fourth magnetic layer 314B consisting essentially of iron. The third magnetic layer 314A is in direct contact with the oxide layer 114 above it.

[0082] In an embodiment, the first magnetic layer 312A and the third magnetic layer

314A are compositionally similar to the first magnetic layer 108 A described in association with Figure 1 A. In an embodiment, the second magnetic layer 312B and the fourth magnetic layer 314B consist essentially of iron. In an embodiment, the second magnetic layer 312B and the fourth magnetic layer 314B compositionally similar to the second magnetic layer 108B described in association with Figure 1 A. In an embodiment, the coupling layer 305 is compositionally similar to the coupling layer 304.

[0083] An interface 311 between the first magnetic layer 312A and the tunnel barrier 106 has perpendicular interfacial magnetic anisotropy due to iron-oxygen hybridization.

Additionally, an interface 313 between the third magnetic layer 314A and the oxide layer 114 has perpendicular interfacial magnetic anisotropy due to iron-oxygen hybridization. In an embodiment, the first magnetic layer 312A and the third magnetic layer 314A are both CoFeB. In one such embodiment, the level of iron-oxygen hybridization and perpendicular interfacial magnetic anisotropy at interface 311 is similar to the iron-oxygen hybridization and

perpendicular interfacial magnetic anisotropy at interface 313. In an embodiment, the perpendicular interfacial magnetic anisotropy at the interface 313 is less than the perpendicular interfacial magnetic anisotropy at interface 311 due to differences in the iron-oxygen

hybridization strengths.

[0084] In an embodiment, first free magnetic layer 312 has a thickness that is greater than the thickness of second free magnetic layer 314. The first free magnetic layer 312 is ferromagnetically coupled to the second free magnetic layer 314.

[0085] In an embodiment, the first magnetic layer 312A and the second magnetic layer

312B of the first free magnetic layer 312 have a combined total thickness between lnm-1.5nm. In an embodiment, the first magnetic layer 312A has a thickness that is greater than the thickness of the second magnetic layer 312B. In an embodiment, the first magnetic layer 312A has a thickness between 0.3nm - lnm. In an embodiment, the second magnetic layer 312B has a thickness between O. lnm - 0.5nm.

[0086] In an embodiment, the third magnetic layer 314A and the fourth magnetic layer 314B of the second magnetic layer 312B have a combined total thickness between 0.6nm -

1.Onm. In an embodiment, the third magnetic layer 314A has a thickness that is greater than the thickness of the fourth magnetic layer 314B. In an embodiment, the third magnetic layer 314A has a thickness between 0.3nm - 0.6nm. In an embodiment, the fourth magnetic layer 314B has a thickness between O. lnm - 0.4nm.

[0087] In an embodiment, the first magnetic layer 312A has a thickness that is greater than the thickness of the third magnetic layer 314 A. In an embodiment, the second magnetic layer 312B has a thickness that is greater than the thickness of the fourth magnetic layer 314B.

[0088] In an embodiment, the first free magnetic layer 312 and the second free magnetic layer 314 of the storage layer 301 A have a combined total thickness that is less than the thickness of the fixed magnetic layer 102. In an embodiment, the magnetic layers in the storage layer 301 A have a combined total thickness between 1.5-2.5nm and the fixed magnetic layer 102 has a thickness between l-3nm.

[0089] Figure 3C illustrates a cross sectional view of a pSTTM device having a material layer stack 300C, in an accordance with an embodiment of the present invention. Material layer stack 300C has a storage layer 301C which includes (a) a first free magnetic layer 316 including a first bilayer stack (b) a coupling layer 306 disposed on first free magnetic layer 316 and (c) a second free magnetic layer 318 including a bilayer stack disposed on the coupling layer 306.

[0090] In an embodiment, the first free magnetic layer 316 includes a first magnetic layer

316A disposed on a second magnetic layer 316B consisting essentially of iron. The second magnetic layer 316B is disposed on the tunnel barrier 106. The coupling layer 306 disposed on first magnetic layer 316A. In an embodiment, the second free magnetic layer 318, disposed on the coupling layer 306, includes a third magnetic layer 318A and a fourth magnetic layer 318B consisting essentially of iron disposed on the third magnetic layer 318 A. The fourth magnetic layer 318B is in direct contact with the oxide layer 114 above it.

[0091] In an embodiment, the first magnetic layer 316A and the third magnetic layer

318A are compositionally similar to the first magnetic layer 108 A described in association with Figure 1 A. In an embodiment, the first magnetic layer 316A and the third magnetic layer 318A are both CoFeB. In an embodiment, the second magnetic layer 316B and the fourth magnetic layer 318B consist essentially of iron. In an embodiment, the second magnetic layer 316B and the fourth magnetic layer 318B compositionally similar to the second magnetic layer 108B described in association with Figure 1 A. In an embodiment, the coupling layer 306 is compositionally similar to the coupling layer 304.

[0092] An interface 315 between the second magnetic layer 316B and the tunnel barrier

106 has perpendicular interfacial magnetic anisotropy due to iron-oxygen hybridization.

Additionally, an interface 317 between the fourth magnetic layer 318B and the oxide layer 114 has perpendicular interfacial magnetic anisotropy due to iron-oxygen hybridization. In an embodiment, the level of iron-oxygen hybridization and perpendicular interfacial magnetic anisotropy at interface 315 is similar to the iron-oxygen hybridization and perpendicular interfacial magnetic anisotropy at interface 317.

[0093] In an embodiment, first free magnetic layer 316 has a thickness that is greater than the thickness of second free magnetic layer 318. The first free magnetic layer 316 is ferromagnetically coupled to the second free magnetic layer 318.

[0094] In an embodiment, the first magnetic layer 316A and the second magnetic layer

316B of the first free magnetic layer 316 have a combined total thickness between lnm-1.5nm. In an embodiment, the first magnetic layer 316A has a thickness that is greater than the thickness of the second magnetic layer 316B. In an embodiment, the first magnetic layer 316A has a thickness between 0.3nm - lnm. In an embodiment, the second magnetic layer 316B has a thickness between O. lnm - 0.5nm.

[0095] In an embodiment, the third magnetic layer 318A and the fourth magnetic layer 318B of the second free magnetic layer 318 have a combined total thickness between 0.6nm - 1.Onm. In an embodiment, the third magnetic layer 318 A has a thickness that is greater than the thickness of the fourth magnetic layer 318B. In an embodiment, the third magnetic layer 318A has a thickness between 0.3nm - 0.6nm. In an embodiment, the fourth magnetic layer 318B has a thickness between O. lnm - 0.4nm.

[0096] In an embodiment, the first magnetic layer 316A has a thickness that is greater than the thickness of the third magnetic layer 318 A. In an embodiment, the second magnetic layer 316B has a thickness that is greater than the thickness of the fourth magnetic layer 318B.

[0097] In an embodiment, the first free magnetic layer 316 and the second free magnetic layer 318 of the storage layer 301C have a combined total thickness that is less than the thickness of the fixed magnetic layer 102. In an embodiment, the magnetic layers in the storage layer

301C have a combined total thickness between 1.5-2.5nm and the fixed magnetic layer 102 has a thickness between 2-3nm.

[0098] Figure 3D illustrates a cross sectional view of a pSTTM device having a material layer stack 300D, in an accordance with an embodiment of the present invention. Material layer stack 300D has a storage layer 301D which includes (a) a first free magnetic layer 320 including a first bilayer stack (b) a coupling layer 309 disposed on first free magnetic layer 320 and (c) a second free magnetic layer 322 including a bilayer stack disposed on the coupling layer 309.

[0099] In an embodiment, the first free magnetic layer 320 includes a first magnetic layer

320A disposed on a second magnetic layer 320B consisting essentially of iron. The second magnetic layer 320B is disposed on the tunnel barrier 106. The coupling layer 309 is disposed on first magnetic layer 320A. In an embodiment, the second free magnetic layer 322, disposed on the coupling layer 309, includes a third magnetic layer 322A disposed on a fourth magnetic layer 322B consisting essentially of iron. The third magnetic layer 322A is in direct contact with the oxide layer 114 above it.

[00100] In an embodiment, the first magnetic layer 320A and the third magnetic layer

322A are compositionally similar to the first magnetic layer 108 A described in association with Figure 1 A. In an embodiment, the first magnetic layer 320A and the third magnetic layer 322A are both CoFeB. In an embodiment, the second magnetic layer 320B and the fourth magnetic layer 322B are compositionally similar to the second magnetic layer 108B described in association with Figure 1 A. In an embodiment, the second magnetic layer 320B and the fourth magnetic layer 322B consist essentially of iron. In an embodiment, the coupling layer 309 is compositionally similar to the coupling layer 304.

[00101] An interface 319 between the second magnetic layer 320B and the tunnel barrier

Additionally, an interface 321 between the third magnetic layer 322A and the oxide layer 114 has perpendicular interfacial magnetic anisotropy due to iron-oxygen hybridization.

[00102] In an embodiment, the level of iron-oxygen hybridization and perpendicular interfacial magnetic anisotropy at interface 319 is similar to the iron-oxygen hybridization and perpendicular interfacial magnetic anisotropy at interface 321. In an embodiment, interface the 319 has a perpendicular interfacial magnetic anisotropy is less than the perpendicular interfacial magnetic anisotropy at interface 321 due to a lower iron-oxygen hybridization strength at interface 319.

[00103] In an embodiment, first free magnetic layer 320 has a thickness that is greater than the thickness of second free magnetic layer 322. The first free magnetic layer 320 is ferromagnetically coupled to the second free magnetic layer 322.

[00104] In an embodiment, the first magnetic layer 320A and the second magnetic layer

320B of the first free magnetic layer 320 have a combined total thickness between lnm-1.5nm. In an embodiment, the first magnetic layer 320A has a thickness that is greater than the thickness of the second magnetic layer 320B. In an embodiment, the first magnetic layer 320A has a thickness between 0.3nm - lnm. In an embodiment, the second magnetic layer 320B has a thickness between O. lnm - 0.5nm.

[00105] In an embodiment, the third magnetic layer 322A and the fourth magnetic layer

322B of the second magnetic layer 320B have a combined total thickness between 0.6nm - 1.Onm. In an embodiment, the third magnetic layer 322A has a thickness that is greater than the thickness of the fourth magnetic layer 322B. In an embodiment, the third magnetic layer 322A has a thickness between 0.3nm - 0.6nm. In an embodiment, the fourth magnetic layer 322B has a thickness between O. lnm - 0.4nm.

[00106] In an embodiment, the first magnetic layer 320A has a thickness that is greater than the thickness of the third magnetic layer 322A. In an embodiment, the second magnetic layer 320B has a thickness that is greater than the thickness of the fourth magnetic layer 322B.

[00107] In an embodiment, the first free magnetic layer 320 and the second free magnetic layer 322 of the storage layer 301C have a combined total thickness that is less than the thickness of the fixed magnetic layer 102. In an embodiment, the magnetic layers in the storage layer 301C have a combined total thickness between 1.5-2.5nm and the fixed magnetic layer 102 has a thickness between 2-3nm.

[00108] Figure 4A illustrates a cross sectional view of a pSTTM device having a material layer stack 400A, in an accordance with an embodiment of the present invention. Material layer stack 400A has a storage layer 401 A which includes (a) a first free magnetic layer 402 (b) a coupling layer 404 disposed on first free magnetic layer 402 and (c) second free magnetic layer 408 consisting essentially of iron disposed on the coupling layer 404. In an embodiment, the first free magnetic layer 402 is compositionally similar to the first magnetic layer 202 described in association with Figure 2A. In an embodiment, the coupling layer 404 is compositionally similar to the coupling layer 304 described in association with Figure 3 A.

[00109] In an embodiment, the material layer stack 400A further includes an oxide layer 114 disposed on the second free magnetic layer 408 as illustrated in Figure 4A. In an

embodiment, the oxide layer 114 includes an MgO. The oxide layer 114 provides a source of oxygen that enables oxygen-iron hybridization at an interface 409 located between an uppermost surface of the second free magnetic layer 408 and a lowermost surface of the oxide layer 114. The oxygen-iron hybridization enables interfacial perpendicular magnetic anisotropy at the interface 409. Furthermore, absence of boron from the interface 409 enables a stronger iron- oxygen hybridization.

[00110] In an embodiment, the second free magnetic layer 408 has a thickness that ranges from 0.6nm to l .Onm. The second free magnetic layer 408 having a thickness of 0.6nm is sufficiently magnetic and is sufficiently ferromagnetically coupled to the first free magnetic layer 402. In an embodiment, the second free magnetic layer 408 has a thickness that is less than the thickness of the first free magnetic layer 402. In an embodiment, the second free magnetic layer 408 has a thickness of lnm and first free magnetic layer 402 has a thickness that is 1.5nm. In an embodiment, the first free magnetic layer 402 and the second free magnetic layer 408 of the storage layer 401 A have a combined total thickness that is less than the thickness of the fixed magnetic layer 102.

[00111] Figure 4B illustrates a cross sectional view of a pSTTM device having a material layer stack 400B, in an accordance with an embodiment of the present invention. Material layer stack 400B has a storage layer 40 IB which includes (a) a first free magnetic layer 410 including a bilayer stack (b) a coupling layer 405 disposed on first free magnetic layer 410 and (c) second free magnetic layer 412 consisting essentially of iron disposed on the coupling layer 405.

[00112] In an embodiment, the first free magnetic layer 410 includes a first magnetic layer 41 OA disposed on the tunnel barrier 106. A second magnetic layer 410B consisting essentially of iron is disposed on the first magnetic layer 41 OA. The coupling layer 405 is disposed on second magnetic layer 410B. In an embodiment, the first magnetic layer 410A is compositionally similar to the first magnetic layer 108 A described in association with Figure 1 A. In an embodiment, the second magnetic layer 410B and the second free magnetic layer 412 have an iron content of at least 99%. In an embodiment, the second magnetic layer 108B has an iron content that is less than 99% and the second free magnetic layer 412 has an iron content of at least 99%. In an embodiment, the coupling layer 405 is compositionally similar to the coupling layer 404.

[00113] An interface 411 between the first magnetic layer 41 OA and the tunnel barrier 106 has interfacial perpendicular magnetic anisotropy due to iron-oxygen hybridization.

Additionally, an interface 413 between the second free magnetic layer 412 and the oxide layer 114 has a similar interfacial perpendicular magnetic anisotropy as interface 409.

[00114] In an embodiment, second free magnetic layer 412 has a thickness greater than thickness of the second magnetic layer 410B. In an embodiment, the second free magnetic layer 412 has a thickness that ranges from 0.6nm to l .Onm. In an embodiment, the second free magnetic layer 412 has a thickness that is less than the combined thickness of the first and second magnetic layers 41 OA and 410B, respectively. In an embodiment, the second free magnetic layer 412 has a thickness of lnm and first free magnetic layer 410 has a thickness that is 1.5nm. In an embodiment, the first free magnetic layer 410 and the second free magnetic layer 412 of the storage layer 401B have a combined total thickness that is less than the thickness of the fixed magnetic layer 102.

[00115] Figure 4C illustrates a cross sectional view of a pSTTM device having a material layer stack 400C, in an accordance with an embodiment of the present invention. Material layer stack 400C has a storage layer 401C which includes (a) a first free magnetic layer 414 including a bilayer stack (b) a coupling layer 406 disposed on first free magnetic layer 414 and (c) second free magnetic layer 416 consisting essentially of iron disposed on the coupling layer 406.

[00116] In an embodiment, the first free magnetic layer 414 includes a first magnetic layer 414A disposed on a second magnetic layer 414B consisting essentially of iron. The second magnetic layer 414B is disposed on the tunnel barrier 106. The coupling layer 406 is disposed on second magnetic layer 414B. In an embodiment, the first magnetic layer 414A is

compositionally similar to the first magnetic layer 108 A described in association with Figure 1 A. In an embodiment, the second magnetic layer 414B and the second free magnetic layer 416 have an iron content of at least 99%. In an embodiment, the second magnetic layer 414B has an iron content that is less than 99% and the second free magnetic layer 416 has an iron content of at least 99%. In an embodiment, the coupling layer 406 is compositionally similar to the coupling layer 404.

[00117] An interface 415 between the second magnetic layer 414B and the tunnel barrier 106 has interfacial perpendicular magnetic anisotropy due to iron-oxygen hybridization.

Additionally, an interface 417 between the second free magnetic layer 416 and the oxide layer 114 has a similar interfacial perpendicular magnetic anisotropy as interfaces 413 and 409. In an embodiment, the interface 417 has an interfacial perpendicular magnetic anisotropy that is similar to the interfacial perpendicular magnetic anisotropy at interface 415.

[00118] In an embodiment, second free magnetic layer 416 has a thickness greater than thickness of the second magnetic layer 414B. In an embodiment, the second free magnetic layer 416 has a thickness that ranges from 0.6nm to l .Onm. In an embodiment, the second free magnetic layer 416 has a thickness that is less than the combined thickness of the first and second magnetic layers 414A and 414B, respectively. In an embodiment, the second free magnetic layer 416 has a thickness of lnm and first free magnetic layer 414 has a thickness that is 1.5nm.

[00119] Figure 5A-5D illustrate cross-sectional views representing various operations in a method of fabricating a pSTTM device in accordance with embodiments of the present invention.

[00120] Figure 5A illustrates a cross-sectional view of the formation of a bottom electrode layer 504 on a conductive interconnect structure 500 formed above a substrate 501. In an embodiment, the conductive interconnect structure 500 includes a conductive interconnect 502 formed in a dielectric layer 503 by a dual damascene process that is well known in the art. In an embodiment, the conductive interconnect 502 includes a material such as copper, tungsten, tantalum or ruthenium and the dielectric layer 503 includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the bottom electrode layer 504 includes an alloy such as TiN or TaN. In an embodiment, the bottom electrode layer 504 is deposited using a physical vapor deposition process or a plasma enhanced chemical vapor deposition (PECVD) process. In an embodiment the bottom electrode layer 504 is first blanket deposited and subsequently planarized to form a topographically smooth uppermost surface having a surface roughness that is less than lnm. A surface roughness of less than 1 nm is sufficient to enable various layers that will be subsequently deposited to have well-defined crystal planes.

[00121] In an embodiment, the substrate 501 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials such as germanium, silicon germanium or a suitable group III-V compound.

[00122] Figure 5B illustrates a cross-sectional view of the formation of the various layers in a material layer stack 550 for a pSTTM device, in an accordance with an embodiment of the present invention. In an embodiment, the individual layers in the material layer stack 550 beginning with a SAF structure 505 are deposited without an air break. In an embodiment, while the deposition process is carried without an air break, the individual layers are blanket deposited using a variety of deposition processes in a cluster tool. In an embodiment, some layers are deposited using a physical vapor deposition (PVD) process. In an embodiment, a co-sputter or a reactive sputtering process is utilized to deposit one or more layers of the material layer stack 550.

[00123] In one embodiment, the SAF structure 505 is formed on the bottom electrode layer 504 by a PVD process. In an embodiment, the SAF structure 505 is similar to the SAF structure 150 described in association with Figure ID. The SAF structure 505 illustrated in Figure 5B includes a non magnetic spacer layer in an uppermost portion of the SAF structure.

[00124] A fixed magnetic layer 506 is deposited on the non magnetic spacer layer in the uppermost portion of the SAF structure 505. In an embodiment, the fixed magnetic layer 506 is deposited to a thickness ranging from 2-3nm and is typically the thickest single magnetic layer in the material layer stack 550.

[00125] A tunnel barrier 508 is then blanket deposited on the fixed magnetic layer 506. In an embodiment, the tunnel barrier 508 includes a material such as MgO or AI2O3. In an embodiment, the tunnel barrier 508 is an MgO and is deposited using a reactive sputter process. In an embodiment, the reactive sputter process is carried out at room temperature. In an embodiment, the MgO is deposited to a thickness between 0.8 to lnm. In an embodiment, the deposition process is carried out in a manner that yields a tunnel barrier 508 having an amorphous structure. In an embodiment, the amorphous tunnel barrier 508 becomes crystalline after a high temperature anneal process to be described further below. In an embodiment, the tunnel barrier 508 is crystalline as deposited.

[00126] A storage layer 560 is then deposited on the uppermost surface of the tunnel barrier 506. In an embodiment, the storage layer includes a first magnetic layer 510A, a second magnetic layer 510B, a coupling layer 512, a third magnetic layer 514A and a fourth magnetic layer 514B. The individual layers of the storage layer are sequentially blanket deposited. In an embodiment, the first magnetic layer 510A is deposited with a boron content of at least 20% to ensure lattice matching of the first magnetic layer 510A with the tunnel barrier 506. In an embodiment, the second magnetic layer 510B has some portions that become damaged by a subsequent deposition of the coupling layer 512. In one such embodiment, the second magnetic layer 510B is deposited thicker and has a portion between 20-50% of the thickness becomes magnetically dead after deposition of the coupling layer 512. In an embodiment, the process of depositing the second magnetic layer 510B can lead to intermixing between the first magnetic layer 510A and the second magnetic layer 510B. In this manner, the second magnetic layer 510B which consists essentially of iron can also include minute trace amounts of boron that is less than 1% of the total content of the second magnetic layer 510B. Likewise, when the fourth magnetic layer 514B is deposited on the third magnetic layer 514A similar intermixing can result between the third magnetic layer 514A and the fourth magnetic layer 514B. In an embodiment, the process of depositing the first magnetic layer 510A, the second magnetic layer 510B, the coupling layer 512, the third magnetic layer 514A and the fourth magnetic layer 514B includes depositing with materials such as the materials corresponding to the individual layers of the storage layer 301 A in the material layer stack 300A (described in association with Figure 3 A.)

[00127] The deposition process continues with the formation of an oxide layer 516 on the uppermost surface of the storage layer 301 A, the formation of a protective layer 518 on the oxide layer 516, formation of a capping layer 520 on the protective layer 518 and finally the formation of a top electrode layer 522 on the capping layer 520, in an accordance with an embodiment of the present invention.

[00128] In an embodiment, the oxide layer 516 is deposited using a room temperature reactive sputter deposition process. In an embodiment, the oxide layer 516 includes a material such as MgO. In an embodiment, the oxide layer 516 is deposited to a thickness between 0.3nm - 0.8nm to minimize the resistance of the material layer stack 550.

[00129] In an embodiment, the protective layer 518 is deposited on the oxide layer 114. In an embodiment, the protective layer 518 has includes a magnetic material such as CoFe or CoFeB. In an embodiment, the protective layer 518 is deposited to a thickness of 0.3-0.6nm so that the protective layer 518 becomes essentially non-magnetic or very weakly magnetic after subsequent deposition of the capping layer 520. In an embodiment, the capping layer 520 is deposited on the uppermost surface of the protective layer 518. In an embodiment, the capping layer 520 includes a metal such as molybdenum or ruthenium. Metals with a lack of oxygen affinity such as molybdenum and ruthenium provide protection against oxygen scavenging from the interface between the fourth magnetic layer 514B and the oxide layer 516.

[00130] In an embodiment, the top electrode layer 522 is blanket deposited on the surface of the capping layer 520. In an embodiment, the top electrode layer 522 includes a material such as Ta. In an embodiment, the thickness of the top electrode layer 522 ranges from 30-70nm. The thickness is chosen to provide etch resistivity during etching of the material layer stack 300A.

[00131] While one material layer stack 550 is shown in this embodiment, any of the embodiments shown in Figures 2A-2D, Figure 3 A-3D and Figures 4A-4D can be fabricated by the deposition techniques described above.

[00132] In an embodiment, after all the layers in the pSTTM material layer stack 550 are deposited, an anneal is performed under conditions well known in the art to promote solid phase epitaxy of the first magnetic layer 51 OA following a template of a crystalline layer of the tunnel barrier 508 (e.g., MgO). A post-deposition anneal of the pSTTM material layer stack 550 is carried out in a furnace at a temperature between 300-400 degrees C. In an embodiment, the anneal is performed immediately post deposition but before patterning of the pSTTM material layer stack 550 to enable crystalline MgO to be formed in the tunnel barrier 508. The annealing process also enables boron to diffuse away from an interface 552 between the first magnetic layer 51 OA and the tunnel barrier 508. The process of diffusing boron away from the interface 552 enables lattice matching between the first magnetic layer 510A and the tunnel barrier 508.

[00133] In an embodiment, the annealing process is also performed in the presence of a magnetic field which sets the magnetization direction of the fixed magnetic layer 506 and the magnetic layers in the storage layer 560. In an embodiment, an applied magnetic field that is directed parallel to the vertical axis of the pSTTM material layer stack 550, during the annealing process, enables a perpendicular anisotropy to be set in the fixed magnetic layer 506 and in the magnetic layers in the storage layer 560. In an embodiment, the annealing process initially aligns the magnetization of the fixed magnetic layer 506 and the magnetic layers in the storage layer 560 to be parallel to each other.

[00134] Figure 5C illustrates a cross-sectional view of the structure in Figure 5C following patterning and etching of the top electrode layer 522. In an embodiment, the patterning of the top electrode layer 522 is carried out by first lithographically patterning a layer of resist formed (not shown) over the pSTTM material layer stack 550. The lithography process defines the shape and size of a pSTTM device and a location where the pSTTM device is to be formed with respect the conductive interconnect 502. In an embodiment, the patterning of the top electrode layer 522 is performed by etching the top electrode layer 522 by a plasma etch process of the top electrode layer 522. In an embodiment, plasma etch process possesses sufficient ion energy and chemical reactivity to render vertical etched profiles of the top electrode layer 522.

[00135] Figure 5D illustrates a cross-sectional view of the structure in Figure 5D following patterning and etching of the pSTTM material layer stack 550 to form a pSTTM device 570. In an embodiment, the plasma etch process etches the entire pSTTM material layer stack 550 in a single introduction into a plasma etch chamber. Depending on the thickness of the magnetic materials in the material layer stack 550, almost 50-70% of the top electrode layer 522 may be consumed during the etch process utilized to form the pSTTM device 570. In an embodiment, the plasma etch process consumes between 50% of the top electrode layer 522 and forms a tapered top electrode layer 522. In an embodiment, the pSTTM device 570 has a profile that is between 75-90 degrees. In an embodiment, the plasma etch process results in non-volatile byproducts containing magnetic and non-magnetic materials and are deposited on the sidewalls of the pSTTM device 570. In an embodiment, the residual non-volatile by products are metallic and can lead to shorting between the fixed magnetic layer 506 and the storage layer 560. In an embodiment, the non-volatile residue is removed from the sidewall of the pSTTM device 570 by a second plasma etch based clean-up process.

[00136] In an embodiment, a dielectric spacer layer 524 is deposited on the pSTTM device 570 and on the uppermost surface of the dielectric layer 503. In an embodiment, the dielectric spacer layer 524 is deposited without a break following the plasma etch process. In an embodiment, the dielectric spacer layer 524 includes a material such as silicon nitride or carbon doped silicon nitride. The dielectric spacer layer 524 does not contain a material that includes oxygen to prevent oxidation of magnetic layers after the clean-up process. In an embodiment, the dielectric spacer layer 524 is plasma etched as illustrated in Figure 5D and exposes an uppermost surface of the top electrode layer 522 and the uppermost surface of the dielectric layer 503. In other embodiments, the dielectric spacer layer 524 is not etched and electrical contact to the top electrode layer 522 is enabled by a blanket deposition of an interlayer dielectric layer on the pSTTM device 570 and a subsequent polish process to expose the top electrode layer 522 (not shown).

[00137] Magnetic measurements of thermal stability and tunneling magneto-resistance ratio (TMR) and resistance area (RA) product may be measured after the material layer stack 550 has been formed. In an embodiment, thermal stability measurements are carried out once the pSTTM devices such as pSTTM device 570 is formed. In an embodiment, a collection of pSTTM devices including pSTTM device 570 having a width of 40nm are fabricated using the material layer stack 550. The collection of pSTTM devices including pSTTM device 570 exhibits mean thermal stability that is 15% higher than a collection of pSTTM devices fabricated from a corresponding material layer stack without a second magnetic layer 510B or a fourth magnetic layer 514B. In one such embodiment, measurements of a mean TMR ratio of the collection of pSTTM devices including pSTTM device 570 exhibit similar mean TMR of collection of pSTTM devices fabricated from a corresponding material layer stack without a second magnetic layer 510B or a fourth magnetic layer 514B.

[00138] In an embodiment, retention measurements of pSTTM devices such as pSTTM device 570 exhibit virtually no retention loss. Retention measurements measure the variation in a magnetic state of the storage layer 560 over a period of time. Since the magnetic state of the storage layer 560 is either parallel or anti-parallel relative to the fixed layer, retention

measurements are performed when the pSTTM device 570 is in a low resistance state as well as when the pSTTM device 570 is in a high resistance state. Retention measurements are a measure of the deviation of the resistance of the pSTTM device 570 from either a low resistance state or from a high resistance state. In an embodiment, the retention measurement is performed at both high and low resistance states of the pSTTM device 570 at 165 degrees Celsius for a time period lasting for 24 hours. In one such embodiment, retention measurements exhibit virtually no deviation in resistance of the pSTTM device 570 at either high or low resistance states.

[00139] Figure 6 illustrates a pSTTM memory device 600, formed on a conductive interconnect 602. In an embodiment, the conductive interconnect 602 is disposed on a contact structure 604 above a drain region 606 of an access transistor 608 disposed above a substrate 610. In an embodiment, a pSTTM memory device 600 is disposed on a conductive interconnect 602 as is illustrated in Figure 6. In an embodiment, the pSTTM memory device 600 is surrounded by a dielectric spacer layer 524. In an embodiment, the pSTTM memory device 600 has a width that is greater than the width of the conductive interconnect 602. In one such embodiment, a portion of the bottom electrode 504 of pSTTM memory device 600 is also disposed on a dielectric layer 603. In an embodiment, the pSTTM memory device 600 has a width smaller than the width of the conductive interconnect 602. In an embodiment, the pSTTM memory device 600 has a width equal to the width of the conductive interconnect 602.

[00140] In an embodiment, the underlying substrate 610 represents a surface used to manufacture integrated circuits. Suitable substrate 610 includes a material such as single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The substrate 610 may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.

[00141] In an embodiment, the access transistor 608 associated with substrate 610 are metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate 610. In various implementations of the invention, the access transistor 608 may be planar transistors, nonplanar transistors, or a combination of both.

Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

[00142] In an embodiment, the access transistor 608 of substrate 610 includes a gate stack formed of at least two layers, a gate dielectric layer 614 and a gate electrode layer 612. The gate dielectric layer 614 may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer 614 to improve its quality when a high-k material is used.

[00143] The gate electrode layer 612 of the access transistor 608 of substrate 610 is formed on the gate dielectric layer 614 and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an

MOS transistor. In some implementations, the gate electrode layer 612 may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer.

[00144] For a PMOS transistor, metals that may be used for the gate electrode layer 612 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an MOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

[00145] In some implementations, the gate electrode may consist of a "U'-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode 612 may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may consist of a combination of U- shaped structures and planar, non-U-shaped structures. For example, the gate electrode 612 may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[00146] In some implementations of the invention, a pair of sidewall spacers 616 may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers 616 may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[00147] As is well known in the art, source region 618 and drain region 606 are formed within the substrate adjacent to the gate stack of each MOS transistor. The source region 618 and drain region 606 are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source region 618 and drain region 606. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source region 618 and drain region 606. In some implementations, the source region 618 and drain region 606 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source region 618 and drain region 606 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source region 618 and drain region 606.

[00148] In an embodiment, a gate contact 620 and a source contact 622 are formed in a second dielectric layer 624 and in the dielectric layer 603 above the gate electrode 612 and source region 618, respectively.

[00149] Figure 7 illustrates a computing device 700 in accordance with one embodiment of the invention. The computing device 700 houses a motherboard 702. The motherboard 702 may include a number of components, including but not limited to a processor 704 and at least one communication chip 706. The processor 704 is physically and electrically coupled to the motherboard 702. In some implementations the at least one communication chip 706 is also physically and electrically coupled to the motherboard 702. In further implementations, the communication chip 706 is part of the processsor 704.

[00150] Depending on its applications, computing device 700 may include other components that may or may not be physically and electrically coupled to the motherboard 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non- volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

[00151] The communication chip 706 enables wireless communications for the transfer of data to and from the computing device 700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.17 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 700 may include a plurality of communication chips 706. For instance, a first communication chip 706 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. [00152] The processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704. In some implementations of embodiments of the invention, the integrated circuit die of the processor includes one or more memory devices, such as a pSTTM memory device 700, built with a pSTTM material layer stack 300A in accordance with embodiments of the present invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[00153] The communication chip 706 also includes an integrated circuit die packaged within the communication chip 706. In accordance with another implementation of an embodiment of the invention, the integrated circuit die of the communication chip includes pSTTM memory elements integrated with access transistors, built in accordance with

embodiments of the present invention.

[00154] In further implementations, another component housed within the computing device 700 may contain a stand-alone integrated circuit memory die that includes one or more memory elements, built in accordance with embodiments of the present invention.

[00155] In various implementations, the computing device 700 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 700 may be any other electronic device that processes data.

[00156] Accordingly, one or more embodiments of the present invention relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be non-volatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present invention relate to the fabrication of a pSTTM material layer stack 300A. Such pSTTM material layer stack 300A may be used in an embedded non-volatile memory application.

[00157] Figure 8 illustrates an interposer 800 that includes one or more embodiments of the invention. The interposer 800 is an intervening substrate used to bridge a first substrate 802 to a second substrate 804. The first substrate 802 may be, for instance, an integrated circuit die. The second substrate 804 may be, for instance, a memory module, a computer mother, or another integrated circuit die. Generally, the purpose of an interposer 800 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 800 may couple an integrated circuit die to a ball grid array (BGA) 806 that can subsequently be coupled to the second substrate 804. In some embodiments, the first and second substrates 802/804 are attached to opposing sides of the interposer 800. In other embodiments, the first and second substrates 802/804 are attached to the same side of the interposer 800. And in further embodiments, three or more substrates are interconnected by way of the interposer 800.

[00158] The interposer 800 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further

implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

[00159] The interposer may include metal interconnects 808 and vias 810, including but not limited to through-silicon vias (TSVs) 810. The interposer 800 may further include embedded devices 814, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, transistors, pSTTM devices, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 800. In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer 800.

[00160] Thus, embodiments of the present invention include perpendicular spin torque transfer memory (pSTTM) devices with enhanced stability and methods to form same.

[00161] Specific embodiments are described herein with respect to perpendicular spin transfer torque memory (pSTTM) devices. It is to be appreciated that embodiments described herein may also be applicable to other non-volatile memory devices. Such non-volatile memory devices may include, but are not limited to, magnetic random access memory (MRAM) devices, spin torque transfer memory (STTM) devices and spin orbit torque (SOT) memory devices.

[00162] Example 1 : A material layer stack for a perpendicular spin transfer torque memory (pSTTM) device includes a fixed magnetic layer. A tunnel barrier is disposed above the fixed magnetic layer. A free magnetic layer is disposed on the tunnel barrier, where the free magnetic layer includes a bilayer stack, where the bilayer stack includes a first magnetic layer disposed on the tunnel barrier and a second magnetic layer consisting essentially of iron is disposed on the first magnetic layer. An oxide layer is disposed on the storage layer.

[00163] Example 2: The material layer stack of example 1, wherein the first magnetic layer includes cobalt and iron.

[00164] Example 3 : The material layer stack of example 2, wherein the first magnetic layer further includes boron.

[00165] Example 4: The material layer stack of example 1 or 3, wherein the boron concentration is at least 30%.

[00166] Example 5: The material layer stack of example 1, wherein the second magnetic layer has an iron content of at least 99% and boron content of less than 1%.

[00167] Example 6: The material layer stack of example 1, 2, 3 or 5, wherein the first magnetic layer and the second magnetic layer of the bilayer stack have a combined total thickness between l .Onm - 2.5nm.

[00168] Example 7: The material layer stack of example 1 or 6, wherein the first magnetic layer in the bilayer stack has a thickness that is greater than the thickness of the second magnetic layer in the bilayer stack.

[00169] Example 8: The material layer stack of example 1, wherein the first magnetic layer has a thickness between 0.6nm - 1.5nm.

[00170] Example 9: The material layer stack of example 1, wherein the second magnetic layer has a thickness between O. lnm - l .Onm.

[00171] Example 10: A material layer stack for a perpendicular spin transfer torque memory (pSTTM) device includes a fixed magnetic layer. A tunnel barrier is disposed above the fixed magnetic layer. A storage layer is disposed on the tunnel barrier, wherein the storage layer includes a first free layer disposed on the tunnel barrier. A coupling layer is disposed on the first free layer and a second free layer is disposed on the coupling layer, wherein one of the first free layer or the second free layer includes a bilayer stack, and wherein the bilayer stack includes a first magnetic layer disposed on the tunnel barrier and a second magnetic layer consisting essentially of iron disposed on the first magnetic layer.

[00172] Example 11 : The material layer stack of example 10, wherein the first free layer includes the single magnetic layer and the second free layer includes the bilayer stack.

[00173] Example 12: The material layer stack of example 10 or 11, wherein the first free layer has a thickness that is greater than the thickness of second free layer comprising the bilayer stack.

[00174] Example 13 : The material layer stack of example 10, wherein the first free layer includes the bilayer stack.

[00175] Example 14: The material layer stack of example 10 or 13, wherein the first free layer comprising the one or more magnetic layers has a thickness that is greater than a thickness of the second free layer comprising a single magnetic layer.

Example 15: The material layer stack of example 10 or 13, wherein the second free layer includes a second bilayer stack, wherein the second bilayer stack has an iron composition of at least 50%.

[00176] Example 16: The material layer stack of example 10, 13 or 15, wherein the second free layer comprising the second bilayer stack has a thickness that is less than the thickness of first free layer comprising the bilayer stack.

[00177] Example 17: The material layer stack of example 16, wherein the first free layer includes a first magnetic layer comprising cobalt, boron and iron and a second magnetic layer consisting essentially of iron and wherein the second free magnetic layer includes a third magnetic layer comprising cobalt, boron and iron and a fourth magnetic layer consisting essentially of iron.

[00178] Example 18: The material layer stack of example 17, wherein the second magnetic layer consisting essentially of iron and having a thickness between 0.1nm-0.6nm is disposed on first magnetic layer and wherein the fourth magnetic layer consisting essentially of iron and having a thickness between 0. lnm-0.6nm is disposed on third magnetic layer.

[00179] Example 19: The material layer stack of example 17, wherein the fourth magnetic layer consisting essentially of iron is disposed on the coupling layer.

[00180] Example 20: The material layer stack of example 17, wherein the first magnetic layer and the third magnetic layer have a boron content between 10%-50%.

[00181] Example 21 : The material layer stack of example 10, wherein the material layer stack further includes an oxide layer disposed on the storage layer. A protective layer is disposed on the oxide layer. A capping layer is disposed directly on the protective layer. A bottom electrode layer is disposed below the fixed layer. A top electrode layer is disposed above the capping layer. A synthetic antiferromagnetic layer disposed between the fixed layer and the bottom electrode layer.

[00182] Example 22: A method of fabricating a material layer stack for a perpendicular spin transfer torque memory (pSTTM) device includes forming a conductive interconnect structure and forming a bottom electrode layer on the conductive interconnect structure. The method further includes forming a fixed magnetic layer above the bottom electrode, forming a tunnel barrier on the fixed magnetic layer, forming a storage layer on the tunnel barrier. Forming the storage layer further includes forming a first free layer on the tunnel barrier, forming a coupling layer on the first free layer, forming a second free layer on the coupling layer, wherein forming the first free layer or the second free layer includes forming a bilayer stack. The method further includes forming an oxide layer on the coupling layer, forming a protective layer on the oxide layer, forming a capping directly on the protective layer and forming a top electrode layer on the capping layer.

[00183] Example 23 : The method of example 22, wherein forming the bilayer stack includes depositing a first magnetic layer including cobalt, boron and iron and depositing a second magnetic layer consisting essentially of iron and further wherein depositing the second magnetic layer on the first magnetic layer causes intermixing between the first magnetic layer and the second magnetic layer.

[00184] Example 24: The method of example 22, further includes patterning the top electrode layer, etching the material layer stack formed on the conductive interconnect structure and performing an in-situ dielectric spacer layer deposition on the etched material layer stack. The method further includes etching the dielectric spacer layer.

Claims

CLAIMS What is claimed is:

1. A material layer stack for a perpendicular spin transfer torque memory (pSTTM) device, the material layer stack comprising:

a fixed magnetic layer;

a tunnel barrier above the fixed magnetic layer;

a free magnetic layer on the tunnel barrier, the free magnetic layer comprising a bilayer stack, wherein the bilayer stack comprises a first magnetic layer on the tunnel barrier and a second magnetic layer consisting essentially of iron on the first magnetic layer; and

an oxide layer on the storage layer.

2. The material layer stack of claim 1, wherein the first magnetic layer comprises cobalt and iron.

3. The material layer stack of claim 2, wherein the first magnetic layer further comprises boron.

4. The material layer stack of claim 3, wherein the boron concentration is at least 30%.

5. The material layer stack of claim 1, wherein the second magnetic layer has an iron content of at least 99% and boron content of less than 1%.

6. The material layer stack of claim 1, wherein the first magnetic layer and the second magnetic layer of the bilayer stack have a combined total thickness between l .Onm - 2.5nm.

7. The material layer stack of claim 1, wherein the first magnetic layer in the bilayer stack has a thickness that is greater than the thickness of the second magnetic layer in the bilayer stack.

8. The material layer stack of claim 1, wherein the first magnetic layer has a thickness between 0.6nm - 1.5nm.

9. The material layer stack of claim 1, wherein the second magnetic layer has a thickness between O. lnm - l .Onm.

A material layer stack for a perpendicular spin transfer torque memory (pSTTM) device, the material layer stack comprising:

a fixed magnetic layer;

a tunnel barrier above the fixed magnetic layer; and

a storage layer on the tunnel barrier, wherein the storage layer comprises a first free layer on the tunnel barrier, a coupling layer on the first free layer and a second free layer on the coupling layer, wherein one of the first free layer or the second free layer comprises a bilayer stack, wherein the bilayer stack comprises a first magnetic layer on the tunnel barrier and a second magnetic layer consisting essentially of iron on the first magnetic layer.

11. The material layer stack of claim 10, wherein the first free layer comprises the single magnetic layer and the second free layer comprises the bilayer stack.

12. The material layer stack of claim 11, wherein the first free layer has a thickness that is greater than the thickness of second free layer comprising the bilayer stack.

13. The material layer stack of claim 10, wherein the first free layer comprises the bilayer stack.

14. The material layer stack of claim 13, wherein the first free layer comprising the one or more magnetic layers has a thickness that is greater than a thickness of the second free layer comprising a single magnetic layer.

15. The material layer stack of claim 13, wherein the second free layer comprises a second bilayer stack, wherein the second bilayer stack has an iron composition of at least 50%.

16. The material layer stack of claim 15, wherein the second free layer comprising the second bilayer stack has a thickness that is less than the thickness of first free layer comprising the bilayer stack.

17. The material layer stack of claim 16, wherein the first free layer comprises a first magnetic layer comprising cobalt, boron and iron and a second magnetic layer consisting essentially of iron and wherein the second free magnetic layer comprises a third magnetic layer comprising cobalt, boron and iron and a fourth magnetic layer consisting essentially of iron.

18. The material layer stack of claim 17, wherein the second magnetic layer consisting essentially of iron and having a thickness between 0. lnm-0.6nm is on the first magnetic layer and wherein the fourth magnetic layer consisting essentially of iron and having a thickness between 0. lnm-0.6nm is on the third magnetic layer.

19. The material layer stack of claim 17, wherein the fourth magnetic layer consisting essentially of iron is on the coupling layer.

20. The material layer stack of claim 17, wherein the first magnetic layer and the third magnetic layer have a boron content between 10%-50%.

21. The material layer stack of claim 10, wherein the material layer stack further comprises: an oxide layer on the storage layer;

a protective layer on the oxide layer;

a capping layer directly on the protective layer;

a bottom electrode layer below the fixed layer;

a top electrode layer above the capping layer; and

a synthetic antiferromagnetic layer between the fixed layer and the bottom electrode layer.

22. A method of fabricating a material layer stack for a perpendicular spin transfer torque memory (pSTTM) device, the method comprising:

forming a conductive interconnect structure;

forming a bottom electrode layer on the conductive interconnect structure;

forming a fixed magnetic layer;

forming a tunnel barrier on the fixed magnetic layer;

forming a storage layer, wherein forming a storage layer further comprises:

forming a first free layer on the tunnel barrier;

forming a coupling layer on the first free layer;

forming a second free layer on the coupling layer, wherein forming the first free layer or the second free layer comprises forming a bilayer stack;

forming an oxide layer on the coupling layer;

forming a protective layer on the oxide layer;

forming a capping directly on the protective layer; and

forming a top electrode layer on the capping layer.

23. The method of claim 22, wherein forming the bilayer stack includes depositing a first magnetic layer including cobalt, boron and iron and depositing a second magnetic layer consisting essentially of iron and further wherein depositing the second magnetic layer on the first magnetic layer causes intermixing between the first magnetic layer and the second magnetic layer.

The method of claim 22, further comprises:

patterning the top electrode;

etching the material layer stack formed on the conductive interconnect structure;

performing a dielectric spacer layer deposition on the etched material layer stack; and

etching the dielectric spacer layer.