WO2018182619A1

WO2018182619A1 - Co-integrating compositionally different semiconductor materials using a common thin seed layer

Info

Publication number: WO2018182619A1
Application number: PCT/US2017/025018
Authority: WO
Inventors: Willy Rachmady; Marko Radosavljevic; Van H. Le; Ravi Pillarisetty; Matthew V. Metz; Ashish Agrawal; Benjamin Chu-Kung; Gilbert Dewey; Seung Hoon Sung
Original assignee: Intel Corporation
Priority date: 2017-03-30
Filing date: 2017-03-30
Publication date: 2018-10-04

Abstract

Techniques are disclosed for monolithically co-integrating compositionally different semiconductor materials using a common thin monocrystalline semiconductor seed layer. In some embodiments, the shared seed layer allows for the overlying compositionally different monocrystalline semiconductor materials to be formed in a defect free or substantially defect free manner. This occurs because the seed layer is sufficiently thin such that it can allow itself to be strained by the growth of overlying monocrystalline semiconductor fin structures, which is referred to as strain transfer or compliant effect. As a result, misfit dislocations that would otherwise form in the overlying monocrystalline semiconductor material of the fins formed on the seed layer may not form at all (or may form at a lower rate/quantity), enabling the monocrystalline semiconductor material fins to be formed in an enhanced quality manner. Non-planar transistor architectures such as FinFET and gate-all-around can be formed using the fins.

Description

CO-INTEGRATING COMPOSITIONALLY DIFFERENT SEMICONDUCTOR MATERIALS

USING A COMMON THIN SEED LAYER

BACKGROUND

Semiconductor devices are electronic components that exploit the electronic properties of semiconductor materials, such as silicon, germanium, and gallium arsenide. A field-effect transistor (FET) is a semiconductor device that includes three terminals: a gate, a source, and a drain. A FET uses an electric field applied by the gate to control the electrical conductivity of a channel through which charge carriers (e.g., electrons or holes) flow from the source to the drain. In instances where the charge carriers are electrons, the FET is referred to as an n-channel device, and in instances where the charge carriers are holes, the FET is referred to as a p -channel device. Some FETs have a fourth terminal called the body or substrate, which can be used to bias the transistor. In addition, metal-oxide-semiconductor FETs (MOSFETs) include a gate dielectric between the gate and the channel. MOSFETs may also be known as metal-insulator- semiconductor FETs (MISFETSs) or insulated-gate FETs (IGFETs). Complementary MOS (CMOS) structures use a combination of p-channel MOSFET (p-MOS) and n-channel MOSFET (n-MOS) to implement logic gates and other digital circuits.

A FinFET is a MOSFET transistor built around a thin strip of semiconductor material (generally referred to as a fin). The conductive channel of the FinFET device resides on the outer portions of the fin adjacent to the gate dielectric. Specifically, current runs along/within both sidewalls of the fin (sides perpendicular to the substrate surface) as well as along the top of the fin (side parallel to the substrate surface). Because the conductive channel of such configurations essentially resides along the three different outer regions of the fin (e.g., top and two sides), such a FinFET design is sometimes referred to as a tri-gate transistor. Other types of FinFET configurations are also available, such as so-called double-gate FinFETs, in which the conductive channel principally resides only along the two sidewalls of the fin (and not along the top of the fin). Generally, such multiple-gate FETs may be referred to as MuGFETs. A nanowire transistor (sometimes referred to as a gate-all-around (GAA) or nanoribbon transistor) is configured similarly to a fin-based transistor, but instead of a finned channel region where the gate is on three portions (and thus, there are three effective gates), one or more nanowires are used for the channel region and the gate material generally surrounds each nanowire. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates a method of forming an integrated circuit (IC) including different and defect free (or substantially defect free) semiconductor material structures using a thin seed layer, in accordance with some embodiments of the present disclosure.

Figures 2A-N illustrate example IC structures formed when carrying out the method of

Figure 1, in accordance with some embodiments of the present disclosure.

Figure 2K' illustrates a blown-out portion of Figure 2K to illustrate a variation including no shallow trench isolation (STI) material, in accordance with some embodiments.

Figures 3 A-B illustrate example cross-sectional views taken along the planes A- A and B-B in Figure 2N, respectively, in accordance with some embodiments.

Figure 4 illustrates a computing system implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed herein, in accordance with some embodiments of the present disclosure.

These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. Further still, some of the features in the drawings may include a patterned and/or shaded fill, which is merely provided to assist in visually identifying the different features. In short, the figures are provided merely to show example structures.

DETAILED DESCRIPTION

With the semiconductor industry utilizing CMOS circuitry for a multitude of applications, where CMOS circuitry includes both n-MOS and p-MOS devices, various issues arise in the co- integration of the n-MOS and p-MOS devices. For instance, when monolithically integrating n- MOS and p-MOS devices using the same substrate, forming high performance versions of both devices can be difficult. In general, n-MOS and p-MOS devices perform better with relatively different semiconductor materials. In the context of forming transistor devices with high- mobility channel materials, germanium (Ge)-rich material (e.g., Ge or silicon germanium with high Ge content) is preferred for p-channel transistors (e.g., p-MOS devices) as Ge-rich material enables relatively high hole mobility, whereas group III-V semiconductor material (e.g., indium gallium arsenide) is preferred for n-channel transistors (e.g., n-MOS devices) as group III-V semiconductor material enables relatively high electron mobility, to provide some examples. However, it is difficult to effectively co-integrate such dissimilar semiconductor material to be used in transistor channels on a common substrate, because it is difficult to form the different semiconductor materials in a suitably defect free manner given the diverse lattice constants of the materials involved (e.g., due to the lattice mismatch between the substrate and at least one of the two materials to be co-integrated). The issue of effectively co -integrating compositionally different semiconductor material that is substantially defect free is particularly challenging when trying to maintain compatibility with conventional CMOS process flows. This issue is further exacerbated when the transistor devices being formed are scaled down to relatively small critical dimensions (e.g., where transistor lateral gate lengths are sub-30 nm).

Thus, and in accordance with numerous embodiments of the present disclosure, techniques are provided for co-integrating compositionally different semiconductor materials using a common thin monocrystalline semiconductor seed layer. In some embodiments, the thin monocrystalline (or single crystal) semiconductor seed layer allows for overlying epitaxial monocrystalline semiconductor material to be formed in a defect free or substantially defect free manner. This occurs because the seed layer may be sufficiently thin such that it allows itself to be strained by the overlying semiconductor material during epitaxial growth of that material. This self-strain effect is referred to as strain transfer or compliant effect. As a result, misfit dislocations that would otherwise be present due to lattice mismatch between the monocrystalline semiconductor seed layer material and the overlying monocrystalline semiconductor material may not form (or may form at a lower rate/quantity), enabling that overlying semiconductor material to be formed with relatively high quality or suitable device quality, in accordance with some embodiments. Thus, as can be understood based on this disclosure, a shared seed layer can be used for forming two or more different overlying monocrystalline semiconductor fin structures, where the different fin structures include compositionally different semiconductor material. For instance, a thin silicon (Si) seed layer (e.g., having a thickness less than 20 nm) can be employed to enable the co-integration of high/device quality Ge-rich fins (e.g., to be used for p-channel transistors) and high/device quality group III-V fins (e.g., to be used for n-channel transistors), to provide an example combination. In such an example combination, if the Si seed layer is not sufficiently thin (e.g., if it has a thickness greater than 20 nm), then the strain transfer or compliant effect may not occur

(or may not fully occur), which would result in misfit dislocations forming in the overlying epitaxial material due to the lattice mismatch between the epitaxial material and the seed layer material, in this specific example case. Therefore, in some embodiments, the thin seed layer can be used to provide a suitable growth surface for a multitude of different semiconductor materials while preventing or otherwise reducing misfit dislocations (and/or other defects) that would otherwise be present without using such a thin seed layer, thereby enabling the monolithic co- integration of compositionally different and defect free (or substantially defect free) semiconductor materials for a single integrated circuit (IC).

In some embodiments, the suitable maximum thickness of the seed layer may be based on the semiconductor material included in the seed layer and/or the overlying material formed on the seed layer, as different semiconductor material may exhibit strain transfer or compliant effect up to different maximum thicknesses. In some embodiments, the seed layer may include a thickness (e.g., the dimension between the overlying monocrystalline material and the underlying material) in the range of 1-50 nm (or in the sub-range of 1-5, 1-10, 1-20, 2-5, 2-20, 2-50, 3-10, 3- 20, 3-50, 5-10, 5-20, 8-20, 10-20, 15-20, or 5-50 nm), or any other suitable thickness value or range that will allow the seed layer itself to be strained by epitaxial growth of diverse semiconductor material thereon, as will be apparent in light of this disclosure. In some embodiments, the seed layer may include a thickness of less than 50, 40, 30, 25, 20, 15, 10, 8, 5, 4, 3, or 2 nm, or less than any other suitable threshold that will allow the seed layer itself to be strained by epitaxial growth of diverse semiconductor material thereon, as will be apparent in light of this disclosure. In some embodiments, it may be desired to form the seed layer in a relatively thin manner, such as with a thickness in the range of 1 -5 nm, so that it is not significantly contributing to conduction or other parasitic effects, for example. In some embodiments, the seed layer may be transferred to a host wafer, such that a structure used for the techniques described herein may include a substrate, the seed layer, and an insulator layer between the substrate and the seed layer (e.g., in a buried oxide (BOX) scheme). Such a structure may be formed via bonding and/or any other suitable techniques (e.g., techniques used in forming silicon on insulator (SOI) structures), to ensure that the seed layer includes monocrystalline semiconductor material (or otherwise suitably structured semiconductor material) from which compositionally different semiconductor materials can be grown. Further, such a structure including a layer of electrically insulating material may provide enhanced isolation for transistors formed above that layer, as compared to structures lacking that electrically insulating layer. As will be apparent in light of this disclosure, the seed layer may include any suitable semiconductor material, such as group IV, group III-V, and/or group II- VI semiconductor material.

The use of "group IV semiconductor material" (or "group IV material" or generally, "IV") herein includes at least one group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon germanium (SiGe), and so forth. The use of "group III-V semiconductor material" (or "group III-V material" or generally, "III-V") herein includes at least one group III element (e.g., aluminum, gallium, indium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), gallium nitride (GaN), and so forth. The use of "group II- VI semiconductor material" (or "group II-VI material" or generally, "II- VI") herein includes at least one group II element (e.g., zinc, cadmium, mercury) and at least one group VI element (e.g., oxygen, sulfur, selenium, tellurium), such as zinc oxide (ZnO), zinc sulfide (ZnS), cadmium selenide (CdSe), cadmium telluride (CdTe), mercury zinc telluride (HgZnTe), mercury cadmium telluride (HgCdTe), and so forth. Note that group II may also be known as the zinc group or IUPAC group 12, group III may also be known as the boron group or IUPAC group 13, group IV may also be known as the carbon group or IUPAC group 14, group V may also be known as the nitrogen family or IUPAC group 15, and group VI may also be known as the oxygen group or IUPAC group 16, for example. Defect free as used herein with respect to semiconductor material or a feature/lay er/structure including semiconductor material means (at least) having no misfit dislocations. Substantially defect free as used herein with respect to semiconductor material or a feature/lay er/structure including semiconductor material means (at least) having no more than 1 or 2 misfit dislocations (in other words, having a maximum of 1 or 2 misfit dislocations) per the material or the feature/lay er/structure. Compositionally different as used herein with respect to semiconductor materials or features/layers/ structures including semiconductor material means (at least) including different semiconductor materials or including the same semiconductor material but with a different compositional ratio (e.g., where the concentration of at least one component of the material is different). For instance, Ge is compositionally different than InGaAs (as they are different semiconductor materials), but Si_0.7Ge_0.3 is also compositionally different than Si_0.4Ge₀.6 (as they include different compositional ratios). Moreover, SiGe with a Ge concentration in the range of 0 to 30% is compositionally different than SiGe with a Ge concentration in the range of 31 to 100%. In some embodiments, the techniques include using a shared seed layer to form the compositionally different semiconductor material in fin-shaped trenches, such that the resulting replacement structures are fin-shaped. In some such embodiments, the fin-shaped trenches may be formed by first forming a sacrificial material on the seed layer, forming the seed layer/sacrificial material stack into fins, forming electrically insulating material (e.g., interlayer dielectric (ILD) material) around the fins, removing a subset of the sacrificial material fins to expose the seed layer and form fin-shaped trenches, growing replacement material on the seed layer and in the fin- shaped trenches to form a first subset of replacement material fins, and repeating the removing and growing processes as many times as desired to form any desired number of subsets of replacement material fins. Further, in some such embodiments, the different replacement materials can be formed into fin structures without using subtractive patterning/etching of the replacement materials, which can be challenging for certain semiconductor materials (e.g., III-V materials) and/or which may cause relatively lower quality fin structures than the aforementioned fin- shaped trench approach. As can be understood based on this disclosure, the replacement material includes semiconductor material to be used in the channel region of one or more transistors, in accordance with some embodiments. For instance, in some such embodiments, a first subset of replacement material fins may be used to form n- channel FETs, while a second subset of replacement material fins may be used to form p-channel FETs, such that the different replacement materials can be selected to benefit/enhance those particular devices (e.g., to provide increased carrier mobility for the particular devices).

Generally, in some embodiments, the techniques described herein can be used for p- channel and/or n-channel transistor devices, such as a p-channel MOSFET (p-MOS), p-channel tunnel FET (p-TFET), n-channel MOSFET (n-MOS), n-channel TFET (n-TFET), and/or other FET devices, to provide some example transistor devices. Further, in some embodiments, the techniques described herein can be used to form complementary transistor circuits, such as CMOS circuits, where the techniques described herein may be used to benefit one or more of the included n-channel and/or p-channel transistors making up a given CMOS circuit. Further still, in some embodiments, the techniques described herein can be used to benefit a multitude of transistor configurations, such as planar and non-planar configurations, where the non-planar configurations may include finned or FinFET configurations (e.g., dual-gate or tri-gate), gate-all- around (GAA) configurations (e.g., nanowire or nanoribbon), or some combination thereof (e.g., beaded-fin configurations), to provide a few examples. For instance, in embodiments where the replacement semiconductor material structures are formed using fin-shaped trenches, the surrounding isolation (e.g., ILD) material need not be recessed, such that planar transistors can be formed using the top surface of the fin-shaped structures. Further, in embodiments where the replacement semiconductor material structures are formed using fin-shaped trenches, the surrounding isolation (e.g., ILD) material may be recessed or removed to allow access to at least a portion of the fin-shaped structures to form finned (e.g., dual-gate or tri-gate) transistor devices. Further still, in embodiments where the replacement semiconductor material structures are formed using fin-shaped trenches, the fin-shaped structures formed may include a multilayer scheme that includes sacrificial layers to be later removed, thereby forming one or more nanowires/nanoribbons to be used for GAA transistor devices. Therefore, the techniques described herein can be used to form a multitude of transistor devices.

Note that, as used herein, the expression "X includes at least one of A and B" refers to an

X that may include, for example, just A only, just B only, or both A and B. To this end, an X that includes at least one of A and B is not to be understood as an X that requires each of A and B, unless expressly so stated. For instance, the expression "X includes A and B" refers to an X that expressly includes both A and B. Moreover, this is true for any number of items greater than two, where "at least one of those items is included in X. For example, as used herein, the expression "X includes at least one of A, B, and C" refers to an X that may include just A only, just B only, just C only, only A and B (and not C), only A and C (and not B), only B and C (and not A), or each of A, B, and C. This is true even if any of A, B, or C happens to include multiple types or variations. To this end, an X that includes at least one of A, B, and C is not to be understood as an X that requires each of A, B, and C, unless expressly so stated. For instance, the expression "X includes A, B, and C" refers to an X that expressly includes each of A, B, and C.

Use of the techniques and structures provided herein may be detectable using tools such as: electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDS); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. In particular, in some embodiments, such tools may indicate an integrated circuit (IC) including monolithically co- integrated defect free (or substantially defect free) and different semiconductor material on (or above) a single seed layer formed on (or above) a substrate. In some embodiments, the seed layer may be sufficiently thin (e.g., having a thickness of less than 50, 40, 30, 25, 20, 15, 10, or 5 nm) such that the seed layer allows itself to be strained during the epitaxial growth of semiconductor material on the seed layer, which is referred to as strain transfer (or compliant effect), as any strain that would have otherwise been formed in that overlying epitaxial semiconductor material is instead transferred to the seed layer (e.g., in the case where the seed layer semiconductor material and the overlying epitaxial semiconductor material are lattice mismatched). Therefore, electron microscopy techniques (e.g., SEM, TEM, STEM) can be used to determine if the techniques described herein are used to form the structures described herein, for example. Numerous configurations and variations will be apparent in light of this disclosure.

Architecture and Methodology

Figure 1 illustrates method 100 of forming an integrated circuit (IC) including different and defect free (or substantially defect free) semiconductor material structures using a thin seed layer, in accordance with some embodiments of the present disclosure. Figures 2A-N illustrate example IC structures formed when carrying out method 100 of Figure 1 , in accordance with some embodiments of the present disclosure. Note that the techniques and structures described herein are primarily depicted and described in the context of forming finned or FinFET transistor configurations (e.g., tri-gate transistor configurations), for ease of illustration. However, in some embodiments, the techniques may be used to form transistors of any suitable geometry or configuration, as will be apparent in light of this disclosure. For example, Figure 2M illustrates an example integrated circuit structure including transistors having nanowire configurations, as will be described in more detail below. Also note that the techniques and structures are primarily depicted and described in the context of forming metal-oxide-semiconductor field-effect transistors (MOSFETs), and specifically, forming both n-channel MOSFET (n-MOS) and p- channel MOSFET (p-MOS) devices. However, in some embodiments, the techniques may be used to benefit any suitable transistor type, as will be apparent in light of this disclosure, such as tunnel FET (TFET) devices or other suitable FET devices. Other example transistor devices include few to single electron quantum transistor devices, for example. As will be apparent in light of this disclosure, because the techniques allow for the monolithic co -integration of different and defect free (or substantially defect free) semiconductor materials, the different materials can be selected based on their suitability for p-channel and n-channel transistor devices, such as selecting high-mobility material for each set of devices (e.g., Ge-rich material for p-channel transistor devices and III-V material for n-channel transistor devices).

In some embodiments, the techniques may be used to form complementary transistor circuits, such as CMOS circuits, that include at least one p-channel transistor and at least one n- channel transistor. Note that in some such embodiments, co-integration of the p-channel and n- channel transistor devices using techniques described herein may include that the devices are electrically connected to each other (e.g., in a CMOS circuit). However, in other embodiments, p-channel and n-channel devices need not be electrically connected to each other to be co- integrated, but may instead operate independently from each other and merely be monolithically formed using the same substrate. Further still, such devices may employ semiconductor materials that are three dimensional crystals as well as two dimensional crystals or nanotubes, for example. Further still, in some embodiments, the different semiconductor material structures formed as described herein need not be formed into transistor devices, but may instead be used for any other suitable purpose, such as to provide electrical isolation between transistors (e.g., where a first semiconductor material structure provides electrical isolation for a second semiconductor material structure), to provide structures for a transistor and a non -transistor semiconductor device (e.g., where a first semiconductor material structure is used to form a transistor and a second semiconductor material structure is used to form a non -transistor structure), to provide structures for other semiconductor devices entirely (e.g., where a first semiconductor material structure is used to form a first non-transistor semiconductor device and where a second semiconductor material structure is used to form a second non -transistor semiconductor device), and/or for any other purpose as will be apparent in light of this disclosure. Generally, being able to monolithically co-integrate compositionally different and defect free (or substantially defect free) monocrystalline semiconductor material using a thin seed layer as described herein can enable a multitude of applications. In some embodiments, the techniques may be used to benefit devices of varying scales, such as IC devices having critical dimensions in the micrometer (micron) range and/or in the nanometer (nm) range (e.g., formed at the 22, 14, 10, 7, 5, or 3 nm process nodes, or beyond).

Method 100 of Figure 1 includes providing 102 a multilayer substrate including a thin seed layer on top, in accordance with some embodiments. An example of such a multilayer substrate is shown in Figure 2A, where the multilayer substrate includes substrate layer 200, insulator layer 205, and seed layer 210, in this example embodiment. Generally, in this example embodiment, substrate layer 200 and seed layer 210 include semiconductor material, while insulator layer 205 includes electrically insulating material, such that the multilayer substrate 200/205/210 includes a semiconductor/insulator/semiconductor configuration. Note that in some embodiments, insulator layer 205 need not be present, such that seed layer 210 may be formed directly on substrate 200, for example. Also note that in some embodiments, additional layers may be included in the multilayer substrate prior to continuing with method 100, for example. In some embodiments, the multilayer substrate of Figure 2A may be formed using any suitable techniques. For instance, the multilayer substrate may be formed using separation by implantation of oxygen (SIMOX) processing, such as in the case of insulator layer 205 being a buried oxide (BOX) layer, whereby oxygen ion beam implantation may be performed followed by high temperature annealing to create a buried silicon dioxide layer (or other suitable insulator layer 205), to provide an example. The multilayer substrate of Figure 2A may also be formed using wafer bonding techniques, whereby the insulator layer is formed by bonding, e.g., oxidized silicon with a second substrate followed by removing the majority of the second substrate, thereby forming seed layer 210 on the top of the multilayer substrate, to provide another example. The multilayer substrate of Figure 2A may also be formed using seed methods, such as growing seed layer 210 directly on insulator layer 205 (e.g., where insulator layer is chemically treated or includes an appropriately oriented monocrystalline structure) or by forming vias through insulator layer 205 from base substrate 200 to form a template from which to grow seed layer 210, to provide some additional examples. In some cases, multilayer substrate may come pre-formed at least in part, such as readily available semiconductor on insulator multilayer substrates (e.g., silicon on insulator (SOI) substrates).

Substrate 200, in some embodiments, may include group IV semiconductor material (such as silicon (Si), germanium (Ge), silicon germanium (SiGe), or silicon carbide (SiC)), group III-V semiconductor material (such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or indium phosphide (InP)), other semiconductor material (e.g., group II-VI semiconductor material), and/or any other suitable material(s) as will be apparent in light of this disclosure. Recall that the use of "group IV semiconductor material" (or "group IV material" or generally, "IV") herein includes at least one group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon germanium (SiGe), and so forth. Also recall that the use of "group III-V semiconductor material" (or "group III-V material" or generally, "III-V") herein includes at least one group III element (e.g., aluminum, gallium, indium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), gallium nitride (GaN), and so forth. Further recall that the use of "group II-VI semiconductor material" (or "group II- VI material" or generally, "II-VI") herein includes at least one group II element (e.g., zinc, cadmium, mercury) and at least one group VI element (e.g., oxygen, sulfur, selenium, tellurium), such as zinc oxide (ZnO), zinc sulfide (ZnS), cadmium selenide (CdSe), cadmium telluride (CdTe), mercury zinc telluride (HgZnTe), mercury cadmium telluride (HgCdTe), and so forth. In some embodiments, substrate 200 may be doped with any suitable n-type and/or p-type dopant (such as in a concentration in the range of IE 16 to 1E22 atoms per cubic cm). For instance, where substrate 200 includes Si, the Si may be p-type doped using a suitable acceptor (e.g., boron) or n-type doped using a suitable donor (e.g., phosphorous, arsenic), to provide some example cases. However, in some embodiments, substrate 200 may be undoped/intrinsic or relatively minimally doped, such as including a dopant concentration of less than 1E16 atoms per cubic centimeter (cm), for example.

In some embodiments, substrate 200 may include a surface crystalline orientation described by a Miller Index of <100>, <110>, or <111>, or its equivalents, as will be apparent in light of this disclosure. Although substrate 200, in this example embodiment, is shown as having a thickness (dimension in the Y-axis direction) similar to other layers shown in the multilayer substrate of Figure 2 A (and similar to features in subsequent features) for ease of illustration, in some instances, substrate 200 may be relatively much thicker than the other layers, such as having a thickness in the range of 1 to 950 microns (or in the sub-range of 20 to 800 microns), for example, or any other suitable thickness value or range as will be apparent in light of this disclosure. In some embodiments, substrate 200 may include a multilayer structure including two or more distinct layers. In some embodiments, substrate 200 may include grading (e.g., increasing and/or decreasing) of one or more material concentrations throughout at least a portion of the substrate 200. In some embodiments, substrate 200 may be used for one or more other IC devices, such as various diodes (e.g., light-emitting diodes (LEDs) or laser diodes), various transistors (e.g., MOSFETs or TFETs), various capacitors (e.g., MOSCAPs), various microelectromechanical systems (MEMS), various nanoelectromechanical systems (NEMS), various sensors, various radio frequency (RF) devices, and/or any other suitable semiconductor or IC device(s), depending on the end use or target application. Accordingly, in some embodiments, the structures described herein may be included in a system-on-chip (SoC) application, as will be apparent in light of this disclosure.

Insulator layer 205, in some embodiments, may include one or more oxides (e.g., silicon dioxide, aluminum oxide), nitrides (e.g., silicon nitride), dielectrics (e.g., high-k or low-k dielectrics), and/or any other suitable electrically insulating material as will be apparent in light of this disclosure. In some embodiments, the multilayer substrate of Figure 2A may be considered an XOI structure, where 'X' represents semiconductor material included in seed layer 210, Ό' represents on, and T represents the electrically insulating material in insulator layer 205, for example. An example of such a structure is a silicon on insulator (SOI) structure. In some embodiments, insulator layer 205 may include any suitable thickness (dimension in the Y- axis direction), such as a thickness in the range of 10 nm to 3 microns (or in the sub-range of 50 nm to 1 micron), for example, or any other suitable thickness value or range as will be apparent in light of this disclosure. In some embodiments, insulator layer 205 may include a multilayer structure including two or more distinct layers. In some embodiments, insulator layer 205 may include grading (e.g., increasing and/or decreasing) of one or more material concentrations throughout at least a portion of the insulator layer 205. As previously described, in some embodiments, insulator layer 205 need not be present. In some such embodiments, seed layer 210 may be formed directly on substrate 200, for example. Further, in some such embodiments, substrate 200 need not include semiconductor material, and may instead include electrically insulating material, such as sapphire and/or other dielectric material, such that the seed layer is still formed on electrically insulating material. However, in some embodiments, seed layer 210 may be formed on semiconductor material (such as where seed layer 210 is formed on a substrate including semiconductor material), for example.

Seed layer 210, in some embodiments, may include monocrystalline group IV semiconductor material (such as Si, Ge, SiGe, or SiC), monocrystalline group III-V semiconductor material (such as GaAs, InGaAs, or InP), other monocrystalline semiconductor material (e.g., group II-VI semiconductor material), and/or any other suitable material(s) as will be apparent in light of this disclosure. In some embodiments, seed layer 210 may be doped with any suitable n-type and/or p-type dopant (such as in a concentration in the range of IE 16 to 1E22 atoms per cubic cm). For instance, where seed layer 210 includes monocrystalline Si, the monocrystalline Si may be p-type doped using a suitable acceptor (e.g., boron) or n-type doped using a suitable donor (e.g., phosphorous, arsenic), to provide some example cases. However, in some embodiments, seed layer 210 may be undoped/intrinsic or relatively minimally doped, such as including a dopant concentration of less than 1E16 atoms per cubic cm, for example. In some embodiments, seed layer 210 may include any suitable thickness (dimension in the Y-axis direction), such as a thickness in the range of 1 -50 nm (or in the sub-range of 1-5, 1-10, 1-20, 2- 5, 2-20, 2-50, 3-10, 3-20, 3-50, 5-10, 5-20, or 5-50 nm), or any other suitable thickness value or range that will allow the seed layer itself to be strained by epitaxial growth of diverse semiconductor material thereon, as will be apparent in light of this disclosure. In some embodiments, seed layer 210 may include a thickness of less than 50, 40, 30, 25, 20, 15, 10, 8, 5, 4, 3, or 2 nm, or less than any other suitable threshold that will allow the seed layer itself to be strained by epitaxial growth of diverse semiconductor material thereon, as will be apparent in light of this disclosure.

In some embodiments, the thickness of seed layer 210 may be selected to ensure that strain transfer (or compliant effect) occurs during the techniques described herein, such that when epitaxial semiconductor material is grown on a sufficiently thin seed layer 210, seed layer 210 will allow itself to be strained by that epitaxial semiconductor material during the growth. In some such embodiments where seed layer 210 is strained by the epitaxial formation of overlying monocrystalline semiconductor material thereon (e.g., where a lattice mismatch is involved), the seed layer may include stress in the range of 0.2-6 gigapascals (GPa) (e.g., 0.2-1, 0.2-2, 0.2-3, 0.2-4, 0.2-5, 0.5-1, 0.5-2, 0.5-3, 0.5-4, 0.5-5, 0.5-6, 1-2, 1-3, 1-4, 1-5, 1-6, 2-3, 2-4, 2-5, 2-6, 3-4, 3-5, 3-6, 4-5, 4-6, or 5-6 GPa), or any other suitable value or range as can be understood based on this disclosure. In some such embodiments where seed layer 210 is strained by the epitaxial formation of overlying monocrystalline semiconductor material thereon (e.g., where a lattice mismatch is involved), the seed layer may include stress of at least 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1.0, 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, or 6.0 GPa, or any other suitable threshold minimum amount as can be understood based on this disclosure. In some embodiments, it may be desired to form seed layer 210 in a relatively thin manner, such as with a thickness in the range of 1-5 nm, so that it is not significantly contributing to conduction or other parasitic effects, for example. In some embodiments, seed layer 210 may include a multilayer structure including two or more distinct layers. In some embodiments, seed layer 210 may include grading (e.g., increasing and/or decreasing) of one or more material concentrations throughout at least a portion of the seed layer 210. Note that seed layer 210 includes shading to assist with merely visually identifying the layer; however, the shading is not intended to limit the present disclosure in any manner.

Method 100 of Figure 1 continues with forming 104 sacrificial layer 212 on seed layer 210 to form the example resulting structure of Figure 2B, in accordance with some embodiments. In some embodiments, sacrificial layer 212 may be formed using any suitable techniques, such as one or more of chemical vapor deposition (CVD), metalorganic CVD (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), and/or any other suitable process as can be understood based on this disclosure. In some embodiments, after sacrificial layer 212 has been deposited/grown/formed, polish and/or planarization processing may occur (e.g., to obtain a desired surface smoothness), such as performing a chemical mechanical polish/planarization (CMP) processing, for example. In this example embodiment, sacrificial layer 212 is blanket grown on the entirety of the multilayer structure of Figure 2A as shown in Figure 2B; however, the present disclosure is not intended to be so limited. In some embodiments, sacrificial layer 212 may include any suitable thickness (dimension in the Y-axis direction), such as a thickness in the range of 4-750 nm (or in the sub-range of 10-500 nm), for example, or any other suitable value or range as will be apparent in light of this disclosure. In some embodiments, sacrificial layer 212 may include a multilayer structure including two or more distinct layers. In some embodiments, sacrificial layer 212 may include grading (e.g., increasing and/or decreasing) of one or more material concentrations throughout at least a portion of the sacrificial layer 212.

Sacrificial layer 212, in some embodiments, may include any suitable material, such as one or more oxides (e.g., silicon dioxide), nitrides (e.g.., silicon nitride), dielectrics or electrically insulating materials, semiconductor material (e.g., group IV, III-V, and/or II- VI semiconductor material), and/or any other suitable material(s) as will be apparent in light of this disclosure. As will be apparent in light of this disclosure, sacrificial layer 212 will be at least partially patterned into sacrificial fins, then isolation material (e.g., ILD material) will be formed around at least a portion of the fins, and then at least a portion of those sacrificial material fins will be removed (to form fin-shaped trenches) and replaced with replacement semiconductor material. Therefore, in some embodiments, the material of sacrificial layer 212 may be selected based at least in part on the sacrificial material being able to be selectively removed relative to the surrounding ILD material (e.g., removed at a relatively faster rate using a given etchant), as will be described in more detail below. In some embodiments, the material of sacrificial layer 212 may be selected based at least in part on the sacrificial material being able to be selectively removed relative to the material of seed layer 210 upon which it is formed (e.g., removed at a relatively faster rate using a given etchant), as will also be described in more detail below.

Method 100 of Figure 1 continues with patterning 106 sacrificial layer 212 and seed layer

210 into fins 211 to form the example resulting structure of Figure 2C, in accordance with some embodiments. In some embodiments, the sacrificial and seed layer fins 211 may be formed using any suitable techniques, such as including one or more masking, patterning, lithography, and/or etching (e.g., wet and/or dry etching) processes, as can be understood based on this disclosure. Note that the sacrificial and seed layer fins 211 (and the trenches 215 therebetween) are shown as having similar or the same sizes and shapes relative to one another in this example structure for ease of illustration; however, the present disclosure is not intended to be so limited. For example, in some embodiments, the sacrificial and seed layer fins 211 may be formed to have varying heights SFh and/or varying widths SFw that may correspond with (or be the same as) the final desired fin heights (Fh) and fin widths (Fw) described in more detail below. For instance, in some embodiments, SFw (dimension in the X-axis direction) may be in the range of 4-400 nm, for example, or any other suitable value or range as will be apparent in light of this disclosure. Further, in some embodiments, SFh (dimension in the Y-axis direction) may be in the range of 5-800 nm, for example, or any other suitable value or range, as will be apparent in light of this disclosure. Further note that although four sacrificial and seed layer fins 211 are shown in the example structure of Figure 2B for ease of illustration, any number of fins may be formed, such as one, two, three, five, ten, hundreds, thousands, millions, and so forth, as can be understood based on this disclosure. Also note that fins 211 are shown in Figure 2C as having a height (SFh) that is relatively greater than the thickness (dimension in the Y-axis direction) of substrate 200 and insulator layer 205, for ease of illustration. However, in some embodiments, the height of fins 211 (shown as SFh) may be relatively less than the thickness of each of those layers 200 and 205, for example.

Method 100 of Figure 1 continues with forming 106 interlay er dielectric (ILD) material 220 around fins 211 to form the example resulting structure of Figure 2D, in accordance with some embodiments. In some embodiments, the ILD material 220 may be deposited/grown using any suitable techniques as will be apparent in light of this disclosure, such as using any of the techniques described herein (e.g., CVD, PVD, ALD), for example. In some embodiments, an polishing and/or planarization processing may be performed after depositing the ILD material 220, such as CMP processing, for example. In some embodiments, ILD material 220 may include any suitable material, such as one or more oxides (e.g., silicon dioxide), nitrides (e.g., silicon nitride), dielectrics, and/or other electrically insulating materials, for example. In some embodiments, the ILD material 220 may be selected based on the material of sacrificial layer 212, for example, such that the two materials are relatively different to enable selectively etching the material of sacrificial layer 212 to thereby form fin-shaped trenches, as will be described in more detail below.

Method 100 of Figure 1 continues with masking off 110 a subset of fins 211 (which each include seed layer 210 and sacrificial layer 212) to allow processing of another subset of the fins 211, thereby forming the example resulting structure of Figure 2E, in accordance with some embodiments. In some embodiments, hardmask 230 may be formed using any suitable techniques, such as by forming hardmask 230 as shown in Figure 2E (e.g., via a deposition or growth process) or by forming a hardmask layer over the entirety of the structure shown in Figure 2D and patterning the hardmask (e.g., via etch processing) to leave just the portion shown over the left-most two fins 211 as illustrated in Figure 2E, for example. In some embodiments, hardmask 230 may include any suitable material, such as one or more oxide, nitride, carbide, and/or dielectric materials, for example, or any other suitable material(s) as will be apparent in light of this disclosure. Specific oxide, nitride, and carbide materials may include silicon oxide (also referred to as silicon dioxide), titanium oxide (also referred to as titanium dioxide), hafnium oxide, aluminum oxide, silicon nitride, titanium nitride, and silicon carbide, to provide some examples. In some embodiments, the material of hardmask 230 material may be selected based on other materials of the structure of Figure 2E (e.g., based on ILD material 220). As shown in Figure 2D, the left-most two fins 211 (a subset of the four fins) have been masked off to allow for processing of the right-most two fins 211 (the other subset of the four fins).

Method 100 of Figure 1 continues with removing 112 sacrificial layer 212 from the other subset of fins (the right-most two fins, in this example case, that are not masked off) to form fin- shaped trenches 225, as shown in the example resulting structure of Figure 2F, in accordance with some embodiments. In some embodiments, the removal process may be performed using any suitable techniques, such as using selective etch processing to remove the material of sacrificial layer 212 without removing the surrounding ILD material 220 or to remove the material of sacrificial layer 212 at a relatively faster rate than the removal of the surrounding ILD material (e.g., at least 1.5-100 times faster). In some such embodiments, ILD material 220 may only be minimally affected by the selective etch processing (or practically not affected at all), such that the majority or all of the ILD material 220 remains, such as is shown in Figure 2F. Note that in this example embodiment, the entirety of sacrificial layer 212 was removed to form fin-shaped trenches 225. Also note that the selective etch processing did not remove material (or may have minimally removed material) from seed layer 210 in this example embodiment, as the selective etch processing was also selective to the material of seed layer 210. This may have been achieved based on the etchant used (e.g., the given etchant selectively removes the material of sacrificial layer 212 without removing the material of seed layer 210 or it removes the material of sacrificial layer 212 at a relatively faster rate, such as at least 1.5-100 times faster) and/or based on the duration of the etch processing (e.g., where the duration is controlled to ensure that the material of seed layer 210 is not removed or minimally removed during the etch processing).

As can be understood based on this disclosure, hardmask 230 prevents sacrificial layer 212 from being removed from the left-most two fins 211 during the removal of sacrificial layer 212 from the right-most two fins 211. As can also be understood, in this example embodiment, the relatively thin seed layer 210 (e.g., with a thickness less than 50, 40, 30, 25, 20, 15, 10, 8, 5, 3, or 2 nm) could not be formed in fin-shaped trenches 225 and have a monocrystalline structure at this stage if the seed layer 210 was not previously formed, because it would include forming the semiconductor material of seed layer 210 on the insulator material of layer 205, thereby resulting in lower crystalline quality semiconductor material (e.g., polycrystalline or amorphous semiconductor material) for seed layer 210. In some embodiments, the narrow or fin- shaped trenches 225 may include the same or similar dimensions as the sacrificial layer 212 portion of fins 211 (e.g., having the same or similar widths as SFw and having the same or similar heights as the thickness of sacrificial layer 212, as described herein). In some embodiments, an aspect ratio trapping (ART) scheme can be used where the fin-shaped trenches 225 in which the replacement material is to be deposited may have a particular height/depth to width ratio (e.g., greater than 1, such as greater than 1.5, 2, 3, 5, 10, or 15) such that the trenches allow for defects in the replacement material to terminate on a side surface as the material grows vertically, such as non-cry stalline/dielectric sidewalls, where the sidewalls are sufficiently high relative to the size of the growth area so as to trap most, if not all, of the defects, thereby achieving replacement fins including relaxed material. However, in some embodiments, the material of the replacement fins formed in fin-shaped trenches 225 may already be formed in a defect free (or substantially defect free) manner and also be formed in a relaxed manner, due to the strain transfer (or compliant effect) that occurs based on the use of relatively thin seed layer 210.

Method 100 of Figure 1 continues with depositing (or otherwise forming) 114 replacement material in the fin-shaped trenches 225 to form first replacement fins 241 as shown in the example resulting structure of Figure 2G, in accordance with some embodiments. In some embodiments, the epitaxial semiconductor material of first replacement fins 241 may be grown/deposited (or otherwise formed) using any suitable techniques, such as using one or more of the deposition processes described herein (e.g., CVD, MOCVD, PVD, ALD, MBE). Note that the replacement material is referred to as such because it is replacing the material of sacrificial layer 212, as can be understood based on this disclosure. Also note that in this example embodiment, first replacement material 241 grew out of fin-shaped trenches 225 in an overfill fashion as shown in Figure 2G; however, in some cases, such overflow of the material need not occur. Further, in this example embodiment, a planarization (or re-planarization) process was then performed after growing (or otherwise forming) the epitaxial semiconductor material of first replacement fins 241, such as via a CMP process, to form the resulting example structure of Figure 2H, in accordance with some embodiments.

Method 100 of Figure 1 continues with repeating 116 boxes 1 10-114 to form two different sets of replacement fins 241 and 242, as shown in the example resulting structure of Figure 21, in accordance with some embodiments. For instance, continuing from the structure of Figure 2H, the processing to form Figure 21 included, in this example embodiment, masking off the rightmost two fins 241 (e.g., using hardmask 230 as described above), removing sacrificial layer 212 from the exposed subset of fins to form fin-shaped trenches, depositing a second replacement material in the fin-shaped trenches formed to form second replacement fins 242, and optionally performing planarization/polish (or re-planarization) processing, as can be understood based on this disclosure. Note that boxes 110-114 may be repeated as many times as desired (and thus box 116 may be repeated as many times as desired) to form any desired number of sets of different replacement material fins, such as 2, 3, 4, 5, 6, 7, 8, 9, 10, or more, for example. Also note that each subset of replacement fins 241 and 242 in the example embodiment illustrates in Figure 21 includes two fins for ease of illustration; however, each subset of replacement material fins could include any number of fins, such as 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 25, 50, 100, hundreds, thousands, millions, or billions, and so forth, as can be understood based on this disclosure. Further note that not all of fins 211 including sacrificial layer 212 need to be replaced, in some embodiments, such that one or more fins 211 including sacrificial layer 212 may remain in the final integrated circuit, where such fins 211 may be artifacts of the techniques described herein and/or be purposefully formed and kept to, e.g., assist with electrically isolating transistors or transistor-based devices, for instance. To merely assist with merely visually identifying the two different sets of replacement fins 241 and 242, each set includes distinct diagonal shading, with the first replacement fins 241 including top right to bottom left diagonal shading and the second replacement fins 242 including top left to bottom right diagonal shading; however, the Crosshatch shading is not intended to limit the present disclosure in any manner.

First replacement fins 241 and second replacement fins 242, in some embodiments, may include group IV semiconductor material (such as Si, Ge, SiGe, or SiC), group III-V semiconductor material (such as GaAs, InGaAs, or InP), other semiconductor material (e.g., group II- VI semiconductor material), and/or any other suitable material(s) as will be apparent in light of this disclosure. In some embodiments, one or more replacement fins (241 and/or 242) may include semiconductor material that is doped with any suitable n-type and/or p-type dopant (such as in a concentration in the range of 1E16 to 1E22 atoms per cubic cm). For instance, where a replacement fin includes SiGe or Ge, the SiGe or Ge may be p-type doped using a suitable acceptor (e.g., boron) or n-type doped using a suitable donor (e.g., phosphorous, arsenic), to provide some example cases. For instance, in the case of forming a MOSFET device from one of the replacement fins, semiconductor material included in that replacement fin may be formed to be n-type or p-type doped (as the semiconductor material of that replacement fin will be used in the channel region of that MOSFET device and it may be desired for it to be doped). However, in some embodiments, one or more replacement fins (241 and/or 242) may include semiconductor material that is undoped/intrinsic or relatively minimally doped, such as including a dopant concentration of less than 1E16 atoms per cubic cm, for example. For instance, in the case of forming a TFET device from one of the replacement fins, semiconductor material included in that replacement fin may be undoped/intrinsic (as the semiconductor material of that replacement fin will be used in the channel region of that TFET device and it may be desired for it to be intrinsic semiconductor material).

In some embodiments, one or more of replacement fins 241 and 242 may include a multilayer structure including two or more distinct layers. In some such embodiments, the replacement fins may be formed using a layer-by-layer epitaxial growth approach (e.g., using an MBE process), such that the replacement fins may or may not appear to have distinct interfaces within the feature, depending on the particular configuration and observation level. In embodiments where a nanowire (or nanoribbon or GAA) transistor is to be formed from a replacement fin, it may include at least one channel layer and at least one sacrificial layer to be removed to release the channel layer to enable forming that nanowire transistor, as will be described in more detail herein (e.g., with respect to Figure 2M and nanowire channel regions 243' and 244'). For instance, in an example embodiment, a replacement fin may include alternating layers of group IV and group III-V semiconductor material, where either the group IV or group III-V material is sacrificial, to enable the formation of one or more nanowires (e.g., where the sacrificial material is subsequently removed, such as during replacement gate processing). In some embodiments, one or more of the replacement fins 241 and 242 may include grading (e.g., increasing and/or decreasing) of one or more material and/or dopant concentrations throughout at least a portion of the structure(s). For instance, the grading may occur as the material of the replacement fin is epitaxially grown (e.g., in the Y-axis direction). Further, in some embodiments, the structures formed including the co-integrated material (e.g., replacement fins 241 and 242) may be used to form transistor devices as will be described in more detail herein; however, the present disclosure is not intended to be so limited. For example, in some embodiments, only some or none of the structures formed including the co- integrated material may be subsequently formed into transistors or transistor-based devices. For instance, in some such embodiments, one or more of the replacement material structures formed (such as one or more of replacement fins 241 and/or 242) may be formed into memory devices, diodes, resistors, sensors, and/or any other suitable semiconductor devices.

As can be understood based on this disclosure, in at least some embodiments, seed layer 210 may be sufficiently thin with respect to the dimension in the Y-axis direction (e.g., having a thickness less than 50, 40, 30, 25, 20, 15, or 10 nm), such that when semiconductor material (e.g., material included in replacement fins 241 and 242) is epitaxially grown on seed layer 210, strain transfer (or compliant effect) occurs, resulting in the seed layer 210 being strained to the overlying epitaxial material grown thereon as opposed to the overlying epitaxial material being strained to the seed layer 210 (which would typically be the case if the seed layer was not sufficiently thin). In some embodiments, the straining of the seed layer 210 may primarily occur where the semiconductor material included in seed layer 210 and the overlying epitaxial semiconductor material formed on seed layer 210 are lattice mismatched (however such situations need not be so limited). In some embodiments, two semiconductor materials may be considered lattice mismatched if the absolute value of the lattice delta (or lattice misfit) between the materials is greater than 2-4% (e.g., greater than 2, 2.5, 3, 3.5, or 4%, or greater than the subrange of 2-3% or 3-4%), or some other suitable threshold value or range as will be apparent in light of this disclosure. The lattice delta or misfit absolute value (as a percentage) can be calculated by |(al-a2)/a2|* 100, where 'al ' is the lattice constant of a first material (e.g., the seed layer material) and 'a2' is the lattice constant of a second material epitaxially grown on the first material (e.g., the epitaxial semiconductor material formed on the seed layer, such as the material included in replacement fins 241 or 242).

For example, with the lattice constants at 300 Kelvin (K) of Si and Ino.53Gao.47As being 5.431 angstroms (A) and 5.8678 A, respectively, the lattice delta or misfit absolute value (as a percentage) between the two materials (where Ino.53Gao.47As is grown on Si) can be calculated as |(5.431-5.8678)/5.8678|* 100, which equals approximately 7.5%. Further, Ge, which has a lattice constant of 5.658 A at 300 K, is lattice mismatched with Si, as the lattice delta or misfit absolute value (as a percentage) between the two materials (where Ge is grown on Si) is approximately 4%. Therefore, the techniques described herein enable the monolithic co -integration of defect free (or substantially defect free) and compositionally different monocrystalline semiconductor materials, even where one or more of the different semiconductor materials are lattice mismatched with the material of seed layer 210 (which acts as a substrate upon which the epitaxial semiconductor material is grown), due to the strain transfer (or compliant effect) described herein. For instance, the techniques described herein enable the monolithic co- integration of defect free (or substantially defect free) Ge or Ge-rich SiGe (e.g., with at least 50% Ge concentration) to be used in p-MOS devices with defect free (or substantially defect free) III- V material (e.g., InGaAs) to be used in n-MOS devices, where all of the material is formed on a sufficiently thin (e.g., less than 20 nm thick) Si seed layer, to provide an example embodiment. Further, in such an example embodiment, the Ge or Ge-rich SiGe p-MOS and III-V n-MOS may be included in a CMOS circuit, particularly where the techniques described herein can enable the formation of the p-MOS and n-MOS devices in close proximity to be used in such a CMOS circuit, for example. Recall that defect free as used herein with respect to semiconductor material or a feature/1 ay er/structure including semiconductor material means (at the least) having no misfit dislocations. Also recall that substantially defect free as used herein with respect to semiconductor material or a feature/lay er/structure including semiconductor material means (at the least) having no more than 1 or 2 misfit dislocations (in other words, having a maximum of 1 or 2 misfit dislocations) per the material or the feature/layer/structure.

In addition, in some embodiments, the strain transfer (or compliant effect) caused by the sufficiently thin seed layer 210 also results in the overlying epitaxial semiconductor material (e.g., the material included in replacement fins 241 and 242) being relaxed (or substantially relaxed) throughout the entirety of replacement fins 241 and 242, such that it includes no (or minimal) strain throughout the entirety of the fin-shaped structure. Note that even where the material of seed layer 210 and the overlying epitaxial semiconductor material (e.g., the material included in replacement fins 241 and 242) are lattice matched (and thus not lattice mismatched), the overlying epitaxial semiconductor material would still be relaxed (or substantially relaxed) throughout the entirety of the fin-shaped structure. In some embodiments, that the semiconductor material included in replacement fins 241 and 242 is relaxed (or substantially relaxed) need not affect the performance of transistors formed therefrom. For instance, in some such embodiments, strain has no effect on group III-V semiconductor material electron mobility, such that III-V material channel used in an n-MOS transistor would not benefit from any included strain. However, the III-V material channel benefits from the relatively higher quality material that can be achieved using the techniques described herein, as the techniques enable forming defect free (or substantially defect free) semiconductor material (including III-V material) on any semiconductor material (included in the seed layer), such that monocrystalline (or single crystal) semiconductor material can be formed on any other semiconductor material regardless of the lattice fit between the two materials. Further, the techniques enable the monolithic co-integration of any desired combination of semiconductor materials, such as co- integrating various IV material (e.g., Si, SiGe, Ge, etc.) with the same or other IV material (e.g., co-integrating SiGe including a first Ge concentration with SiGe including a second Ge concentration different than the first), co -integrating various IV material with various III-V material (e.g., InGaAs, GaAs, InP, etc.), co -integrating various IV material with various II-VI material (e.g., ZnO, ZnS, CdSe, etc.), co -integrating various III-V material with the same or other III-V material (e.g., co-integrating InGaAs including a first In concentration with InGaAs including a second In concentration different than the first), co -integrating various III-V material with various II-VI material, co-integrating various II- V material with the same or other II-V material (e.g., co-integrating ZnO with CdSe), and/or any other suitable semiconductor material combination as can be understood based on this disclosure. In some embodiments, first replacement fins 241 include a first monocrystalline semiconductor material, second replacement fins 242 include a second monocrystalline semiconductor material, and seed layer 210 includes a third monocrystalline semiconductor material, where the first, second, and third monocrystalline semiconductor materials may: all be the same (e.g., they may all be SiGe, with or without varying concentrations of Ge); all be different; or only two of them may be the same, with or without varying concentrations (e.g., the third may be Si and first and second may both be SiGe with or without varying concentrations of Ge, or the first and third may be both be Si while the second is a III-V material, or the second and third may both be InGaAs with or without varying concentrations of In while the first is Ge, and so forth). In some embodiments where the aforementioned first, second, and third monocrystalline semiconductor materials are involved, the second monocrystalline semiconductor material may be compositionally different than the first monocrystalline semiconductor material, such that they either include different semiconductor material (e.g., one includes gallium and arsenide and the other includes germanium) or they may include the same semiconductor material but at different ratios (e.g., both include SiGe, but with non-overlapping values for the Ge concentration, such as one including SiGe with a Ge concentration of 0-30% and the other including SiGe with a Ge concentration of 31 -100%). In some embodiments where the aforementioned first, second, and third monocrystalline semiconductor materials are involved, the third monocrystalline semiconductor material may be compositionally different than the first monocrystalline semiconductor material and/or the second monocrystalline semiconductor material. Thus, in some embodiments where the aforementioned first, second, and third monocrystalline semiconductor materials are involved, all three of the monocrystalline semiconductor materials may include compositionally different material relative to one another. For instance, in such an embodiment, the third monocrystalline semiconductor material may include Si (which may be doped or undoped), while the first monocrystalline semiconductor material may include InGaAs (which may be doped or undoped) and the second monocrystalline semiconductor material may include Ge (which may be doped or undoped). Note that when discussing monocrystalline semiconductor materials being compositionally different as described herein, any included dopants do not affect whether or not two monocrystalline semiconductor materials are compositionally different, such that p-type monocrystalline Si doped with boron would not be compositionally different than n-type monocrystalline Si doped with phosphorous, to provide an illustrative example. Thus, if there is not at least a 1 or 2% difference in composition between two monocrystalline semiconductor materials, they may not be considered compositionally different in accordance with some embodiments. In some embodiments, whether two monocrystalline semiconductor materials are compositionally different may be based on the absolute value of the difference between the lattice constants of those two materials being at least 0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19, or 0.2 A at 300K, or some other suitable threshold value as can be understood based on this disclosure. Numerous material variations and configurations will be apparent in light of this disclosure, and the materials of the different features described herein may be expressed based on the actual material and/or based on material relative to another feature, as can be understood based on this disclosure.

Method 100 of Figure 1 continues with recessing or removing 118 ILD material 220 to expose the two sets of replacement fins 241 and 242, in accordance with some embodiments. As shown in the example resulting structure of Figure 2J, the processing included removing ILD material 220 to fully expose fins 213 (which include seed layer 210 and replacement fins 241 and 242) and trenches 245 therebetween, in this example embodiment. However, in other embodiments, ILD material 220 may merely be recessed such that it may be used as shallow trench isolation (STI) material to help electrically isolate the fins 213, such as for STI material 222 shown in the example structure of Figure 2K, for instance. Therefore, in some embodiments, seed layer 210 may be included in the active channel portion of transistors formed from fins 213, while in other embodiments, seed layer 210 may not be included in the active channel portion of transistors formed from fins 213, or some combination may occur (e.g., seed layer 210 is included in the active channel portion of some transistors and not included in others). For instance, in the example structure of Figure 2K, seed layer 210 is not included in the portion of fin 213 to be used as the transistor active channel portion (and having a height AFh), whereas the example structure of Figure 2K' illustrates that STI material 222 is not present, such that seed layer 210 can be included in the portion of fin 213 to be used as the transistor active channel portion. In some embodiments, removing or recessing ILD material 220 may be performed using any suitable techniques, such as any suitable etch (e.g., wet and/or dry etch) processing, for example. The ILD material 220 may be recessed and not fully removed by controlling the processing, such as the duration and/or the etchants used, for example.

In the structures of Figures 2J-K, STI material 222 need not be included, as insulator layer 205 may provide suitable electrical isolation between adjacent fins 213, for example. However, in embodiments where seed layer 210 is not formed on an insulator layer (e.g., where insulator layer 205 is not present), STI material 222 may be included to provide electrical isolation between fins 213. Regardless, if STI material 222 is present in the end structure, it may be formed by recessing ILD material 220, removing ILD material 220 and replacing it with new STI material, or some combination thereof (e.g., recessing ILD material 220 without completely removing it and also forming additional STI material on top of the ILD material). In some embodiments, STI material 222 may include any suitable material, such as one or more oxides, nitrides, dielectrics, and/or other suitable electrically insulating material(s), for example. In the example structure of Figure 2K, the STI material is at a level near the bottom of replacement fins 241 and 242. However, in other embodiments, the STI material may be at a higher or lower point (where higher and lower are relative to the Y-axis direction). Further, as previously described, in some embodiments, STI material 222 need not be present. For example Figure 2K' illustrates a blown-out portion of Figure 2K to illustrate a variation including no shallow trench isolation (STI) material, in accordance with some embodiments. In some such embodiments, the electrical isolation between fins 213 may be provided by insulator layer 205, for example, as the insulator layer 205 would act as the sub-fin (and sub-channel) portion of the structure. Note that in some embodiments, ILD material 220 need not be recessed or removed, such as when forming planar transistors from replacement fins 241 and 242, for example.

Fins 213, which include seed layer 210 and replacement fin portion (either 241 or 242), are shown as having widths Fw and heights Fh in the example structure of Figure 2J. As can be understood based on this disclosure, fin widths Fw may be similar to or the same as starting fin widths SFw previously described, and fin heights Fh may be similar to or the same as starting fin heights SFh previously described. Generally, the fin widths Fw (dimension in the X-axis direction) may be in the range of 4-400 nm (e.g., in the subrange of 4-10, 4-20, 4-50, 4-100, 4- 200, 10-20, 10-50, 10-100, 10-200, 10-400, 50-100, 50-200, 50-400, or 100-400 nm), for example, or any other suitable value or range, as will be apparent in light of this disclosure. Further, in some embodiments, the fin heights Fh (dimension in the Y-axis direction) may be in the range of 5-800 nm (e.g., in the subrange of 5-10, 5-20, 5-50, 5-100, 5-200, 5-400, 10-20, 10- 50, 10-100, 10-200, 10-400, 10-800, 50-100, 50-200, 50-400, 50-800, 100-400, 100-800, or 400- 800 nm), for example, or any other suitable value or range, as will be apparent in light of this disclosure. In some embodiments, the height to width ratio of the fins (Fh:Fw) may be greater than 1, such as greater than 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9, 10, 15, or 20, or any other suitable threshold ratio, as will be apparent in light of this disclosure.

Note that fin-shaped structures 213 (and the trenches 245 therebetween) are shown as having similar sizes and shapes relative to one another in this example structure for ease of illustration; however, the present disclosure is not intended to be so limited. For example, in some embodiments, the fin-shaped structures 213 may be formed to have varying heights Fh and/or varying widths Fw, depending on the desired configuration. For instance, in some such embodiments, the fins within a replacement material set may vary in size and/or shape (e.g., the two right-most fins may vary relative to each other) and/or the fins of different replacement material sets may vary in size and/or shape (e.g., at least one fin from the set of fins including replacement fins 241 may differ relative to at least one fin from the set of fins including replacement fins 242). Note that although the fin-shaped structures 213 are shown as perfect rectangular fins, the present disclose is not intended to be so limited. For example, in some embodiments, the structures may more-so resemble a pyramid that tapers inward as you move toward the top of the structure (with either a pointed or flat top) or some other fin-like shape that generally includes a larger height Fh than width Fw. Further note that although a total of four fins 213 are shown in the example structure of Figure 2 J for ease of illustration (two each in the set including replacement fins 241 and the set including replacement fins 242), any number of fins may be formed, such as two, three, five, ten, hundreds, thousands, millions, billions, and so forth, as can be understood based on this disclosure.

Method 100 of Figure 1 continues with completing 120 transistor processing to form one or more transistors, where the additional processing includes gate stack and source/drain (S/D) processing, in accordance with some embodiments. Continuing from the example structure of Figure 2J, the processing is described herein in the context of a gate last transistor fabrication flow, where the processing includes forming a dummy gate stack, performing the S/D processing, and then forming the final gate stack after the S/D regions have been processed. In other embodiments, the techniques may be performed using a gate first process flow. In such example embodiments, a dummy gate stack need not be formed, as the final gate stack can be formed in the first instance. However, the description of the continued processing will be described using a gate last process flow, to allow for such a gate last flow (which may include additional processing) to be adequately described. Regardless, the end structure of either a gate first or a gate last process flow will include the final gate stack, as will be apparent in light of this disclosure.

As shown in the example structure of Figure 2K, the processing continues with forming a dummy gate stack, including dummy gate dielectric 252 and dummy gate (or dummy gate electrode) 254, in accordance with some embodiments. As described above, the formation of the dummy gate stack is optional, because it need not be performed in all embodiments (such as those employing a gate first process flow). In this example embodiment, dummy gate dielectric 252 (e.g., dummy oxide material) and dummy gate (or dummy gate electrode) 254 (e.g., dummy poly-silicon material) may be used for a replacement gate process. Note that side-wall spacers 250, referred to generally as gate spacers (or simply, spacers), on either side of the dummy gate stack were also formed, and such spacers 250 can help determine the channel length and/or help with replacement gate processing, for example. As can be understood based on this disclosure, the dummy gate stack (and spacers 250) help define the channel region and source/drain (S/D) regions of each fin, where the channel region is below the dummy gate stack (as it will be located below the final gate stack), and the S/D regions are on either side of the channel region (e.g., not below the dummy gate stack). Note that because the IC structures are being described in the context of forming finned transistors, the final gate stack will also be adjacent to either side of the fin, as the gate stack will reside along three walls of the finned channel regions, in some such embodiments. Formation of the dummy gate stack may include depositing the dummy gate dielectric material 252 and dummy gate (or dummy gate electrode) material 254, patterning the dummy gate stack, depositing gate spacer material 250, and performing a spacer etch to form the structure shown in Figure 2K, for example. Spacers 250 may include any suitable material, such as any suitable electrical insulator, dielectric, oxide (e.g., silicon oxide), and/or nitride (e.g., silicon nitride) material, as will be apparent in light of this disclosure. Note that in some embodiments, a hardmask (not shown) may be formed over the dummy gate stack (which may or may not also be formed over spacers 250) to protect the dummy gate stack during subsequent processing, for example.

Continuing from the example structure of Figure 2K, completing 120 the transistor processing includes performing source/drain (S/D) processing to form the example resulting structure of Figure 2L, in accordance with some embodiments. The S/D regions 260, in some embodiments, may be formed using any suitable techniques, such as masking regions outside of the S/D regions to be processed, etching at least a portion of the exposed replacement fins 241 and 242 from the structure of Figure 2K, and forming/depositing/growing the S/D regions 260 (e.g., using any suitable techniques, such as CVD, MOCVD, ALD, PVD, MBE), for example. However, in some embodiments, the replacement fins 241 and 242 need not be completely removed, but they may remain (at least in part) in the final S/D regions and be doped and/or cladded and/or have any other suitable processing performed to convert them into suitable S/D regions, for example. In this example embodiment, as the material of the S/D regions 260 is replacement material, there is a distinct interface between the underlying sub-fin portions (including the remainder of replacement fins 241 and 242) and S/D regions 260, as shown in Figure 2L. In some embodiments, one or more of the S/D regions 260 may have a multilayer structure including two or more distinct layers, for example. In some embodiments, one or more of the S/D regions 260 may include grading (e.g., increasing and/or decreasing) the content/concentration of one or more materials in some or all of the region(s). In some embodiments, the S/D regions 260 may be formed one polarity at a time, such as performing processing for one of n-type and p-type S/D regions, and then performing processing for the other of the n-type and p-type S/D regions. In some embodiments, the S/D regions may include any suitable material, such as semiconductor material (e.g., group IV, III-V, and/or II- VI semiconductor material) and/or any other suitable material, as will be apparent in light of this disclosure. In some embodiments, the S/D regions corresponding to a given channel region may include the same group of semiconductor material as what is included in the given channel region, such that if the given channel region includes group IV semiconductor material, the corresponding S/D regions may also include group IV semiconductor material (whether the same IV material or different); however, the present disclosure is not intended to be so limited. In some embodiments, the S/D regions may include any suitable doping scheme, such as including suitable n-type and/or p-type dopant (e.g., in a concentration in the range of 1E16 to 1E22 atoms per cubic cm). However, in some embodiments, at least one S/D region 260 may be undoped/intrinsic or relatively minimally doped, such as including a dopant concentration of less than 1E16 atoms per cubic cm, for example. To provide some examples, in embodiments, where corresponding S/D regions on either side of a given channel region are to be used for a MOSFET device, the S/D regions may include the same type of dopants (e.g., where both are p-type doped or both are n-type doped). Specifically, for an n-MOS device, the included S/D regions include semiconductor material that is n-type doped, and for a p-MOS device, the included S/D regions include semiconductor material that is p-type doped, in some embodiments. Whereas for a TFET device, the S/D regions for a given channel region may be oppositely doped, such that one is p-type doped and the other is n-type doped, in some embodiments. Note that for ease of illustration and description, all S/D regions are shown as being the same and are identified collectively by numeral 260. However, in some embodiments, the S/D regions 260 of the different finned structures may include differing materials, dopant schemes, shapes, sizes, corresponding channel regions (e.g., 1, 2, 3, or more), and/or any other suitable difference as can be understood based on this disclosure. Numerous transistor S/D configurations and variations will be apparent in light of this disclosure.

Continuing from the example structure of Figure 2L, completing 120 the transistor processing includes performing gate stack processing to form the example resulting structure of Figure 2M, in accordance with some embodiments. As shown in Figure 2M, the processing in this example embodiment included depositing interlay er dielectric (ILD) layer 270 on the structure of Figure 2L, followed by optional planarization and/or polishing to reveal the dummy gate stack. Note that ILD layer 270 is shown as transparent in the example structure of Figure 2M to allow for the underlying features to be seen (and the ILD layer 270 may actually be transparent or translucent at such a small scale); however, the present disclosure is not intended to be so limited. Also note that ILD layer 270 may include a multilayer structure, even though it is illustrated as a single layer. Further note that in some cases, ILD layer 270 and STI material 222 may not include a distinct interface as shown in Figure 2L, particularly where, e.g., the ILD layer 270 and STI material 222 include the same dielectric material. In some embodiments, the ILD layer 270 may include any suitable material, such as one or more oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), dielectrics, and/or electrically insulating material, for example. The gate stack processing, in this example embodiment, continued with removing the dummy gate stack (including dummy gate 254 and dummy gate dielectric 252) to allow for the final gate stack to be formed. Recall that in some embodiments, the formation of the final gate stack, which includes gate dielectric 282 and gate electrode 284, may be performed using a gate first flow (e.g., an up-front hi-k gate process). In such embodiments, the final gate processing may have been performed prior to the S/D processing, for example. However, in this example embodiment, the gate stack is formed using a gate last flow (also called a replacement gate or replacement metal gate (RMG) process). In such gate last processing, the process may include dummy gate oxide deposition, dummy gate electrode (e.g., poly-Si) deposition, and, optionally, patterning hardmask deposition, as previously described. Regardless of whether gate first or gate last processing is employed, the final gate stack can include gate dielectric 282 and gate electrode 284 as shown in Figure 2M, in accordance with some embodiments.

Note that when the dummy gate is removed, the channel regions of replacement material fins 241 and 242 (that were covered by the dummy gate) are exposed to allow for any desired processing of those channel regions of the fins. Such processing of the channel regions may include various different techniques, such as removing and replacing the channel region with replacement material, doping the channel region of the fin as desired, forming the fin into one or more nanowires (or nanoribbons) for a gate-all-around (GAA) transistor configuration, cleaning/polishing the channel region, and/or any other suitable processing as will be apparent in light of this disclosure. For instance, finned channel regions 243 and 244 are illustrated (which are the channel regions of the right-most finned structure and the second-from-the-left finned structure, respectively), which may be from the original fin structures (e.g., replacement fin structure 241 and 242) formed in Figure 2 J, for example. However, in some embodiments, those finned channel regions may be modified from the original fins, such as doping the channel regions with a desired suitable n-type or p-type dopant, for example. To provide another example, nanowire channel regions 243' and 244' (which are the channel regions of the second- from-the-right structure and the left-most structure) may have been formed after the dummy gate was removed and the channel regions of the fins were exposed, by converting a multilayer finned structure into the two nanowires (or nanoribbons) shown in each channel region 243' and 244', for example. The formation of the nanowire channel regions may be formed using any suitable techniques, such as selective etch processing to remove sacrificial material and release the final nanowires (or nanoribbons) to be used in a transistor channel, for instance. Although nanowire channel regions 243' and 244' each include two nanowires (or nanoribbons), a nanowire (or nanoribbon or GAA) transistor formed using the techniques disclosed herein may include any number of nanowires (or nanoribbons) such as 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, or more, depending on the desired configuration. In some embodiments, a nanowire or nanoribbon may be considered fin-shaped where the gate stack wraps around each fin-shaped nanowire or nanoribbon in a GAA transistor configuration.

As can be understood based on this disclosure, the channel region may be at least below the gate stack, in some embodiments. For instance, in the case of a planar transistor configuration, the channel region may just be below the gate stack. However, in the case of a finned transistor configuration, the channel region may be below and between the gate stack, as the gate stack may be formed on three sides of the finned structure (e.g., in a tri-gate manner), as is known in the art. Further, in the case of a nanowire (or nanoribbon or GAA) transistor configuration, the gate stack may substantially (or completely) surround each nanowire/nanoribbon in the channel region. Regardless, in some embodiments, the gate of a transistor may proximate to the channel region of that transistor. In some embodiments, the channel region may include semiconductor material (e.g., group IV, III-V, and/or II-VI semiconductor material), for example, such as the material described herein with reference to replacement fins 241 and 242. In some embodiments, the channel region of a given transistor may be doped (e.g., with any suitable n-type and/or p-type dopants) or intrinsic/undoped, depending on the particular configuration. As previously described, the techniques enable the formation of defect free (or substantially defect free) and different material in the channel regions of transistors monolithically co-integrated on/above a common substrate. Thus, a first channel region material (e.g., Ge or Ge-rich SiGe) may be used to benefit p-MOS devices (e.g., to increase charge carrier/hole mobility), while a second channel region material may be used to benefit n-MOS devices (e.g., to increase charge carrier/electron mobility). Note that S/D regions 260 are adjacent to either side of a given channel region, as can be seen in Figure 2M. In other words, each channel region is between corresponding S/D regions 260. Also note that the configuration/geometry of a transistor formed using the techniques described herein may primarily be described based on the shape/configuration of the respective channel region of that transistor, for example. For instance, a nanowire (or nanoribbon or GAA) transistor may be referred to as such because it includes one or more nanowires (or nanoribbons) in the channel region of that transistor, but the S/D regions need not include such a nanowire (or nanoribbon) shape.

Continuing with the example structure of Figure 2M, after the dummy gate has been removed and any desired channel region processing has been performed, the final gate stack can be formed, in accordance with some embodiments. In this example embodiment, the final gate stack includes gate dielectric 282 and gate electrode 284, as shown in Figure 2M. The gate dielectric 282 may include, for example, any suitable oxide (such as silicon dioxide), high-k dielectric material, and/or any other suitable material as will be apparent in light of this disclosure. Examples of high-k dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. In some embodiments, an annealing process may be carried out on the gate dielectric 282 to improve its quality when high- k dielectric material is used. The gate electrode 284 may include a wide range of materials, such as polysilicon or various suitable metals or metal alloys, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), titanium nitride (TiN), or tantalum nitride (TaN), for example. In some embodiments, gate dielectric 282 and/or gate electrode 284 may include a multilayer structure of two or more material layers, for example. In some embodiments, gate dielectric 282 and/or gate electrode 284 may include grading (e.g., increasing and/or decreasing) the content/concentration of one or more materials in at least a portion of the feature(s). One or more additional layers may also be present in the final gate stack, in some embodiments, such as one or more work function layers or other suitable layers, for example. Note that although gate dielectric 282 is only shown below gate electrode 284 in the example embodiment of Figure 2M, in other embodiments, the gate dielectric 282 may also be present on one or both sides of gate electrode 284, such that the gate dielectric 282 is between gate electrode 284 and one or both spacers 250, for example. Numerous different gate stack configurations will be apparent in light of this disclosure.

Continuing from the example structure of Figure 2M, completing 120 the transistor processing can include performing S/D contact processing to form the example resulting structure of Figure 2N, in accordance with some embodiments. As shown in Figure 2N, S/D contacts 290 were formed to make contact to each of the S/D regions 260, in this example embodiment. In some embodiments, S/D contacts 290 may be formed using any suitable techniques, such as forming contact trenches in ILD layer 270 over the respective S/D regions 260 and depositing metal or metal alloy (or other suitable electrically conductive material) in the trenches. In some embodiments, S/D contact 290 formation may include silicidation, germanidation, other IV-idation, III-V-idation, II-VI-idation, and/or annealing processes, for example. In some embodiments, S/D contacts 290 may include aluminum or tungsten, although any suitable conductive metal or alloy can be used, such as silver, nickel -platinum, or nickel- aluminum, for example. In some embodiments, one or more of the S/D contacts 290 may include a resistance reducing metal and a contact plug metal, or just a contact plug, for instance. Example contact resistance reducing metals include, for instance, nickel, aluminum, titanium, gold, gold-germanium, nickel-platinum, nickel aluminum, and/or other such resistance reducing metals or alloys. Example contact plug metals include, for instance, aluminum, copper, nickel, platinum, titanium, or tungsten, or alloys thereof, although any suitably conductive contact metal or alloy may be used. In some embodiments, additional layers may be present in the S/D contact 290 regions, such as adhesion layers (e.g., titanium nitride) and/or liner or barrier layers (e.g., tantalum nitride), if so desired. In some embodiments, a contact resistance reducing layer may be present between a given S/D region 260 and its corresponding S/D contact 290, such as a relatively highly doped (e.g., with dopant concentrations greater than 1E18, 1E19, 1E20, 1E21, or 1E22 atoms per cubic cm) intervening semiconductor material layer, for example. In some such embodiments, the contact resistance reducing layer may include semiconductor material and/or impurity dopants based on the included material and/or dopant concentration of the corresponding S/D region, for example.

Figures 3 A-B illustrate example cross-sectional views taken along the planes A- A and B-B in Figure 2N, respectively, in accordance with some embodiments. The cross-sectional views of Figures 3 A-B are provided to assist in illustrating different features of the structure of Figure 2N, for example. Therefore, the previous relevant description with respect to the each similarly numbered feature is equally applicable to Figures 3A-B. However, note that the dimensions of the features shown in Figures 3 A-B may differ in some ways (relative to the features in the structure of Figure 2N), for ease of illustration. Also note that some variations occur between the structures, such as the shape of spacers 250 and of channel regions 243 and 244, for example. In some embodiments, the length of gate electrode 284 (e.g., the dimension between spacers 250 in the Z-axis direction), which is indicated as Lg, may be any suitable length as can be understood based on this disclosure. For instance, in some embodiments, the gate length may be the same as or similar to the channel length (e.g., the gate length may be approximately longer than the channel length, such as 1-20% longer, due to potential diffusion of dopant from the S/D regions into the channel region), which may also be any suitable length as can also be understood based on this disclosure. For instance, in some embodiments, the gate length may be in the range of 3 - 100 nm (e.g., 3-10, 3-20, 3-30, 3-50, 5-10, 5-20, 5-30, 5-50, 5-100, 10-20, 10-30, 10-50, 10-100, 20-30, 20-50, 20-100, or 50-100 nm), or any other suitable value or range as will be apparent in light of this disclosure. In some embodiments, the gate length may be less than a given threshold, such as less than 100, 50, 40, 30, 25, 20, 15, 10, 8, or 5 nm, or less than any other suitable threshold as will be apparent in light of this disclosure. In some embodiments, the techniques enable maintaining a desired device performance when scaling to such low thresholds, such as sub-50, sub-40, sub-30, or sub-20 nm thresholds, as can be understood based on this disclosure.

After the transistor processing has been completed (and/or while it is being completed), general integrated circuit (IC) processing 122 may occur as desired, in accordance with some embodiments. Such additional processing to complete an IC may include back-end or back-end- of-line (BEOL) processing to form one or more metallization layers and/or to interconnect the transistor devices formed, for example. Any other suitable processing may be performed, as will be apparent in light of this disclosure. Note that the processes 102-122 in method 100 of Figure 1 are shown in a particular order for ease of description. However, one or more of the processes may be performed in a different order or may not be performed at all (and thus be optional), in accordance with some embodiments. For example, forming a dummy gate is an optional process that need not be performed in embodiments employing a gate first process flow. Numerous variations on method 100 and the techniques described herein will be apparent in light of this disclosure. Recall that the techniques may be used to monolithically co-integrate different and defect free (or substantially defect free) semiconductor materials on/above the same substrate using a thin seed layer. The different semiconductor material structures may then be used to form one or more transistor-based devices, such as one or more FETs (e.g., one or more MOSFETs, TFETs, and so forth). In some embodiments, the techniques may be used to co- integrate the different and defect free (or substantially defect free) semiconductor material to form p-channel and n-channel FETs (e.g., p-MOS and n-MOS) to be used in a complementary transistor-based circuit (e.g., CMOS). In some such embodiments, because the techniques enable the co-integration of any desired semiconductor material, the different semiconductor material selected to be co-integrated may be selected to improve performance. For instance, in some embodiments, high-mobility semiconductor material may be selected for the different devices, such as using Ge or Ge-rich SiGe for p-channel devices (e.g., p-MOS) and III-V material (e.g., InGaAs) for n-channel devices (e.g., n-MOS). In addition, the techniques may be used to form transistor devices having a multitude of configurations, such as planar devices, finned or FinFET devices (e.g., dual-gate or tri-gate devices), nanowire (or nanoribbon or GAA) devices, and beaded-fin devices (e.g., where the channel region shape is between a finned and a nanowire shape), to provide a few examples. Numerous variations and configurations will be apparent in light of this disclosure.

Example System

Figure 4 illustrates a computing system 1000 implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed herein, in accordance with some embodiments of the present disclosure. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc.

Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as variously described herein. As will be appreciated in light of this disclosure, note that multi -standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing system 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set -top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device or system that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. Note that reference to a computing system is intended to include computing devices, apparatuses, and other structures configured for computing or processing information.

Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example 1 is an integrated circuit (IC) including: a substrate; a first device above the substrate and including a first monocrystalline semiconductor material; a second device above the substrate and including a second monocrystalline semiconductor material compositionally different than the first monocrystalline semiconductor material; and a layer including a third monocrystalline semiconductor material compositionally different from the first and second monocrystalline semiconductor materials, the layer between the substrate and the first monocrystalline semiconductor material, the layer also between the substrate and the second monocrystalline semiconductor material, wherein the layer includes a thickness between the substrate and the first monocrystalline semiconductor material of less than 50 nanometers (nm) and the layer also includes a thickness between the substrate and the second monocrystalline semiconductor material of less than 50 nm.

Example 2 includes the subject matter of Example 1, wherein the substrate includes silicon.

Example 3 includes the subject matter of Example 1 or 2, further including an additional layer between the layer and the substrate, the additional layer including electrically insulating material.

Example 4 includes the subject matter of Example 3, wherein the additional layer includes oxide material.

Example 5 includes the subject matter of any of Examples 1-4, wherein the layer includes a thickness between the substrate and the first monocrystalline semiconductor material of less than 20 nm and the layer also includes a thickness between the substrate and the second monocrystalline semiconductor material of less than 20 nm.

Example 6 includes the subject matter of any of Examples 1-5, wherein the first and second monocrystalline semiconductor materials each include at least one of group IV monocrystalline semiconductor material, group III-V monocrystalline semiconductor material, and group II- VI monocrystalline semiconductor material.

Example 7 includes the subject matter of any of Examples 1-6, wherein the first monocrystalline semiconductor material is on the layer and the second monocrystalline semiconductor material is also on the layer. Example 8 includes the subject matter of any of Examples 1-7, wherein the first monocrystalline semiconductor includes gallium and arsenic and the second monocrystalline semiconductor material includes germanium.

Example 9 includes the subject matter of any of Examples 1-8, wherein the layer includes group IV monocrystalline semiconductor material.

Example 10 includes the subject matter of any of Examples 1-9, wherein the layer includes silicon.

Example 11 includes the subject matter of any of Examples 1-10, wherein the layer includes group III-V monocrystalline semiconductor material.

Example 12 includes the subject matter of any of Examples 1-11, wherein: the first device is a first transistor including a first channel region, the first channel region including at least a portion of the first monocrystalline semiconductor material; and the second device is a second transistor including a second channel region, the second channel region including at least a portion of the second monocrystalline semiconductor material.

Example 13 includes the subject matter of any of Examples 1-12, wherein one of the first and second devices is an n-channel transistor and the other of the first and second devices is a p- channel transistor.

Example 14 includes the subject matter of any of Examples 1-13, further including a gate stack proximate to at least two sides of a structure including one of the first and second monocrystalline semiconductor materials.

Example 15 includes the subject matter of any of Examples 1-14, further including a gate stack around a structure including at least one of the first and second monocrystalline semiconductor materials.

Example 16 includes the subject matter of any of Examples 1-15, further including a complementary metal-oxide-semiconductor (CMOS) circuit including the first and second devices.

Example 17 is a computing system including the subject matter of any of Examples 1-16.

Example 18 is an integrated circuit (IC) including: a substrate; a first transistor above the substrate, the first transistor including a first fin that includes a first monocrystalline semiconductor material; a second transistor above the substrate, the second transistor including a second fin that includes a second monocrystalline semiconductor material compositionally different than the first monocrystalline semiconductor material; a first layer between the substrate and the first fin, the first layer also between the substrate and the second fin, the first layer including a third monocrystalline semiconductor material compositionally different than the first and second semiconductor materials; and a second layer between the substrate and the first layer, the second layer including electrically insulating material; wherein the first layer includes a thickness between the substrate and the first fin of less than 50 nanometers (nm) and the first layer also includes a thickness between the substrate and the second fin of less than 50 nm.

Example 19 includes the subject matter of Example 18, wherein the substrate includes silicon.

Example 20 includes the subject matter of Example 18 or 19, wherein the second layer includes oxide material.

Example 21 includes the subject matter of any of Examples 18-20, wherein the first layer includes a thickness between the substrate and the first fin of less than 20 nm and the first layer also includes a thickness between the substrate and the second fin of less than 20 nm.

Example 22 includes the subject matter of any of Examples 18-21, wherein the first and second fins are on the first layer.

Example 23 includes the subject matter of any of Examples 18-22, wherein the first and second fins each include at least one of group IV monocrystalline semiconductor material, group III-V monocrystalline semiconductor material, and group II-VI monocrystalline semiconductor material.

Example 24 includes the subject matter of any of Examples 18-23, wherein the first and second fins include monocrystalline semiconductor material from different groups selected from group IV monocrystalline semiconductor material, group III-V monocrystalline semiconductor material, and group II-VI monocrystalline semiconductor material.

Example 25 includes the subject matter of any of Examples 18-24, wherein the first fin includes indium, gallium, and arsenic, and the second fin includes germanium.

Example 26 includes the subject matter of any of Examples 18-25, wherein the first layer includes silicon.

Example 27 includes the subject matter of any of Examples 18-26, wherein the monocrystalline semiconductor material included in both the first and second fins is substantially defect free, such that the first and second fins each include two or less misfit dislocations per fin. Example 28 includes the subject matter of any of Examples 18-27, wherein the monocrystalline semiconductor material included in both the first and second fins is defect free, such that the first and second fins each include no misfit dislocations.

Example 29 includes the subject matter of any of Examples 18-28, wherein: the first transistor includes a first channel region, the first channel region including at least a portion of the first fin; and the second transistor structure includes a second channel region, the second channel region including at least a portion of the second fin.

Example 30 includes the subject matter of Example 29, wherein one of the first and second transistors is an n-channel field-effect transistor and the other of the first and second transistors is a p-channel field-effect transistor.

Example 31 includes the subject matter of any of Examples 29-30, the first transistor further including a gate proximate to multiple sides of the channel region of the first fin, such that the first transistor includes a double-gate or tri-gate transistor structure.

Example 32 includes the subject matter of any of Examples 29-31, the second transistor further including a gate around all sides of the channel region of the second fin, such that the second transistor includes a gate-all-around transistor structure.

Example 33 includes the subject matter of any of Examples 18-32, further including a complementary metal-oxide-semiconductor (CMOS) circuit including the first and second transistors.

Example 34 is a mobile computing system including the subject matter of any of Examples

18-33.

Example 35 is a method of forming an integrated circuit (IC), the method including: providing a substrate; forming a layer above the substrate; forming a first fin on the layer, the first fin including a first monocrystalline semiconductor material; and forming a second fin on the layer, the second fin including a second monocrystalline semiconductor material compositionally different than the first monocrystalline semiconductor material; wherein the layer includes a third monocrystalline semiconductor material compositionally different from the first and second monocrystalline semiconductor materials, wherein the layer includes a thickness between the substrate and the first fin of less than 50 nanometers (nm) and the layer also includes a thickness between the substrate and the second fin of less than 50 nm.

Example 36 includes the subject matter of Example 35, wherein the substrate includes a multilayer structure, the multilayer structure including a first layer that includes a bulk semiconductor material and a second layer that includes electrically insulating material, wherein the second layer is above and on the first layer.

Example 37 includes the subject matter of Example 35 or 36, wherein the layer is formed above the substrate by one of bonding the layer to the substrate, epitaxially depositing the layer on the substrate, and using a semiconductor-on-insulator substrate fabrication process.

Example 38 includes the subject matter of any of Examples 35-37, wherein the first and second fins are epitaxially deposited in fin-shaped trenches having bottoms, the fin-shaped trenches formed in electrically insulating material such that the bottoms of the fin-shaped trenches each include a top surface of the layer.

Example 39 includes the subject matter of any of Examples 35-38, further including: forming sacrificial fins on the layer prior to forming the first and second fins on the layer; and removing the sacrificial fins on the layer prior to forming the first and second fins on the layer, such that the removal of the sacrificial fins forms fin-shaped trenches in which the first and second fins are formed.

Example 40 includes the subject matter of any of Examples 35-39, wherein the layer includes a thickness between the substrate and the first fin of less than 20 nm and the layer also includes a thickness between the substrate and the second fin of less than 20 nm.

Example 41 includes the subject matter of any of Examples 35-40, wherein the first, second, and third monocrystalline semiconductor materials all include different semiconductor materials.

Example 42 includes the subject matter of any of Examples 35-41, wherein at least one of the first and second fins has a tapered cross-section such that the fin is wider at its bottom than its top.

Example 43 includes the subject matter of any of Examples 35-42, wherein the first and second fins include monocrystalline semiconductor material from different groups selected from group IV monocrystalline semiconductor material, group III-V monocrystalline semiconductor material, and group monocrystalline II-VI semiconductor material.

Example 44 includes the subject matter of any of Examples 35-43, further including: forming a first transistor including a first channel region, wherein the first channel region includes at least a portion of the first fin; and forming a second transistor including a second channel region, wherein the second channel region includes at least a portion of the second fin. Example 45 includes the subject matter of Example 44, wherein one of the first and second transistors is an n-channel transistor, and wherein the other of the first and second transistors is a p-channel transistor.

Example 46 includes the subject matter of any of Examples 35-45, wherein the first fin includes a channel region of a first transistor, the method further including: forming a first gate structure on multiple sides of the channel region of the first fin, such that the first transistor includes a double-gate or tri-gate transistor structure.

Example 47 includes the subject matter of any of Examples 35-46, wherein the second fin includes a channel region of a second transistor, the method further including: forming a second gate structure on all sides of the channel region of the second fin, such that the second transistor includes a gate-all-around transistor structure.

Example 48 includes the subject matter of Example 46 or 47, further including: forming a source region and a drain region, such that the channel region is between the source and drain regions; and forming a source contact structure on the source region, and a drain contact structure on the drain region.

The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.

Claims

CLAIMS What is claimed is:

1. An integrated circuit (IC) comprising:

a substrate;

a first device above the substrate and including a first monocrystalline semiconductor material;

a second device above the substrate and including a second monocrystalline semiconductor material compositionally different than the first monocrystalline semiconductor material; and

a layer including a third monocrystalline semiconductor material compositionally different from the first and second monocrystalline semiconductor materials, the layer between the substrate and the first monocrystalline semiconductor material, the layer also between the substrate and the second monocrystalline semiconductor material, wherein the layer includes a thickness between the substrate and the first monocrystalline semiconductor material of less than 50 nanometers (nm) and the layer also includes a thickness between the substrate and the second monocrystalline semiconductor material of less than 50 nm.

2. The IC of claim 1, wherein the substrate includes silicon.

3. The IC of claim 1, further comprising an additional layer between the layer and the substrate, the additional layer including electrically insulating material.

4. The IC of claim 3, wherein the additional layer includes oxide material.

5. The IC of claim 1, wherein the layer includes a thickness between the substrate and the first monocrystalline semiconductor material of less than 20 nm and the layer also includes a thickness between the substrate and the second monocrystalline semiconductor material of less than 20 nm.

6. The IC of claim 1, wherein the first and second monocrystalline semiconductor materials each include at least one of group IV monocrystalline semiconductor material, group III-V monocrystalline semiconductor material, and group II-VI monocrystalline semiconductor material.

7. The IC of claim 1, wherein the first monocrystalline semiconductor material is on the layer and the second monocrystalline semiconductor material is also on the layer.

8. The IC of claim 1, wherein the first monocrystalline semiconductor includes gallium and arsenic and the second monocrystalline semiconductor material includes germanium.

9. The IC of claim 1, wherein the layer includes group IV monocrystalline semiconductor material.

10. The IC of claim 1, wherein the layer includes silicon.

11. The IC of claim 1, wherein the layer includes group III-V monocrystalline semiconductor material.

12. The IC of claim 1, wherein:

the first device is a first transistor including a first channel region, the first channel region including at least a portion of the first monocrystalline semiconductor material; and

the second device is a second transistor including a second channel region, the second channel region including at least a portion of the second monocrystalline semiconductor material.

13. The IC of claim 1, wherein one of the first and second devices is an n-channel transistor and the other of the first and second devices is a p-channel transistor.

14. The IC of claim 1, further comprising a gate stack proximate to at least two sides of a structure including one of the first and second monocrystalline semiconductor materials.

15. The IC of claim 1, further comprising a gate stack around a structure including at least one of the first and second monocrystalline semiconductor materials.

16. The IC of claim 1, further comprising a complementary metal-oxide- semiconductor (CMOS) circuit including the first and second devices.

17. A computing system comprising the IC of any of claims 1 -16.

18. An integrated circuit (IC) comprising: a substrate;

a first transistor above the substrate, the first transistor including a first fin that includes a first monocrystalline semiconductor material;

a second transistor above the substrate, the second transistor including a second fin that includes a second monocrystalline semiconductor material compositionally different than the first monocrystalline semiconductor material;

a first layer between the substrate and the first fin, the first layer also between the substrate and the second fin, the first layer including a third monocrystalline semiconductor material compositionally different than the first and second semiconductor materials; and

a second layer between the substrate and the first layer, the second layer including electrically insulating material;

wherein the first layer includes a thickness between the substrate and the first fin of less than 50 nanometers (nm) and the first layer also includes a thickness between the substrate and the second fin of less than 50 nm.

19. The IC of claim 18, wherein the first layer includes a thickness between the substrate and the first fin of less than 20 nm and the first layer also includes a thickness between the substrate and the second fin of less than 20 nm.

20. The IC of claim 18, wherein the first fin includes indium, gallium, and arsenic, and the second fin includes germanium.

21. The IC of claim 18, wherein the first layer includes silicon.

22. The IC of any of claims 18-21, wherein the monocrystalline semiconductor material included in both the first and second fins is substantially defect free, such that the first and second fins each include two or less misfit dislocations per fin.

23. A method of forming an integrated circuit (IC), the method comprising:

providing a substrate;

forming a layer above the substrate;

forming a first fin on the layer, the first fin including a first monocrystalline semiconductor material; and forming a second fin on the layer, the second fin including a second monocrystalline semiconductor material compositionally different than the first monocrystalline semiconductor material;

wherein the layer includes a third monocrystalline semiconductor material compositionally different from the first and second monocrystalline semiconductor materials, wherein the layer includes a thickness between the substrate and the first fin of less than 50 nanometers (nm) and the layer also includes a thickness between the substrate and the second fin of less than 50 nm.

24. The method of claim 23, wherein the substrate includes a multilayer structure, the multilayer structure including a first layer that includes a bulk semiconductor material and a second layer that includes electrically insulating material, wherein the second layer is above and on the first layer.

25. The method of claim 23 or 24, further comprising:

forming sacrificial fins on the layer prior to forming the first and second fins on the layer; and

removing the sacrificial fins on the layer prior to forming the first and second fins on the layer, such that the removal of the sacrificial fins forms fin-shaped trenches in which the first and second fins are formed.