WO2018165832A1 - Cmos image sensor - Google Patents

Cmos image sensor Download PDF

Info

Publication number
WO2018165832A1
WO2018165832A1 PCT/CN2017/076510 CN2017076510W WO2018165832A1 WO 2018165832 A1 WO2018165832 A1 WO 2018165832A1 CN 2017076510 W CN2017076510 W CN 2017076510W WO 2018165832 A1 WO2018165832 A1 WO 2018165832A1
Authority
WO
WIPO (PCT)
Prior art keywords
source
gate
image sensor
drain
pixel
Prior art date
Application number
PCT/CN2017/076510
Other languages
French (fr)
Inventor
Makoto Monoi
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Priority to CN201780085024.3A priority Critical patent/CN110291782B/en
Priority to PCT/CN2017/076510 priority patent/WO2018165832A1/en
Publication of WO2018165832A1 publication Critical patent/WO2018165832A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14638—Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14641—Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • the present invention relates to the field of an image sensor, in particular, a high dynamic range complementary metal oxide semiconductor (CMOS) image sensor and its pixel structure.
  • CMOS complementary metal oxide semiconductor
  • Fig. 1 shows a circuit diagram of a pixel circuit of a general CMOS image sensor
  • Fig. 2 shows a top view of the pixel circuit arranged on a surface of a silicon substrate.
  • the meaning of the abbreviations are as follows: PD: a photodiode where light is converted to signal electron, TG: a transfer gate that transfers signal charge to an FD, FD: a floating diffusion where signal charge is converted to signal voltage, Cfd: capacitance of the FD, RS: a reset gate that sets the voltage of FD, AMP: an amplifier transistor that converts signal voltage of the FD to a low impedance output signal, SL: a selector transistor, ADC: an analog digital converter.
  • Fig. 3 shows a pulse timing chart for the pixel circuit in Fig. 1
  • Fig. 4 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along A-B in Fig. 2
  • Fig. 5 shows a potential diagram according to the timing in Fig. 3.
  • t1 the falling edge of the first pulse of the TG and RS
  • Tint denotes integration period.
  • the time period between t1 and t2 is much longer than the time period between t2, t3, and t4.
  • the signal charge is stored in the PD.
  • an FD voltage is set to a baseline level, the SL is turned on, and the AMP converts a signal voltage of the FD to a low impedance output signal.
  • a signal line level is converted to a digital value as the baseline level (0_HG) (HG: High gain) , and after signal charge is transferred from the PD to the FD by opening the TG (the second pulse of TG) , at t4, the signal is converted to a digital value as a signal (Signal_HG) . It take some time from the falling edge of the second pulse of the TG to the time when the ADC outputs Signal_HG. In this structure, the amount of signal charge is limited by the capacity of PD and the amount is not large.
  • Fig. 6 shows a pixel circuit of a high dynamic range CMOS image sensor in the prior art that enlarges the amount of signal charge.
  • Fig. 7 shows a top view of the pixel circuit arranged on a surface of a silicon substrate.
  • SW a switching transistor that connects to RS and controls capacitance of the FD
  • Ca additional capacitance.
  • Fig. 8 shows a pulse timing chart for the pixel circuit in Fig. 6,
  • Fig. 9 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along A-B in Fig. 7, and
  • Fig. 10 shows a potential diagram according to the timing in Fig. 8.
  • the Ca is, for example, made of metal-insulator-metal capacitor above the silicon substrate. Referring to Figs. 8 to 10, at t1 (the falling edge of the first pulse of TG) , charge in the PD is cleared and signal integration starts. Tint denotes integration period. Around t2, signal charge is stored in the PD, FD, and Ca.
  • a CMOS image sensor is provided to shrink the pixel size of a high dynamic range pixel.
  • CMOS image sensor includes:
  • a photodiode (PD) , an anode of which is connected to a ground, and a cathode of which is connected to a source of a transfer gate (TG) ;
  • FD floating diffusion
  • the TG the source of which is connected to the cathode of the PD, and a drain of which is connected to the FD;
  • SW switching transistor
  • RS reset gate
  • the RS the source of which is connected to the drain of the SW and the Ca, and a drain of which is connected to the FD;
  • AMP amplifier transistor
  • the PD is arranged in a first row on a substrate
  • any of the AMP, SW, and RS is arranged in a second row on the substrate, and
  • the rest of the AMP, SW, and RS are arranged in a third row on the substrate.
  • the CMOS image sensor further includes a second PD which extends from the inside to the back of the substrate, the TG extends from the surface of the substrate to the second PD, and charge moves from the second PD to the TG.
  • the second row and the third row are orthogonal.
  • the CMOS image sensor further includes a second PD which extends from the inside to the back of the substrate, the TG extends from the surface of the substrate to the second PD, and charge moves from the second PD to the TG.
  • any of the TG, FD, SW, and RS is stacked on the PD.
  • CMOS image sensor includes: a plurality of pixel circuits arranged in lattice manner, wherein each pixel circuit includes
  • FD1 a first floating diffusion
  • a first reset gate (RS1) , a source of which is connected to a power source voltage, and a drain of which is connected to the FD1;
  • AMP1 a first amplifier transistor, a gate of which is connected to the FD1, and a source of which is connected to the power source voltage;
  • FD2 floating diffusion
  • a second reset gate (RS2) , a source of which is connected to the power source voltage, and a drain of which is connected to the FD2;
  • AMP2 a second amplifier transistor
  • each pixel unit includes:
  • a photodiode (PD) , an anode of which is connected to a ground, and a cathode of which is connected to a source of a transfer gate (TG) and the D1;
  • SW switching transistor
  • the CMOS image sensor includes a potential region between the D1 and the PD, wherein the potential of the potential region is different from the potential of the region for accumulating signal charge of the PD, and the potential region is a barrier against transfer of signal charge.
  • the gate of the RS1 is ON during a predetermined period, and the gate of the SW is ON, and then, the gate of the TG and the gate of the RS2 is ON during a predetermined period.
  • the CMOS image sensor further includes a second PD which extends from the inside to the back of the substrate, the TG extends from the surface of the substrate to the second PD, and charge moves from the second PD to the TG.
  • any of the TG, FD, SW, and RS is stacked on the PD.
  • CMOS image sensor includes: a plurality of pixel circuits arranged in lattice manner, wherein each pixel circuit includes
  • FD1 a first floating diffusion
  • a first reset gate (RS1) , a source of which is connected to a power source voltage, and a drain of which is connected to the FD1;
  • AMP1 a first amplifier transistor, a gate of which is connected to the FD1, and a source of which is connected to the power source voltage;
  • FD2 floating diffusion
  • a second reset gate (RS2) , a source of which is connected to the power source voltage, and a drain of which is connected to the FD2;
  • AMP2 a second amplifier transistor
  • each pixel unit includes:
  • a photodiode (PD) , an anode of which is connected to a ground, and a cathode of which is connected to a source of a transfer gate (TG) and the D1;
  • the TG the source of which is connected to the cathode of the PD, and a drain of which is connected to the FD1;
  • SW switching transistor
  • drains of the SWs of the sixth to eighth pixel units, the fifth pixel unit of the pixel circuit arranged at the lower side, the first to third pixel units of the pixel circuit arranged at the right side, and the fourth pixel unit of the pixel circuit arranged at the lower right are connected to said FD2,
  • the drains of the SWs of the first to third pixel units are connected to the FD2 of the pixel circuit arranged at the left side,
  • the drain of the SW of the fourth pixel unit is connected to the FD2 of the pixel circuit arranged at the upper left, and
  • the drain of the SW of the fifth pixel unit is connected to the FD2 of the pixel circuit arranged at the upper side.
  • the gate of the RS1 is ON during a predetermined period, and the gate of the SW is ON, and then, the gate of the TG and the gate of the RS2 is ON during a predetermined period.
  • the CMOS image sensor further includes a second PD which extends from the inside to the back of the substrate, the TG extends from the surface of the substrate to the second PD, and charge moves from the second PD to the TG.
  • any of the TG, FD, SW, and RS is stacked on the PD.
  • CMOS image sensor includes:
  • a photodiode (PD) , an anode of which is connected to a ground, and a cathode of which is connected to a source of a transfer gate (TG) ;
  • FD floating diffusion
  • the TG the source of which is connected to the cathode of the PD, and a drain of which is connected to the FD;
  • SW switching transistor
  • RS reset gate
  • the RS the source of which is connected to the drain of the SW and the Ca, and a drain of which is connected to the FD;
  • AMP amplifier transistor
  • the CMOS image sensor further includes a second PD which extends from the inside to the back of the substrate, the TG extends from the surface of the substrate to the second PD, and charge moves from the second PD to the TG.
  • any of the TG, FD, SW, and RS is stacked on the PD.
  • a CMOS image sensor is provided according to the various implementation manners to shrink the pixel size of a high dynamic range pixel.
  • FIG. 1 shows a circuit diagram of a pixel circuit of a general CMOS image sensor
  • FIG. 2 shows a top view of the pixel circuit arranged on a surface of a silicon substrate
  • FIG. 3 shows a pulse timing chart for the pixel circuit in Fig. 1;
  • FIG. 4 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along A-B in Fig. 2;
  • FIG. 5 shows a potential diagram according to the timing in Fig. 3;
  • FIG. 6 shows a pixel circuit of a high dynamic range CMOS image sensor in the prior art that enlarges the amount of signal charge
  • FIG. 7 shows a top view of the pixel circuit arranged on a surface of a silicon substrate
  • FIG. 8 shows a pulse timing chart for the pixel circuit in Fig. 6;
  • FIG. 9 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along A-B in Fig. 7;
  • FIG. 10 shows a potential diagram according to the timing in Fig. 8.
  • FIG. 11 shows a top view of a pixel circuit arranged on a surface of a silicon substrate according to the first embodiment of the present invention
  • FIG. 12 shows a top view of a pixel circuit arranged on a surface of a silicon substrate according to the second embodiment of the present invention
  • FIG. 13 shows a top view of a pixel circuit arranged on a surface of a silicon substrate according to the third embodiment of the present invention
  • FIG. 14 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along C-D in Fig. 11;
  • FIG. 15 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along E-F in Fig. 13;
  • FIG. 16 shows a circuit diagram of an alternative solution
  • FIG. 17 shows a top view of one pixel circuit arranged on a surface of a silicon substrate
  • FIG. 18 shows a pulse timing chart for the pixel circuit in Fig. 16
  • FIG. 19 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along G-H in Fig. 17;
  • FIG. 20 shows a potential diagram according to the timing in Fig. 18.
  • Fig. 11 shows a top view of a pixel circuit arranged on a surface of a silicon substrate according to the first embodiment of the present invention.
  • Pixel transistors AMP, SL, SW, and RS
  • the length of the side of the area shown in Fig. 11 is about 0.7 times as that of the area shown in Fig. 7 in an actual measurement.
  • an CMOS image sensor includes a PD, an anode of which is connected to a ground, and a cathode of which is connected to a source of a TG; an FD; a Ca; the TG, the source of which is connected to the cathode of the PD, and a drain of which is connected to the FD; an SW, a source of which is connected to a power source voltage, and a drain of which is connected to a source of an RS and the Ca; the RS, the source of which is connected to the drain of the SW and the Ca, and a drain of which is connected to the FD; an AMP, a gate of which is connected to the FD, a source of which is connected to the power source voltage, and a drain of which is connected to a source of an SL; and the SL, the source of which is connected to the drain of the AMP, and a drain of which is connected to a signal line.
  • the PD, the TG, and the FD are arranged in order in a first row on a substrate, the AMP and the SL are arranged in a second row on the substrate, and the SW and the RS are arranged in a third row on the substrate.
  • the AMP, the SL, the SW, and the RS are located on relatively thick p-type area (the lower half area in Fig. 11)
  • the PD, the TG, and the FD are surrounded by a relatively thin p-type area (the upper half area in Fig. 11) .
  • the locations of the second row and the third row, the locations of the AMP and the SL, and the locations of the SW and the RS may be changed.
  • Fig. 12 shows a top view of a pixel circuit arranged on a surface of a silicon substrate according to the second embodiment of the present invention. Pixel transistors are arranged in crisscross.
  • the PD, the TG, and the FD are arranged in order in a first row on a substrate in the oblique direction, the AMP and the SL are arranged in a second row on the substrate in the horizontal direction, and the SW and the RS are arranged in third row on the substrate in the vertical direction.
  • the AMP, the SL, the SW, and the RS are located on relatively thick p-type area, and the PD, the TG, and the FD are surrounded by relatively thin p-type area.
  • the locations of the second row and the third row, the locations of the AMP and the SL, and the locations of the SW and the RS may be changed.
  • Fig. 13 shows a top view of a pixel circuit arranged on a surface of a silicon substrate according to the third embodiment of the present invention.
  • Fig. 15 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along E-F in Fig. 13.
  • TG extends into the silicon substrate and signal charge from PD2 is transferred vertically (arrow in Fig. 15) to FD via TG.
  • Fig. 14 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along C-D in Fig. 11.
  • signal charge is transferred in the horizontal direction on the surface of the substrate (arrow in Fig. 14) and this requires large PD area on the surface.
  • the vertical TG reduces PD area on the surface. Any of TG, FD, SW, and RS may be stacked on PD.
  • Fig. 14 most of signal charge transferred to FD is stored in PD region.
  • the signal charge in PD2 is difficult to move to FD because PD2 is physically distant from FD.
  • PD region is much smaller than that in Fig. 14 and can store much less signal charge. So, most of signal charge transferred to FD is stored in PD2 region.
  • Charge transfer from PD2 to FD is improved by the vertically extended TG.
  • pixel size can be reduced.
  • the length of the side of the area shown in Fig. 13 is about 0.7 times as that of the area shown in Fig. 11, and the length of the side of the area shown in Fig. 13 is about 0.5 times as that of the area shown in Fig. 7.
  • Fig. 16 shows a circuit diagram of an alternative solution.
  • Fig. 16 includes four pixel circuits connected each other.
  • the upward connection relations of the upper two pixel circuits in Fig. 16 are same as the upward connection relations of the lower two pixel circuits, and the downward connection relations of the lower two pixel circuits in Fig. 16 (not shown) are same as the downward connection relations of the upper two pixel circuits.
  • Fig. 17 shows a top view of one pixel circuit arranged on a surface of a silicon substrate. A plurality of pixel circuits are arranged in lattice manner. In Fig.
  • the SWs at the upper left and the lower left of the FD at position C1 (position C in the vertical direction and position 1 in the horizontal direction) and the SW at the upper left of the FD at position E1 belong to the pixel circuit arranged at the left side.
  • the SWs at the upper right and the lower right of the FD at position C3 and the SW at the upper right of the FD at position E3 belong to the pixel circuit arranged at the right side.
  • the SW at the lower right of the FD at position E1 and the SW at the lower left of the FD at position E3 belong to the pixel circuit arranged at the lower side.
  • the SW at the lower left of the FD at position E1 belongs to the pixel circuit at the lower left.
  • the SW at the lower right of the FD at position E3 belongs to the pixel circuit arranged at the lower right.
  • FD2 at position C1, C3, E1, and E3 are shared with adjacent pixel circuit.
  • the FD2s at position A1 and A3, the SW at the lower right of the FD at position A1, and the SW at the lower left of the FD at position A3 are not shown in Fig. 17.
  • Fig. 17 shows one pixel circuits, and the circuit diagram shown in Fig. 16 corresponds 2-by-2 pixel circuits.
  • a CMOS image sensor includes a plurality of pixel circuits arranged in lattice manner.
  • each pixel circuit includes a first floating diffusion (FD1) ; a first reset gate (RS1) , a source of which is connected to a power source voltage, and a drain of which is connected to the FD1; a first amplifier transistor (AMP1) , a gate of which is connected to the FD1, a source of which is connected to the power source voltage, and a drain of which is connected to a source of a first selector transistor (SL1) ; the SL1, the source of which is connected to the drain of the AMP1, and a drain of which is connected to a first signal line; a second floating diffusion (FD2) ; a second reset gate (RS2) , a source of which is connected to the power source voltage, and a drain of which is connected to the FD2; a second amplifier transistor (AMP2) , a gate of which is connected to the FD2, a source of which is
  • Each pixel unit includes: a diffusion (D1) ; a PD, an anode of which is connected to a ground, and a cathode of which is connected to a source of a TG and the D1; the TG, the source of which is connected to the cathode of the PD and the D1, and a drain of which is connected to the FD1; a Ca connected to the D1; an SW, a source of which is connected to the D1.
  • D1 diffusion
  • a PD an anode of which is connected to a ground
  • a cathode of which is connected to a source of a TG and the D1
  • the TG the source of which is connected to the cathode of the PD and the D1
  • a drain of which is connected to the FD1
  • a Ca connected to the D1
  • an SW a source of which is connected to the D1.
  • each pixel circuit shown in Fig. 16 are first to eighth pixel units from left to right
  • the first to fourth pixel units in each pixel circuit in Fig. 16 correspond to left four pixel units from bottom to top in Fig. 17
  • the fifth to eighth pixel units in each pixel circuit in Fig. 16 correspond to right four pixel units from top to bottom in Fig. 17.
  • the drains of the SWs of the sixth to eighth pixel units of a predetermined pixel circuit, the fifth pixel unit of the pixel circuit arranged at the lower side, the first to third pixel units of the pixel circuit arranged at the right side, and the fourth pixel unit of the pixel circuit arranged at the lower right are connected to the FD2 of the predetermined pixel circuit
  • the drains of the SWs of the first to third pixel units of the predetermined pixel circuit are connected to the FD2 of the pixel circuit arranged at the left side
  • the drain of the SW of the fourth pixel unit of the predetermined pixel circuit is connected to the FD2 of the pixel circuit arranged at the upper left
  • the drain of the SW of the fifth pixel unit of the predetermined pixel circuit is connected to the FD2 of the pixel circuit arranged at the upper side.
  • each pixel circuit has eight pixel units.
  • the number of the pixel units is not limited to eight.
  • Fig. 18 shows a pulse timing chart for the pixel circuit in Fig. 16
  • Fig. 19 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along G-H in Fig. 17,
  • Fig. 20 shows a potential diagram according to the timing in Fig. 18.
  • t1 the falling edge of the first pulse of the TG
  • Tint denotes integration period
  • PDx is potential barrier between PD and D1.
  • excess charge over PDx overflow into D1.
  • signal charge is stored in the PD and Ca.
  • the overflow charge at the PD flows directly from PD to Ca.
  • FD1 is set to a baseline voltage and D1 connects to FD2 by opening the SW.
  • both signals of the FD1 and FD2 are AD converted simultaneously as a baseline signal of HG (0_HG) and a signal of the LG (Signal_LG) , respectively.
  • the signal in the PD is transferred to the FD1 and FD2 is set to a baseline voltage level.
  • both signals of the FD1 and FD2 are AD converted simultaneously as a signal of the HG (Signal_HG) and a baseline signal of LG (0_LG) , respectively.
  • a circuit including the AMP, SL and RS is equipped per four PDs. A number of pixel transistors is reduced and therefore pixel size can be reduced. Furthermore, signals of the HG and LG output are in parallel, so readout speed is faster.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

A CMOS image sensor includes: a PD, an anode of which is connected to a ground, and a cathode of which is connected to a source of a TG; an FD; a Ca; the TG, the source of which is connected to the cathode of the PD, and a drain of which is connected to the FD; an SW, a source of which is connected to a power source voltage, and a drain of which is connected to a source of an RS and the Ca; the RS, the source of which is connected to the drain of the SW and the Ca, and a drain of which is connected to the FD; an AMP, a gate of which is connected to the FD, a source of which is connected to the power source voltage, wherein the PD is arranged in a first row on a substrate, any of the AMP, SW, and RS is arranged in a second row on the substrate, and the rest of the AMP, SW, and RS are arranged in a third row on the substrate. The CMOS image sensor achieves to shrink the pixel size of a high dynamic range pixel.

Description

CMOS IMAGE SENSOR TECHNICAL FIELD
The present invention relates to the field of an image sensor, in particular, a high dynamic range complementary metal oxide semiconductor (CMOS) image sensor and its pixel structure.
BACKGROUND
Fig. 1 shows a circuit diagram of a pixel circuit of a general CMOS image sensor, and Fig. 2 shows a top view of the pixel circuit arranged on a surface of a silicon substrate. The meaning of the abbreviations are as follows: PD: a photodiode where light is converted to signal electron, TG: a transfer gate that transfers signal charge to an FD, FD: a floating diffusion where signal charge is converted to signal voltage, Cfd: capacitance of the FD, RS: a reset gate that sets the voltage of FD, AMP: an amplifier transistor that converts signal voltage of the FD to a low impedance output signal, SL: a selector transistor, ADC: an analog digital converter.
Fig. 3 shows a pulse timing chart for the pixel circuit in Fig. 1, Fig. 4 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along A-B in Fig. 2, and Fig. 5 shows a potential diagram according to the timing in Fig. 3. Referring to Figs. 3 to 5, at t1 (the falling edge of the first pulse of the TG and RS) , charge in the PD is cleared and signal integration starts. Tint denotes integration period. As a wavy line is shown at the left side in Fig. 3, the time period between t1 and t2 is much longer than the time period between t2, t3, and t4. Around t2, the signal charge is stored in the PD. At t3 (the falling edge of the second pulse of RS) , an FD voltage is set to a baseline level, the SL is turned on, and the AMP converts a signal voltage of the FD to a low impedance output signal. At the ADC, a signal line level is converted to a digital value as the baseline level (0_HG) (HG: High gain) , and after signal charge is transferred from the PD to the FD by opening the TG (the second pulse of TG) , at t4, the signal is converted to a digital value as a signal (Signal_HG) . It take some time from the falling edge of the second pulse of the TG to the time when the ADC outputs Signal_HG. In this structure, the amount of signal charge is limited by the capacity of PD and the amount is not large.
Fig. 6 shows a pixel circuit of a high dynamic range CMOS image sensor in the prior art that enlarges the amount of signal charge. Fig. 7 shows a top view of the pixel circuit arranged on a  surface of a silicon substrate. As shown in Figs. 6 and 7, the SW and Ca are added to the circuit in Fig. 1. The meaning of the abbreviations are as follows: SW: a switching transistor that connects to RS and controls capacitance of the FD, Ca: additional capacitance.
Fig. 8 shows a pulse timing chart for the pixel circuit in Fig. 6, Fig. 9 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along A-B in Fig. 7, and Fig. 10 shows a potential diagram according to the timing in Fig. 8. The Ca is, for example, made of metal-insulator-metal capacitor above the silicon substrate. Referring to Figs. 8 to 10, at t1 (the falling edge of the first pulse of TG) , charge in the PD is cleared and signal integration starts. Tint denotes integration period. Around t2, signal charge is stored in the PD, FD, and Ca. Since after t1, the gate of TG is low level and the gate of RS is high level, threshold level of TG is high, threshold level of RS is low, and overflow charge at PD flows from the PD to Ca and FD via the TG as shown in Fig. 10. Signal is AD converted as a signal at LG (LG: low gain) , i.e. the ADC outputs Signal_LG. Then the signal at the Ca and FD is cleared and at t3, the FD voltage is AD converted as a baseline level of the HG signal, i.e. the ADC outputs 0_HG. Then the signal remaining at the PD is transferred to the FD and at t4, signal is AD converted as a signal of HG, i.e. the ADC outputs Signal_HG. In this structure, the amount of signal charge is total of capacity of the PD and Ca. By Ca, large amount of signal charge is attained.
Comparing Fig. 2 and Fig. 7, the high dynamic range pixel is larger than the general pixel due to the additional SW.
SUMMARY
A CMOS image sensor is provided to shrink the pixel size of a high dynamic range pixel.
According to a first aspect, a CMOS image sensor is provided, where the CMOS image sensor includes:
a photodiode (PD) , an anode of which is connected to a ground, and a cathode of which is connected to a source of a transfer gate (TG) ；
a floating diffusion (FD) ；
a capacitor (Ca) ；
the TG, the source of which is connected to the cathode of the PD, and a drain of which is connected to the FD；
a switching transistor (SW) , a source of which is connected to a power source voltage, and a drain of which is connected to a source of a reset gate (RS) and the Ca；
the RS, the source of which is connected to the drain of the SW and the Ca, and a drain of  which is connected to the FD； and
an amplifier transistor (AMP) , a gate of which is connected to the FD, and a source of which is connected to the power source voltage,
wherein the PD is arranged in a first row on a substrate,
any of the AMP, SW, and RS is arranged in a second row on the substrate, and
the rest of the AMP, SW, and RS are arranged in a third row on the substrate.
In a first possible implementation manner of the first aspect, the CMOS image sensor further includes a second PD which extends from the inside to the back of the substrate, the TG extends from the surface of the substrate to the second PD, and charge moves from the second PD to the TG.
In a second possible implementation manner of the first aspect, the second row and the third row are orthogonal.
With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner of the second aspect, the CMOS image sensor further includes a second PD which extends from the inside to the back of the substrate, the TG extends from the surface of the substrate to the second PD, and charge moves from the second PD to the TG.
With reference to the first aspect or the first to third possible implementation manner of the first aspect, in a third possible implementation manner of the second aspect, any of the TG, FD, SW, and RS is stacked on the PD.
According to a second aspect, a CMOS image sensor is provided, where the CMOS image sensor includes: a plurality of pixel circuits arranged in lattice manner, wherein each pixel circuit includes
a first floating diffusion (FD1) ；
a first reset gate (RS1) , a source of which is connected to a power source voltage, and a drain of which is connected to the FD1；
a first amplifier transistor (AMP1) , a gate of which is connected to the FD1, and a source of which is connected to the power source voltage；
a second floating diffusion (FD2) ；
a second reset gate (RS2) , a source of which is connected to the power source voltage, and a drain of which is connected to the FD2；
a second amplifier transistor (AMP2) , a gate of which is connected to the FD2, and a source of which is connected to the power source voltage； and
pixel units,
wherein each pixel unit includes:
a diffusion (D1) ；
a photodiode (PD) , an anode of which is connected to a ground, and a cathode of which is connected to a source of a transfer gate (TG) and the D1；
a capacitor (Ca) connected to the D1；
a switching transistor (SW) , a source of which is connected to the D1.
In a first possible implementation manner of the second aspect, the CMOS image sensor includes a potential region between the D1 and the PD, wherein the potential of the potential region is different from the potential of the region for accumulating signal charge of the PD, and the potential region is a barrier against transfer of signal charge.
With reference to the second aspect or the first possible implementation manner of the second aspect, in a second possible implementation manner of the second aspect, after the charge of the PD is cleared, the gate of the RS1 is ON during a predetermined period, and the gate of the SW is ON, and then, the gate of the TG and the gate of the RS2 is ON during a predetermined period.
With reference to the second aspect or the first or second possible implementation manner of the second aspect, in a third possible implementation manner of the second aspect, the CMOS image sensor further includes a second PD which extends from the inside to the back of the substrate, the TG extends from the surface of the substrate to the second PD, and charge moves from the second PD to the TG.
With reference to the second aspect or the first to third possible implementation manner of the second aspect, in a third possible implementation manner of the second aspect, any of the TG, FD, SW, and RS is stacked on the PD.
According to a third aspect, a CMOS image sensor is provided, where the CMOS image sensor includes: a plurality of pixel circuits arranged in lattice manner, wherein each pixel circuit includes
a first floating diffusion (FD1) ；
a first reset gate (RS1) , a source of which is connected to a power source voltage, and a drain of which is connected to the FD1；
a first amplifier transistor (AMP1) , a gate of which is connected to the FD1, and a source of which is connected to the power source voltage；
a second floating diffusion (FD2) ；
a second reset gate (RS2) , a source of which is connected to the power source voltage, and a drain of which is connected to the FD2；
a second amplifier transistor (AMP2) , a gate of which is connected to the FD2, and a source of  which is connected to the power source voltage； and
first to eight pixel units,
wherein each pixel unit includes:
a diffusion (D1) ；
a photodiode (PD) , an anode of which is connected to a ground, and a cathode of which is connected to a source of a transfer gate (TG) and the D1；
the TG, the source of which is connected to the cathode of the PD, and a drain of which is connected to the FD1；
a capacitor (Ca) connected to the D1；
a switching transistor (SW) , a source of which is connected to the D1,
wherein the drains of the SWs of the sixth to eighth pixel units, the fifth pixel unit of the pixel circuit arranged at the lower side, the first to third pixel units of the pixel circuit arranged at the right side, and the fourth pixel unit of the pixel circuit arranged at the lower right are connected to said FD2,
the drains of the SWs of the first to third pixel units are connected to the FD2 of the pixel circuit arranged at the left side,
the drain of the SW of the fourth pixel unit is connected to the FD2 of the pixel circuit arranged at the upper left, and
the drain of the SW of the fifth pixel unit is connected to the FD2 of the pixel circuit arranged at the upper side.
In a first possible implementation manner of the third aspect, after the charge of the PD is cleared, the gate of the RS1 is ON during a predetermined period, and the gate of the SW is ON, and then, the gate of the TG and the gate of the RS2 is ON during a predetermined period.
With reference to the third aspect or the first possible implementation manner of the third aspect, in a first possible implementation manner of the third aspect, the CMOS image sensor further includes a second PD which extends from the inside to the back of the substrate, the TG extends from the surface of the substrate to the second PD, and charge moves from the second PD to the TG.
With reference to the third aspect or the first or second possible implementation manner of the third aspect, in a first possible implementation manner of the third aspect, any of the TG, FD, SW, and RS is stacked on the PD.
According to a fourth aspect, a CMOS image sensor is provided, where the CMOS image sensor includes:
a photodiode (PD) , an anode of which is connected to a ground, and a cathode of which is  connected to a source of a transfer gate (TG) ；
a floating diffusion (FD) ；
a capacitor (Ca) ；
the TG, the source of which is connected to the cathode of the PD, and a drain of which is connected to the FD；
a switching transistor (SW) , a source of which is connected to a power source voltage, and a drain of which is connected to a source of a reset gate (RS) and the Ca；
the RS, the source of which is connected to the drain of the SW and the Ca, and a drain of which is connected to the FD； and
an amplifier transistor (AMP) , a gate of which is connected to the FD, and a source of which is connected to the power source voltage,
wherein the CMOS image sensor further includes a second PD which extends from the inside to the back of the substrate, the TG extends from the surface of the substrate to the second PD, and charge moves from the second PD to the TG.
In a first possible implementation manner of the fourth aspect, any of the TG, FD, SW, and RS is stacked on the PD.
A CMOS image sensor is provided according to the various implementation manners to shrink the pixel size of a high dynamic range pixel.
BRIEF DESCRIPTION OF DRAWINGS
To describe the technical solutions in the embodiments of the present invention or in the prior art more clearly, the following briefly introduces the accompanying drawings required for describing the embodiments or the prior art. Apparently, the accompanying drawings in the following description show merely some embodiments of the present invention, and a person of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts.
FIG. 1 shows a circuit diagram of a pixel circuit of a general CMOS image sensor；
FIG. 2 shows a top view of the pixel circuit arranged on a surface of a silicon substrate；
FIG. 3 shows a pulse timing chart for the pixel circuit in Fig. 1；
FIG. 4 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along A-B in Fig. 2；
FIG. 5 shows a potential diagram according to the timing in Fig. 3；
FIG. 6 shows a pixel circuit of a high dynamic range CMOS image sensor in the prior art that enlarges the amount of signal charge；
FIG. 7 shows a top view of the pixel circuit arranged on a surface of a silicon substrate；
FIG. 8 shows a pulse timing chart for the pixel circuit in Fig. 6；
FIG. 9 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along A-B in Fig. 7；
FIG. 10 shows a potential diagram according to the timing in Fig. 8；
FIG. 11 shows a top view of a pixel circuit arranged on a surface of a silicon substrate according to the first embodiment of the present invention；
FIG. 12 shows a top view of a pixel circuit arranged on a surface of a silicon substrate according to the second embodiment of the present invention；
FIG. 13 shows a top view of a pixel circuit arranged on a surface of a silicon substrate according to the third embodiment of the present invention；
FIG. 14 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along C-D in Fig. 11；
FIG. 15 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along E-F in Fig. 13；
FIG. 16 shows a circuit diagram of an alternative solution；
FIG. 17 shows a top view of one pixel circuit arranged on a surface of a silicon substrate；
FIG. 18 shows a pulse timing chart for the pixel circuit in Fig. 16；
FIG. 19 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along G-H in Fig. 17； and
FIG. 20 shows a potential diagram according to the timing in Fig. 18.
DESCRIPTION OF EMBODIMENTS
The following clearly and completely describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. The described embodiments are merely some but not all of the embodiments of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
Fig. 11 shows a top view of a pixel circuit arranged on a surface of a silicon substrate according to the first embodiment of the present invention. Pixel transistors (AMP, SL, SW, and RS) are located in two rows. The length of the side of the area shown in Fig. 11 is about 0.7 times as that of the area shown in Fig. 7 in an actual measurement.
Referring to Fig. 6, an CMOS image sensor includes a PD, an anode of which is connected to a ground, and a cathode of which is connected to a source of a TG； an FD； a Ca； the TG, the source of which is connected to the cathode of the PD, and a drain of which is connected to the FD； an SW, a source of which is connected to a power source voltage, and a drain of which is connected to a source of an RS and the Ca； the RS, the source of which is connected to the drain of the SW and the Ca, and a drain of which is connected to the FD； an AMP, a gate of which is connected to the FD, a source of which is connected to the power source voltage, and a drain of which is connected to a source of an SL； and the SL, the source of which is connected to the drain of the AMP, and a drain of which is connected to a signal line. Referring to Fig. 11, the PD, the TG, and the FD are arranged in order in a first row on a substrate, the AMP and the SL are arranged in a second row on the substrate, and the SW and the RS are arranged in a third row on the substrate. In Fig. 11, the AMP, the SL, the SW, and the RS are located on relatively thick p-type area (the lower half area in Fig. 11) , and the PD, the TG, and the FD are surrounded by a relatively thin p-type area (the upper half area in Fig. 11) . The locations of the second row and the third row, the locations of the AMP and the SL, and the locations of the SW and the RS may be changed.
Fig. 12 shows a top view of a pixel circuit arranged on a surface of a silicon substrate according to the second embodiment of the present invention. Pixel transistors are arranged in crisscross.
Referring to Fig. 12, the PD, the TG, and the FD are arranged in order in a first row on a substrate in the oblique direction, the AMP and the SL are arranged in a second row on the substrate in the horizontal direction, and the SW and the RS are arranged in third row on the substrate in the vertical direction. In Fig. 12, the AMP, the SL, the SW, and the RS are located on relatively thick p-type area, and the PD, the TG, and the FD are surrounded by relatively thin p-type area. The locations of the second row and the third row, the locations of the AMP and the SL, and the locations of the SW and the RS may be changed.
Fig. 13 shows a top view of a pixel circuit arranged on a surface of a silicon substrate according to the third embodiment of the present invention. Fig. 15 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along E-F in Fig. 13. TG extends into the silicon substrate and signal charge from PD2 is transferred vertically (arrow in Fig. 15) to FD via TG. Fig. 14 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along C-D in Fig. 11. In Fig. 14, signal charge is transferred in the horizontal direction on the surface of the substrate (arrow in Fig. 14) and this requires large PD area on the surface. On the other hand, as shown in Figs. 13 and 15, the vertical TG reduces PD area on the surface. Any of TG, FD, SW, and RS may be stacked on PD.
In Fig. 14, most of signal charge transferred to FD is stored in PD region. The signal charge in PD2 is difficult to move to FD because PD2 is physically distant from FD. In Fig. 15, PD region is much smaller than that in Fig. 14 and can store much less signal charge. So, most of signal charge transferred to FD is stored in PD2 region. Charge transfer from PD2 to FD is improved by the vertically extended TG. Thus, in these embodiments, pixel size can be reduced. In actual measurements, the length of the side of the area shown in Fig. 13 is about 0.7 times as that of the area shown in Fig. 11, and the length of the side of the area shown in Fig. 13 is about 0.5 times as that of the area shown in Fig. 7.
Fig. 16 shows a circuit diagram of an alternative solution. Fig. 16 includes four pixel circuits connected each other. The upward connection relations of the upper two pixel circuits in Fig. 16 (not shown) are same as the upward connection relations of the lower two pixel circuits, and the downward connection relations of the lower two pixel circuits in Fig. 16 (not shown) are same as the downward connection relations of the upper two pixel circuits. Fig. 17 shows a top view of one pixel circuit arranged on a surface of a silicon substrate. A plurality of pixel circuits are arranged in lattice manner. In Fig. 17, the SWs at the upper left and the lower left of the FD at position C1 (position C in the vertical direction and position 1 in the horizontal direction) and the SW at the upper left of the FD at position E1 belong to the pixel circuit arranged at the left side. The SWs at the upper right and the lower right of the FD at position C3 and the SW at the upper right of the FD at position E3 belong to the pixel circuit arranged at the right side. The SW at the lower right of the FD at position E1 and the SW at the lower left of the FD at position E3 belong to the pixel circuit arranged at the lower side. The SW at the lower left of the FD at position E1 belongs to the pixel circuit at the lower left. The SW at the lower right of the FD at position E3 belongs to the pixel circuit arranged at the lower right. FD2 at position C1, C3, E1, and E3 are shared with adjacent pixel circuit. The FD2s at position A1 and A3, the SW at the lower right of the FD at position A1, and the SW at the lower left of the FD at position A3 are not shown in Fig. 17.
In Fig. 17, four PDs are connected to FD1 via TG and two FD1 are connected to AMP1. Additional capacitance Ca is connected to a diffusion (D1) between PD and SW. The D1 contains thick n-type impurity. Four ‘Ca’s are connected to FD2 via SW and two FD2 are connected to AMP2. Fig. 17 shows one pixel circuits, and the circuit diagram shown in Fig. 16 corresponds 2-by-2 pixel circuits.
A CMOS image sensor includes a plurality of pixel circuits arranged in lattice manner. Referring to Figs. 16 and 17, each pixel circuit includes a first floating diffusion (FD1) ； a first reset gate (RS1) , a source of which is connected to a power source voltage, and a drain of which is connected to the FD1； a first amplifier transistor (AMP1) , a gate of which is connected to the FD1,  a source of which is connected to the power source voltage, and a drain of which is connected to a source of a first selector transistor (SL1) ； the SL1, the source of which is connected to the drain of the AMP1, and a drain of which is connected to a first signal line； a second floating diffusion (FD2) ； a second reset gate (RS2) , a source of which is connected to the power source voltage, and a drain of which is connected to the FD2； a second amplifier transistor (AMP2) , a gate of which is connected to the FD2, a source of which is connected to the power source voltage, and a drain of which is connected to a source of a second selector transistor (SL2) ； the SL2, the source of which is connected to the drain of the AMP2, and a drain of which is connected to a second signal line； and first to eight pixel units.
Each pixel unit includes: a diffusion (D1) ； a PD, an anode of which is connected to a ground, and a cathode of which is connected to a source of a TG and the D1； the TG, the source of which is connected to the cathode of the PD and the D1, and a drain of which is connected to the FD1； a Ca connected to the D1； an SW, a source of which is connected to the D1.
Assuming that eight pixel units in each pixel circuit shown in Fig. 16 are first to eighth pixel units from left to right, the first to fourth pixel units in each pixel circuit in Fig. 16 correspond to left four pixel units from bottom to top in Fig. 17, and the fifth to eighth pixel units in each pixel circuit in Fig. 16 correspond to right four pixel units from top to bottom in Fig. 17.
The drains of the SWs of the sixth to eighth pixel units of a predetermined pixel circuit, the fifth pixel unit of the pixel circuit arranged at the lower side, the first to third pixel units of the pixel circuit arranged at the right side, and the fourth pixel unit of the pixel circuit arranged at the lower right are connected to the FD2 of the predetermined pixel circuit, the drains of the SWs of the first to third pixel units of the predetermined pixel circuit are connected to the FD2 of the pixel circuit arranged at the left side, the drain of the SW of the fourth pixel unit of the predetermined pixel circuit is connected to the FD2 of the pixel circuit arranged at the upper left, and the drain of the SW of the fifth pixel unit of the predetermined pixel circuit is connected to the FD2 of the pixel circuit arranged at the upper side.
In Figs. 16 and 17, each pixel circuit has eight pixel units. However, the number of the pixel units is not limited to eight.
Fig. 18 shows a pulse timing chart for the pixel circuit in Fig. 16, Fig. 19 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along G-H in Fig. 17, and Fig. 20 shows a potential diagram according to the timing in Fig. 18. Referring to Figs. 18 to 20, at t1 (the falling edge of the first pulse of the TG) , charge in the PD is cleared and signal integration starts. Tint denotes integration period. PDx is potential barrier between PD and D1. During t1 and t2, excess charge over PDx overflow into D1. Around t2, signal charge is stored in the PD and Ca. The  overflow charge at the PD flows directly from PD to Ca. At t2’ , FD1 is set to a baseline voltage and D1 connects to FD2 by opening the SW. At t3, both signals of the FD1 and FD2 are AD converted simultaneously as a baseline signal of HG (0_HG) and a signal of the LG (Signal_LG) , respectively. Then the signal in the PD is transferred to the FD1 and FD2 is set to a baseline voltage level. At t4, both signals of the FD1 and FD2 are AD converted simultaneously as a signal of the HG (Signal_HG) and a baseline signal of LG (0_LG) , respectively. In this embodiment, a circuit including the AMP, SL and RS is equipped per four PDs. A number of pixel transistors is reduced and therefore pixel size can be reduced. Furthermore, signals of the HG and LG output are in parallel, so readout speed is faster.
What is disclosed above is merely exemplary embodiments of the present invention, and certainly is not intended to limit the scope of protection of the present invention. A person of ordinary skill in the art may understand that all or some of the processes that implement the foregoing embodiments and equivalent modifications made in accordance with the claims of the present invention shall fall within the scope of the present invention.

Claims (16)

  1. A complementary metal oxide semiconductor (CMOS) image sensor, comprising:
    a photodiode (PD) , an anode of which is connected to a ground, and a cathode of which is connected to a source of a transfer gate (TG) ；
    a floating diffusion (FD) ；
    a capacitor (Ca) ；
    the TG, the source of which is connected to the cathode of the PD, and a drain of which is connected to the FD；
    a switching transistor (SW) , a source of which is connected to a power source voltage, and a drain of which is connected to a source of a reset gate (RS) and the Ca；
    the RS, the source of which is connected to the drain of the SW and the Ca, and a drain of which is connected to the FD； and
    an amplifier transistor (AMP) , a gate of which is connected to the FD, and a source of which is connected to the power source voltage,
    wherein the PD is arranged in a first row on a substrate,
    any of the AMP, SW, and RS is arranged in a second row on the substrate, and
    the rest of the AMP, SW, and RS are arranged in a third row on the substrate.
  2. The CMOS image sensor according to claim 1, further comprising a second PD which extends from the inside to the back of the substrate, the TG extends from the surface of the substrate to the second PD, and charge moves from the second PD to the TG.
  3. The CMOS image sensor according to claim 1, wherein the second row and the third row are orthogonal.
  4. The CMOS image sensor according to claim 3, further comprising a second PD which extends from the inside to the back of the substrate, the TG extends from the surface of the substrate to the second PD, and charge moves from the second PD to the TG.
  5. The CMOS image sensor according to any one of claims 1 to 4, wherein any of the TG, FD, SW, and RS is stacked on the PD.
  6. A complementary metal oxide semiconductor (CMOS) image sensor, comprising a plurality of pixel circuits arranged in lattice manner, wherein each pixel circuit comprises
    a first floating diffusion (FD1) ；
    a first reset gate (RS1) , a source of which is connected to a power source voltage, and a drain of which is connected to the FD1；
    a first amplifier transistor (AMP1) , a gate of which is connected to the FD1, and a source of which is connected to the power source voltage；
    a second floating diffusion (FD2) ；
    a second reset gate (RS2) , a source of which is connected to the power source voltage, and a drain of which is connected to the FD2；
    a second amplifier transistor (AMP2) , a gate of which is connected to the FD2, and a source of which is connected to the power source voltage； and
    pixel units,
    wherein each pixel unit comprises:
    a diffusion (D1) ；
    a photodiode (PD) , an anode of which is connected to a ground, and a cathode of which is connected to a source of a transfer gate (TG) and the D1；
    a capacitor (Ca) connected to the D1；
    a switching transistor (SW) , a source of which is connected to the D1.
  7. The CMOS image sensor according to claim 6, comprising a potential region between the D1 and the PD, wherein the potential of the potential region is different from the potential of the region for accumulating signal charge of the PD, and the potential region is a barrier against transfer of signal charge.
  8. The CMOS image sensor according to claim 6 or 7, wherein after the charge of the PD is cleared, the gate of the RS1 is ON during a predetermined period, and the gate of the SW is ON, and then, the gate of the TG and the gate of the RS2 is ON during a predetermined period.
  9. The CMOS image sensor according to any one of claims 6 to 8, further comprising a second PD which extends from the inside to the back of the substrate, the TG extends from the surface of the substrate to the second PD, and charge moves from the second PD to the TG.
  10. The CMOS image sensor according to any one of claims 6 to 9, wherein any of the TG, FD, SW, and RS is stacked on the PD.
  11. A complementary metal oxide semiconductor (CMOS) image sensor, comprising a plurality of pixel circuits arranged in lattice manner, wherein each pixel circuit comprises
    a first floating diffusion (FD1) ；
    a first reset gate (RS1) , a source of which is connected to a power source voltage, and a drain of which is connected to the FD1；
    a first amplifier transistor (AMP1) , a gate of which is connected to the FD1, and a source of which is connected to the power source voltage；
    a second floating diffusion (FD2) ；
    a second reset gate (RS2) , a source of which is connected to the power source voltage, and a drain of which is connected to the FD2；
    a second amplifier transistor (AMP2) , a gate of which is connected to the FD2, and a source of which is connected to the power source voltage； and
    first to eight pixel units,
    wherein each pixel unit comprises:
    a diffusion (D1) ；
    a photodiode (PD) , an anode of which is connected to a ground, and a cathode of which is connected to a source of a transfer gate (TG) and the D1；
    the TG, the source of which is connected to the cathode of the PD, and a drain of which is connected to the FD1；
    a capacitor (Ca) connected to the D1；
    a switching transistor (SW) , a source of which is connected to the D1,
    wherein the drains of the SWs of the sixth to eighth pixel units, the fifth pixel unit of the pixel circuit arranged at the lower side, the first to third pixel units of the pixel circuit arranged at the right side, and the fourth pixel unit of the pixel circuit arranged at the lower right are connected to said FD2,
    the drains of the SWs of the first to third pixel units are connected to the FD2 of the pixel circuit arranged at the left side,
    the drain of the SW of the fourth pixel unit is connected to the FD2 of the pixel circuit arranged at the upper left, and
    the drain of the SW of the fifth pixel unit is connected to the FD2 of the pixel circuit arranged at the upper side.
  12. The CMOS image sensor according to claim 11, wherein after the charge of the PD is cleared, the gate of the RS1 is ON during a predetermined period, and the gate of the SW is ON, and then, the gate of the TG and the gate of the RS2 is ON during a predetermined period.
  13. The CMOS image sensor according to claim 11 or 12, further comprising a second PD which extends from the inside to the back of the substrate, the TG extends from the surface of the substrate to the second PD, and charge moves from the second PD to the TG.
  14. The CMOS image sensor according to any one of claims 11 to 13, wherein any of the TG, FD, SW, and RS is stacked on the PD.
  15. A complementary metal oxide semiconductor (CMOS) image sensor, comprising:
    a photodiode (PD) , an anode of which is connected to a ground, and a cathode of which is connected to a source of a transfer gate (TG) ；
    a floating diffusion (FD) ；
    a capacitor (Ca) ；
    the TG, the source of which is connected to the cathode of the PD, and a drain of which is connected to the FD；
    a switching transistor (SW) , a source of which is connected to a power source voltage, and a drain of which is connected to a source of a reset gate (RS) and the Ca；
    the RS, the source of which is connected to the drain of the SW and the Ca, and a drain of which is connected to the FD； and
    an amplifier transistor (AMP) , a gate of which is connected to the FD, and a source of which is connected to the power source voltage,
    wherein the CMOS image sensor further comprises a second PD which extends from the inside to the back of the substrate, the TG extends from the surface of the substrate to the second PD, and charge moves from the second PD to the TG.
  16. The CMOS image sensor according to claim 15, wherein any of the TG, FD, SW, and RS is stacked on the PD.
PCT/CN2017/076510 2017-03-13 2017-03-13 Cmos image sensor WO2018165832A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201780085024.3A CN110291782B (en) 2017-03-13 2017-03-13 CMOS image sensor
PCT/CN2017/076510 WO2018165832A1 (en) 2017-03-13 2017-03-13 Cmos image sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2017/076510 WO2018165832A1 (en) 2017-03-13 2017-03-13 Cmos image sensor

Publications (1)

Publication Number Publication Date
WO2018165832A1 true WO2018165832A1 (en) 2018-09-20

Family

ID=63521822

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/076510 WO2018165832A1 (en) 2017-03-13 2017-03-13 Cmos image sensor

Country Status (2)

Country Link
CN (1) CN110291782B (en)
WO (1) WO2018165832A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060203114A1 (en) * 2005-03-08 2006-09-14 Eastman Kodak Company Three-transistor CMOS active pixel
CN101444085A (en) * 2006-05-11 2009-05-27 广津总吉 Semiconductor image sensing device
CN101729805A (en) * 2008-10-22 2010-06-09 索尼株式会社 Solid state image sensor, method for driving a solid state image sensor, imaging apparatus, and electronic device
CN101753866A (en) * 2005-06-02 2010-06-23 索尼株式会社 Semiconductor image sensor module and method for manufacturing same
CN102265605A (en) * 2008-12-26 2011-11-30 广津和子 Solid-state image pickup element and method for controlling same
US20120175499A1 (en) * 2008-04-07 2012-07-12 Cmosis Nv Pixel array with global shutter

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3794637B2 (en) * 2003-03-07 2006-07-05 松下電器産業株式会社 Solid-state imaging device
EP1557886A3 (en) * 2004-01-26 2006-06-07 Matsushita Electric Industrial Co., Ltd. Solid-state imaging device and camera
US9229096B2 (en) * 2011-07-27 2016-01-05 Semiconductor Components Industries, Llc Time-of-flight imaging systems
CN103928486B (en) * 2014-05-08 2017-02-15 格科微电子（上海）有限公司 Image sensor and forming method thereof
TWI696278B (en) * 2015-03-31 2020-06-11 日商新力股份有限公司 Image sensor, camera device and electronic device
KR20160126523A (en) * 2015-04-24 2016-11-02 에스케이하이닉스 주식회사 Ramp Signal Generator, and CMOS Image Sensor Using That

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060203114A1 (en) * 2005-03-08 2006-09-14 Eastman Kodak Company Three-transistor CMOS active pixel
CN101753866A (en) * 2005-06-02 2010-06-23 索尼株式会社 Semiconductor image sensor module and method for manufacturing same
CN101444085A (en) * 2006-05-11 2009-05-27 广津总吉 Semiconductor image sensing device
US20120175499A1 (en) * 2008-04-07 2012-07-12 Cmosis Nv Pixel array with global shutter
CN101729805A (en) * 2008-10-22 2010-06-09 索尼株式会社 Solid state image sensor, method for driving a solid state image sensor, imaging apparatus, and electronic device
CN102265605A (en) * 2008-12-26 2011-11-30 广津和子 Solid-state image pickup element and method for controlling same

Also Published As

Publication number Publication date
CN110291782B (en) 2020-09-29
CN110291782A (en) 2019-09-27

Similar Documents

Publication Publication Date Title
US10084008B2 (en) Solid-state imaging device
US9602750B2 (en) Image sensor pixels having built-in variable gain feedback amplifier circuitry
US8471310B2 (en) Image sensor pixels with back-gate-modulated vertical transistor
US9293503B2 (en) Solid-state imaging device, method for driving the same, method for manufacturing the same, and electronic device
US20140061436A1 (en) Solid state imaging device
JP5959829B2 (en) Solid-state imaging device
US11082652B2 (en) Image sensors, image detecting systems including the image sensors, and methods of operating the image sensors
US20180261643A1 (en) Solid-state image sensor and electronic device
JP2016219849A (en) Solid-state imaging device
KR20160001918U (en) Global shutter image sensor pixels having improved shutter efficiency
US9627431B2 (en) Solid-state imaging device
US20160148960A1 (en) Solid-state imaging device
US10741600B2 (en) Imaging device including semiconductor substrate and pixel
US11356625B2 (en) Semiconductor structure and operating method for improving charge transfer of image sensor device
US8653566B2 (en) Solid-state imaging device
US20150123173A1 (en) 3d stacked image sensor with pmos components
WO2018165832A1 (en) Cmos image sensor
US20150122971A1 (en) 3d stacked image sensor
US20240194702A1 (en) Photodetection device and electronic device
US11652117B2 (en) Image sensing device
US8587041B2 (en) Solid-state imaging device and method of manufacturing the same
WO2018176490A1 (en) Cmos image sensor with xy address exposure control
JP2020080377A (en) Solid-state imaging device
US20240321923A1 (en) Image sensor
US20230420475A1 (en) Photoelectric conversion device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17900648

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17900648

Country of ref document: EP

Kind code of ref document: A1