WO2018165296A1 - Methods for wet metal seed deposition for bottom up gapfill of features - Google Patents

Methods for wet metal seed deposition for bottom up gapfill of features Download PDF

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Publication number
WO2018165296A1
WO2018165296A1 PCT/US2018/021338 US2018021338W WO2018165296A1 WO 2018165296 A1 WO2018165296 A1 WO 2018165296A1 US 2018021338 W US2018021338 W US 2018021338W WO 2018165296 A1 WO2018165296 A1 WO 2018165296A1
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WIPO (PCT)
Prior art keywords
features
metal
substrate
metal precursor
dilution liquid
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PCT/US2018/021338
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French (fr)
Inventor
Samantha Tan
Boris VOLOSSKIY
Taeseung Kim
Praveen Nalla
Novy Tjokro
Artur Kolics
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Lam Research Corp
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Lam Research Corp
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Priority to CN201880016403.1A priority Critical patent/CN110383458B/en
Priority to KR1020197028986A priority patent/KR102559156B1/en
Publication of WO2018165296A1 publication Critical patent/WO2018165296A1/en
Anticipated expiration legal-status Critical
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/044Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroless plating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/038Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/052Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein
    • H10W20/0526Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein by thermal treatment thereof
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/055Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/098Manufacture or treatment of dielectric parts thereof by filling between adjacent conductive parts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44Conductive materials thereof
    • H10W20/4403Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4437Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal

Definitions

  • the present disclosure relates to substrate processing methods, and more particularly to substrate processing methods including wet metal seed deposition at bottoms of features of a substrate followed by bottom up gapfill of the features.
  • Substrates such as semiconductor wafers are produced by depositing, etching and patterning film layers.
  • Deposition processes include physical vapor deposition (PVD), chemical vapor deposition (CVD) and atomic layer deposition (ALD).
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • a seed layer is deposited at bottoms of features such as trenches or vias.
  • a method of depositing a metal seed for performing bottom-up gapfill of features of a substrate includes providing a substrate including a plurality of features; flowing a dilute metal precursor solution into the features.
  • the dilute metal precursor solution includes a metal precursor and a dilution liquid.
  • the method includes evaporating the dilution liquid to locate the metal precursor at bottoms of the plurality of features; exposing the substrate to a plasma treatment to reduce the metal precursor to at least one of a metal or a metal alloy and to form a seed layer; performing a heat treatment on the substrate; and using a selective gapfill process to fill the features with a transition metal in contact with the seed layer.
  • the substrate includes a liner layer and the dilute metal precursor solution is applied to the liner layer.
  • the liner layer is made of a material selected from a group consisting of titanium nitride (TiN), tungsten carbonitride (WCN), and tantalum nitride (TaN).
  • the liner layer is made of a material selected from a group consisting of silicon dioxide, a metal, or a dielectric.
  • the transition metal is selected from a group consisting of nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), ruthenium (Ru), iridium (Ir), platinum (Pt), palladium (Pd) and tungsten (W).
  • the at least one of the metal or the metal alloy is selected to catalytically react with the transition metal but not the liner layer.
  • the selective gapfill process includes electroless deposition.
  • the dilution liquid comprises at least one of a carrier liquid and a solvent.
  • the dilution liquid is water-free.
  • the dilution liquid comprises a liquid selected from a group consisting of alcohol, ether, ester, perflouro-ether.
  • the dilution liquid comprises a liquid selected from a group consisting isopropyl alcohol (IPA) and ethyl alcohol (EtOH).
  • the features have openings having a width that is less than or equal to 10 nm.
  • the features have openings having a width in a range from 7 to 9 nm.
  • the features have openings having a width in a range from 4 to 7 nm.
  • the seed layer has a thickness in a range from 2-4 nm.
  • the heat treatment comprises annealing at a temperature in a range from 200°C to 400°C.
  • the heat treatment comprises annealing at a temperature in a range from 250°C to 350°C.
  • evaporating the dilution liquid includes exposing the substrate to a gradient dry process.
  • the dilute metal precursor solution is at least one of deposited or condensed in the plurality of features using by capillary action.
  • FIG. 1 is a side cross-sectional view of an example of a substrate including features such as trenches or vias according to the present disclosure
  • FIG. 2 is a side cross-sectional view of an example of the substrate of FIG. 1 with a liner layer according to the present disclosure
  • FIG. 3 is a side cross-sectional view of an example of the substrate of FIG. 2 and a dilute metal precursor solution at least partially filling the features according to the present disclosure
  • FIG. 4 is a side cross-sectional view of an example of the substrate of FIG. 3 after drying according to the present disclosure
  • FIG. 5 is a side cross-sectional view of an example of the substrate of FIG. 3 after exposure to plasma according to the present disclosure
  • FIG. 6 is a side cross-sectional view of an example of the substrate of FIG. 3 after bottom-up, selective gapfill of features according to the present disclosure.
  • FIG. 7 is an example of an example of a flowchart for bottom up gapfill of features according to the present disclosure.
  • reference numbers may be reused to identify similar and/or identical elements.
  • Deposition methods described herein are used to deposit a metal seed layer at bottoms of features such as trenches or vias for subsequent selective metal gapfill.
  • the substrate includes a liner or barrier layer.
  • selective gapfill refers to deposition of metal on some exposed materials (such as on a metal seed layer) and not on other exposed layers (such as a liner layer or feature sidewalls).
  • the metal seed layer has a thickness in a range from of 2-4 nm localized at the bottoms of the features.
  • the metal seed layer is used to grow the transition metal by electroless deposition (ELD) or other selective gapfill processes can be used.
  • ELD electroless deposition
  • the method includes condensing or flowing a dilute metal precursor solution over the substrate to fill the features.
  • the features are filled by capillary action of liquids.
  • the dilute metal precursor solution includes a metal precursor and a liquid carrier or solvent. Once the metal precursor solution is located in the features, the solvent or carrier liquid is removed by evaporation to allow the metal precursor to concentrate and deposit only at the bottoms of the features.
  • the substrate is exposed to plasma treatment in a plasma chamber to reduce the metal precursor to a metal or metal alloy and to form a seed layer.
  • a heat treatment step may be used to improve precursor adhesion to an underlying barrier layer.
  • the heat treatment step includes annealing the substrate at a temperature in a range between 200° C and 400° C.
  • the heat treatment step includes annealing the substrate at a temperature in a range between 250° C and 350° C.
  • the heat treatment step is performed in a reducing atmosphere including a reducing gas mixture.
  • the reducing gas mixture includes molecular hydrogen (H2), molecular hydrogen and molecular nitrogen (H2/N2), or molecular hydrogen and ammonia (H2/NH3) to convert the metal precursor to the metallic form.
  • the substrate with the activated metal/metal alloy seed layer located at the bottom of the features is transported to an electroless deposition (ELD) tool for a selective deposition process to achieve bottom-up gapfill in the features.
  • ELD electroless deposition
  • the ELD process is selective since only the reduced precursor at the bottoms of the features is catalytically active for the plating process.
  • selective bottom-up fill can be performed using electrochemical plating (ECP), chemical vapor deposition (CVD) or other process.
  • the deposition method according to the present disclosure can be used for transition metals such as nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), ruthenium (Ru), iridium (Ir), platinum (Pt), palladium (Pd) and tungsten (W).
  • the deposition method is used for metal gapfill in contact holes and middle of line (MOL) and BEOL trenches/vias.
  • the liner layer includes titanium/titanium nitride (TiN), tungsten carbonitride (WCN), or tantalum/tantalum nitride (TaN).
  • the deposition process can be used with oxide sidewalls or with any other metal or dielectric barrier materials.
  • the solvent or carrier liquid that is selected will depend on the metal precursor that is used.
  • the solvent or carrier liquid for the metal precursor is water-free to minimize formation of metal oxide during the subsequent processing.
  • the solvent or carrier liquid has low surface tension and high solubility for the metal precursors, such as alcohols (e.g. isopropyl alcohol (IPA), ethyl alcohol (EtOH)), ethers, esters, perflouro-ethers, etc.
  • the metal precursor comprises a stable salt (inorganic or organometallic) at room temperature.
  • the metal precursor does not decompose or sublime when exposed to ambient temperatures and pressures.
  • the metal precursor is soluble in low boiling point organic solvents ( ⁇ 80°C to 90°C).
  • the solvents have a low boiling point (e.g. less than 100°C), low surface tension to enable capillary filling of narrow trenches and holes (e.g. less than 10 nm in width, in a range from 7-9 nm or in a range from 4-7 nm, etc.) and no water or low water content.
  • a concentration of salt in the solvent does not exceed a solubility constant (Ksp) of salt in the final 10-20% of volume in the trench to prevent early precipitation onto sidewalls.
  • Ksp solubility constant
  • a gradient drying process is used to concentrate the organometallic or salt at bottoms of the features without leaving metallic deposits on the sidewalls.
  • the gradient dry process includes ramping or increasing temperature at one or more predetermined rates over a predetermined period.
  • a reduction process that is used to convert organometallic or salt to metal does not damage a liner/barrier/substrate material.
  • the substrate 50 is shown to include features 52 such as trenches or vias.
  • the features 52 are defined in a layer 56 that is arranged on one or more underlying layers 54.
  • the layer 56 may be made of silicon dioxide (Si02) or another suitable film material.
  • the features 52 have a width that is less than or equal to 10 nm.
  • a liner layer 60 is deposited on the layer 56.
  • the liner layer 60 may be deposited on the layer 56 using any suitable approach including chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced CVD (PECVD), plasma enhanced ALD (PEALD), or any other suitable process.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PECVD plasma enhanced CVD
  • PEALD plasma enhanced ALD
  • a dilute metal precursor solution 64 is used to fill the features 52.
  • the dilute metal precursor solution 64 includes a metal precursor that is mixed with a solvent or carrier liquid.
  • the metal precursor includes a metal precursor that is used to form a transition metal.
  • the dilute metal precursor solution 64 fills the features 52 by capillary action.
  • FIGs. 4-6 additional processing of the substrate 50 is performed.
  • the substrate 50 is subjected to heat or another process such as vacuum to evaporate the solvent or carrier liquid from the dilute metal precursor solution 64. In some examples, a gradient dry process is used.
  • the gradient dry process involves slowly ramping up a temperature of the substrate to cause evaporation of the dilution liquid and to slowly lower a meniscus and reduce metal buildup on sidewalls of the features.
  • IPA isopropyl alcohol
  • the temperature is slowly ramped up from room temperature to 60°C at a rate of 1 -2oC/min to concentrate the metal precursor at the bottom of the feature.
  • the metal precursor 68 remains at a bottom of the features.
  • the substrate 50 is subjected to a reducing plasma process to reduce the metal precursor 68 to a metal or metal alloy and form a seed layer 70.
  • the reducing plasma process uses molecular hydrogen gas.
  • the plasma process includes a capacitively coupled plasma (CCP) process or an inductively coupled plasma (ICP) process.
  • the reduction process can moved to an annealing chamber with H2/N2 or NH3/H2 at 200°C to 400°C for a predetermined period. In some examples, the predetermined period is in a range from 2-20 minutes to completely convert the metal precursor to metallic form.
  • the seed layer has a thickness in a range from 2 to 4 nm.
  • electroless deposition (ELD) or another selective gapfill process is performed to fill the features with a transition metal 72.
  • a method 100 for forming a seed layer and bottom-up selective gapfill of features with a transition metal is shown.
  • a substrate is provided that includes features such as trenches or vias.
  • the substrate includes a liner layer.
  • the features of the substrate are filled with a dilute metal precursor solution.
  • the carrier liquid or solvent is evaporated.
  • a gradient dry process is used.
  • the substrate is exposed to plasma to reduce the metal precursor to a metal or metal alloy and form a seed layer.
  • an optional heat treatment such as annealing may be performed to improve adhesion.
  • electroless deposition ELD
  • an electroless deposition method described in U.S. Patent No. 9,287, 183 is used to fill the features, although other electroless deposition methods may be used.
  • an electroless deposition tool shown and described in U.S. Patent No. 8,906,446 or U.S. Patent No. 6,913,651 is used, although other electroless deposition tools may be used.
  • features such as trenches are defined in a silicon dioxide (Si02) layer.
  • a tungsten carbonitride (WCN) liner layer is deposited.
  • a cobalt salt precursor such as cobalt (II) chloride (CoCI2) is diluted in isopropyl alcohol (IPA) and applied in the features by capillary action.
  • IPA isopropyl alcohol
  • the substrate is gradient dried from top surfaces thereof such that the IPA evaporates and the cobalt salt precursor condenses at bottoms of the features.
  • the substrate is exposed to a plasma process using plasma gas including molecular hydrogen (H2). The plasma reduces the cobalt salt precursor to cobalt metal and forms a seed layer in the following reaction:

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Abstract

A method of depositing a metal seed for performing bottom-up gapfill of features of a substrate includes providing a substrate including a plurality of features; flowing a dilute metal precursor solution into the features, wherein the dilute metal precursor solution includes a metal precursor and a dilution liquid; evaporating the dilution liquid to locate the metal precursor at bottoms of the plurality of features; exposing the substrate to a plasma treatment to reduce the metal precursor to at least one of a metal or a metal alloy and to form a seed layer; performing a heat treatment on the substrate; and using a selective gapfill process to fill the features with a transition metal in contact with the seed layer.

Description

METHODS FOR WET METAL SEED DEPOSITION FOR BOTTOM UP GAPFILL OF FEATURES
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority to U.S. Utility Application No. 15/453,098, filed on March 8, 2017. The entire disclosure of the above application is incorporated herein by reference.
FIELD
[0002] The present disclosure relates to substrate processing methods, and more particularly to substrate processing methods including wet metal seed deposition at bottoms of features of a substrate followed by bottom up gapfill of the features.
BACKGROUND
[0003] The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. [0004] Substrates such as semiconductor wafers are produced by depositing, etching and patterning film layers. Deposition processes include physical vapor deposition (PVD), chemical vapor deposition (CVD) and atomic layer deposition (ALD). In some circumstances, a seed layer is deposited at bottoms of features such as trenches or vias. However, none of these deposition processes is able to selectively deposit material on bottom surfaces of trenches or vias. These deposition processes can only perform conformal or non-selective seed deposition. Other disadvantages of these deposition processes include pinch-off at openings of the features and seams/roughness resulting from sidewall growth. SUMMARY
[0005] A method of depositing a metal seed for performing bottom-up gapfill of features of a substrate includes providing a substrate including a plurality of features; flowing a dilute metal precursor solution into the features. The dilute metal precursor solution includes a metal precursor and a dilution liquid. The method includes evaporating the dilution liquid to locate the metal precursor at bottoms of the plurality of features; exposing the substrate to a plasma treatment to reduce the metal precursor to at least one of a metal or a metal alloy and to form a seed layer; performing a heat treatment on the substrate; and using a selective gapfill process to fill the features with a transition metal in contact with the seed layer.
[0006] In other features, the substrate includes a liner layer and the dilute metal precursor solution is applied to the liner layer. The liner layer is made of a material selected from a group consisting of titanium nitride (TiN), tungsten carbonitride (WCN), and tantalum nitride (TaN). The liner layer is made of a material selected from a group consisting of silicon dioxide, a metal, or a dielectric.
[0007] In other features, the transition metal is selected from a group consisting of nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), ruthenium (Ru), iridium (Ir), platinum (Pt), palladium (Pd) and tungsten (W). The at least one of the metal or the metal alloy is selected to catalytically react with the transition metal but not the liner layer. The selective gapfill process includes electroless deposition.
[0008] In other features, the dilution liquid comprises at least one of a carrier liquid and a solvent. The dilution liquid is water-free. The dilution liquid comprises a liquid selected from a group consisting of alcohol, ether, ester, perflouro-ether. The dilution liquid comprises a liquid selected from a group consisting isopropyl alcohol (IPA) and ethyl alcohol (EtOH).
[0009] In other features, the features have openings having a width that is less than or equal to 10 nm. The features have openings having a width in a range from 7 to 9 nm. The features have openings having a width in a range from 4 to 7 nm. The seed layer has a thickness in a range from 2-4 nm. The heat treatment comprises annealing at a temperature in a range from 200°C to 400°C. The heat treatment comprises annealing at a temperature in a range from 250°C to 350°C.
[0010] In other features, evaporating the dilution liquid includes exposing the substrate to a gradient dry process. The dilute metal precursor solution is at least one of deposited or condensed in the plurality of features using by capillary action.
[0011] Further areas of applicability of the present disclosure will become apparent from the detailed description, the claims and the drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:
[0013] FIG. 1 is a side cross-sectional view of an example of a substrate including features such as trenches or vias according to the present disclosure; [0014] FIG. 2 is a side cross-sectional view of an example of the substrate of FIG. 1 with a liner layer according to the present disclosure;
[0015] FIG. 3 is a side cross-sectional view of an example of the substrate of FIG. 2 and a dilute metal precursor solution at least partially filling the features according to the present disclosure; [0016] FIG. 4 is a side cross-sectional view of an example of the substrate of FIG. 3 after drying according to the present disclosure;
[0017] FIG. 5 is a side cross-sectional view of an example of the substrate of FIG. 3 after exposure to plasma according to the present disclosure;
[0018] FIG. 6 is a side cross-sectional view of an example of the substrate of FIG. 3 after bottom-up, selective gapfill of features according to the present disclosure; and
[0019] FIG. 7 is an example of an example of a flowchart for bottom up gapfill of features according to the present disclosure. [0020] In the drawings, reference numbers may be reused to identify similar and/or identical elements.
DETAILED DESCRIPTION
[0021] Deposition methods described herein are used to deposit a metal seed layer at bottoms of features such as trenches or vias for subsequent selective metal gapfill. In some examples, the substrate includes a liner or barrier layer. As used herein, the term selective gapfill refers to deposition of metal on some exposed materials (such as on a metal seed layer) and not on other exposed layers (such as a liner layer or feature sidewalls). In some examples, the metal seed layer has a thickness in a range from of 2-4 nm localized at the bottoms of the features. In some examples, the metal seed layer is used to grow the transition metal by electroless deposition (ELD) or other selective gapfill processes can be used.
[0022] The method includes condensing or flowing a dilute metal precursor solution over the substrate to fill the features. In some examples, the features are filled by capillary action of liquids. The dilute metal precursor solution includes a metal precursor and a liquid carrier or solvent. Once the metal precursor solution is located in the features, the solvent or carrier liquid is removed by evaporation to allow the metal precursor to concentrate and deposit only at the bottoms of the features.
[0023] The substrate is exposed to plasma treatment in a plasma chamber to reduce the metal precursor to a metal or metal alloy and to form a seed layer. A heat treatment step may be used to improve precursor adhesion to an underlying barrier layer. In some examples, the heat treatment step includes annealing the substrate at a temperature in a range between 200° C and 400° C. In some examples, the heat treatment step includes annealing the substrate at a temperature in a range between 250° C and 350° C. In some examples, the heat treatment step is performed in a reducing atmosphere including a reducing gas mixture. In some examples, the reducing gas mixture includes molecular hydrogen (H2), molecular hydrogen and molecular nitrogen (H2/N2), or molecular hydrogen and ammonia (H2/NH3) to convert the metal precursor to the metallic form.
[0024] In some examples, the substrate with the activated metal/metal alloy seed layer located at the bottom of the features is transported to an electroless deposition (ELD) tool for a selective deposition process to achieve bottom-up gapfill in the features. The ELD process is selective since only the reduced precursor at the bottoms of the features is catalytically active for the plating process. In some examples, selective bottom-up fill can be performed using electrochemical plating (ECP), chemical vapor deposition (CVD) or other process. [0025] The deposition method according to the present disclosure can be used for transition metals such as nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), ruthenium (Ru), iridium (Ir), platinum (Pt), palladium (Pd) and tungsten (W). In some examples, the deposition method is used for metal gapfill in contact holes and middle of line (MOL) and BEOL trenches/vias. In some examples, the liner layer includes titanium/titanium nitride (TiN), tungsten carbonitride (WCN), or tantalum/tantalum nitride (TaN). Alternately, the deposition process can be used with oxide sidewalls or with any other metal or dielectric barrier materials.
[0026] The solvent or carrier liquid that is selected will depend on the metal precursor that is used. In some examples, the solvent or carrier liquid for the metal precursor is water-free to minimize formation of metal oxide during the subsequent processing. In some examples, the solvent or carrier liquid has low surface tension and high solubility for the metal precursors, such as alcohols (e.g. isopropyl alcohol (IPA), ethyl alcohol (EtOH)), ethers, esters, perflouro-ethers, etc.
[0027] In some examples, the metal precursor comprises a stable salt (inorganic or organometallic) at room temperature. In some examples, the metal precursor does not decompose or sublime when exposed to ambient temperatures and pressures. In some examples, the metal precursor is soluble in low boiling point organic solvents (< 80°C to 90°C). In some examples, the solvents have a low boiling point (e.g. less than 100°C), low surface tension to enable capillary filling of narrow trenches and holes (e.g. less than 10 nm in width, in a range from 7-9 nm or in a range from 4-7 nm, etc.) and no water or low water content. In some examples, a concentration of salt in the solvent does not exceed a solubility constant (Ksp) of salt in the final 10-20% of volume in the trench to prevent early precipitation onto sidewalls.
[0028] In some examples, a gradient drying process is used to concentrate the organometallic or salt at bottoms of the features without leaving metallic deposits on the sidewalls. As used herein, the gradient dry process includes ramping or increasing temperature at one or more predetermined rates over a predetermined period. In some examples, a reduction process that is used to convert organometallic or salt to metal does not damage a liner/barrier/substrate material.
[0029] Referring now to FIGs. 1 -3, processing of a substrate 50 is shown. In FIG. 1 , the substrate 50 is shown to include features 52 such as trenches or vias. The features 52 are defined in a layer 56 that is arranged on one or more underlying layers 54. In some examples, the layer 56 may be made of silicon dioxide (Si02) or another suitable film material. In some examples, the features 52 have a width that is less than or equal to 10 nm. [0030] In FIG. 2, a liner layer 60 is deposited on the layer 56. The liner layer 60 may be deposited on the layer 56 using any suitable approach including chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced CVD (PECVD), plasma enhanced ALD (PEALD), or any other suitable process.
[0031] In FIG. 3, a dilute metal precursor solution 64 is used to fill the features 52. In some examples, the dilute metal precursor solution 64 includes a metal precursor that is mixed with a solvent or carrier liquid. In some examples, the metal precursor includes a metal precursor that is used to form a transition metal. In some examples, the dilute metal precursor solution 64 fills the features 52 by capillary action. [0032] Referring now to FIGs. 4-6, additional processing of the substrate 50 is performed. In FIG. 4, the substrate 50 is subjected to heat or another process such as vacuum to evaporate the solvent or carrier liquid from the dilute metal precursor solution 64. In some examples, a gradient dry process is used. The gradient dry process involves slowly ramping up a temperature of the substrate to cause evaporation of the dilution liquid and to slowly lower a meniscus and reduce metal buildup on sidewalls of the features. For example, with an isopropyl alcohol (IPA) carrier, the temperature is slowly ramped up from room temperature to 60°C at a rate of 1 -2oC/min to concentrate the metal precursor at the bottom of the feature.
[0033] After evaporation is complete, the metal precursor 68 remains at a bottom of the features. In FIG. 5, the substrate 50 is subjected to a reducing plasma process to reduce the metal precursor 68 to a metal or metal alloy and form a seed layer 70. In some examples, the reducing plasma process uses molecular hydrogen gas. In some examples, the plasma process includes a capacitively coupled plasma (CCP) process or an inductively coupled plasma (ICP) process. In another example, the reduction process can moved to an annealing chamber with H2/N2 or NH3/H2 at 200°C to 400°C for a predetermined period. In some examples, the predetermined period is in a range from 2-20 minutes to completely convert the metal precursor to metallic form.
[0034] In some examples, the seed layer has a thickness in a range from 2 to 4 nm. In FIG. 6, electroless deposition (ELD) or another selective gapfill process is performed to fill the features with a transition metal 72.
[0035] Referring now to FIG. 7, a method 100 for forming a seed layer and bottom-up selective gapfill of features with a transition metal is shown. At 1 10, a substrate is provided that includes features such as trenches or vias. In some examples, the substrate includes a liner layer. At 1 14, the features of the substrate are filled with a dilute metal precursor solution.
[0036] At 120, the carrier liquid or solvent is evaporated. In some examples, a gradient dry process is used. At 124, the substrate is exposed to plasma to reduce the metal precursor to a metal or metal alloy and form a seed layer. At 126, an optional heat treatment such as annealing may be performed to improve adhesion.
[0037] At 128, selective bottom-up gapfill of the features is performed using electroless deposition (ELD) or another selective gapfill process is used. In some examples, an electroless deposition method described in U.S. Patent No. 9,287, 183 is used to fill the features, although other electroless deposition methods may be used. In some examples, an electroless deposition tool shown and described in U.S. Patent No. 8,906,446 or U.S. Patent No. 6,913,651 is used, although other electroless deposition tools may be used.
[0038] In one example, features such as trenches are defined in a silicon dioxide (Si02) layer. A tungsten carbonitride (WCN) liner layer is deposited. A cobalt salt precursor such as cobalt (II) chloride (CoCI2) is diluted in isopropyl alcohol (IPA) and applied in the features by capillary action. The substrate is gradient dried from top surfaces thereof such that the IPA evaporates and the cobalt salt precursor condenses at bottoms of the features. The substrate is exposed to a plasma process using plasma gas including molecular hydrogen (H2). The plasma reduces the cobalt salt precursor to cobalt metal and forms a seed layer in the following reaction:
CoCI2 (s) + 2H (g)→ Co (s) + 2 HCI (g)
Then, cobalt metal is deposited in the features using a bottom-up electroless fill process. [0039] The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. It should be understood that one or more steps within a method may be executed in different order (or concurrently) without altering the principles of the present disclosure. Further, although each of the embodiments is described above as having certain features, any one or more of those features described with respect to any embodiment of the disclosure can be implemented in and/or combined with features of any of the other embodiments, even if that combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and permutations of one or more embodiments with one another remain within the scope of this disclosure.

Claims

CLAIMS What is claimed is:
1 . A method of depositing a metal seed for performing bottom-up gapfill of features of a substrate, comprising:
providing a substrate including a plurality of features;
flowing a dilute metal precursor solution into the features, wherein the dilute metal precursor solution includes a metal precursor and a dilution liquid;
evaporating the dilution liquid to locate the metal precursor at bottoms of the plurality of features;
exposing the substrate to a plasma treatment to reduce the metal precursor to at least one of a metal or a metal alloy and to form a seed layer only at the bottoms of the plurality of features;
performing a heat treatment on the substrate; and
using a selective gapfill process to fill the features with a transition metal in contact with the seed layer and not other exposed portions of the plurality of features.
2. The method of claim 1 , wherein the substrate includes a liner layer and the dilute metal precursor solution is applied to the liner layer.
3. The method of claim 2, wherein the liner layer is made of a material selected from a group consisting of titanium nitride (TiN), tungsten carbonitride
(WCN), and tantalum nitride (TaN).
4. The method of claim 2, wherein the liner layer is made of a material selected from a group consisting of silicon dioxide, a metal, or a dielectric.
5. The method of claim 1 , wherein the transition metal is selected from a group consisting of nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), ruthenium (Ru), iridium (Ir), platinum (Pt), palladium (Pd) and tungsten (W).
6. The method of claim 2, wherein the at least one of the metal or the metal alloy is selected to catalytically react with the transition metal but not the liner layer.
7. The method of claim 1 , wherein the selective gapfill process includes electroless deposition.
8. The method of claim 1 , wherein the dilution liquid comprises at least one of a carrier liquid and a solvent.
9. The method of claim 1 , wherein the dilution liquid is water-free.
10. The method of claim 1 , wherein the dilution liquid comprises a liquid selected from a group consisting of alcohol, ether, ester, perflouro-ether.
1 1 . The method of claim 1 , wherein the dilution liquid comprises a liquid selected from a group consisting isopropyl alcohol (IPA) and ethyl alcohol (EtOH).
12. The method of claim 1 , wherein the features have openings having a width that is less than or equal to 10 nm.
13. The method of claim 1 , wherein the features have openings having a width in a range from 7 to 9 nm.
14. The method of claim 1 , wherein the features have openings having a width in a range from 4 to 7 nm.
15. The method of claim 1 , wherein the seed layer has a thickness in a range from 2-4 nm.
16. The method of claim 1 , wherein the heat treatment comprises annealing at a temperature in a range from 200°C to 400°C.
17. The method of claim 1 , wherein the heat treatment comprises annealing at a temperature in a range from 250°C to 350°C.
18. The method of claim 1 , wherein evaporating the dilution liquid includes exposing the substrate to a gradient dry process.
19. The method of claim 1 , wherein the dilute metal precursor solution is at least one of deposited or condensed in the plurality of features using by capillary action.
20. A method of depositing a metal seed for performing bottom-up gapfill of features of a substrate, comprising:
providing a substrate including a plurality of features;
flowing a dilute metal precursor solution into the features, wherein the dilute metal precursor solution includes a metal precursor and a dilution liquid;
evaporating the dilution liquid to locate the metal precursor at bottoms of the plurality of features;
exposing the substrate to a plasma treatment to reduce the metal precursor to at least one of a metal or a metal alloy and to form a seed layer;
performing a heat treatment on the substrate; and
using a selective gapfill process to fill the features with a transition metal in contact with the seed layer,
wherein evaporating the dilution liquid includes exposing the substrate to a gradient dry process.
21 . The method of claim 20, wherein the substrate includes a liner layer and the dilute metal precursor solution is applied to the liner layer.
22. The method of claim 20, wherein the transition metal is selected from a group consisting of nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), ruthenium (Ru), iridium (Ir), platinum (Pt), palladium (Pd) and tungsten (W).
23. The method of claim 20, wherein the selective gapfill process includes electroless deposition.
24. The method of claim 20, wherein the dilution liquid comprises at least one of a carrier liquid and a solvent.
25. The method of claim 20, wherein the dilution liquid is water-free.
26. The method of claim 20, wherein the dilution liquid comprises a liquid selected from a group consisting of alcohol, ether, ester, perflouro-ether.
27. The method of claim 20, wherein the dilution liquid comprises a liquid selected from a group consisting isopropyl alcohol (IPA) and ethyl alcohol (EtOH).
28. The method of claim 20, wherein the dilute metal precursor solution is at least one of deposited or condensed in the plurality of features using by capillary action.
PCT/US2018/021338 2017-03-08 2018-03-07 Methods for wet metal seed deposition for bottom up gapfill of features Ceased WO2018165296A1 (en)

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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11488830B2 (en) * 2018-08-23 2022-11-01 Applied Materials, Inc. Oxygen free deposition of platinum group metal films
KR20220124100A (en) * 2021-03-02 2022-09-13 에이에스엠 아이피 홀딩 비.브이. Methods and systems for filling gaps
KR20220124103A (en) 2021-03-02 2022-09-13 에이에스엠 아이피 홀딩 비.브이. Methods and systems for filling gaps
KR20220124630A (en) 2021-03-02 2022-09-14 에이에스엠 아이피 홀딩 비.브이. Methods and systems for forming layers comprising vanadium and oxygen
TW202322193A (en) * 2021-09-30 2023-06-01 荷蘭商Asm Ip私人控股有限公司 Method and system for forming material within a gap
TW202348832A (en) 2022-05-03 2023-12-16 荷蘭商Asm Ip私人控股有限公司 Vapor deposition process, method of filling gap on substrate with vanadium oxide, and method of forming gap fill layer
WO2024129544A1 (en) * 2022-12-12 2024-06-20 Applied Materials, Inc. Post-treatment for removing residues from dielectric surface

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7074690B1 (en) * 2004-03-25 2006-07-11 Novellus Systems, Inc. Selective gap-fill process
US20090226611A1 (en) * 2008-03-07 2009-09-10 Tokyo Electron Limited Void-free copper filling of recessed features using a smooth non-agglomerated copper seed layer
US20140199523A1 (en) * 2008-06-30 2014-07-17 3M Innovative Properties Company Method of forming a microstructure
US20150076711A1 (en) * 2012-11-19 2015-03-19 Nthdegree Technologies Worldwide Inc. Conductive ink for filling vias
US20160190008A1 (en) * 2012-03-27 2016-06-30 Novellus Systems, Inc. Tungsten feature fill

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0855913A (en) * 1994-06-07 1996-02-27 Texas Instr Inc <Ti> Selective void filling method for submicron interconnects
US5674787A (en) 1996-01-16 1997-10-07 Sematech, Inc. Selective electroless copper deposited interconnect plugs for ULSI applications
GB9717368D0 (en) * 1997-08-18 1997-10-22 Crowther Jonathan Cold plasma metallization
US6793796B2 (en) * 1998-10-26 2004-09-21 Novellus Systems, Inc. Electroplating process for avoiding defects in metal features of integrated circuit devices
JP2001015517A (en) * 1999-07-02 2001-01-19 Ebara Corp Semiconductor device and its manufacture
KR100407681B1 (en) * 2000-06-26 2003-12-01 주식회사 하이닉스반도체 Method of forming a metal line in a semiconductor device
JP5021867B2 (en) 2001-04-09 2012-09-12 第一工業製薬株式会社 Polyether polymer compound, ion conductive polymer composition and electrochemical device using the same
US7258899B1 (en) * 2001-12-13 2007-08-21 Amt Holdings, Inc. Process for preparing metal coatings from liquid solutions utilizing cold plasma
US6913651B2 (en) 2002-03-22 2005-07-05 Blue29, Llc Apparatus and method for electroless deposition of materials on semiconductor substrates
US20060240187A1 (en) * 2005-01-27 2006-10-26 Applied Materials, Inc. Deposition of an intermediate catalytic layer on a barrier layer for copper metallization
US7446034B2 (en) 2005-10-06 2008-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Process for making a metal seed layer
US20070099422A1 (en) * 2005-10-28 2007-05-03 Kapila Wijekoon Process for electroless copper deposition
DE102006001253B4 (en) * 2005-12-30 2013-02-07 Advanced Micro Devices, Inc. A method of forming a metal layer over a patterned dielectric by wet-chemical deposition with an electroless and a power controlled phase
US7566661B2 (en) * 2006-05-22 2009-07-28 Lavoie Adrien R Electroless treatment of noble metal barrier and adhesion layer
US7858525B2 (en) * 2007-03-30 2010-12-28 Intel Corporation Fluorine-free precursors and methods for the deposition of conformal conductive films for nanointerconnect seed and fill
US7799679B2 (en) * 2008-06-24 2010-09-21 Intel Corporation Liquid phase molecular self-assembly for barrier deposition and structures formed thereby
US7776741B2 (en) * 2008-08-18 2010-08-17 Novellus Systems, Inc. Process for through silicon via filing
US20140124361A1 (en) * 2008-11-07 2014-05-08 Lam Research Corporation Method and apparatus for filling interconnect structures
US20100188457A1 (en) * 2009-01-05 2010-07-29 Madigan Connor F Method and apparatus for controlling the temperature of an electrically-heated discharge nozzle
AU2010310750B2 (en) * 2009-10-23 2015-02-26 President And Fellows Of Harvard College Self-aligned barrier and capping layers for interconnects
CN102286760B (en) * 2010-05-19 2016-10-05 诺发系统有限公司 Method of electrochemically filling high aspect ratio large recessed features with metal, aqueous electroplating bath solution, electroplating apparatus and system
JP5981455B2 (en) * 2011-01-26 2016-08-31 エンソン インコーポレイテッド Filling via holes in the microelectronics industry
CN102738071B (en) * 2011-04-15 2018-04-03 诺发系统有限公司 Method and apparatus for filling an interconnect structure
KR101823660B1 (en) * 2013-08-09 2018-01-30 주식회사 엘지화학 Method for forming conductive pattern by direct radiation of electromagnetic wave, and resin structure having conductive pattern thereon
TWI633604B (en) * 2013-09-27 2018-08-21 美商應用材料股份有限公司 Method for realizing seamless cobalt gap filling
US10049921B2 (en) * 2014-08-20 2018-08-14 Lam Research Corporation Method for selectively sealing ultra low-k porous dielectric layer using flowable dielectric film formed from vapor phase dielectric precursor
US9349637B2 (en) * 2014-08-21 2016-05-24 Lam Research Corporation Method for void-free cobalt gap fill
EP3034655A1 (en) * 2014-12-19 2016-06-22 ATOTECH Deutschland GmbH Trench pattern wet chemical copper metal filling using a hard mask structure
US9617648B2 (en) * 2015-03-04 2017-04-11 Lam Research Corporation Pretreatment of nickel and cobalt liners for electrodeposition of copper into through silicon vias
US9287183B1 (en) 2015-03-31 2016-03-15 Lam Research Corporation Using electroless deposition as a metrology tool to highlight contamination, residue, and incomplete via etch
US9935004B2 (en) * 2016-01-21 2018-04-03 Applied Materials, Inc. Process and chemistry of plating of through silicon vias

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7074690B1 (en) * 2004-03-25 2006-07-11 Novellus Systems, Inc. Selective gap-fill process
US20090226611A1 (en) * 2008-03-07 2009-09-10 Tokyo Electron Limited Void-free copper filling of recessed features using a smooth non-agglomerated copper seed layer
US20140199523A1 (en) * 2008-06-30 2014-07-17 3M Innovative Properties Company Method of forming a microstructure
US20160190008A1 (en) * 2012-03-27 2016-06-30 Novellus Systems, Inc. Tungsten feature fill
US20150076711A1 (en) * 2012-11-19 2015-03-19 Nthdegree Technologies Worldwide Inc. Conductive ink for filling vias

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