WO2018142854A1 - Fll circuit and squid sensor - Google Patents

Fll circuit and squid sensor Download PDF

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Publication number
WO2018142854A1
WO2018142854A1 PCT/JP2018/000278 JP2018000278W WO2018142854A1 WO 2018142854 A1 WO2018142854 A1 WO 2018142854A1 JP 2018000278 W JP2018000278 W JP 2018000278W WO 2018142854 A1 WO2018142854 A1 WO 2018142854A1
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circuit
output voltage
integration
value
integrating
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PCT/JP2018/000278
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French (fr)
Japanese (ja)
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宏志 松村
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富士通株式会社
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/02—Measuring direction or magnitude of magnetic fields or magnetic flux
    • G01R33/035—Measuring direction or magnitude of magnetic fields or magnetic flux using superconductive devices

Definitions

  • the present invention relates to an FLL circuit and a SQUID sensor.
  • a superconducting quantum interference device which is a loop-like element in which two superconductors are Josephson joined at two locations, can detect a minute magnetic field.
  • the SQUID functions as a converter that converts the magnitude of the magnetic field into a voltage.
  • the voltage is very small and easily affected by environmental noise.
  • a sensor using SQUID (hereinafter referred to as SQUID sensor) uses a stabilization circuit called an FLL (Flux Locked Loop) circuit.
  • the FLL circuit amplifies the output voltage of the SQUID with an amplifier circuit, and smoothes the amplified output voltage with an integrating circuit.
  • the smoothed voltage is negatively fed back to the SQUID as a feedback magnetic flux through the feedback resistor and the coil.
  • the output voltage of the FLL circuit does not depend on variations in the device characteristics of the SQUID itself, and becomes a value proportional to the magnitude of the magnetic field.
  • the integrating circuit of the FLL circuit includes a resistor and a capacitor, and in order to detect a minute magnetic field with high sensitivity, the time constant of the resistor and the capacitor may be increased.
  • the time constant of the integration circuit is increased, there is a problem that the tracking of the FLL circuit is delayed with respect to a sudden change in the magnetic field, and the stability of the detection of the magnetic field is lowered.
  • an object of the present invention is to provide an FLL circuit and a SQUID sensor that can improve the stability of detection of a magnetic field.
  • a first output voltage having a first time constant and output from a SQUID or a second output voltage obtained by amplifying the first output voltage is time-integrated, and a first integration signal is obtained.
  • the second integration circuit When the second integration circuit to output and the first value indicating the speed of change of the first output voltage is greater than a threshold value, the second integration circuit is operated, and the first value is A control circuit for stopping the operation of the second integration circuit when it is smaller than a threshold value; a coil for generating a feedback magnetic flux to be supplied to the SQUID based on the first integration signal or the second integration signal; , A FLL circuit is provided.
  • a SQUID sensor is provided.
  • the stability of magnetic field detection can be improved.
  • FIG. 1 is a diagram illustrating an example of the SQUID sensor and the FLL circuit according to the first embodiment.
  • the SQUID sensor 10 includes a SQUID 11, an FLL circuit 12, and an AD (Analog to Digital) conversion circuit 13.
  • the SQUID 11 outputs an output voltage based on the input magnetic field ⁇ and the feedback magnetic flux ⁇ f.
  • the FLL circuit 12 is a circuit that stabilizes the output voltage of the SQUID 11.
  • the AD conversion circuit 13 performs AD conversion on the output voltage of the FLL circuit 12 and outputs a digital value as a detection result of the magnetic field ⁇ .
  • the FLL circuit 12 includes an amplifier circuit 12a, a bias power supply 12b, integration circuits 12c and 12d, a switch 12e, a control circuit 12f, resistors 12g and 12h, a coil 12i, and a switch 12j.
  • the amplifier circuit 12a receives the output voltage of the SQUID 11 and the bias voltage Vb generated by the bias power supply 12b, and amplifies the output voltage of the SQUID 11. In order to detect a minute change in the magnetic field ⁇ , it is desirable to use a low-noise preamplifier as the amplifier circuit 12a.
  • the integration circuits 12c and 12d have a function of smoothing the output voltage of the amplification circuit 12a by time integration.
  • the integration circuit 12c has a time constant ⁇ 1, and outputs an integration signal obtained by time-integrating the output signal of the amplification circuit 12a.
  • the integrating circuit 12d has a time constant ⁇ 2 smaller than the time constant ⁇ 1, and is connected to the output terminal of the amplifier circuit 12a via the switch 12e. That is, the output voltage of the amplifier circuit 12a is supplied to the integrating circuit 12d via the switch 12e.
  • the integration circuit 12d outputs an integration signal obtained by time-integrating the output voltage of the amplification circuit 12a when the switch 12e is on.
  • the control circuit 12f operates the integration circuit 12d when a value indicating the speed of change of the output voltage of the SQUID 11 (for example, a positive differential value or an absolute value of a negative differential value described later) is larger than a threshold value. Further, the control circuit 12f stops the operation of the integrating circuit 12d when the value indicating the change speed of the output voltage is smaller than the threshold value.
  • a value indicating the speed of change of the output voltage of the SQUID 11 for example, a positive differential value or an absolute value of a negative differential value described later
  • control circuit 12f operates the integration circuit 12d by turning on the switch 12e when the value indicating the change speed of the output voltage is larger than the threshold value.
  • control circuit 12f stops the operation of the integrating circuit 12d by turning off the switch 12e when the value indicating the change speed of the output voltage is smaller than the threshold value.
  • the control circuit 12f obtains a value representing the speed of change of the output voltage by, for example, differentiating the output voltage of the SQUID 11 with time.
  • a positive differential value is obtained
  • a negative differential value is obtained.
  • the control circuit 12f turns on the switch 12e, and the absolute value of the positive differential value or the negative differential value is smaller than the threshold value. If it is smaller, the switch 12e is turned off.
  • the control circuit 12f turns on the switch 12e when the negative differential value is smaller than the negative threshold value, and turns off the switch 12e when the negative differential value is larger than the negative threshold value. May be.
  • control circuit 12f can operate the integrating circuit 12d when detecting a rapid change of the output voltage of the SQUID 11 to the positive side and a rapid change to the negative side.
  • the control circuit 12f can be realized using, for example, a differentiation circuit and a comparison circuit (see FIG. 3).
  • the output voltage output from the SQUID 11 is input to the control circuit 12f.
  • the control circuit 12f may control the switch 12e based on the output signal of the amplifier circuit 12a. .
  • One end of the coil 12i is connected to the output terminal of the integrating circuit 12c through the resistor 12g, and is connected to the output terminal of the integrating circuit 12d through the resistor 12h. The other end of the coil 12i is grounded.
  • the coil 12i generates a feedback magnetic flux ⁇ f to be supplied to the SQUID 11 based on the integration signal output from the integration circuit 12c or the integration circuit 12d.
  • the switch 12j supplies one of the integration signals output from the integration circuit 12c and the integration circuit 12d to the AD conversion circuit 13 based on the control signal output from the control circuit 12f.
  • the switch 12j connects the integration circuit 12d and the AD conversion circuit 13, and disconnects the integration circuit 12c and the AD conversion circuit 13.
  • the switch 12j disconnects the integration circuit 12d and the AD conversion circuit 13 and connects the integration circuit 12c and the AD conversion circuit 13.
  • the switch 12e and the switch 12j can be realized using, for example, a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor).
  • MOSFET Metal-Oxide Semiconductor Field Effect Transistor
  • one of the source terminal or the drain terminal of the nMOS is connected to the output terminal of the amplifier circuit 12a, the other is connected to the integrating circuit 12d, and the gate terminal Is connected to the control circuit 12f.
  • H (High) level the nMOS is turned on.
  • the logic level of the control signal is L (Low) level
  • the nMOS is turned off. .
  • an nMOS and a p-channel MOSFET (hereinafter abbreviated as pMOS) can be used.
  • one of the source terminal or the drain terminal of the pMOS is connected to the integration circuit 12c, the other is connected to the AD conversion circuit 13, and the gate terminal is connected to the control circuit 12f.
  • one of the source terminal or the drain terminal of the nMOS is connected to the integrating circuit 12d, the other is connected to the AD conversion circuit 13, and the gate terminal is connected to the control circuit 12f.
  • the AD conversion circuit 13 may select one of the integration signal output from the integration circuit 12c and the integration signal output from the integration circuit 12d based on the control signal output from the control circuit 12f and perform AD conversion. . In that case, the switch 12j may not be provided.
  • the integration circuits 12c and 12d output an integration signal having an appropriate magnitude as a detection result (analog value)
  • the amplification circuit 12a may be omitted.
  • the output voltage of the SQUID 11 is supplied to the integrating circuit 12c and also supplied to the integrating circuit 12d via the switch 12e.
  • SQUID11 and the coil 12i are provided in the cooling device (for example, Dewar cooler) which cools SQUID11 with liquid nitrogen.
  • the cooling device for example, Dewar cooler
  • FIG. 2 is a diagram illustrating an example of the integration circuit. Although FIG. 2 shows an example of the integrating circuit 12d, the integrating circuit 12c can also be realized with the same circuit configuration.
  • the integrating circuit 12d has an input terminal 12d1, a resistor 12d2, a capacitor 12d3, an operational amplifier 12d4, and an output terminal 12d5.
  • One end of the resistor 12d2 is connected to the input terminal 12d1, and the other end of the resistor 12d2 is connected to one end of the capacitor 12d3 and the inverting input terminal (denoted as “ ⁇ ”) of the operational amplifier 12d4.
  • the other end of the capacitor 12d3 is connected to the output terminal 12d5 and the output terminal of the operational amplifier 12d4.
  • a non-inverting input terminal (denoted as “+”) of the operational amplifier 12d4 is grounded.
  • an integration signal obtained by time-integrating the output signal of the amplification circuit 12a input from the input terminal 12d1 is output from the output terminal 12d5.
  • the resistance value of the resistor 12d2 is R and the capacitance of the capacitor 12d3 is C
  • the time constant ⁇ 2 of the integrating circuit 12d is R ⁇ C.
  • FIG. 3 is a diagram illustrating an example of the control circuit.
  • the control circuit 12f includes a differentiation circuit 12f1 and a comparison circuit 12f2.
  • the differentiating circuit 12f1 outputs a differential value (a value proportional to the change of the output voltage) indicating the speed of change of the output voltage of the SQUID 11.
  • the comparison circuit 12f2 outputs a control signal for turning on the switch 12e when the differentiation value output from the differentiation circuit 12f1 is positive and larger than a positive threshold value or when the differentiation value is negative and smaller than a negative threshold value.
  • the comparison circuit 12f2 outputs a control signal for turning off the switch 12e.
  • FIG. 4 is a diagram illustrating an example of a differentiation circuit.
  • the differentiation circuit 12f1 has an input terminal 12f11, a capacitor 12f12, a resistor 12f13, an operational amplifier 12f14, and an output terminal 12f15.
  • One end of the capacitor 12f12 is connected to the input terminal 12f11, and the other end of the capacitor 12f12 is connected to one end of the resistor 12f13 and the inverting input terminal of the operational amplifier 12f14.
  • the other end of the resistor 12f13 is connected to the output terminal 12f15 and the output terminal of the operational amplifier 12f14.
  • the non-inverting input terminal of the operational amplifier 12f14 is grounded.
  • FIG. 5 is a diagram illustrating an example of the comparison circuit.
  • the comparison circuit 12f2 has an input terminal 12f21, comparison circuits 12f22 and 12f23, an OR circuit 12f24, and an output terminal 12f25.
  • the comparison circuit 12f22 compares the differential value input from the input terminal 12f21 with the positive threshold value Vref +, and outputs a voltage having a logic level of H level when the differential value is greater than the threshold value Vref +. In other cases, the comparison circuit 12f22 outputs a voltage having a logic level of L level.
  • the comparison circuit 12f23 compares the differential value input from the input terminal 12f21 with a negative threshold value Vref ⁇ , and outputs a voltage having a logic level of H level when the differential value is smaller than the threshold value Vref ⁇ . In other cases, the comparison circuit 12f23 outputs a voltage having a logic level of L level.
  • One input terminal of the OR circuit 12f24 is connected to the output terminal of the comparison circuit 12f22, and the other input terminal of the OR circuit 12f24 is connected to the output terminal of the comparison circuit 12f23.
  • the output terminal of the OR circuit 12f24 is connected to the output terminal 12f25.
  • the OR circuit 12f24 outputs an H level voltage as a control signal and turns on the switch 12e when the logical level of the output voltage of at least one of the comparison circuits 12f22 and 12f23 is the H level.
  • the OR circuit 12f24 outputs the L level voltage as a control signal and turns off the switch 12e when the logical levels of the output voltages of both the comparison circuits 12f22 and 12f23 are L level.
  • FIG. 6 is a timing chart showing an operation example of the SQUID sensor when the change in the magnetic field is relatively gradual.
  • FIG. 6 shows an example of the time change of the magnetic field ⁇ , the output voltage of the SQUID 11, the output voltage (differential value) of the differentiation circuit 12f1, and the output voltage (control signal) of the comparison circuit 12f2. Further, an example of the time change of the output voltage (integrated signal) of the integrating circuit 12c with the time constant ⁇ 1 and the output voltage (integrated signal) of the integrating circuit 12d with the time constant ⁇ 2 is shown.
  • the magnetic field ⁇ increases and decreases between timing t1 and timing t2.
  • the output voltage of the SQUID 11 also increases.
  • the increase in the output voltage of the SQUID 11 is also gradual.
  • the output voltage (positive differential value) of the differentiation circuit 12f1 becomes smaller than the threshold value Vref +
  • the logic level of the output voltage of the comparison circuit 12f2 becomes L level, and the switch 12e is turned off.
  • the integration circuit 12d does not operate, and the output voltage of the integration circuit 12d does not rise.
  • the output voltage of the integrating circuit 12c rises gently. Based on the output voltage of the integrating circuit 12c, a feedback magnetic flux ⁇ f is generated in the coil 12i and negatively fed back to the SQUID 11.
  • the output voltage of the SQUID 11 When the magnetic field ⁇ starts to drop, the output voltage of the SQUID 11 also drops.
  • the output voltage drop of the SQUID 11 is also gradual.
  • the output voltage (negative differential value) of the differentiation circuit 12f1 becomes larger than the threshold value Vref ⁇ , the logic level of the output voltage of the comparison circuit 12f2 remains L level, and the switch 12e remains off. .
  • the output voltage of the integrating circuit 12d does not rise.
  • the output voltage of the integrating circuit 12c drops due to the action of negative feedback.
  • the switch 12j since the logic level of the output voltage of the comparison circuit 12f2 serving as a control signal for the switch 12j remains L level, the switch 12j connects the integration circuit 12c and the AD conversion circuit 13, The connection between the integration circuit 12d and the AD conversion circuit 13 is disconnected. Therefore, the AD conversion circuit 13 converts the output voltage of the integration circuit 12c into a digital value and outputs the digital value as a detection result of the magnetic field ⁇ .
  • the integration circuit 12c having a larger time constant than the integration circuit 12d, the SN (Signal-Noise) ratio becomes large, and the minute magnetic field ⁇ . But it can be detected with high sensitivity. That is, the detection sensitivity of the SQUID sensor 10 can be improved.
  • FIG. 7 is a timing chart illustrating an operation example of the SQUID sensor when the change in the magnetic field is relatively fast. 7, similarly to FIG. 6, the magnetic field ⁇ , the output voltage of the SQUID 11, the output voltage of the differentiation circuit 12 f 1, the output voltage of the comparison circuit 12 f 2, the output voltage of the integration circuit 12 c of the time constant ⁇ 1, and the integration circuit of the time constant ⁇ 2 An example of the time variation of the 12d output voltage is shown.
  • the magnetic field ⁇ increases and decreases between timing t3 and timing t4.
  • the magnetic field ⁇ changes in a shorter time than the example of FIG.
  • the output voltage of the SQUID 11 also increases. Since the change of the magnetic field ⁇ is faster than that in the case of FIG. 6, the increase of the output voltage of the SQUID 11 is also faster than that in the case of FIG.
  • the output voltage (positive differential value) of the differentiating circuit 12f1 is larger than the threshold value Vref +, the logic level of the output voltage of the comparing circuit 12f2 is H level, and the switch 12e is turned on. To do.
  • the integrating circuit 12d operates and the output voltage of the integrating circuit 12d increases. Further, the output voltage of the integrating circuit 12c also rises gently.
  • the time constant ⁇ 2 of the integrating circuit 12d is smaller than the time constant ⁇ 1 of the integrating circuit 12c, the speed at which the output voltage of the integrating circuit 12d increases is faster than the speed at which the output voltage of the integrating circuit 12c increases. Therefore, in the coil 12i, a feedback magnetic flux ⁇ f based mainly on the output voltage of the integrating circuit 12d is generated and negatively fed back to the SQUID 11.
  • the output voltage of the integrating circuit 12d becomes proportional to the magnetic field ⁇ by the action of this negative feedback.
  • the magnetic field ⁇ is a function of time ⁇ (t)
  • the output voltage of the integrating circuit 12d is a function of time Vout2 (t)
  • the resistance value of the resistor 12h is Rf2
  • the mutual inductance of the coil 12i is Mf
  • Vout2 (t) ( Rf2 / Mf) ⁇ ⁇ (t).
  • the logic level of the output voltage of the comparison circuit 12f2 serving as a control signal for the switch 12j is almost H level during the period from the timing t3 to the timing t4 when the magnetic field ⁇ changes. Therefore, the switch 12j connects the integration circuit 12d and the AD conversion circuit 13 during most of the period from the timing t3 to the timing t4, and disconnects the connection between the integration circuit 12c and the AD conversion circuit 13. Therefore, the AD conversion circuit 13 mainly converts the output voltage of the integration circuit 12d into a digital value, and outputs the digital value as a detection result of the magnetic field ⁇ .
  • the output voltage of the integrating circuit 12c cannot follow the rapid change of the magnetic field ⁇ , but the output voltage of the integrating circuit 12d can follow the rapid change of the magnetic field ⁇ .
  • the followability to magnetic field changes is improved, and the stability of magnetic field detection is improved. That is, by improving the followability to the magnetic field change, the response speed (slew rate) of the SQUID sensor 10 is improved, and the rapidly changing magnetic field ⁇ can be detected stably.
  • the slew rate can be expressed by the maximum value of the time change of the magnetic field that can be followed.
  • the detection sensitivity of the SQUID sensor 10 can be improved by the operation of the integration circuit 12c with the time constant ⁇ 1, and thus the SQUID sensor of the first embodiment. 10 can realize a highly sensitive and stable magnetic field detection.
  • the time constant ⁇ 2 is 1 ⁇ 4 of the time constant ⁇ 1.
  • the slew rate is 10 mT / sec and the detection sensitivity is 15 fT / Hz 1/2 when magnetic field detection is performed using one integration circuit 12 c without using the integration circuit 12 d.
  • the slew rate is set to 40 mT / sec and the detection sensitivity is set to 25 fT / Hz by further operating the integration circuit 12d in addition to the integration circuit 12c when a sudden magnetic field change as shown in FIG. 7 occurs. It can be 1/2 . That is, a four times higher slew rate characteristic can be realized without deteriorating the detection sensitivity. This means that, for example, when the SQUID sensor 10 is used for ore exploration, the exploration time can be reduced to 1 ⁇ 4, and exploration efficiency can be improved.
  • the integrating circuit 12c is operated even when the output voltage of the differentiating circuit 12f1 is larger than the threshold value Vref + or smaller than the threshold value Vref ⁇ . However, the integrating circuit 12c is not operated. May be. In that case, a switch is provided between the output terminal of the amplifier circuit 12a and the integrating circuit 12c, and the control circuit 12f turns off the switch when turning on the switch 12e.
  • the magnetic field ⁇ is directly input to the SQUID 11.
  • the detection coil that detects the magnetic field ⁇ and the signal magnetic flux based on the magnetic field ⁇ detected by the detection coil are generated and supplied to the SQUID 11.
  • An input coil can be used.
  • the FLL circuit 12 including the two integration circuits 12c and 12d is shown.
  • the number of integration circuits is not limited to two, and may be three or more. Examples thereof will be described below.
  • FIG. 8 is a diagram illustrating an example of the SQUID sensor and the FLL circuit according to the second embodiment.
  • the SQUID sensor 20 includes a SQUID 21, an FLL circuit 22, and an AD conversion circuit 23.
  • the SQUID 21 outputs an output voltage based on the input magnetic field ⁇ and the feedback magnetic flux ⁇ f.
  • the FLL circuit 22 is a circuit that stabilizes the output voltage of the SQUID 21.
  • the AD conversion circuit 23 AD-converts the output voltage of the FLL circuit 22 and outputs a digital value as a detection result of the magnetic field ⁇ .
  • the FLL circuit 22 includes an amplifier circuit 22a, a bias power source 22b, integration circuits 22c, 22d, and 22e, switches 22f and 22g, a control circuit 22h, resistors 22i, 22j, and 22k, and a coil 22l.
  • the amplification circuit 22a receives the output voltage of the SQUID 21 and the bias voltage Vb generated by the bias power supply 22b, and amplifies the output voltage of the SQUID 21. In order to detect a minute change in the magnetic field ⁇ , it is desirable to use a low-noise preamplifier as the amplifier circuit 22a.
  • the integration circuits 22c, 22d, and 22e have a function of smoothing the output signal of the amplification circuit 22a by time integration.
  • the integration circuit 22c has a time constant ⁇ 3 and outputs an integration signal obtained by time-integrating the output signal of the amplification circuit 22a.
  • the integrating circuit 22d has a time constant ⁇ 4 smaller than the time constant ⁇ 3, and is connected to the output terminal of the amplifying circuit 22a via a switch 22f. That is, the output voltage of the amplification circuit 22a is supplied to the integration circuit 22d via the switch 22f.
  • the integration circuit 22d outputs an integration signal obtained by time-integrating the output signal of the amplification circuit 22a when the switch 22f is on.
  • the integrating circuit 22e has a time constant ⁇ 5 smaller than the time constant ⁇ 4, and is connected to the output terminal of the amplifying circuit 22a via a switch 22g. That is, the output voltage of the amplification circuit 22a is supplied to the integration circuit 22e via the switch 22g.
  • the integration circuit 22e outputs an integration signal obtained by time-integrating the output signal of the amplification circuit 22a when the switch 22g is on.
  • the control circuit 22h has a smaller value among the plurality of integration circuits 22c to 22e as the value indicating the speed of change of the output voltage of the SQUID 11 (for example, the absolute value of the positive differential value or the negative differential value) increases.
  • An integration circuit having a time constant is operated.
  • the control circuit 22h includes a differentiation circuit 22h1 and comparison circuits 22h2 and 22h3.
  • the differentiating circuit 22h1 obtains a value representing the speed of change of the output voltage by time-differentiating the output voltage of the SQUID 21.
  • the differentiation circuit 22h1 can be realized by a circuit similar to the differentiation circuit 12f1 shown in FIG.
  • the comparison circuit 22h2 is a control signal for turning on the switch 22f when the positive differential value output from the differentiation circuit 22h1 is larger than the positive threshold value Vref1 + or the negative differential value is smaller than the negative threshold value Vref1-. Is output. In other cases, the comparison circuit 22h2 outputs a control signal for turning off the switch 22f.
  • the comparison circuit 22h3 outputs a control signal for turning on the switch 22g when the positive differential value output from the differentiation circuit 22h1 is larger than the positive threshold value Vref2 + or the negative differential value is smaller than the negative threshold value Vref2-. Output. In other cases, the comparison circuit 22h3 outputs a control signal for turning off the switch 22g.
  • the threshold value Vref2 + is larger than the threshold value Vref1 +, and the threshold value Vref2- is smaller than the threshold value Vref1-.
  • the comparison circuits 22h2 and 22h3 can be realized by a circuit similar to the comparison circuit 12f2 shown in FIG.
  • control circuit 22h receives the output voltage output from the SQUID 21, but may control the switches 22f and 22g based on the output signal of the amplifier circuit 22a.
  • One end of the coil 22l is connected to the output terminal of the integrating circuit 22c through the resistor 22i, the output terminal of the integrating circuit 22d through the resistor 22j, and the output terminal of the integrating circuit 22e through the resistor 22k.
  • the other end of the coil 22l is grounded.
  • the coil 22l generates a feedback magnetic flux ⁇ f to be supplied to the SQUID 21 based on the integration signal output from the integration circuit 22c, the integration circuit 22d, and the integration circuit 22e.
  • the integration signals output from the integration circuits 22c to 22e are supplied to the AD conversion circuit 23.
  • the AD conversion circuit 23 selects an integration signal output from any of the integration circuits 22c to 22e based on the control signal output from the comparison circuits 22h2 and 22h3, and performs AD conversion. For example, when the control circuit 22h outputs a control signal for turning on the switch 22g and a control signal for turning on the switch 22f, the AD conversion circuit 23 selects the integration signal output from the integration circuit 22e and performs AD conversion. When the control circuit 22h outputs a control signal for turning on the switch 22f and a control signal for turning off the switch 22g, the AD conversion circuit 23 selects the integration signal output by the integration circuit 22d and performs AD conversion. When the control circuit 22h outputs a control signal for turning off the switch 22f and a control signal for turning off the switch 22g, the AD conversion circuit 23 selects the integration signal output from the integration circuit 22c and performs AD conversion.
  • the switches 22f and 22g can be realized using, for example, a MOSFET.
  • the AD conversion circuit 23 selecting an integration signal to be AD converted based on the two control signals output from the control circuit, a switch is provided in the FLL circuit 22 and AD conversion is performed based on the two control signals The integration signal supplied to the circuit 23 may be selected.
  • the amplification circuit 22a may be omitted.
  • the output voltage of the SQUID 21 is supplied to the integrating circuit 22c, supplied to the integrating circuit 22d through the switch 22f, and supplied to the integrating circuit 22e through the switch 22g.
  • an integration circuit having a small time constant operates from the three integration circuits 22c to 22e as the magnetic field change becomes faster. For example, when the change in the magnetic field is faster as the positive differential value output from the differentiation circuit 22h1 is larger than the threshold value Vref2 + or the negative differential value is smaller than the threshold value Vref2-, the integration circuit 22e having the smallest time constant operates. To do.
  • the integrating circuit 22d operates.
  • the time constant of the integration circuits 22c to 22e is the largest. Only the large integration circuit 22c operates.
  • the same effects as those of the SQUID sensor 10 and the FLL circuit 12 of the first embodiment can be obtained, and various magnetic field change speeds can be obtained. You can select the slew rate corresponding to the size.
  • FIG. 9 is a diagram illustrating an application example to an apparatus for exploring a metal deposit.
  • FIG. 9 shows an example in which the exploration device 31 is mounted on the vehicle 30.
  • the exploration device 31 includes a SQUID 31a, an FLL circuit 31b, an AD conversion circuit 31c, and a display device 31d.
  • the voltage converted by the SQUID 31a is stabilized by the FLL circuit 31b and supplied to the AD conversion circuit 31c.
  • the AD converter circuit 31c converts the output voltage (integrated signal) of the FLL circuit 31b into a digital value. Based on the digital value, for example, the time change of the magnetic field is displayed on the display device 31d under the control of a processor (not shown). Is done.
  • the exploration device 31 explores the metal deposits 32a and 32b that generate the magnetic field existing in the ground
  • the change speed of the magnetic field detected by the exploration device 31 increases as the speed of the vehicle 30 increases.
  • the FLL circuit 12 of the first embodiment or the FLL circuit 22 of the second embodiment as the FLL circuit 31b, it becomes possible to follow a change in the magnetic field, so that stable magnetic field detection is possible.
  • the metal deposit 32b exists deeper in the ground than the metal deposit 32a, and the magnetic field detected by the exploration device 31 is small.
  • the FLL circuit 12 of the first embodiment or the FLL circuit 22 of the second embodiment as the FLL circuit 31b, the magnetic field can be detected without reducing the detection sensitivity. Can be detected with high sensitivity.
  • SQUID sensor 11 SQUID 12 FLL circuit 12a Amplifier circuit 12b Bias power supply 12c, 12d Integration circuit 12e, 12j Switch 12f Control circuit 12g, 12h Resistance 12i Coil 13 AD converter circuit Vb Bias voltage ⁇ Magnetic field ⁇ f Feedback magnetic flux ⁇ 1, ⁇ 2 Time constant

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Abstract

[Problem] To improve stability in detecting a magnetic field. [Solution] An integration circuit 12c has a time constant τ1, time-integrates a first output voltage output from a SQUID 11 or a second output voltage obtained by amplifying the first output voltage, and outputs a first integration signal. An integration circuit 12d has a time constant τ2, which is smaller than the time constant τ1, and outputs a second integration signal obtained by time-integrating the first output voltage or the second output voltage. A control circuit 12f operates the integration circuit 12d when a first value, which indicates a rate of change of the first output voltage, is greater than a threshold, and stops an operation of the integration circuit 12d when the first value is less than the threshold. A coil 12i generates a feedback magnetic flux φf, which is supplied to the SQUID 11, on the basis of the first integration signal or the second integration signal.

Description

ＦＬＬ回路及びＳＱＵＩＤセンサFLL circuit and SQUID sensor
　本発明は、ＦＬＬ回路及びＳＱＵＩＤセンサに関する。 The present invention relates to an FLL circuit and a SQUID sensor.
　２つの超伝導体を２箇所でジョセフソン接合したループ状の素子であるＳＱＵＩＤ（Superconducting Quantum Interference Device）は、微小な磁場を検出できることが知ら
れている。 It is known that a superconducting quantum interference device (SQUID), which is a loop-like element in which two superconductors are Josephson joined at two locations, can detect a minute magnetic field.
　ＳＱＵＩＤは磁場の大きさを電圧に変換する変換器として機能する。しかしその電圧は微小で、環境ノイズの影響を受けやすい。そのため、ＳＱＵＩＤを用いたセンサ（以下ＳＱＵＩＤセンサという）では、ＦＬＬ（Flux Locked Loop）回路と呼ばれる安定化回路が用いられる。ＦＬＬ回路は、ＳＱＵＩＤの出力電圧を増幅回路で増幅し、増幅した出力電圧を積分回路で平滑化する。平滑化された電圧は、フィードバック抵抗とコイルを介して、ＳＱＵＩＤに帰還磁束としてネガティブフィードバックされる。これによって、ＦＬＬ回路の出力電圧は、ＳＱＵＩＤ自身のデバイス特性変動に依存しなくなり、磁場の大きさに比例した値となる。 The SQUID functions as a converter that converts the magnitude of the magnetic field into a voltage. However, the voltage is very small and easily affected by environmental noise. For this reason, a sensor using SQUID (hereinafter referred to as SQUID sensor) uses a stabilization circuit called an FLL (Flux Locked Loop) circuit. The FLL circuit amplifies the output voltage of the SQUID with an amplifier circuit, and smoothes the amplified output voltage with an integrating circuit. The smoothed voltage is negatively fed back to the SQUID as a feedback magnetic flux through the feedback resistor and the coil. As a result, the output voltage of the FLL circuit does not depend on variations in the device characteristics of the SQUID itself, and becomes a value proportional to the magnitude of the magnetic field.
特開平５－１１０３４号公報Japanese Patent Laid-Open No. 5-11034 特開平４－２６８４７３号公報JP-A-4-268473
　ところで、ＦＬＬ回路の積分回路は抵抗とキャパシタを含み、微小な磁場を高感度に検出するためには、抵抗とキャパシタによる時定数を大きくすればよい。
　しかし、積分回路の時定数を大きくした場合、磁場の急激な変化に対してＦＬＬ回路の追従が遅れ、磁場の検出の安定性が下がる問題がある。 By the way, the integrating circuit of the FLL circuit includes a resistor and a capacitor, and in order to detect a minute magnetic field with high sensitivity, the time constant of the resistor and the capacitor may be increased.
However, when the time constant of the integration circuit is increased, there is a problem that the tracking of the FLL circuit is delayed with respect to a sudden change in the magnetic field, and the stability of the detection of the magnetic field is lowered.
　１つの側面では、本発明は、磁場の検出の安定性を向上できるＦＬＬ回路及びＳＱＵＩＤセンサを提供することを目的とする。 In one aspect, an object of the present invention is to provide an FLL circuit and a SQUID sensor that can improve the stability of detection of a magnetic field.
　１つの実施態様では、第１の時定数を有し、ＳＱＵＩＤが出力する第１の出力電圧または前記第１の出力電圧を増幅した第２の出力電圧を時間積分し、第１の積分信号を出力する第１の積分回路と、前記第１の時定数よりも小さい第２の時定数を有し、前記第１の出力電圧または前記第２の出力電圧を時間積分した第２の積分信号を出力する第２の積分回路と、前記第１の出力電圧の変化の速さを表す第１の値が閾値よりも大きい場合に前記第２の積分回路を動作させ、前記第１の値が前記閾値よりも小さい場合に前記第２の積分回路の動作を停止する制御回路と、前記第１の積分信号または前記第２の積分信号に基づいて、前記ＳＱＵＩＤに供給する帰還磁束を発生するコイルと、を有するＦＬＬ回路が提供される。 In one embodiment, a first output voltage having a first time constant and output from a SQUID or a second output voltage obtained by amplifying the first output voltage is time-integrated, and a first integration signal is obtained. A first integration circuit that outputs, and a second integration signal that has a second time constant smaller than the first time constant, and that is obtained by time-integrating the first output voltage or the second output voltage. When the second integration circuit to output and the first value indicating the speed of change of the first output voltage is greater than a threshold value, the second integration circuit is operated, and the first value is A control circuit for stopping the operation of the second integration circuit when it is smaller than a threshold value; a coil for generating a feedback magnetic flux to be supplied to the SQUID based on the first integration signal or the second integration signal; , A FLL circuit is provided.
　また、１つの実施態様では、ＳＱＵＩＤセンサが提供される。 Also, in one embodiment, a SQUID sensor is provided.
　１つの側面では、磁場の検出の安定性を向上できる。 In one aspect, the stability of magnetic field detection can be improved.
第１の実施の形態のＳＱＵＩＤセンサ及びＦＬＬ回路の一例を示す図である。It is a figure which shows an example of the SQUID sensor and FLL circuit of 1st Embodiment. 積分回路の一例を示す図である。It is a figure which shows an example of an integration circuit. 制御回路の一例を示す図である。It is a figure which shows an example of a control circuit. 微分回路の一例を示す図である。It is a figure which shows an example of a differentiation circuit. 比較回路の一例を示す図である。It is a figure which shows an example of a comparison circuit. 磁場の変化が比較的緩やかな場合のＳＱＵＩＤセンサの動作例を示すタイミングチャートである。It is a timing chart which shows the operation example of a SQUID sensor in case the change of a magnetic field is comparatively slow. 磁場の変化が比較的速い場合のＳＱＵＩＤセンサの動作例を示すタイミングチャートである。It is a timing chart which shows the operation example of a SQUID sensor in case the change of a magnetic field is comparatively quick. 第２の実施の形態のＳＱＵＩＤセンサ及びＦＬＬ回路の一例を示す図である。It is a figure which shows an example of the SQUID sensor and FLL circuit of 2nd Embodiment. 金属鉱床を探査する装置への適用例を示す図である。It is a figure which shows the example of application to the apparatus which searches a metal deposit.
　以下、発明を実施するための形態を、図面を参照しつつ説明する。
　（第１の実施の形態）
　図１は、第１の実施の形態のＳＱＵＩＤセンサ及びＦＬＬ回路の一例を示す図である。 Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating an example of the SQUID sensor and the FLL circuit according to the first embodiment.
　ＳＱＵＩＤセンサ１０は、ＳＱＵＩＤ１１、ＦＬＬ回路１２、ＡＤ（Analog to Digital）変換回路１３を有する。
　ＳＱＵＩＤ１１は、入力される磁場φと、帰還磁束φｆとに基づいた出力電圧を出力する。 The SQUID sensor 10 includes a SQUID 11, an FLL circuit 12, and an AD (Analog to Digital) conversion circuit 13.
The SQUID 11 outputs an output voltage based on the input magnetic field φ and the feedback magnetic flux φf.
　ＦＬＬ回路１２は、ＳＱＵＩＤ１１の出力電圧を安定化する回路である。
　ＡＤ変換回路１３は、ＦＬＬ回路１２の出力電圧をＡＤ変換し、磁場φの検出結果としてデジタル値を出力する。 The FLL circuit 12 is a circuit that stabilizes the output voltage of the SQUID 11.
The AD conversion circuit 13 performs AD conversion on the output voltage of the FLL circuit 12 and outputs a digital value as a detection result of the magnetic field φ.
　ＦＬＬ回路１２は、増幅回路１２ａ、バイアス電源１２ｂ、積分回路１２ｃ，１２ｄ、スイッチ１２ｅ、制御回路１２ｆ、抵抗１２ｇ，１２ｈ、コイル１２ｉ、スイッチ１２ｊを有する。 The FLL circuit 12 includes an amplifier circuit 12a, a bias power supply 12b, integration circuits 12c and 12d, a switch 12e, a control circuit 12f, resistors 12g and 12h, a coil 12i, and a switch 12j.
　増幅回路１２ａは、ＳＱＵＩＤ１１の出力電圧と、バイアス電源１２ｂが生成するバイアス電圧Ｖｂを受け、ＳＱＵＩＤ１１の出力電圧を増幅する。微小な磁場φの変化を検出するために、増幅回路１２ａとして、低雑音のプリアンプを用いることが望ましい。 The amplifier circuit 12a receives the output voltage of the SQUID 11 and the bias voltage Vb generated by the bias power supply 12b, and amplifies the output voltage of the SQUID 11. In order to detect a minute change in the magnetic field φ, it is desirable to use a low-noise preamplifier as the amplifier circuit 12a.
　積分回路１２ｃ，１２ｄは、増幅回路１２ａの出力電圧を時間積分することで平滑化する機能をもつ。
　積分回路１２ｃは、時定数τ１を有し、増幅回路１２ａの出力信号を時間積分した積分信号を出力する。 The integration circuits 12c and 12d have a function of smoothing the output voltage of the amplification circuit 12a by time integration.
The integration circuit 12c has a time constant τ1, and outputs an integration signal obtained by time-integrating the output signal of the amplification circuit 12a.
　積分回路１２ｄは、時定数τ１よりも小さい時定数τ２を有し、増幅回路１２ａの出力端子にスイッチ１２ｅを介して接続されている。つまり、積分回路１２ｄには、増幅回路１２ａの出力電圧がスイッチ１２ｅを介して供給される。積分回路１２ｄは、スイッチ１２ｅがオンのときに増幅回路１２ａの出力電圧を時間積分した積分信号を出力する。 The integrating circuit 12d has a time constant τ2 smaller than the time constant τ1, and is connected to the output terminal of the amplifier circuit 12a via the switch 12e. That is, the output voltage of the amplifier circuit 12a is supplied to the integrating circuit 12d via the switch 12e. The integration circuit 12d outputs an integration signal obtained by time-integrating the output voltage of the amplification circuit 12a when the switch 12e is on.
　制御回路１２ｆは、ＳＱＵＩＤ１１の出力電圧の変化の速さを表す値（たとえば、後述の正の微分値または負の微分値の絶対値）が閾値よりも大きい場合に積分回路１２ｄを動
作させる。また、制御回路１２ｆは、出力電圧の変化の速さを表す値が閾値よりも小さい場合に積分回路１２ｄの動作を停止する。 The control circuit 12f operates the integration circuit 12d when a value indicating the speed of change of the output voltage of the SQUID 11 (for example, a positive differential value or an absolute value of a negative differential value described later) is larger than a threshold value. Further, the control circuit 12f stops the operation of the integrating circuit 12d when the value indicating the change speed of the output voltage is smaller than the threshold value.
　図１の例では、制御回路１２ｆは、出力電圧の変化の速さを表す値が閾値よりも大きい場合にスイッチ１２ｅをオンすることで積分回路１２ｄを動作させる。また、制御回路１２ｆは、出力電圧の変化の速さを表す値が閾値よりも小さい場合にスイッチ１２ｅをオフすることで積分回路１２ｄの動作を停止する。 In the example of FIG. 1, the control circuit 12f operates the integration circuit 12d by turning on the switch 12e when the value indicating the change speed of the output voltage is larger than the threshold value. In addition, the control circuit 12f stops the operation of the integrating circuit 12d by turning off the switch 12e when the value indicating the change speed of the output voltage is smaller than the threshold value.
　制御回路１２ｆは、たとえば、ＳＱＵＩＤ１１の出力電圧を時間微分することで、出力電圧の変化の速さを表す値を求める。ＳＱＵＩＤ１１の出力電圧が上昇するときには、正の微分値が得られ、ＳＱＵＩＤ１１の出力電圧が下降するときには、負の微分値が得られる。制御回路１２ｆは、たとえば、正の微分値または負の微分値の絶対値が、閾値よりも大きい場合にスイッチ１２ｅをオンし、正の微分値または負の微分値の絶対値が、閾値よりも小さい場合にスイッチ１２ｅをオフする。なお、制御回路１２ｆは、負の微分値が、負の閾値よりも小さい場合に、スイッチ１２ｅをオンし、負の微分値が、負の閾値よりも大きい場合に、スイッチ１２ｅをオフするようにしてもよい。 The control circuit 12f obtains a value representing the speed of change of the output voltage by, for example, differentiating the output voltage of the SQUID 11 with time. When the output voltage of SQUID 11 increases, a positive differential value is obtained, and when the output voltage of SQUID 11 decreases, a negative differential value is obtained. For example, when the absolute value of the positive differential value or the negative differential value is larger than the threshold value, the control circuit 12f turns on the switch 12e, and the absolute value of the positive differential value or the negative differential value is smaller than the threshold value. If it is smaller, the switch 12e is turned off. The control circuit 12f turns on the switch 12e when the negative differential value is smaller than the negative threshold value, and turns off the switch 12e when the negative differential value is larger than the negative threshold value. May be.
　これによって、制御回路１２ｆは、ＳＱＵＩＤ１１の出力電圧の正側への急速な変化と、負側への急速な変化を検出した場合に、積分回路１２ｄを動作させることができる。制御回路１２ｆは、たとえば、微分回路と比較回路を用いて実現できる（図３参照）。 Thereby, the control circuit 12f can operate the integrating circuit 12d when detecting a rapid change of the output voltage of the SQUID 11 to the positive side and a rapid change to the negative side. The control circuit 12f can be realized using, for example, a differentiation circuit and a comparison circuit (see FIG. 3).
　なお、図１の例では、制御回路１２ｆには、ＳＱＵＩＤ１１が出力する出力電圧が入力されているが、制御回路１２ｆは、増幅回路１２ａの出力信号に基づいて、スイッチ１２ｅを制御してもよい。 In the example of FIG. 1, the output voltage output from the SQUID 11 is input to the control circuit 12f. However, the control circuit 12f may control the switch 12e based on the output signal of the amplifier circuit 12a. .
　コイル１２ｉの一端は、抵抗１２ｇを介して積分回路１２ｃの出力端子に接続されているとともに、抵抗１２ｈを介して積分回路１２ｄの出力端子に接続されている。コイル１２ｉの他端は接地されている。コイル１２ｉは、積分回路１２ｃまたは積分回路１２ｄが出力する積分信号に基づいて、ＳＱＵＩＤ１１に供給する帰還磁束φｆを発生する。 One end of the coil 12i is connected to the output terminal of the integrating circuit 12c through the resistor 12g, and is connected to the output terminal of the integrating circuit 12d through the resistor 12h. The other end of the coil 12i is grounded. The coil 12i generates a feedback magnetic flux φf to be supplied to the SQUID 11 based on the integration signal output from the integration circuit 12c or the integration circuit 12d.
　スイッチ１２ｊは、制御回路１２ｆが出力する制御信号に基づいて、積分回路１２ｃと積分回路１２ｄが出力する積分信号の一方を、ＡＤ変換回路１３に供給する。制御回路１２ｆがスイッチ１２ｅをオンするときには、スイッチ１２ｊは、積分回路１２ｄとＡＤ変換回路１３とを接続し、積分回路１２ｃとＡＤ変換回路１３との接続を切断する。制御回路１２ｆがスイッチ１２ｅをオフするときには、スイッチ１２ｊは、積分回路１２ｄとＡＤ変換回路１３との接続を切断し、積分回路１２ｃとＡＤ変換回路１３とを接続する。 The switch 12j supplies one of the integration signals output from the integration circuit 12c and the integration circuit 12d to the AD conversion circuit 13 based on the control signal output from the control circuit 12f. When the control circuit 12f turns on the switch 12e, the switch 12j connects the integration circuit 12d and the AD conversion circuit 13, and disconnects the integration circuit 12c and the AD conversion circuit 13. When the control circuit 12f turns off the switch 12e, the switch 12j disconnects the integration circuit 12d and the AD conversion circuit 13 and connects the integration circuit 12c and the AD conversion circuit 13.
　なお、スイッチ１２ｅやスイッチ１２ｊは、たとえば、ＭＯＳＦＥＴ（Metal-Oxide Semiconductor Field Effect Transistor）を用いて実現できる。
　スイッチ１２ｅとしてｎチャネル型ＭＯＳＦＥＴ（以下ｎＭＯＳと略す）を用いた場合、ｎＭＯＳのソース端子またはドレイン端子の一方が、増幅回路１２ａの出力端子に接続され、他方が積分回路１２ｄに接続され、ゲート端子が制御回路１２ｆに接続される。そして、制御回路１２ｆが出力する制御信号の論理レベルがＨ（High）レベルの場合に、ｎＭＯＳがオン状態となり、制御信号の論理レベルがＬ（Low）レベルの場合に、ｎＭＯＳがオフ状態となる。 The switch 12e and the switch 12j can be realized using, for example, a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor).
When an n-channel MOSFET (hereinafter abbreviated as nMOS) is used as the switch 12e, one of the source terminal or the drain terminal of the nMOS is connected to the output terminal of the amplifier circuit 12a, the other is connected to the integrating circuit 12d, and the gate terminal Is connected to the control circuit 12f. When the logic level of the control signal output from the control circuit 12f is H (High) level, the nMOS is turned on. When the logic level of the control signal is L (Low) level, the nMOS is turned off. .
　スイッチ１２ｊとして、ｎＭＯＳとｐチャネル型ＭＯＳＦＥＴ（以下ｐＭＯＳと略す）を用いることができる。その場合、ｐＭＯＳのソース端子またはドレイン端子の一方が、積分回路１２ｃに接続され、他方がＡＤ変換回路１３に接続され、ゲート端子が制御回路１２ｆに接続される。また、ｎＭＯＳのソース端子またはドレイン端子の一方が、積分回
路１２ｄに接続され、他方がＡＤ変換回路１３に接続され、ゲート端子が制御回路１２ｆに接続される。そして、制御回路１２ｆが出力する制御信号の論理レベルがＨレベルの場合に、ｎＭＯＳがオン状態、ｐＭＯＳがオフ状態となり、制御信号の論理レベルがＬレベルの場合に、ｎＭＯＳがオフ状態、ｐＭＯＳがオン状態となる。 As the switch 12j, an nMOS and a p-channel MOSFET (hereinafter abbreviated as pMOS) can be used. In that case, one of the source terminal or the drain terminal of the pMOS is connected to the integration circuit 12c, the other is connected to the AD conversion circuit 13, and the gate terminal is connected to the control circuit 12f. Also, one of the source terminal or the drain terminal of the nMOS is connected to the integrating circuit 12d, the other is connected to the AD conversion circuit 13, and the gate terminal is connected to the control circuit 12f. When the logic level of the control signal output from the control circuit 12f is H level, the nMOS is turned on and the pMOS is turned off. When the logic level of the control signal is L level, the nMOS is turned off and the pMOS is turned on. Turns on.
　なお、ＡＤ変換回路１３が、制御回路１２ｆが出力する制御信号に基づいて、積分回路１２ｃが出力する積分信号と、積分回路１２ｄが出力する積分信号の一方を選択してＡＤ変換してもよい。その場合、スイッチ１２ｊはなくてもよい。 The AD conversion circuit 13 may select one of the integration signal output from the integration circuit 12c and the integration signal output from the integration circuit 12d based on the control signal output from the control circuit 12f and perform AD conversion. . In that case, the switch 12j may not be provided.
　また、たとえば、ＳＱＵＩＤ１１の出力電圧がある程度大きく、積分回路１２ｃ，１２ｄが、検出結果（アナログ値）として適切な大きさの積分信号を出力する場合、増幅回路１２ａはなくてもよい。その場合、ＳＱＵＩＤ１１の出力電圧が、積分回路１２ｃに供給されるとともに、スイッチ１２ｅを介して積分回路１２ｄに供給される。 For example, when the output voltage of the SQUID 11 is large to some extent and the integration circuits 12c and 12d output an integration signal having an appropriate magnitude as a detection result (analog value), the amplification circuit 12a may be omitted. In that case, the output voltage of the SQUID 11 is supplied to the integrating circuit 12c and also supplied to the integrating circuit 12d via the switch 12e.
　なお、図示を省略しているが、たとえば、ＳＱＵＩＤ１１とコイル１２ｉは、液体窒素によりＳＱＵＩＤ１１を冷却する冷却装置（たとえば、デュワー冷却器）内に設けられる。 In addition, although illustration is abbreviate | omitted, for example, SQUID11 and the coil 12i are provided in the cooling device (for example, Dewar cooler) which cools SQUID11 with liquid nitrogen.
　（積分回路１２ｃ，１２ｄの一例）
　図２は、積分回路の一例を示す図である。
　図２では、積分回路１２ｄの例が示されているが、積分回路１２ｃについても同様の回路構成で実現できる。 (Example of integration circuits 12c and 12d)
FIG. 2 is a diagram illustrating an example of the integration circuit.
Although FIG. 2 shows an example of the integrating circuit 12d, the integrating circuit 12c can also be realized with the same circuit configuration.
　積分回路１２ｄは、入力端子１２ｄ１、抵抗１２ｄ２、キャパシタ１２ｄ３、オペアンプ１２ｄ４、出力端子１２ｄ５を有する。
　抵抗１２ｄ２の一端は入力端子１２ｄ１に接続されており、抵抗１２ｄ２の他端は、キャパシタ１２ｄ３の一端及び、オペアンプ１２ｄ４の反転入力端子（“－”と表記されている）に接続されている。キャパシタ１２ｄ３の他端は、出力端子１２ｄ５及びオペアンプ１２ｄ４の出力端子に接続されている。オペアンプ１２ｄ４の非反転入力端子（“＋”と表記されている）は、接地されている。 The integrating circuit 12d has an input terminal 12d1, a resistor 12d2, a capacitor 12d3, an operational amplifier 12d4, and an output terminal 12d5.
One end of the resistor 12d2 is connected to the input terminal 12d1, and the other end of the resistor 12d2 is connected to one end of the capacitor 12d3 and the inverting input terminal (denoted as “−”) of the operational amplifier 12d4. The other end of the capacitor 12d3 is connected to the output terminal 12d5 and the output terminal of the operational amplifier 12d4. A non-inverting input terminal (denoted as “+”) of the operational amplifier 12d4 is grounded.
　このような積分回路１２ｄでは、入力端子１２ｄ１から入力される増幅回路１２ａの出力信号を時間積分した積分信号が、出力端子１２ｄ５から出力される。抵抗１２ｄ２の抵抗値をＲ、キャパシタ１２ｄ３のキャパシタンスをＣとすると、積分回路１２ｄの時定数τ２は、Ｒ×Ｃである。 In such an integration circuit 12d, an integration signal obtained by time-integrating the output signal of the amplification circuit 12a input from the input terminal 12d1 is output from the output terminal 12d5. When the resistance value of the resistor 12d2 is R and the capacitance of the capacitor 12d3 is C, the time constant τ2 of the integrating circuit 12d is R × C.
　（制御回路１２ｆの一例）
　図３は、制御回路の一例を示す図である。
　制御回路１２ｆは、微分回路１２ｆ１と比較回路１２ｆ２を有する。 (Example of control circuit 12f)
FIG. 3 is a diagram illustrating an example of the control circuit.
The control circuit 12f includes a differentiation circuit 12f1 and a comparison circuit 12f2.
　微分回路１２ｆ１は、ＳＱＵＩＤ１１の出力電圧の変化の速さを表す微分値（出力電圧の変化に比例した値）を出力する。
　比較回路１２ｆ２は、微分回路１２ｆ１が出力する微分値が正で、正の閾値よりも大きいか、微分値が負で、負の閾値よりも小さい場合に、スイッチ１２ｅをオンする制御信号を出力する。微分値が正で、正の閾値よりも小さいか、微分値が負で、負の閾値よりも大きい場合に、比較回路１２ｆ２は、スイッチ１２ｅをオフする制御信号を出力する。 The differentiating circuit 12f1 outputs a differential value (a value proportional to the change of the output voltage) indicating the speed of change of the output voltage of the SQUID 11.
The comparison circuit 12f2 outputs a control signal for turning on the switch 12e when the differentiation value output from the differentiation circuit 12f1 is positive and larger than a positive threshold value or when the differentiation value is negative and smaller than a negative threshold value. . When the differential value is positive and smaller than the positive threshold value or the differential value is negative and larger than the negative threshold value, the comparison circuit 12f2 outputs a control signal for turning off the switch 12e.
　図４は、微分回路の一例を示す図である。
　微分回路１２ｆ１は、入力端子１２ｆ１１、キャパシタ１２ｆ１２、抵抗１２ｆ１３、オペアンプ１２ｆ１４、出力端子１２ｆ１５を有する。 FIG. 4 is a diagram illustrating an example of a differentiation circuit.
The differentiation circuit 12f1 has an input terminal 12f11, a capacitor 12f12, a resistor 12f13, an operational amplifier 12f14, and an output terminal 12f15.
　キャパシタ１２ｆ１２の一端は入力端子１２ｆ１１に接続されており、キャパシタ１２ｆ１２の他端は、抵抗１２ｆ１３の一端及び、オペアンプ１２ｆ１４の反転入力端子に接続されている。抵抗１２ｆ１３の他端は、出力端子１２ｆ１５及びオペアンプ１２ｆ１４の出力端子に接続されている。オペアンプ１２ｆ１４の非反転入力端子は、接地されている。 One end of the capacitor 12f12 is connected to the input terminal 12f11, and the other end of the capacitor 12f12 is connected to one end of the resistor 12f13 and the inverting input terminal of the operational amplifier 12f14. The other end of the resistor 12f13 is connected to the output terminal 12f15 and the output terminal of the operational amplifier 12f14. The non-inverting input terminal of the operational amplifier 12f14 is grounded.
　このような微分回路１２ｆ１では、入力端子１２ｆ１１から入力されるＳＱＵＩＤ１１の出力電圧を時間微分した微分値が、出力端子１２ｆ１５から出力される。
　図５は、比較回路の一例を示す図である。 In such a differentiation circuit 12f1, a differential value obtained by time-differentiating the output voltage of the SQUID 11 input from the input terminal 12f11 is output from the output terminal 12f15.
FIG. 5 is a diagram illustrating an example of the comparison circuit.
　比較回路１２ｆ２は、入力端子１２ｆ２１、比較回路１２ｆ２２，１２ｆ２３、ＯＲ回路１２ｆ２４、出力端子１２ｆ２５を有する。
　比較回路１２ｆ２２は、入力端子１２ｆ２１から入力される微分値と、正の閾値Ｖｒｅｆ＋とを比較し、微分値が、閾値Ｖｒｅｆ＋よりも大きい場合に、論理レベルがＨレベルの電圧を出力する。それ以外の場合には、比較回路１２ｆ２２は、論理レベルがＬレベルの電圧を出力する。 The comparison circuit 12f2 has an input terminal 12f21, comparison circuits 12f22 and 12f23, an OR circuit 12f24, and an output terminal 12f25.
The comparison circuit 12f22 compares the differential value input from the input terminal 12f21 with the positive threshold value Vref +, and outputs a voltage having a logic level of H level when the differential value is greater than the threshold value Vref +. In other cases, the comparison circuit 12f22 outputs a voltage having a logic level of L level.
　比較回路１２ｆ２３は、入力端子１２ｆ２１から入力される微分値と、負の閾値Ｖｒｅｆ－とを比較し、微分値が、閾値Ｖｒｅｆ－よりも小さい場合に、論理レベルがＨレベルの電圧を出力する。それ以外の場合には、比較回路１２ｆ２３は、論理レベルがＬレベルの電圧を出力する。 The comparison circuit 12f23 compares the differential value input from the input terminal 12f21 with a negative threshold value Vref−, and outputs a voltage having a logic level of H level when the differential value is smaller than the threshold value Vref−. In other cases, the comparison circuit 12f23 outputs a voltage having a logic level of L level.
　ＯＲ回路１２ｆ２４の一方の入力端子は、比較回路１２ｆ２２の出力端子に接続されており、ＯＲ回路１２ｆ２４の他方の入力端子は、比較回路１２ｆ２３の出力端子に接続されている。ＯＲ回路１２ｆ２４の出力端子は、出力端子１２ｆ２５に接続されている。 One input terminal of the OR circuit 12f24 is connected to the output terminal of the comparison circuit 12f22, and the other input terminal of the OR circuit 12f24 is connected to the output terminal of the comparison circuit 12f23. The output terminal of the OR circuit 12f24 is connected to the output terminal 12f25.
　ＯＲ回路１２ｆ２４は、比較回路１２ｆ２２，１２ｆ２３の少なくとも一方の出力電圧の論理レベルがＨレベルである場合には、Ｈレベルの電圧を、制御信号として出力し、スイッチ１２ｅをオンする。ＯＲ回路１２ｆ２４は、比較回路１２ｆ２２，１２ｆ２３の両方の出力電圧の論理レベルがＬレベルである場合には、Ｌレベルの電圧を、制御信号として出力し、スイッチ１２ｅをオフする。 The OR circuit 12f24 outputs an H level voltage as a control signal and turns on the switch 12e when the logical level of the output voltage of at least one of the comparison circuits 12f22 and 12f23 is the H level. The OR circuit 12f24 outputs the L level voltage as a control signal and turns off the switch 12e when the logical levels of the output voltages of both the comparison circuits 12f22 and 12f23 are L level.
　以下、第１の実施の形態のＳＱＵＩＤセンサ１０の動作例を説明する。
　（ＳＱＵＩＤセンサ１０の動作例）
　図６は、磁場の変化が比較的緩やかな場合のＳＱＵＩＤセンサの動作例を示すタイミングチャートである。 Hereinafter, an operation example of the SQUID sensor 10 according to the first embodiment will be described.
(Operation example of SQUID sensor 10)
FIG. 6 is a timing chart showing an operation example of the SQUID sensor when the change in the magnetic field is relatively gradual.
　図６には、磁場φ、ＳＱＵＩＤ１１の出力電圧、微分回路１２ｆ１の出力電圧（微分値）、比較回路１２ｆ２の出力電圧（制御信号）の時間変化の例が示されている。さらに、時定数τ１の積分回路１２ｃの出力電圧（積分信号）、時定数τ２の積分回路１２ｄの出力電圧（積分信号）の時間変化の例が示されている。 FIG. 6 shows an example of the time change of the magnetic field φ, the output voltage of the SQUID 11, the output voltage (differential value) of the differentiation circuit 12f1, and the output voltage (control signal) of the comparison circuit 12f2. Further, an example of the time change of the output voltage (integrated signal) of the integrating circuit 12c with the time constant τ1 and the output voltage (integrated signal) of the integrating circuit 12d with the time constant τ2 is shown.
　図６の例では、タイミングｔ１からタイミングｔ２の間で磁場φの増加及び減少が生じている。
　磁場φが大きくなり始めると、ＳＱＵＩＤ１１の出力電圧も上昇する。図６の例では、磁場φの変化が比較的緩やかであるため、ＳＱＵＩＤ１１の出力電圧の上昇も緩やかである。このとき、微分回路１２ｆ１の出力電圧（正の微分値）が、閾値Ｖｒｅｆ＋よりも小さくなるため、比較回路１２ｆ２の出力電圧の論理レベルはＬレベルとなり、スイッチ１２ｅはオフする。これにより、積分回路１２ｄは動作せず、積分回路１２ｄの出力電圧は
上昇しない。一方、積分回路１２ｃの出力電圧は、緩やかに上昇する。そして、積分回路１２ｃの出力電圧に基づいて、コイル１２ｉで帰還磁束φｆが発生し、ＳＱＵＩＤ１１にネガティブフィードバックされる。 In the example of FIG. 6, the magnetic field φ increases and decreases between timing t1 and timing t2.
When the magnetic field φ starts to increase, the output voltage of the SQUID 11 also increases. In the example of FIG. 6, since the change of the magnetic field φ is relatively gradual, the increase in the output voltage of the SQUID 11 is also gradual. At this time, since the output voltage (positive differential value) of the differentiation circuit 12f1 becomes smaller than the threshold value Vref +, the logic level of the output voltage of the comparison circuit 12f2 becomes L level, and the switch 12e is turned off. Thereby, the integration circuit 12d does not operate, and the output voltage of the integration circuit 12d does not rise. On the other hand, the output voltage of the integrating circuit 12c rises gently. Based on the output voltage of the integrating circuit 12c, a feedback magnetic flux φf is generated in the coil 12i and negatively fed back to the SQUID 11.
　このネガティブフィードバックの作用によって、磁場φによるＳＱＵＩＤ１１への入力磁束と帰還磁束φｆとが互いに打ち消し合い、ＳＱＵＩＤ１１に鎖交する磁束はゼロになるように（ＳＱＵＩＤ１１の出力電圧がゼロになるように）安定化される。この安定化状態では、積分回路１２ｃの出力電圧は磁場φに比例するようになる。 By this negative feedback action, the input magnetic flux to the SQUID 11 due to the magnetic field φ and the feedback magnetic flux φf cancel each other, and the magnetic flux interlinking with the SQUID 11 becomes zero (so that the output voltage of the SQUID 11 becomes zero). It becomes. In this stabilized state, the output voltage of the integrating circuit 12c is proportional to the magnetic field φ.
　磁場φを時間の関数φ（ｔ）、積分回路１２ｃの出力電圧を時間の関数Ｖｏｕｔ１（ｔ）、抵抗１２ｇの抵抗値をＲｆ１、コイル１２ｉの相互インダクタンスをＭｆとすると、Ｖｏｕｔ１（ｔ）＝（Ｒｆ１／Ｍｆ）・φ（ｔ）となる。 When the magnetic field φ is a function of time φ (t), the output voltage of the integrating circuit 12c is a function of time Vout1 (t), the resistance value of the resistor 12g is Rf1, and the mutual inductance of the coil 12i is Mf, Vout1 (t) = ( Rf1 / Mf) · φ (t).
　磁場φが下がり始めると、ＳＱＵＩＤ１１の出力電圧も下降する。ここでも図６に示すように、磁場φの変化が比較的緩やかであるため、ＳＱＵＩＤ１１の出力電圧の下降も緩やかである。このとき、微分回路１２ｆ１の出力電圧（負の微分値）が、閾値Ｖｒｅｆ－よりも大きくなるため、比較回路１２ｆ２の出力電圧の論理レベルはＬレベルのままとなり、スイッチ１２ｅはオフのままである。これにより、積分回路１２ｄの出力電圧は上昇しない。一方、積分回路１２ｃの出力電圧は、ネガティブフィードバックの作用によって下降する。 When the magnetic field φ starts to drop, the output voltage of the SQUID 11 also drops. Here, as shown in FIG. 6, since the change in the magnetic field φ is relatively gradual, the output voltage drop of the SQUID 11 is also gradual. At this time, since the output voltage (negative differential value) of the differentiation circuit 12f1 becomes larger than the threshold value Vref−, the logic level of the output voltage of the comparison circuit 12f2 remains L level, and the switch 12e remains off. . Thereby, the output voltage of the integrating circuit 12d does not rise. On the other hand, the output voltage of the integrating circuit 12c drops due to the action of negative feedback.
　また、図６の例では、スイッチ１２ｊに対する制御信号となる比較回路１２ｆ２の出力電圧の論理レベルはＬレベルのままであるため、スイッチ１２ｊは、積分回路１２ｃとＡＤ変換回路１３とを接続し、積分回路１２ｄとＡＤ変換回路１３との接続を切断する。このため、ＡＤ変換回路１３は、積分回路１２ｃの出力電圧をデジタル値に変換して、そのデジタル値を磁場φの検出結果として出力する。 In the example of FIG. 6, since the logic level of the output voltage of the comparison circuit 12f2 serving as a control signal for the switch 12j remains L level, the switch 12j connects the integration circuit 12c and the AD conversion circuit 13, The connection between the integration circuit 12d and the AD conversion circuit 13 is disconnected. Therefore, the AD conversion circuit 13 converts the output voltage of the integration circuit 12c into a digital value and outputs the digital value as a detection result of the magnetic field φ.
　このように、磁場φの変化が比較的緩やかである場合には、積分回路１２ｄよりも時定数が大きい積分回路１２ｃを用いることで、ＳＮ（Signal-Noise）比が大きくなり、微小な磁場φでも高感度に検出できるようになる。つまり、ＳＱＵＩＤセンサ１０の検出感度を向上できる。 Thus, when the change of the magnetic field φ is relatively gradual, by using the integration circuit 12c having a larger time constant than the integration circuit 12d, the SN (Signal-Noise) ratio becomes large, and the minute magnetic field φ. But it can be detected with high sensitivity. That is, the detection sensitivity of the SQUID sensor 10 can be improved.
　図７は、磁場の変化が比較的速い場合のＳＱＵＩＤセンサの動作例を示すタイミングチャートである。
　図７には、図６と同様に、磁場φ、ＳＱＵＩＤ１１の出力電圧、微分回路１２ｆ１の出力電圧、比較回路１２ｆ２の出力電圧、時定数τ１の積分回路１２ｃの出力電圧、時定数τ２の積分回路１２ｄの出力電圧の時間変化の例が示されている。 FIG. 7 is a timing chart illustrating an operation example of the SQUID sensor when the change in the magnetic field is relatively fast.
7, similarly to FIG. 6, the magnetic field φ, the output voltage of the SQUID 11, the output voltage of the differentiation circuit 12 f 1, the output voltage of the comparison circuit 12 f 2, the output voltage of the integration circuit 12 c of the time constant τ 1, and the integration circuit of the time constant τ 2 An example of the time variation of the 12d output voltage is shown.
　図７の例では、タイミングｔ３からタイミングｔ４の間で磁場φの増加及び減少が生じている。図７の例では、図６の例よりも磁場φが短い時間で変化している。
　磁場φが大きくなり始めると、ＳＱＵＩＤ１１の出力電圧も上昇する。磁場φの変化が図６の場合と比べて速いため、ＳＱＵＩＤ１１の出力電圧の上昇も、図６の場合と比べて速い。このとき、図７の例では、微分回路１２ｆ１の出力電圧（正の微分値）が、閾値Ｖｒｅｆ＋よりも大きくなっており、比較回路１２ｆ２の出力電圧の論理レベルはＨレベルとなり、スイッチ１２ｅはオンする。これにより、積分回路１２ｄが動作し、積分回路１２ｄの出力電圧が上昇する。また、積分回路１２ｃの出力電圧も緩やかに上昇する。 In the example of FIG. 7, the magnetic field φ increases and decreases between timing t3 and timing t4. In the example of FIG. 7, the magnetic field φ changes in a shorter time than the example of FIG.
When the magnetic field φ starts to increase, the output voltage of the SQUID 11 also increases. Since the change of the magnetic field φ is faster than that in the case of FIG. 6, the increase of the output voltage of the SQUID 11 is also faster than that in the case of FIG. At this time, in the example of FIG. 7, the output voltage (positive differential value) of the differentiating circuit 12f1 is larger than the threshold value Vref +, the logic level of the output voltage of the comparing circuit 12f2 is H level, and the switch 12e is turned on. To do. As a result, the integrating circuit 12d operates and the output voltage of the integrating circuit 12d increases. Further, the output voltage of the integrating circuit 12c also rises gently.
　積分回路１２ｄの時定数τ２は、積分回路１２ｃの時定数τ１よりも小さいため、積分回路１２ｄの出力電圧が上昇する速さは、積分回路１２ｃの出力電圧が上昇する速さよりも速い。そのため、コイル１２ｉでは、主に、積分回路１２ｄの出力電圧に基づいた帰還
磁束φｆが発生し、ＳＱＵＩＤ１１にネガティブフィードバックされる。 Since the time constant τ2 of the integrating circuit 12d is smaller than the time constant τ1 of the integrating circuit 12c, the speed at which the output voltage of the integrating circuit 12d increases is faster than the speed at which the output voltage of the integrating circuit 12c increases. Therefore, in the coil 12i, a feedback magnetic flux φf based mainly on the output voltage of the integrating circuit 12d is generated and negatively fed back to the SQUID 11.
　このネガティブフィードバックの作用によって、積分回路１２ｄの出力電圧は磁場φに比例するようになる。磁場φを時間の関数φ（ｔ）、積分回路１２ｄの出力電圧を時間の関数Ｖｏｕｔ２（ｔ）、抵抗１２ｈの抵抗値をＲｆ２、コイル１２ｉの相互インダクタンスをＭｆとすると、Ｖｏｕｔ２（ｔ）＝（Ｒｆ２／Ｍｆ）・φ（ｔ）となる。 The output voltage of the integrating circuit 12d becomes proportional to the magnetic field φ by the action of this negative feedback. When the magnetic field φ is a function of time φ (t), the output voltage of the integrating circuit 12d is a function of time Vout2 (t), the resistance value of the resistor 12h is Rf2, and the mutual inductance of the coil 12i is Mf, Vout2 (t) = ( Rf2 / Mf) · φ (t).
　磁場φの変化が小さくなると、微分回路１２ｆ１の出力電圧が閾値Ｖｒｅｆ＋よりも小さくなる。このため、比較回路１２ｆ２の出力電圧の論理レベルがＬレベルとなり、スイッチ１２ｅはオフする。しかし、図７の例では、図６の例と比べて、すぐに磁場φが減少し始め、微分回路１２ｆ１の出力電圧（負の微分値）が、閾値Ｖｒｅｆ－よりも小さくなっている。このため、比較回路１２ｆ２の出力電圧の論理レベルが再びＨレベルとなり、スイッチ１２ｅは再びオンする。これにより、積分回路１２ｄの出力電圧は、入力磁場の減少に対応して、下降していく。 When the change in the magnetic field φ becomes small, the output voltage of the differentiating circuit 12f1 becomes smaller than the threshold value Vref +. For this reason, the logic level of the output voltage of the comparison circuit 12f2 becomes L level, and the switch 12e is turned off. However, in the example of FIG. 7, compared with the example of FIG. 6, the magnetic field φ starts to decrease immediately, and the output voltage (negative differential value) of the differentiating circuit 12f1 is smaller than the threshold value Vref−. For this reason, the logic level of the output voltage of the comparison circuit 12f2 becomes H level again, and the switch 12e is turned on again. As a result, the output voltage of the integrating circuit 12d decreases corresponding to the decrease in the input magnetic field.
　また、図７の例では、スイッチ１２ｊに対する制御信号となる比較回路１２ｆ２の出力電圧の論理レベルは、磁場φが変化するタイミングｔ３からタイミングｔ４の期間では、ほとんどＨレベルである。そのため、スイッチ１２ｊは、タイミングｔ３からタイミングｔ４のほとんどの期間で積分回路１２ｄとＡＤ変換回路１３とを接続し、積分回路１２ｃとＡＤ変換回路１３との接続を切断する。このため、ＡＤ変換回路１３は、主に積分回路１２ｄの出力電圧をデジタル値に変換して、そのデジタル値を磁場φの検出結果として出力する。 Further, in the example of FIG. 7, the logic level of the output voltage of the comparison circuit 12f2 serving as a control signal for the switch 12j is almost H level during the period from the timing t3 to the timing t4 when the magnetic field φ changes. Therefore, the switch 12j connects the integration circuit 12d and the AD conversion circuit 13 during most of the period from the timing t3 to the timing t4, and disconnects the connection between the integration circuit 12c and the AD conversion circuit 13. Therefore, the AD conversion circuit 13 mainly converts the output voltage of the integration circuit 12d into a digital value, and outputs the digital value as a detection result of the magnetic field φ.
　図７に示すように、積分回路１２ｃの出力電圧は、磁場φの急速な変化に追従できていないが、積分回路１２ｄの出力電圧は、磁場φの急速な変化に追従できている。
　このように、ＦＬＬ回路１２に時定数が異なる複数の積分回路１２ｃ，１２ｄを設け、磁場変化が急な場合に時定数τ２の積分回路１２ｄを動作させる（高速帰還パスを機能させる）ことで、磁場変化への追従性が向上し、磁場検出の安定性が向上する。つまり、磁場変化への追従性が向上することで、ＳＱＵＩＤセンサ１０の応答速度（スルーレート）が向上し、急激に変化する磁場φを安定に検出できる。なお、スルーレートは、追従可能な磁場の時間変化の最大値で表せる。 As shown in FIG. 7, the output voltage of the integrating circuit 12c cannot follow the rapid change of the magnetic field φ, but the output voltage of the integrating circuit 12d can follow the rapid change of the magnetic field φ.
In this way, by providing the FLL circuit 12 with a plurality of integration circuits 12c and 12d having different time constants, and operating the integration circuit 12d with the time constant τ2 when the magnetic field change is sudden (to make the high-speed feedback path function), The followability to magnetic field changes is improved, and the stability of magnetic field detection is improved. That is, by improving the followability to the magnetic field change, the response speed (slew rate) of the SQUID sensor 10 is improved, and the rapidly changing magnetic field φ can be detected stably. The slew rate can be expressed by the maximum value of the time change of the magnetic field that can be followed.
　また、前述のように磁場φの変化が比較的緩やかな場合には、時定数τ１の積分回路１２ｃの動作により、ＳＱＵＩＤセンサ１０の検出感度を向上できるため、第１の実施の形態のＳＱＵＩＤセンサ１０によれば、高感度で安定な磁場検出が実現できる。 In addition, when the change in the magnetic field φ is relatively gradual as described above, the detection sensitivity of the SQUID sensor 10 can be improved by the operation of the integration circuit 12c with the time constant τ1, and thus the SQUID sensor of the first embodiment. 10 can realize a highly sensitive and stable magnetic field detection.
　たとえば、時定数τ２が、時定数τ１の１／４であるとする。また、積分回路１２ｄを用いずに１つの積分回路１２ｃを用いて磁場検出を行う場合のスルーレートが１０ｍＴ／ｓｅｃ、検出感度が１５ｆＴ／Ｈｚ1/2であるとする。このような場合、図７に示したよ
うな急激な磁場変化が生じたときに積分回路１２ｃの他に積分回路１２ｄをさらに動作させることで、スルーレートを４０ｍＴ／ｓｅｃ、検出感度を２５ｆＴ／Ｈｚ1/2とするこ
とができる。つまり、検出感度を悪化させることなく、４倍の高スルーレート特性を実現できる。これは、たとえば、ＳＱＵＩＤセンサ１０を鉱床探査に用いた場合、探査時間を１／４に短縮できることを意味し、探査効率を向上できる。 For example, it is assumed that the time constant τ2 is ¼ of the time constant τ1. Further, it is assumed that the slew rate is 10 mT / sec and the detection sensitivity is 15 fT / Hz 1/2 when magnetic field detection is performed using one integration circuit 12 c without using the integration circuit 12 d. In such a case, the slew rate is set to 40 mT / sec and the detection sensitivity is set to 25 fT / Hz by further operating the integration circuit 12d in addition to the integration circuit 12c when a sudden magnetic field change as shown in FIG. 7 occurs. It can be 1/2 . That is, a four times higher slew rate characteristic can be realized without deteriorating the detection sensitivity. This means that, for example, when the SQUID sensor 10 is used for ore exploration, the exploration time can be reduced to ¼, and exploration efficiency can be improved.
　なお、上記の例では、微分回路１２ｆ１の出力電圧が閾値Ｖｒｅｆ＋よりも大きい場合、または閾値Ｖｒｅｆ－よりも小さい場合でも、積分回路１２ｃを動作させるものとしたが、積分回路１２ｃを動作させないようにしてもよい。その場合、増幅回路１２ａの出力端子と、積分回路１２ｃとの間にスイッチが設けられ、制御回路１２ｆは、スイッチ１２ｅをオンするときには、そのスイッチをオフする。 In the above example, the integrating circuit 12c is operated even when the output voltage of the differentiating circuit 12f1 is larger than the threshold value Vref + or smaller than the threshold value Vref−. However, the integrating circuit 12c is not operated. May be. In that case, a switch is provided between the output terminal of the amplifier circuit 12a and the integrating circuit 12c, and the control circuit 12f turns off the switch when turning on the switch 12e.
　また、上記の例では、ＳＱＵＩＤ１１に直接、磁場φが入力されるものとして説明したが、磁場φを検出する検出コイルと、検出コイルが検出した磁場φに基づいて信号磁束を発生しＳＱＵＩＤ１１に供給する入力コイルを用いることもできる。 In the above example, the magnetic field φ is directly input to the SQUID 11. However, the detection coil that detects the magnetic field φ and the signal magnetic flux based on the magnetic field φ detected by the detection coil are generated and supplied to the SQUID 11. An input coil can be used.
　また、上記の例では、２つの積分回路１２ｃ，１２ｄを有するＦＬＬ回路１２を示したが、積分回路の数は、２つに限定されず、３つ以上であってもよい。以下その例を説明する。 In the above example, the FLL circuit 12 including the two integration circuits 12c and 12d is shown. However, the number of integration circuits is not limited to two, and may be three or more. Examples thereof will be described below.
　（第２の実施の形態）
　図８は、第２の実施の形態のＳＱＵＩＤセンサ及びＦＬＬ回路の一例を示す図である。
　ＳＱＵＩＤセンサ２０は、ＳＱＵＩＤ２１、ＦＬＬ回路２２、ＡＤ変換回路２３を有する。 (Second Embodiment)
FIG. 8 is a diagram illustrating an example of the SQUID sensor and the FLL circuit according to the second embodiment.
The SQUID sensor 20 includes a SQUID 21, an FLL circuit 22, and an AD conversion circuit 23.
　ＳＱＵＩＤ２１は、入力される磁場φと、帰還磁束φｆとに基づいた出力電圧を出力する。
　ＦＬＬ回路２２は、ＳＱＵＩＤ２１の出力電圧を安定化する回路である。 The SQUID 21 outputs an output voltage based on the input magnetic field φ and the feedback magnetic flux φf.
The FLL circuit 22 is a circuit that stabilizes the output voltage of the SQUID 21.
　ＡＤ変換回路２３は、ＦＬＬ回路２２の出力電圧をＡＤ変換し、磁場φの検出結果としてデジタル値を出力する。
　ＦＬＬ回路２２は、増幅回路２２ａ、バイアス電源２２ｂ、積分回路２２ｃ，２２ｄ，２２ｅ、スイッチ２２ｆ，２２ｇ、制御回路２２ｈ、抵抗２２ｉ，２２ｊ，２２ｋ、コイル２２ｌを有する。 The AD conversion circuit 23 AD-converts the output voltage of the FLL circuit 22 and outputs a digital value as a detection result of the magnetic field φ.
The FLL circuit 22 includes an amplifier circuit 22a, a bias power source 22b, integration circuits 22c, 22d, and 22e, switches 22f and 22g, a control circuit 22h, resistors 22i, 22j, and 22k, and a coil 22l.
　増幅回路２２ａは、ＳＱＵＩＤ２１の出力電圧と、バイアス電源２２ｂが生成するバイアス電圧Ｖｂを受け、ＳＱＵＩＤ２１の出力電圧を増幅する。微小な磁場φの変化を検出するために、増幅回路２２ａとして、低雑音のプリアンプを用いることが望ましい。 The amplification circuit 22a receives the output voltage of the SQUID 21 and the bias voltage Vb generated by the bias power supply 22b, and amplifies the output voltage of the SQUID 21. In order to detect a minute change in the magnetic field φ, it is desirable to use a low-noise preamplifier as the amplifier circuit 22a.
　積分回路２２ｃ，２２ｄ，２２ｅは、増幅回路２２ａの出力信号を時間積分することで平滑化する機能をもつ。
　積分回路２２ｃは、時定数τ３を有し、増幅回路２２ａの出力信号を時間積分した積分信号を出力する。 The integration circuits 22c, 22d, and 22e have a function of smoothing the output signal of the amplification circuit 22a by time integration.
The integration circuit 22c has a time constant τ3 and outputs an integration signal obtained by time-integrating the output signal of the amplification circuit 22a.
　積分回路２２ｄは、時定数τ３よりも小さい時定数τ４を有し、増幅回路２２ａの出力端子にスイッチ２２ｆを介して接続されている。つまり、積分回路２２ｄには、増幅回路２２ａの出力電圧がスイッチ２２ｆを介して供給される。積分回路２２ｄは、スイッチ２２ｆがオンのときに増幅回路２２ａの出力信号を時間積分した積分信号を出力する。 The integrating circuit 22d has a time constant τ4 smaller than the time constant τ3, and is connected to the output terminal of the amplifying circuit 22a via a switch 22f. That is, the output voltage of the amplification circuit 22a is supplied to the integration circuit 22d via the switch 22f. The integration circuit 22d outputs an integration signal obtained by time-integrating the output signal of the amplification circuit 22a when the switch 22f is on.
　積分回路２２ｅは、時定数τ４よりも小さい時定数τ５を有し、増幅回路２２ａの出力端子にスイッチ２２ｇを介して接続されている。つまり、積分回路２２ｅには、増幅回路２２ａの出力電圧がスイッチ２２ｇを介して供給される。積分回路２２ｅは、スイッチ２２ｇがオンのときに増幅回路２２ａの出力信号を時間積分した積分信号を出力する。 The integrating circuit 22e has a time constant τ5 smaller than the time constant τ4, and is connected to the output terminal of the amplifying circuit 22a via a switch 22g. That is, the output voltage of the amplification circuit 22a is supplied to the integration circuit 22e via the switch 22g. The integration circuit 22e outputs an integration signal obtained by time-integrating the output signal of the amplification circuit 22a when the switch 22g is on.
　制御回路２２ｈは、ＳＱＵＩＤ１１の出力電圧の変化の速さを表す値（たとえば、前述の正の微分値または負の微分値の絶対値）が大きくなるほど、複数の積分回路２２ｃ～２２ｅのうち、小さい時定数を有する積分回路を動作させる。 The control circuit 22h has a smaller value among the plurality of integration circuits 22c to 22e as the value indicating the speed of change of the output voltage of the SQUID 11 (for example, the absolute value of the positive differential value or the negative differential value) increases. An integration circuit having a time constant is operated.
　第２の実施の形態のＦＬＬ回路２２において、制御回路２２ｈは、微分回路２２ｈ１、比較回路２２ｈ２，２２ｈ３を有する。
　微分回路２２ｈ１は、ＳＱＵＩＤ２１の出力電圧を時間微分することで、出力電圧の変
化の速さを表す値を求める。ＳＱＵＩＤ２１の出力電圧が上昇するときには、正の微分値が得られ、ＳＱＵＩＤ２１の出力電圧が下降するときには、負の微分値が得られる。微分回路２２ｈ１は、図４に示した微分回路１２ｆ１と同様の回路で実現できる。 In the FLL circuit 22 of the second embodiment, the control circuit 22h includes a differentiation circuit 22h1 and comparison circuits 22h2 and 22h3.
The differentiating circuit 22h1 obtains a value representing the speed of change of the output voltage by time-differentiating the output voltage of the SQUID 21. When the output voltage of the SQUID 21 increases, a positive differential value is obtained, and when the output voltage of the SQUID 21 decreases, a negative differential value is obtained. The differentiation circuit 22h1 can be realized by a circuit similar to the differentiation circuit 12f1 shown in FIG.
　比較回路２２ｈ２は、微分回路２２ｈ１が出力する正の微分値が、正の閾値Ｖｒｅｆ１＋よりも大きいか、負の微分値が、負の閾値Ｖｒｅｆ１－よりも小さい場合に、スイッチ２２ｆをオンする制御信号を出力する。それ以外の場合には、比較回路２２ｈ２は、スイッチ２２ｆをオフする制御信号を出力する。 The comparison circuit 22h2 is a control signal for turning on the switch 22f when the positive differential value output from the differentiation circuit 22h1 is larger than the positive threshold value Vref1 + or the negative differential value is smaller than the negative threshold value Vref1-. Is output. In other cases, the comparison circuit 22h2 outputs a control signal for turning off the switch 22f.
　比較回路２２ｈ３は、微分回路２２ｈ１が出力する正の微分値が、正の閾値Ｖｒｅｆ２＋よりも大きいか、負の微分値が負の閾値Ｖｒｅｆ２－よりも小さい場合に、スイッチ２２ｇをオンする制御信号を出力する。それ以外の場合には、比較回路２２ｈ３は、スイッチ２２ｇをオフする制御信号を出力する。 The comparison circuit 22h3 outputs a control signal for turning on the switch 22g when the positive differential value output from the differentiation circuit 22h1 is larger than the positive threshold value Vref2 + or the negative differential value is smaller than the negative threshold value Vref2-. Output. In other cases, the comparison circuit 22h3 outputs a control signal for turning off the switch 22g.
　閾値Ｖｒｅｆ２＋は、閾値Ｖｒｅｆ１＋よりも大きく、閾値Ｖｒｅｆ２－は、閾値Ｖｒｅｆ１－よりも小さい。比較回路２２ｈ２，２２ｈ３は、図５に示した比較回路１２ｆ２と同様の回路で実現できる。 The threshold value Vref2 + is larger than the threshold value Vref1 +, and the threshold value Vref2- is smaller than the threshold value Vref1-. The comparison circuits 22h2 and 22h3 can be realized by a circuit similar to the comparison circuit 12f2 shown in FIG.
　なお、図８の例では、制御回路２２ｈは、ＳＱＵＩＤ２１が出力する出力電圧を入力しているが、増幅回路２２ａの出力信号に基づいて、スイッチ２２ｆ，２２ｇを制御してもよい。 In the example of FIG. 8, the control circuit 22h receives the output voltage output from the SQUID 21, but may control the switches 22f and 22g based on the output signal of the amplifier circuit 22a.
　コイル２２ｌの一端は、抵抗２２ｉを介して積分回路２２ｃの出力端子、抵抗２２ｊを介して積分回路２２ｄの出力端子、抵抗２２ｋを介して積分回路２２ｅの出力端子に接続されている。コイル２２ｌの他端は接地されている。コイル２２ｌは、積分回路２２ｃ、積分回路２２ｄ、積分回路２２ｅが出力する積分信号に基づいて、ＳＱＵＩＤ２１に供給する帰還磁束φｆを発生する。 One end of the coil 22l is connected to the output terminal of the integrating circuit 22c through the resistor 22i, the output terminal of the integrating circuit 22d through the resistor 22j, and the output terminal of the integrating circuit 22e through the resistor 22k. The other end of the coil 22l is grounded. The coil 22l generates a feedback magnetic flux φf to be supplied to the SQUID 21 based on the integration signal output from the integration circuit 22c, the integration circuit 22d, and the integration circuit 22e.
　なお、図８の例では、積分回路２２ｃ～２２ｅが出力する積分信号は、ＡＤ変換回路２３に供給される。ＡＤ変換回路２３は、比較回路２２ｈ２，２２ｈ３が出力する制御信号に基づいて、積分回路２２ｃ～２２ｅの何れかが出力する積分信号を選択してＡＤ変換する。たとえば、制御回路２２ｈがスイッチ２２ｇをオンする制御信号とスイッチ２２ｆをオンする制御信号を出力した場合、ＡＤ変換回路２３は、積分回路２２ｅが出力する積分信号を選択してＡＤ変換する。また、制御回路２２ｈがスイッチ２２ｆをオンする制御信号とスイッチ２２ｇをオフする制御信号を出力した場合、ＡＤ変換回路２３は、積分回路２２ｄが出力する積分信号を選択してＡＤ変換する。また、制御回路２２ｈがスイッチ２２ｆをオフする制御信号とスイッチ２２ｇをオフする制御信号を出力した場合、ＡＤ変換回路２３は、積分回路２２ｃが出力する積分信号を選択してＡＤ変換する。 In the example of FIG. 8, the integration signals output from the integration circuits 22c to 22e are supplied to the AD conversion circuit 23. The AD conversion circuit 23 selects an integration signal output from any of the integration circuits 22c to 22e based on the control signal output from the comparison circuits 22h2 and 22h3, and performs AD conversion. For example, when the control circuit 22h outputs a control signal for turning on the switch 22g and a control signal for turning on the switch 22f, the AD conversion circuit 23 selects the integration signal output from the integration circuit 22e and performs AD conversion. When the control circuit 22h outputs a control signal for turning on the switch 22f and a control signal for turning off the switch 22g, the AD conversion circuit 23 selects the integration signal output by the integration circuit 22d and performs AD conversion. When the control circuit 22h outputs a control signal for turning off the switch 22f and a control signal for turning off the switch 22g, the AD conversion circuit 23 selects the integration signal output from the integration circuit 22c and performs AD conversion.
　なお、図１のスイッチ１２ｅと同様、スイッチ２２ｆ，２２ｇは、たとえば、ＭＯＳＦＥＴを用いて実現できる。
　また、ＡＤ変換回路２３が、制御回路が出力する２つの制御信号に基づいてＡＤ変換する積分信号を選択する代わりに、ＦＬＬ回路２２にスイッチを設けて、２つの制御信号に基づいて、ＡＤ変換回路２３に供給する積分信号を選択するようにしてもよい。 As with the switch 12e in FIG. 1, the switches 22f and 22g can be realized using, for example, a MOSFET.
Further, instead of the AD conversion circuit 23 selecting an integration signal to be AD converted based on the two control signals output from the control circuit, a switch is provided in the FLL circuit 22 and AD conversion is performed based on the two control signals The integration signal supplied to the circuit 23 may be selected.
　また、たとえば、ＳＱＵＩＤ２１の出力電圧がある程度大きく、積分回路２２ｃ～２２ｅが、検出結果（アナログ値）として適切な大きさの積分信号を出力する場合、増幅回路２２ａはなくてもよい。その場合、ＳＱＵＩＤ２１の出力電圧が、積分回路２２ｃに供給されるとともに、スイッチ２２ｆを介して積分回路２２ｄに供給され、スイッチ２２ｇを介して積分回路２２ｅに供給される。 Further, for example, when the output voltage of the SQUID 21 is large to some extent and the integration circuits 22c to 22e output an integration signal having an appropriate magnitude as a detection result (analog value), the amplification circuit 22a may be omitted. In this case, the output voltage of the SQUID 21 is supplied to the integrating circuit 22c, supplied to the integrating circuit 22d through the switch 22f, and supplied to the integrating circuit 22e through the switch 22g.
　上記のようなＳＱＵＩＤセンサ２０及びＦＬＬ回路２２によれば、磁場変化が速くなるほど、３つの積分回路２２ｃ～２２ｅの中から、小さな時定数をもつ積分回路が動作することになる。たとえば、微分回路２２ｈ１が出力する正の微分値が、閾値Ｖｒｅｆ２＋より大きい、または負の微分値が閾値Ｖｒｅｆ２－よりも小さくなるほど磁場変化が速い場合には、時定数の最も小さい積分回路２２ｅが動作する。微分回路２２ｈ１が出力する正の微分値が、閾値Ｖｒｅｆ２＋より小さく閾値Ｖｒｅｆ１＋より大きい、または負の微分値が閾値Ｖｒｅｆ２－よりも大きく閾値Ｖｒｅｆ１－より小さくなるような磁場変化の場合には、積分回路２２ｄが動作する。微分回路２２ｈ１が出力する正の微分値が、閾値Ｖｒｅｆ１＋より小さい、または負の微分値が閾値Ｖｒｅｆ１－より大きくなるような磁場変化の場合には、積分回路２２ｃ～２２ｅのうち、時定数が最も大きい積分回路２２ｃのみが動作する。 According to the SQUID sensor 20 and the FLL circuit 22 as described above, an integration circuit having a small time constant operates from the three integration circuits 22c to 22e as the magnetic field change becomes faster. For example, when the change in the magnetic field is faster as the positive differential value output from the differentiation circuit 22h1 is larger than the threshold value Vref2 + or the negative differential value is smaller than the threshold value Vref2-, the integration circuit 22e having the smallest time constant operates. To do. In the case of a magnetic field change in which the positive differential value output from the differentiating circuit 22h1 is smaller than the threshold value Vref2 + and larger than the threshold value Vref1 +, or the negative differential value is larger than the threshold value Vref2- and smaller than the threshold value Vref1-, the integrating circuit 22d operates. In the case of a magnetic field change in which the positive differential value output from the differentiation circuit 22h1 is smaller than the threshold value Vref1 + or the negative differential value becomes larger than the threshold value Vref1-, the time constant of the integration circuits 22c to 22e is the largest. Only the large integration circuit 22c operates.
　このような第２の実施の形態のＳＱＵＩＤセンサ２０及びＦＬＬ回路２２によれば、第１の実施の形態のＳＱＵＩＤセンサ１０及びＦＬＬ回路１２と同様の効果が得られるとともに、様々な磁場変化の速さに対応したスルーレートが選択できる。 According to the SQUID sensor 20 and the FLL circuit 22 of the second embodiment, the same effects as those of the SQUID sensor 10 and the FLL circuit 12 of the first embodiment can be obtained, and various magnetic field change speeds can be obtained. You can select the slew rate corresponding to the size.
　上記のようなＳＱＵＩＤセンサ１０，２０は、金属鉱床の探査や、脳磁場や心臓磁場などの生体磁場計測など、磁場を検出する様々な分野に適用できる。
　図９は、金属鉱床を探査する装置への適用例を示す図である。 The SQUID sensors 10 and 20 as described above can be applied to various fields for detecting magnetic fields, such as exploration of metal deposits and measurement of biomagnetic fields such as brain magnetic fields and cardiac magnetic fields.
FIG. 9 is a diagram illustrating an application example to an apparatus for exploring a metal deposit.
　図９には、車両３０に探査装置３１を搭載した例が示されている。探査装置３１は、ＳＱＵＩＤ３１ａ、ＦＬＬ回路３１ｂ、ＡＤ変換回路３１ｃ、表示装置３１ｄを有する。
　ＳＱＵＩＤ３１ａで変換された電圧はＦＬＬ回路３１ｂで安定化され、ＡＤ変換回路３１ｃに供給される。そして、ＡＤ変換回路３１ｃでＦＬＬ回路３１ｂの出力電圧（積分信号）がデジタル値に変換され、そのデジタル値に基づいて、たとえば、図示しないプロセッサの制御により、表示装置３１ｄに磁場の時間変化が表示される。 FIG. 9 shows an example in which the exploration device 31 is mounted on the vehicle 30. The exploration device 31 includes a SQUID 31a, an FLL circuit 31b, an AD conversion circuit 31c, and a display device 31d.
The voltage converted by the SQUID 31a is stabilized by the FLL circuit 31b and supplied to the AD conversion circuit 31c. Then, the AD converter circuit 31c converts the output voltage (integrated signal) of the FLL circuit 31b into a digital value. Based on the digital value, for example, the time change of the magnetic field is displayed on the display device 31d under the control of a processor (not shown). Is done.
　たとえば、探査装置３１が、地中に存在する磁場を発生する金属鉱床３２ａ，３２ｂを探査する際、車両３０の速度が速いほど、探査装置３１が検出する磁場の変化速度が速くなる。ＦＬＬ回路３１ｂとして、第１の実施の形態のＦＬＬ回路１２や第２の実施の形態のＦＬＬ回路２２を用いることで、磁場変化に追従できるようになるので、安定した磁場検出が可能になる。 For example, when the exploration device 31 explores the metal deposits 32a and 32b that generate the magnetic field existing in the ground, the change speed of the magnetic field detected by the exploration device 31 increases as the speed of the vehicle 30 increases. By using the FLL circuit 12 of the first embodiment or the FLL circuit 22 of the second embodiment as the FLL circuit 31b, it becomes possible to follow a change in the magnetic field, so that stable magnetic field detection is possible.
　なお、金属鉱床３２ｂは、金属鉱床３２ａよりも地中深くに存在し、探査装置３１で検出される磁場は小さい。しかし、ＦＬＬ回路３１ｂとして、第１の実施の形態のＦＬＬ回路１２や第２の実施の形態のＦＬＬ回路２２を用いることで、検出感度を落とさずに磁場検出できるため、このような小さい磁場についても高感度に検出できる。 The metal deposit 32b exists deeper in the ground than the metal deposit 32a, and the magnetic field detected by the exploration device 31 is small. However, by using the FLL circuit 12 of the first embodiment or the FLL circuit 22 of the second embodiment as the FLL circuit 31b, the magnetic field can be detected without reducing the detection sensitivity. Can be detected with high sensitivity.
　以上、実施の形態に基づき、本発明のＦＬＬ回路及びＳＱＵＩＤセンサの一観点について説明してきたが、これらは一例にすぎず、上記の記載に限定されるものではない。 As described above, one aspect of the FLL circuit and the SQUID sensor of the present invention has been described based on the embodiments, but these are only examples and are not limited to the above description.
　１０　ＳＱＵＩＤセンサ
　１１　ＳＱＵＩＤ
　１２　ＦＬＬ回路
　１２ａ　増幅回路
　１２ｂ　バイアス電源
　１２ｃ，１２ｄ　積分回路
　１２ｅ，１２ｊ　スイッチ
　１２ｆ　制御回路
　１２ｇ，１２ｈ　抵抗
　１２ｉ　コイル
　１３　ＡＤ変換回路
　Ｖｂ　バイアス電圧
　φ　磁場
　φｆ　帰還磁束
　τ１，τ２　時定数 10 SQUID sensor 11 SQUID
12 FLL circuit 12a Amplifier circuit 12b Bias power supply 12c, 12d Integration circuit 12e, 12j Switch 12f Control circuit 12g, 12h Resistance 12i Coil 13 AD converter circuit Vb Bias voltage φ Magnetic field φf Feedback magnetic flux τ1, τ2 Time constant

Claims (6)

  1. 　第１の時定数を有し、ＳＱＵＩＤが出力する第１の出力電圧または前記第１の出力電圧を増幅した第２の出力電圧を時間積分し、第１の積分信号を出力する第１の積分回路と、
    　前記第１の時定数よりも小さい第２の時定数を有し、前記第１の出力電圧または前記第２の出力電圧を時間積分した第２の積分信号を出力する第２の積分回路と、
    　前記第１の出力電圧の変化の速さを表す第１の値が閾値よりも大きい場合に前記第２の積分回路を動作させ、前記第１の値が前記閾値よりも小さい場合に前記第２の積分回路の動作を停止する制御回路と、
    　前記第１の積分信号または前記第２の積分信号に基づいて、前記ＳＱＵＩＤに供給する帰還磁束を発生するコイルと、
    　を有するＦＬＬ回路。     A first integration having a first time constant, time-integrating a first output voltage output by the SQUID or a second output voltage obtained by amplifying the first output voltage, and outputting a first integration signal. Circuit,
    A second integrating circuit having a second time constant smaller than the first time constant and outputting a second integrated signal obtained by time-integrating the first output voltage or the second output voltage;
    The second integration circuit is operated when a first value representing the speed of change of the first output voltage is larger than a threshold value, and when the first value is smaller than the threshold value, the second value is changed. A control circuit for stopping the operation of the integrating circuit;
    A coil that generates a feedback magnetic flux to be supplied to the SQUID based on the first integration signal or the second integration signal;
    A FLL circuit.
  2. 　前記第２の積分回路には、前記第１の出力電圧または前記第２の出力電圧が、スイッチを介して供給され、
    　前記制御回路は、前記第１の値が前記閾値よりも大きい場合に前記スイッチをオンすることで前記第２の積分回路を動作させ、前記第１の値が前記閾値よりも小さい場合に前記スイッチをオフすることで前記第２の積分回路の動作を停止する、
    　請求項１に記載のＦＬＬ回路。     The second integration circuit is supplied with the first output voltage or the second output voltage via a switch,
    The control circuit operates the second integrating circuit by turning on the switch when the first value is larger than the threshold, and the switch when the first value is smaller than the threshold. To stop the operation of the second integration circuit,
    The FLL circuit according to claim 1.
  3. 　前記制御回路は、前記第１の出力電圧または前記第２の出力電圧を時間微分した微分値を出力する微分回路と、
    　前記微分値と、正の第１の閾値または負の第２の閾値との大小関係に基づいて前記スイッチのオンオフを制御するための制御信号を出力する比較回路と、
    　を有する請求項２に記載のＦＬＬ回路。     The control circuit outputs a differential value obtained by time-differentiating the first output voltage or the second output voltage;
    A comparison circuit that outputs a control signal for controlling on / off of the switch based on a magnitude relationship between the differential value and a positive first threshold value or a negative second threshold value;
    The FLL circuit according to claim 2, comprising:
  4. 　前記比較回路は、前記微分値が正であり、前記第１の閾値よりも大きい場合、または前記微分値が負であり、前記第２の閾値よりも小さい場合、前記スイッチをオンする前記制御信号を出力し、前記微分値が正であり、前記第１の閾値よりも小さい場合、または前記微分値が負であり、前記第２の閾値よりも大きい場合、前記スイッチをオフする前記制御信号を出力する、
    　請求項３に記載のＦＬＬ回路。     The comparison circuit is configured to turn on the switch when the differential value is positive and larger than the first threshold value, or when the differential value is negative and smaller than the second threshold value. When the differential value is positive and smaller than the first threshold value, or the differential value is negative and larger than the second threshold value, the control signal for turning off the switch is Output,
    The FLL circuit according to claim 3.
  5. 　前記第１の積分回路と前記第２の積分回路と、を含み、それぞれが異なる時定数を有する複数の積分回路を有し、
    　前記制御回路は、前記第１の値が大きくなるほど、前記複数の積分回路のうち、小さい時定数を有する積分回路を動作させる、
    　請求項１乃至４の何れか一項に記載のＦＬＬ回路。     A plurality of integrating circuits including the first integrating circuit and the second integrating circuit, each having a different time constant;
    The control circuit operates an integration circuit having a small time constant among the plurality of integration circuits as the first value increases.
    The FLL circuit according to any one of claims 1 to 4.
  6. 　帰還磁束と、入力される磁場とに基づいた第１の出力電圧を出力するＳＱＵＩＤと、
    　第１の時定数を有し、前記第１の出力電圧または前記第１の出力電圧を増幅した第２の出力電圧を時間積分し、第１の積分信号を出力する第１の積分回路と、
    　前記第１の時定数よりも小さい第２の時定数を有し、前記第１の出力電圧または前記第２の出力電圧を時間積分した第２の積分信号を出力する第２の積分回路と、
    　前記第１の出力電圧の変化の速さを表す第１の値が閾値よりも大きい場合に前記第２の積分回路を動作させ、前記第１の値が前記閾値よりも小さい場合に前記第２の積分回路の動作を停止する制御回路と、
    　前記第１の積分信号または前記第２の積分信号に基づいて、前記ＳＱＵＩＤに供給する前記帰還磁束を発生するコイルと、
    　を有するＳＱＵＩＤセンサ。     A SQUID that outputs a first output voltage based on the feedback magnetic flux and the input magnetic field;
    A first integration circuit having a first time constant, time-integrating the first output voltage or the second output voltage obtained by amplifying the first output voltage, and outputting a first integration signal;
    A second integrating circuit having a second time constant smaller than the first time constant and outputting a second integrated signal obtained by time-integrating the first output voltage or the second output voltage;
    The second integration circuit is operated when a first value representing the speed of change of the first output voltage is larger than a threshold value, and when the first value is smaller than the threshold value, the second value is changed. A control circuit for stopping the operation of the integrating circuit;
    A coil that generates the feedback magnetic flux to be supplied to the SQUID based on the first integration signal or the second integration signal;
    A SQUID sensor.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0511034A (en) * 1991-07-03 1993-01-19 Seiko Instr Inc High-sensitivity fluxmeter
JPH11264862A (en) * 1998-03-18 1999-09-28 Seiko Instruments Inc Superconductive quantum interference element flux meter
JP2000321343A (en) * 1999-05-13 2000-11-24 Sumitomo Electric Ind Ltd Method and device for adjusting magnetic field bias in modulation drive circuit for squid
US6337567B1 (en) * 1999-04-22 2002-01-08 Lg Electronics Inc. Apparatus and method for measuring second-order gradient of magnetic field using super conductor quantum interference device
JP2002148322A (en) * 2000-11-09 2002-05-22 Seiko Instruments Inc Signal detector using superconducting quantum interference element and its measuring method
JP2015501919A (en) * 2011-11-14 2015-01-19 ネオセラ リミテッド ライアビリティ カンパニー DCSQUID-based RF magnetometer that operates over 200MHz bandwidth

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0511034A (en) * 1991-07-03 1993-01-19 Seiko Instr Inc High-sensitivity fluxmeter
JPH11264862A (en) * 1998-03-18 1999-09-28 Seiko Instruments Inc Superconductive quantum interference element flux meter
US6337567B1 (en) * 1999-04-22 2002-01-08 Lg Electronics Inc. Apparatus and method for measuring second-order gradient of magnetic field using super conductor quantum interference device
JP2000321343A (en) * 1999-05-13 2000-11-24 Sumitomo Electric Ind Ltd Method and device for adjusting magnetic field bias in modulation drive circuit for squid
JP2002148322A (en) * 2000-11-09 2002-05-22 Seiko Instruments Inc Signal detector using superconducting quantum interference element and its measuring method
JP2015501919A (en) * 2011-11-14 2015-01-19 ネオセラ リミテッド ライアビリティ カンパニー DCSQUID-based RF magnetometer that operates over 200MHz bandwidth

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