WO2018141834A1 - Composant semi-conducteur optoélectronique et procédé de fabrication correspondant - Google Patents

Composant semi-conducteur optoélectronique et procédé de fabrication correspondant Download PDF

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Publication number
WO2018141834A1
WO2018141834A1 PCT/EP2018/052490 EP2018052490W WO2018141834A1 WO 2018141834 A1 WO2018141834 A1 WO 2018141834A1 EP 2018052490 W EP2018052490 W EP 2018052490W WO 2018141834 A1 WO2018141834 A1 WO 2018141834A1
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Prior art keywords
contact
semiconductor layer
layer sequence
semiconductor component
contacts
Prior art date
Application number
PCT/EP2018/052490
Other languages
German (de)
English (en)
Inventor
Siegfried Herrmann
Original Assignee
Osram Opto Semiconductors Gmbh
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Publication of WO2018141834A1 publication Critical patent/WO2018141834A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/387—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer

Definitions

  • An object to be solved is to provide an optoelectronic semiconductor device which can be produced efficiently and which can generate a variable illumination pattern.
  • this includes
  • the semiconductor layer sequence is an active zone for generating radiation, in particular for generating visible light such as blue light.
  • the active zone which has, for example, a multi-quantum well structure, in short MQW, is arranged between a first layer region and a second layer region of the semiconductor layer sequence.
  • the first and / or the second layer region may each be composed of one or more sub-layers.
  • the first layer region is a p-doped one
  • the semiconductor component is a light-emitting diode, in short LED.
  • the semiconductor layer sequence is preferably based on a III-V compound semiconductor material.
  • the semiconductor material is, for example, a nitride compound semiconductor material such as Al n In] __ n _ m N m Ga or a phosphide compound semiconductor material such as
  • the semiconductor layer sequence is particularly preferably based on AlInGaN. According to at least one embodiment, the
  • the semiconductor device is free of one
  • An average roughness of the roughening is for example between 0, 2 ym and 2 ym. At one of the active zone facing away from the second
  • Layer region in particular in the roughening, is preferably a material having a refractive index of at most 1.7 or 1.6, based on a maximum wavelength
  • this material is by a
  • Passivation layer approximately from S1O2 and / or through a
  • the semiconductor device on a first electrical contact structure.
  • the first layer region is electrically contacted via the first contact structure.
  • the second layer region is electrically contacted via the second contact structure.
  • the second contact structure is an n
  • this includes
  • Semiconductor device a carrier substrate.
  • the carrier substrate is located on one of the semiconductor layer sequence
  • the carrier substrate is preferably the semiconductor component mechanically supporting and supporting
  • the carrier substrate may be electrically conductive or, preferably, electrically insulating or at least surrounded by an electrically insulating coating.
  • the carrier substrate may be translucent or else be opaque. Preferably, no or only a negligible proportion, for example at most 5% or 1%, of the radiation generated in operation in the active zone reaches the carrier substrate.
  • the carrier substrate comprises or consists of one or more of the following materials: a ceramic such as aluminum nitride, a metal such as copper or aluminum or molybdenum, a glass, a plastic, a
  • the first comprises
  • Contact structure one or more surface contacts.
  • the at least one surface contact is located directly on the semiconductor layer sequence, in particular directly on the first layer region. Current is impressed in the semiconductor layer sequence via the surface contact.
  • the semiconductor layer sequence extends continuously over the at least one surface contact. That is, as seen in plan view, the first surface contact is completely off of
  • the second contact structure comprises a plurality of contact pins, also as vias
  • Contact pins can be electrically controlled independently of each other, even within a surface contact.
  • the at least two or at least three contact pins extend from one side of the semiconductor layer sequence on which the first contact structure is located through
  • the contact pins are electrical vias through the active zone.
  • the contact pins of the semiconductor layer sequence are preferably electrically insulated.
  • Optoelectronic semiconductor device one of a
  • Growth substrate detached semiconductor layer sequence with an active zone for generating light between a first layer region and a second layer region. Furthermore, a first and a second electrical contact structure are present, via which the first layer region and the second layer region are electrically contacted.
  • Carrier substrate is located at one of
  • the first contact structure comprises at least one surface contact, which is located directly on the
  • the second contact structure comprises at least two contact pins, which are preferably electrically independently controllable.
  • the contact pins extend from one side of the semiconductor layer sequence, at which the first
  • Contact structure is, through the surface contact, the first layer region and the active zone into the second layer region.
  • the semiconductor component is a surface-mountable chip without a growth substrate, wherein the surface contacts, optionally together with components from the second contact structure, form a segmented mirror.
  • the surface contacts optionally together with components from the second contact structure, form a segmented mirror.
  • Semiconductor layer sequence may be designed geometrically in the same way as a segmentation in the surface contacts, for example by means of etching.
  • the semiconductor component described here is preferably a coarse segmentation of an LED chip, for example in nine segments.
  • the semiconductor device described here is a comparatively simply constructed LED chip, which due to the described segmentation a
  • the semiconductor component comprises a plurality of the surface contacts.
  • the surface contacts may lie in a common plane perpendicular to the growth direction of the semiconductor layer sequence. At least some or all of them are
  • Luminous regions can be individually and independently controlled via the contact pins and / or the surface contacts.
  • the contact pins or groups of contact pins are electrically independent
  • the luminous areas, in particular adjacent contact pins do not form a sharp cut-off line. This applies, in particular, to a side of the semiconductor layer sequence facing away from the first contact structure, for example directly at this end
  • the contact pins extend in the continuous, contiguous and except for the
  • Contact pin within the surface contacts preferably not further structured second layer region.
  • some, most or each of the surface contacts are more than one of
  • Control of the luminous areas is possible. More preferably, there are several lines along which contact pins are located. These rows of contact pins may have one or more rows of surface contacts
  • the pads are, for example, for surface mounting, short SMT, set up or for an electrically conductive bonding.
  • the electrical connection surfaces are designed for connection to bonding wires and thus as bond pads.
  • the connection surfaces are realized by one or more metal layers.
  • most or all of the electrical pads are located on a side of the semiconductor layer sequence facing away from the
  • connection surfaces or a part of the connection surfaces are contacted via bonding wires, then these connection surfaces preferably point in the direction away from the carrier substrate.
  • Connection surfaces for bonding wires may be on one side of the semiconductor layer sequence facing the
  • Support substrates are located, alternatively or additionally could surface mounting pads on one of
  • Carrier substrate be present.
  • this includes
  • Carrier substrate several electrical feedthroughs.
  • Feedthroughs preferably extend from the connection surfaces on a side of the carrier substrate facing away from the semiconductor layer sequence to the at least one surface contact and / or to the contact pins or the contact webs.
  • the feedthroughs can completely cover the carrier substrate run through. When seen in plan view, the feedthroughs can lie completely within the carrier substrate or else at an edge of the carrier substrate.
  • the second comprises
  • Contact structure multiple contact webs.
  • the contact webs are at a lateral current distribution, ie to a
  • the contact webs can form the second mirror plane, which is further away from the semiconductor layer sequence than the surface contacts.
  • Contact structure electrically connected to each other. From this the lines can be built up. Along one of the rows is preferably only exactly one contact web before, alternatively, several separate and not electrically directly interconnected contact webs along the rows of contact pins follow each other. In accordance with at least one embodiment, the contact webs together with the at least one surface contact form one
  • Mirrors for the light generated during operation of the semiconductor device. These are preferably the surface contacts and the Contact webs of a material that reflects the generated radiation, in particular a metal such as
  • Aluminum or silver designed, at least on one of the semiconductor layer sequence facing side.
  • the mirror formed by the contact webs and the at least one surface contact, when viewed in plan view, covers at least 90% or 95% or 98% of a base area of the semiconductor layer sequence.
  • the contact webs and the at least one surface contact when viewed in plan view, covers at least 90% or 95% or 98% of a base area of the semiconductor layer sequence.
  • Layer area a negligible lateral conductivity. That is, in the first layer area occurs in
  • Layer range at least 100 c ⁇ V ⁇ ⁇ - ⁇ ⁇ - and / or at most 600 cm ⁇ -V ⁇ ⁇ -s ⁇ ⁇ -.
  • electron mobilities are in the range of 440 cm 2 V _1 s _1 or 200 cm 2 V _1 s _1 reported.
  • Charge carrier mobility in particular a
  • Puncture mobility, of the first layer range is preferred only at most 30 c ⁇ V ⁇ ⁇ -s ⁇ ⁇ - or 10 cm ⁇ -V ⁇ ⁇ -s ⁇ ⁇ -.
  • Mg-doped GaN to hole mobilities give 5 cm2v _ ls --'-.
  • the lateral sidewall is a lateral sidewall formed from a lateral sidewall formed from a lateral sidewall formed from a lateral sidewall formed from a lateral sidewall formed from a lateral sidewall formed from a lateral sidewall formed from a lateral sidewall formed from a lateral sidewall formed from a lateral sidewall formed from a lateral sidewall formed from a lateral sidewall formed from a lateral sidewall formed from a lateral sidewall surface potential.
  • Conductivity of the second layer region by at least a factor of 10 or 30 or 100 greater than the lateral
  • Conductivity of the first layer region may be opposite to the lateral conductivity of the second layer region
  • a negligible lateral conductivity means, for example, that a current direction or average
  • Semiconductor layer sequence deviates.
  • the semiconductor layer sequence deviates.
  • the semiconductor layer sequence continuous and contiguous, and preferably also continuously over all surface contacts and / or light areas away. This applies, in particular neglecting recesses for the contact pins, preferably also with a constant thickness. In other words, the semiconductor layer sequence in this case is not structured like the surface contacts. According to at least one embodiment, the
  • the intermediate area is enclosed in a closed track, so that within this track exactly one
  • Luminous area is located. Likewise, a plurality of luminous areas can be used together, in particular all luminous areas of a
  • the carrier substrate continuously, contiguous and completely across the semiconductor layer sequence.
  • the carrier substrate can be a constant, constant thickness
  • this includes
  • the grid frame is located on a side facing away from the surface contacts of the semiconductor layer sequence, such as directly on the
  • the grid frame is produced by galvanization.
  • the grid frame is radiopaque for the generated during operation
  • the grid frame is designed to be reflective, but can also be absorbent for the generated
  • the grid frame is a structured metallization on the semiconductor layer sequence.
  • the grid frame may be made of a plastic material and be printed about or may be made of a ceramic and about as
  • prefabricated component placed and / or glued.
  • Grid frame formed several stitches.
  • the individual stitches can be predominantly or completely surrounded by the grid frame all around, seen in plan view.
  • the meshes may be open so that the grid frame does not wrap around the
  • Semiconductor device extends around.
  • the meshes are each assigned to one or more of the luminous regions. There may be a one-to-one correspondence between the stitches and the light areas and / or the contact pins.
  • one of the stitches or some of the stitches or all stitches are partially or completely filled by an optical medium.
  • Optics medium may be heading away from the
  • the optical medium comprises one or more phosphors for partial or complete conversion of in the
  • Semiconductor layer sequence generated light in the long-wavelength light one or more filter materials for filtering one or more spectral regions of the generated radiation and / or one or more scattering means for scattering the generated radiation.
  • the mesh can also several
  • Optics media for example in the form of one over the other
  • the at least one outer reflector extends in a plan view preferably around the semiconductor layer sequence and / or the carrier substrate and / or the grid frame.
  • the outer reflector is for example by a
  • reflective potting such as a silicone with
  • Titanium dioxide particles formed. Towards away from the
  • the semiconductor device radiates the generated light during operation only on a side facing away from the contact structures of the semiconductor layer sequence.
  • this includes
  • the at least one optical element is designed for beam steering and / or beam shaping of the generated light.
  • Optical element around a lens, a reflector and / or a prism Optical element around a lens, a reflector and / or a prism.
  • Optic elements available.
  • Optic elements are formed out of a single base layer.
  • one or more or all of the optical elements are so on the
  • the illuminating area is about 1 m away from the semiconductor device.
  • this includes
  • Semiconductor component at least two or three or five of the surface contacts. Alternatively or additionally, at most 50 or 25 or 15 or 10 surface contacts are present.
  • a number of the contact pins of the semiconductor device is at least three or six or nine and / or at most 200 or 150 or 100 or 30.
  • At least two, three or four and / or at most ten or eight or six contact pins are present per surface contact. In other words There is no fine pixelation within the surface contacts, but there is only one per surface contact
  • the at least one surface contact has a lateral dimension, in the direction parallel to the growth direction of the semiconductor layer sequence, of at least 15 ⁇ m ⁇ 50 ⁇ m or 25 ⁇ m ⁇ 100 ⁇ m or
  • this lateral dimension is at most 300 ym x 900 ym or
  • Semiconductor device provided for a flash.
  • it is a flash in a mobile
  • Image capture device such as a camera or a
  • the mobile imaging device includes one or more of these
  • the reflective, approximately mirrored contact structures such as the surface contacts and / or the contact webs have a galvanic reinforcement.
  • the Glavican reinforcement allows an improvement of the current carrying capacity.
  • a metal such as copper serves as a reinforcing material, such as having a thickness of at least 0.5 ym and / or of at most 1 ym or 5 ym or 15 ym.
  • the reinforcing material is preferably applied to a diffusion barrier which is attached to a mirror layer of the relevant contact structure, for example with or made of silver and / or a transparent conductive oxide, in short TCO, such as ITO. This can be a combination of high
  • Reflectivity with high current carrying capacity to reach For example, in the case of a semiconductor layer sequence with an edge length of 1 mm, three tracks each with 1 A current carrying capacity may be present, the tracks being formed by the surface contacts and / or the contact webs.
  • a thickness of the respective contact structure as a whole is preferably at least 0.1 ⁇ m or 0.5 ⁇ m and / or at most 2 ⁇ m or 10 ⁇ m or 20 ⁇ m.
  • the present invention can also be applied to a mobile
  • Image pickup device or to a headlight about for a motor vehicle such as a car with at least one such optoelectronic semiconductor device to be directed.
  • a method of manufacturing a semiconductor device as described in connection with one or more of the above embodiments is given. Features of the semiconductor device are therefore also disclosed for the method and vice versa. In at least one embodiment, the method is for producing one or more semiconductor devices
  • a flashlight or an LED-based headlamp can be realized, which essentially has only the size of the underlying LED chip and can include an integrated beam-shaping optical system. Thus, can be the highest
  • Beam shaping optics necessary, which would otherwise still be necessary.
  • a selective illumination of a target area in terms of location and color is possible.
  • a cost-adaptive radiating light source can be realized.
  • the semiconductor component described here can also be used to realize a movable object illumination.
  • Lighting unit with a motion sensor with
  • Semiconductor component produced light cone track the object to be illuminated controlled and light up targeted.
  • the semiconductor device as an SMD component of the surface mounting accessible, such as a reflow soldering, so that a standard contact and
  • Standard contacting method can be used.
  • a phosphor can be integrated in the component, so that the phosphor about mechanical abrasion and other Environmental influences is protected during installation.
  • the integrated phosphor offers design advantages in the end use, as the phosphor is less visible.
  • the grid frame and the phosphor and the optics can be applied in the wafer composite, such as by soldering, electroplating and / or gluing.
  • LED-based micropixel arrays can be tapped efficiently and inexpensively, in particular applications that have spatial, color and / or temporal variability
  • FIGS 1 to 8 are schematic representations of
  • Figure 9 is a schematic sectional view of a
  • FIG. 10 shows schematic sectional views of FIG
  • Figure 1 is an embodiment of a
  • the semiconductor device 1 has a semiconductor layer sequence 2.
  • An active zone 23 for generating light, such as blue light, is located between a first one
  • the semiconductor layer sequence 2 is preferably based on the AlInGaN material system.
  • the first electrical contact structure 31 is provided for electrically contacting the first layer region 21 and the second contact structure 32 for
  • the first contact structure 31 has three surface contacts 41, which follow one another along a y-direction and extend along a growth direction G of the
  • the pads 33 are for
  • a carrier substrate 6 On the side facing away from the semiconductor layer sequence 2 8 of the contact structures 31, 32 is a carrier substrate 6. About the carrier substrate 6, the semiconductor device 1 to an external, not shown mounting platform such as a circuit board can be fastened, such as by soldering or gluing.
  • the carrier substrate 6 may be opaque and out
  • an electrically insulating carrier layer 61 in particular directly to the contact structures 31, 32, and from a
  • the further carrier layer 62 may be designed as a metallization and serve as a mounting layer for the semiconductor device 1.
  • the second contact structure 32 comprises three contact webs 34.
  • the contact webs 34 extend continuously over the semiconductor layer sequence 2 along the y direction.
  • the contact webs 34 are electrically independent of each other via the pads 33 of the second contact structure 32 can be controlled, wherein per contact land 34 preferably exactly one pad 33 is provided.
  • Contact webs 34 extend contact pin 42 through the surface contacts 41, through the first layer region 21 and through the active zone 23 through to the second
  • Surface contact 41 more, preferably three, contact pin 42 available. Through the three surface contacts 41, each with three contact pins 42, there are a total of nine luminous areas 5, indicated schematically by a dashed line in FIG. 1B. Between adjacent surface contacts 41, the luminous regions 5 are sharply delimited from one another, since the first layer region 21 exhibits only an insignificant electrical transverse conductivity, so that, viewed in plan view, next to the
  • Semiconductor layer sequence 2 is configured as continuous and continuous according to Figure 1, the luminous regions 5 along the x-direction, along which the surface contacts 41 extend continuously, merging into each other. This is illustrated in FIG. 1B by a hatching between the luminous areas 5 merging into one another.
  • the surface contacts 41 are as
  • Terminal surfaces 33 the individual lighting areas 5 can be controlled individually or in groups. That's it possible, as in all other embodiments, that only a simplified electrical interconnection takes place, so that only certain segment images and thus certain combinations of shining in operation
  • Luminous areas are possible. Due to the comparatively small number of connection surfaces, for example, six connection surfaces 33, a simple application-oriented interconnection is possible. In order to simplify the illustration, electrical insulation layers between the contact structures 31, 32 are not shown in FIG. About such electrical insulation short circuits are prevented. In FIG. 1, only the
  • Contact structure 31, 32 are each located along a straight line at the edge of the semiconductor layer sequence 2, seen in plan view.
  • an electrical insulation layer 66 On one side of the semiconductor layer sequence 2 facing away from the contact structures 31, 32 there is preferably an electrical insulation layer 66, which is referred to as a
  • Passivation layer is used.
  • the first passivation layer is made of
  • Insulation layer 66 designed thin, for example, with a thickness of at most 1 ym or 0.5 ym, in particular, the insulating layer 66 is thinner than the semiconductor layer sequence 2. Deviating from the illustration of Figure 1, it is possible that at the light exit surface, directly from of the
  • Insulation layer 66 is covered, a roughening of
  • a carrier substrate 6 which comprises the in particular continuous carrier layers 61, 62, so that electrical contacting can take place upwards.
  • the technique described is also suitable for so-called Mold Supported Chips, in which a galvanic substrate is filled with a molding material.
  • metallic, galvanically produced through contacts are present, which are of a shaped body, for example of a
  • the pads 33 for the second contact structure 32 are located on an underside of the semiconductor device 1 and are connected via electrical vias with the
  • Pads 33 and the contact webs 34 consists
  • the carrier substrate 6, in deviation from FIG. 1 is electrically conductive.
  • the contact webs 34, which are merely optional in this case, and the contact pins 42 are electrically short-circuited via the carrier substrate 6.
  • Carrier substrate 6 in this case is for example made of a metal such as molybdenum or of a semiconductor material such as silicon.
  • an electrically conductive carrier substrate 6 is also used, for example made of silicon, see the sectional view in FIG. 3C.
  • an electrically conductive carrier substrate 6 is also used, for example made of silicon, see the sectional view in FIG. 3C.
  • Support substrate 6 is formed a plurality of isolation trenches 68, through which the carrier substrate 6 is divided into a plurality of electrically separate regions. For example, each of these areas is assigned to one of the terminal areas 33 for the first and / or the second contact structure 31, 32.
  • each of these areas is assigned to one of the terminal areas 33 for the first and / or the second contact structure 31, 32.
  • a total of six pads 33 are electrically connected via the plated-through holes 44 through the carrier substrate 6 with the contact webs 34 and the surface contacts 41.
  • Semiconductor layer sequence 2 are.
  • a plurality of optical elements 75 are optionally formed in the form of a converging lens.
  • the optical elements 75 are preferably one-to-one assigned to the luminous areas 5.
  • Embodiment in Figure 5 are located between the optical elements 75 and the semiconductor layer sequence 2, a grid frame 7, see also the perspective view in Figure 6.
  • the grid frame 7, for example, by electroplating on a seed layer and / or with a
  • Meshes 71 are preferably uniquely associated with the luminous regions 5.
  • the grid frame 7 is applied directly to the semiconductor layer sequence 2 or to the insulation layer 66 not shown in FIGS. 5 and 6. A thickness of the grid frame 7 in the direction away from the
  • Semiconductor layer sequence 2 is, for example, at least 100 ym and / or at most 300 ym.
  • a web width of webs of the lattice frame 7 is approximately at least 5 ym or 10 ym and / or at most 50% of a period of the stitches 71 in the x-direction and / or in the y-direction.
  • square or rectangular mesh 71 have one
  • Aspect ratio corresponding to that of the target area to be illuminated preferably an aspect ratio of 4: 3 or 16: 9 or the aspect ratio of the segment to be illuminated.
  • the lattice frame 7 thus also corresponds to a segmentation of 3 ⁇ 3.
  • the meshes 71 and the luminous regions 5 preferably have the same aspect ratios as the luminous pattern to be generated in the far field.
  • the approximately metallic grid frame 7 preferably exhibits a high reflectivity for the generated light, for example a reflectivity of at least 85% or 90%, averaged over the generated wavelengths.
  • Surfaces of the lattice frame 7 may be designed to be specularly reflective or diffusely reflective.
  • FIG. 5 illustrates that the meshes 71 are optionally filled with an optical medium 72.
  • the optical medium 72 includes, for example, a phosphor for producing white light, for example.
  • the meshes 71 may also be filled with different optical media 72.
  • the optical medium 72 can
  • the optical medium 72 is introduced, for example, via a doctor blade technique.
  • the lattice frame 7 reduces optical crosstalk between adjacent optical media 72 and / or between adjacent luminous areas.
  • a spacing of the optical elements to the semiconductor layer sequence 2 is preferably defined by the grid frame 7.
  • the optic elements 75 are applied off-center are.
  • the main emission directions of the emitted light L symbolized by arrows, are tilted with respect to the growth direction G.
  • the surfaces of the optical elements 75 may, as in all other embodiments, be spherical, aspheric, toroidal or quadrant symmetric polynomial.
  • the optical elements 75 may be larger than the mesh 71.
  • planar regions may be present between the optical elements 75, so that only a part of the emitted light passes through the associated optical element 75 and thus a diffuse background radiation is superimposed on a radiation formed, for example collimated, by the optical elements 75.
  • An area covered with the optical elements 75 is preferably at least 30% or 50% and / or at most 90% or 80% of the total area. According to the figures 1 to 6 extends the
  • the semiconductor layer sequence 2 can be completely removed between adjacent luminous regions, with optionally an optical insulation layer 67, for example of an absorbing or reflecting material, being introduced. This is illustrated in FIG.
  • the semiconductor layer sequence 2 between adjacent luminous regions is only partially removed, see FIG. 8.
  • the first one is
  • the second layer region 22 is completely or predominantly removed and optionally also the active zone 23, so that at least the first layer region 21 is still partly present.
  • FIG. 9 shows an exemplary embodiment of a mobile
  • Imaging device 10 is shown.
  • the image capture device 10 is, for example, a mobile phone.
  • the semiconductor device 1 described here has the
  • Imaging device 10 additionally preferably has at least one sensor 11, for example a CCD field. Furthermore, a display 12 is optionally available.
  • FIG. 10A a production method is shown schematically in FIG.
  • the semiconductor layer sequence 2 is grown on a growth substrate 9.
  • FIG. 10B the contact structures 31, 32 are produced.
  • the carrier substrate 6 is attached, and subsequently the growth substrate 9 is removed, compare FIG. 1C. Finally, a separation takes place to the
  • Attachment of the carrier substrate 6 are generated, for example only the contact pins 42, the surface contacts 41 and the contact webs 34.
  • the pads 33 are preferably prepared only after the attachment of the carrier substrate 6 and after the detachment of the growth substrate 9.
  • Layer region 22 can thereby effectively block the light passing through the interstices of the area contacts 41 for
  • different angles can also be selected.
  • a distance between the surface contacts 41 and / or the luminous regions 5 in the exemplary embodiments is, for example
  • Mirror segments in particular the surface contacts 41, can each be designed as free-form surfaces, so that a lighting pattern can be generated.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Led Device Packages (AREA)

Abstract

Le composant semi-conducteur optoélectronique (1) comprend une succession de couches semi-conductrices (2) détachée d'un substrat de croissance (9) et comportant une zone active (23) destinée à générer de la lumière entre une première zone de couches (21) et une seconde zone de couches (22). En outre, une première (31) et une seconde structure de contact électrique (32) sont présentes qui réalisent le contact électrique avec les zones de couche (31, 32). Un substrat de support (6) est situé sur un côté de la première et de la seconde structure de contact (31, 32) qui est opposé à la succession de couches semi-conductrices (2). La première structure de contact (31) comprend des contacts de surface (41) directement sur la succession de couches semi-conductrice (2) et de manière continue au-delà de la succession de couches semi-conductrices (2). La seconde structure de contact (32) comprend des broches de contact (42) qui peuvent être commandées de préférence indépendamment électriquement et qui s'étendent jusque dans la seconde région de couches (22) en passant par les contacts de surface (41), la première zone de couches (21) et la zone active (23).
PCT/EP2018/052490 2017-02-06 2018-02-01 Composant semi-conducteur optoélectronique et procédé de fabrication correspondant WO2018141834A1 (fr)

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DE102017102247.3A DE102017102247A1 (de) 2017-02-06 2017-02-06 Optoelektronisches Halbleiterbauteil und Herstellungsverfahren hierfür
DE102017102247.3 2017-02-06

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Publication number Priority date Publication date Assignee Title
WO2020074351A1 (fr) * 2018-10-12 2020-04-16 Osram Opto Semiconductors Gmbh Composant à semi-conducteur optoélectronique

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DE19645035C1 (de) * 1996-10-31 1998-04-30 Siemens Ag Mehrfarbiges Licht abstrahlende Bildanzeigevorrichtung
WO2003043013A1 (fr) * 2001-11-16 2003-05-22 Thin Film Electronics Asa Appareil optoelectronique a adressage matriciel et element electrode integre
DE10236854A1 (de) * 2002-08-07 2004-02-26 Samsung SDI Co., Ltd., Suwon Verfahren und Vorrichtung zur Strukturierung von Elektroden von organischen lichtemittierenden Elementen
DE102007030129A1 (de) * 2007-06-29 2009-01-02 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung einer Mehrzahl optoelektronischer Bauelemente und optoelektronisches Bauelement
US20110241031A1 (en) 2008-12-23 2011-10-06 Osram Opto Semiconductors Gmbh Optoelectronic projection device
WO2013186035A1 (fr) * 2012-06-14 2013-12-19 Osram Opto Semiconductors Gmbh Puce semi-conductrice optoélectronique
WO2017060355A1 (fr) 2015-10-08 2017-04-13 Osram Opto Semiconductors Gmbh Composant et procédé de fabrication d'un composant

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DE102008011809A1 (de) 2007-12-20 2009-06-25 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement
DE102015108532A1 (de) 2015-05-29 2016-12-01 Osram Opto Semiconductors Gmbh Anzeigevorrichtung mit einer Mehrzahl getrennt voneinander betreibbarer Bildpunkte

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19645035C1 (de) * 1996-10-31 1998-04-30 Siemens Ag Mehrfarbiges Licht abstrahlende Bildanzeigevorrichtung
WO2003043013A1 (fr) * 2001-11-16 2003-05-22 Thin Film Electronics Asa Appareil optoelectronique a adressage matriciel et element electrode integre
DE10236854A1 (de) * 2002-08-07 2004-02-26 Samsung SDI Co., Ltd., Suwon Verfahren und Vorrichtung zur Strukturierung von Elektroden von organischen lichtemittierenden Elementen
DE102007030129A1 (de) * 2007-06-29 2009-01-02 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung einer Mehrzahl optoelektronischer Bauelemente und optoelektronisches Bauelement
US20110241031A1 (en) 2008-12-23 2011-10-06 Osram Opto Semiconductors Gmbh Optoelectronic projection device
WO2013186035A1 (fr) * 2012-06-14 2013-12-19 Osram Opto Semiconductors Gmbh Puce semi-conductrice optoélectronique
WO2017060355A1 (fr) 2015-10-08 2017-04-13 Osram Opto Semiconductors Gmbh Composant et procédé de fabrication d'un composant

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020074351A1 (fr) * 2018-10-12 2020-04-16 Osram Opto Semiconductors Gmbh Composant à semi-conducteur optoélectronique

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