WO2018139495A1

WO2018139495A1 - Switch circuit

Info

Publication number: WO2018139495A1
Application number: PCT/JP2018/002160
Authority: WO
Inventors: 勝利徳田
Original assignee: 株式会社村田製作所
Priority date: 2017-01-30
Filing date: 2018-01-24
Publication date: 2018-08-02

Abstract

Provided is a switch circuit with which an increase in input electric power can be achieved while capping an increase in circuit area. The switch circuit is provided with: an input terminal to which a signal is input; an output terminal from which a signal is output; and a plurality of FETs in a multistage connection between the input terminal and the output terminal, the plurality of FETs being on/off-controlled in accordance with a control voltage supplied to the gate of each FET. The plurality of FETs include a first FET and a second FET provided at a position farther from the input terminal than is the first FET, wherein the first FET has a gate length longer than a gate length of the second FET.

Description

Switch circuit

The present invention relates to a switch circuit.

For example, a field effect transistor (FET) is used for a switch circuit mounted on a mobile communication device such as a mobile phone. In a switch circuit constituted by such FETs, a configuration is known in which the withstand voltage of the switch circuit is improved by connecting a plurality of FETs in multiple stages in order to satisfy the demand for an increase in input power. In this configuration, since a voltage divided by the number of stages of FETs connected in multiple stages is applied between the source and drain of each FET, an input allowable voltage according to the number of stages of FETs can be obtained.

Since the power of the signal supplied to the input terminal of the switch circuit is divided by the parasitic capacitance of each FET, a phenomenon occurs in which the voltage applied between the source and drain of each FET gradually decreases from the input terminal to the output terminal. . In order to avoid such a non-uniform source-drain voltage, for example, Patent Document 1 includes a capacitive element between the gate and source of an FET closest to the input terminal and between the gates of adjacent FETs. Thus, a configuration for evenly distributing the source-drain voltage of each FET is disclosed.

US Patent Application Publication No. 2014/0009214

Now, with the recent improvement in performance of mobile communication devices, the demand for reduction in circuit scale and increase in input power in switch circuits has become increasingly severe. In this regard, in the switch circuit disclosed in Patent Document 1, even when the source-drain voltage of each FET is evenly distributed, the FET can be destroyed if input power exceeding the withstand voltage of each FET is applied. On the other hand, when the number of FETs is increased, the withstand voltage of the switch circuit is improved, but there is a problem that the circuit area is increased.

The present invention has been made in view of such circumstances, and an object thereof is to provide a switch circuit that realizes an increase in input power while suppressing an increase in circuit area.

In order to achieve such an object, a switching circuit according to one aspect of the present invention includes an input terminal to which a signal is input, an output terminal to which a signal is output, and a plurality of stages connected in multiple stages between the input terminal and the output terminal. A plurality of FETs that are controlled to be turned on and off according to a control voltage supplied to each gate, and the plurality of FETs are located farther from the input terminal than the first FET. A gate length of the first FET is longer than a gate length of the second FET.

According to the present invention, it is possible to provide a switch circuit that realizes an increase in input power while suppressing an increase in circuit area.

It is a figure which shows the structural example of 100 A of switch circuits which concern on 1st Embodiment of this invention. It is a graph which shows the relationship between the gate length of FET, and withstand voltage. It is a figure which shows the structural example of the switch circuit 100B which concerns on 2nd Embodiment of this invention. It is a figure showing an example of composition of switch circuit 100C concerning a modification of a 2nd embodiment of the present invention. It is a figure which shows the structural example of switch circuit 100D which concerns on the other modification of 2nd Embodiment of this invention. It is a figure which shows the structural example of the switch circuit 100E which concerns on 3rd Embodiment of this invention. It is a figure which shows the structural example of the switch circuit 100F which concerns on 4th Embodiment of this invention. It is a figure which shows the structural example of the switch circuit 100G which concerns on the modification of 4th Embodiment of this invention. It is a figure which shows the structural example of the switch circuit 100H which concerns on 5th Embodiment of this invention. It is a figure which shows the structural example of the switch circuit 100I which concerns on the modification of 5th Embodiment of this invention. It is a figure which shows the structural example of the switch circuit 100J which concerns on the other modification of 5th Embodiment of this invention. It is a figure which shows the structural example of the switch circuit 100K which concerns on 6th Embodiment of this invention. It is a figure which shows the structural example of the switch circuit 100L which concerns on the modification of 6th Embodiment of this invention. It is a figure which shows the structural example of the switch circuit 100M which concerns on the other modification of 6th Embodiment of this invention. It is a figure which shows the structural example of the switch circuit 100N which concerns on 7th Embodiment of this invention. It is a figure which shows the structural example of the switch circuit 100P which concerns on the modification of 7th Embodiment of this invention. It is a graph which shows an example of the simulation result of the source-drain voltage in the switch circuit which concerns on 1st and 2nd embodiment of this invention, and a comparative example. It is a graph which shows an example of the simulation result of withstand voltage and on-resistance in the switch circuit concerning the 1st and 2nd embodiments of the present invention, and a comparative example.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

FIG. 1 is a diagram illustrating a configuration example of a switch circuit 100A according to the first embodiment of the present invention. An apparatus in which the switch circuit 100A is used is not particularly limited, but in the present specification, as an example, a description will be given assuming that the switch circuit 100A is used in a power amplification module mounted on a mobile communication device such as a mobile phone. Specifically, for example, the switch circuit 100A may be applied to a switch that passes a radio frequency (RF) signal input from an input terminal to an output terminal. In particular, the switch circuit 100A is a band switching switch provided between the power amplifier and the antenna (that is, the signal path after the RF signal is amplified by the power amplifier) in order to increase the input power as described later. And may be applied to antenna switches and the like.

As shown in FIG. 1, the switch circuit 100A includes an input terminal 10, an output terminal 20, N FETs 30 (1) to 30 (N) (N is an integer of 2 or more), and N resistive elements 40 (1 ) To 40 (N). Here, the i-th FET (i is an integer not less than 1 and not more than N) counted from the input terminal 10 side is represented as “30 (i)”. The same applies to other elements. In the present specification, an N-channel MOSFET (Metal-oxide-semiconductor Field Effect Transistor) will be described as an example of the FET. Although the same effect can be obtained with a configuration using a P-channel MOSFET, the detailed description is omitted because it is the same as the configuration using an N-channel MOSFET.

N FETs 30 (1) to 30 (N) (hereinafter, when these N FETs are not distinguished, they are also simply referred to as “each FET 30”. The same applies to other elements). 10 and the output terminal 20 are connected in multiple stages. Specifically, the FETs 30 (1) to 30 (N) are connected in series, that is, the drain and source of adjacent FETs are connected, and the gate is connected to one end of each resistance element 40. A control voltage is supplied to the gate of each FET 30 via each resistance element 40. When all the FETs connected in multiple stages are turned on by the control voltage, the input terminal 10 and the output terminal 20 are electrically connected. In this case, the input signal RFin supplied to the source of the FET 30 (1) is output as the output signal RFout from the drain of the FET 30 (N). On the other hand, when at least one stage of the FET is turned off, conduction between the input terminal 10 and the output terminal 20 is not established, and an output signal is not output.

Here, if various conditions such as the gate length, gate width, threshold value, etc. of the FETs 30 connected in multiple stages are all the same, the power of the signal supplied to the input terminal of the switch circuit is divided by the parasitic capacitance of each FET. Therefore, the source-drain voltage of each FET becomes non-uniform. Specifically, the source-drain voltage of each FET gradually increases from the output terminal 20 to the input terminal 10. Therefore, a voltage exceeding the withstand voltage can be applied between the source and drain of the FET close to the input terminal, particularly when the switch circuit is off. Therefore, the allowable input voltage of the switch circuit is limited by the withstand voltage of the FET close to the input terminal. In this regard, in the present embodiment, by adjusting the gate length of each FET 30, the input allowable voltage can be increased beyond the limitation. Hereinafter, the adjustment of the gate length will be specifically described.

FIG. 2 is a graph showing the relationship between the FET gate length and the withstand voltage. The graph shown in FIG. 2 shows the withstand voltage of the single-stage FET when the gate length of the FET is 0.24 μm, 0.28 μm, and 0.32 μm. The vertical axis indicates the withstand voltage (V) between the source and drain of the FET, and the horizontal axis indicates the gate length (μm) of the FET. As shown in FIG. 2, the withstand voltage of the FET improves as the gate length increases. Therefore, even in a multi-stage connected FET, the withstand voltage of the FET can be improved by adjusting the gate length of the FET according to the source-drain voltage.

That is, in the switch circuit 100A shown in FIG. 1, the gate length of each FET 30 is adjusted to be intentionally nonuniform. Specifically, for example, the gate lengths of several stages of FETs counted from the input terminal 10 side in each FET 30 are adjusted to be longer than the gate lengths of the other FETs. As a result, the withstand voltage of the FET close to the input terminal 10 is improved, so that the FET is suppressed from being broken even when a higher voltage is applied between the source and drain than other FETs. On the other hand, the withstand voltage of the FET far from the input terminal 10 is not improved, but the FET has a low voltage applied between the source and the drain as compared with other FETs, so the possibility of destruction is low. In general, the shorter the gate length of the FET, the lower the resistance value of the on-resistance. Therefore, in the FET far from the input terminal, the insertion length of the switch circuit can be reduced by relatively shortening the gate length.

With the above-described configuration, the switch circuit 100A is configured so that, among the FETs 30 connected in multiple stages, the gate length of the FETs close to the input terminal 10 is longer than the gate lengths of the other FETs. It is possible to increase the input allowable voltage. That is, the switch circuit 100A can realize an increase in input power while suppressing an increase in circuit area.

In the switch circuit 100A, the gate length of the FET far from the input terminal 10 (that is, the FET having a relatively low source-drain voltage) is designed to be shorter than the gate length of the other FETs. As a result, the resistance value of the on-resistance is lowered and the insertion loss of the switch circuit is reduced as compared with the configuration in which the gate lengths of all the FETs are increased.

The specific configuration of the gate length is not particularly limited, but an example will be described below. For example, the FET 30 (1) (first FET) provided at a position closest to the input terminal 10 among the FETs 30 and the FET 30 (2) (second FET) provided at a position farther from the input terminal 10 than the FET 30 (1). Attention is paid to the FET 30 (3) (third FET) provided at a position farther from the input terminal 10 than the FET 30 (2). At this time, the gate length of the FET 30 (1) is longer than the gate length of the FET 30 (2), the gate length of the FET 30 (2) is longer than the gate length of the FET 30 (3), and the gates of the FETs 30 (3) to 30 (N). The lengths may be substantially the same length.

Alternatively, if the gate length of the i-th FET counted from the input terminal 10 in each FET 30 is L (i), L (1)> L (2) ≧... ≧ L (N−1) ≧ L (N) The gate length may be designed so that That is, the gate length may be adjusted so that the FET closer to the input terminal 10 has a longer gate length and the FET farther from the input terminal 10 has a shorter gate length. As a result, the withstand voltage is increased in an FET having a relatively high voltage between the source and the drain, and the insertion loss is reduced in an FET having a relatively low voltage between the source and the drain.

Furthermore, the gate width of the FET connected in multiple stages may be adjusted in addition to the gate length. Specifically, for example, the gate width of the FET 30 (1) may be wider than the gate width of the FET 30 (2). Alternatively, the gate width may be adjusted so that the FET closer to the input terminal 10 has a wider gate width and the FET farther from the input terminal 10 has a smaller gate width. Thereby, for example, the source-drain voltage of each FET 30 can be adjusted to be uniform. Alternatively, by adjusting the gate width according to the gate length of each FET 30, it is possible to adjust so that a voltage close to the withstand voltage of each FET 30 is applied between the source and drain. Therefore, the input allowable voltage can be further increased as compared with the configuration in which the gate width is uniform.

Note that the FETs 30 (1) to 30 (N) are not limited to MOSFETs, and may be FETs such as JFETs (Junction Field Effect Transistors) and MESFETs (Metal-semiconductor Field Effect Transistors). The number of FETs connected in multiple stages is not particularly limited as long as it is two or more. Further, the FETs connected in multiple stages may be configured by connecting individual FETs in series as shown in FIG. 1, or a multi-gate FET may be used. The same applies to the following embodiments.

FIG. 3 is a diagram illustrating a configuration example of the switch circuit 100B according to the second embodiment of the present invention. In the second and subsequent embodiments, the same elements as those of the switch circuit 100A are denoted by the same reference numerals and description thereof is omitted. Further, description of matters common to the first embodiment is omitted, and only different points will be described. In particular, the same operation effect by the same configuration will not be sequentially described for each embodiment. In the switch circuit 100 </ b> B, a capacitive element is provided between the source and drain of each FET 30.

The capacitive elements 50 (1) to 50 (N) are connected between the sources and drains of the FETs 30 (1) to 30 (N), respectively. By adjusting the capacitance value of each capacitive element 50, the voltage applied between the source and drain of each FET 30 can be adjusted. Specifically, for example, the capacitance value of the capacitive element connected to the FET close to the input terminal 10 of each FET 30 is relatively large, and the capacitance value of the capacitive element connected to the FET far from the input terminal 10 is relatively large. By making it smaller, it is possible to achieve an even distribution of the source-drain voltage of the FET. In this configuration, for example, the source-drain voltage of the FET may not be distributed completely evenly due to the restriction of the size of the capacitive element accompanying the reduction in the circuit scale of the switch circuit. In this case, by applying the configuration of the switch circuit 100A, that is, by adjusting the length of the gate length of each FET 30, it is possible to improve the withstand voltage of some FETs and compensate for the nonuniformity of the source-drain voltage. it can.

Alternatively, in accordance with the withstand voltage of each FET 30, the capacitance value of the capacitive element connected to the FET having a high withstand voltage is made relatively large, and the capacitance value of the capacitive element connected to the FET having a low withstand voltage is made relatively small. Thus, a voltage close to the withstand voltage can be applied to all FETs. Therefore, the input allowable voltage of the switch circuit can be further increased as compared with the switch circuit 100A.

FIG. 4 is a diagram illustrating a configuration example of a switch circuit 100C according to a modification of the second embodiment of the present invention. In the switching circuit 100 </ b> C, a capacitive element is provided between the source of the FET 30 (1) closest to the input terminal 10 among the FETs 30 and the drain of each FET 30.

One end of each of the capacitive elements 51 (1) to 51 (N) is connected to the source of the FET 30 (1) closest to the input terminal 10 (that is, the electrode on the input terminal side), and the other end is connected to each FET 30 (1). To 30 (N) drains (ie, electrodes on the output terminal side). Thereby, each capacitive element 51 is connected between a terminal (source of FET 30 (1)) to which a signal having the highest signal level is supplied and the drain of each FET 30, and the drain voltage of each FET 30 is raised. Here, since each FET 30 is farther away from the input terminal 10, the amount of increase in the drain voltage becomes smaller, so the necessary capacitance value becomes smaller. Therefore, in the switch circuit 100C, the drain voltage of each FET 30 can be raised by the capacitive element having a capacitance value smaller than that of each capacitive element 50 in the switch circuit 100B, and the source-drain voltage can be evenly distributed.

Even with such a configuration, the switch circuit 100C can improve the withstand voltage by adjusting the length of the gate length of each FET 30 similarly to the switch circuit 100A. Further, since the required capacitance values of the capacitive elements 51 (1) to 51 (N) become smaller as the switch circuit 100C is farther from the input terminal 10, an increase in circuit area can be suppressed compared to the switch circuit 100B. .

In the example shown in FIG. 4, capacitive elements are connected in all FETs 30 (1) to 30 (N). However, some FETs (for example, on the side closer to the input terminal 10 in each FET 30). Capacitance elements may be connected only to some FETs).

FIG. 5 is a diagram illustrating a configuration example of a switch circuit 100D according to another modification of the second embodiment of the present invention. The switch circuit 100D differs from the switch circuit 100C in the connection configuration of the capacitive elements. In FIG. 5, the case of N = 7 is shown as an example, but the number of FETs is not limited to this.

In the switch circuit 100D, a plurality of FETs have one unit, and one end of each capacitive element 52 is connected to the source of the FET closest to the input terminal 10 in the unit. Specifically, in the example shown in FIG. 5, FETs 30 (1) to 30 (3) form a first unit, and FETs 30 (5) to FET 30 (7) form a second unit. . One end of each of the capacitive elements 52 (1) to 52 (3) is connected to the source of the FET 30 (1) (that is, the FET closest to the input terminal 10 in the first unit), and the other end is connected to each FET 30 (1 ) To 30 (3) drains. On the other hand, one end of each of the capacitive elements 52 (5) to 52 (7) is connected to the source of the FET 30 (5) (that is, the FET closest to the input terminal 10 in the second unit), and the other end is connected to each FET 30. (5) to 30 (7) connected to the drain. Further, the capacitive element 52 (4) corresponding to the FET 30 (4) located between the first and second units has one end connected to the source of the FET 30 (4) and the other end FET 30 (4). Connected to the drain.

In the above configuration, it is possible to avoid that the capacitance value of the capacitive element connected to the FET far from the input terminal becomes extremely small as compared with the configuration of the switch circuit 100C shown in FIG. Therefore, it is not necessary to use a minute capacity that is relatively difficult to control.

Even with such a configuration, the switch circuit 100D can improve the withstand voltage by adjusting the gate length of each FET 30 in the same manner as the switch circuit 100A. Further, since the switch circuit 100D does not need to use a very small capacity compared to the switch circuit 100C, the ratio of good products is improved.

FIG. 6 is a diagram illustrating a configuration example of the switch circuit 100E according to the third embodiment of the present invention. In the switch circuit 100E, a resistance element is provided between the source and drain of each FET 30.

The resistance elements 41 (1) to 41 (N) are connected between the sources and drains of the FETs 30 (1) to 30 (N), respectively. Thus, by connecting each resistance element 41 between the source and drain of each FET 30, the DC voltage of the source and drain of each FET 30 when the switch circuit is OFF is stabilized. Even with such a configuration, the switch circuit 100E can improve the withstand voltage by adjusting the length of the gate length of each FET 30 in the same manner as the switch circuit 100A. The resistance element 41 may be used in combination with any other embodiment.

FIG. 7 is a diagram illustrating a configuration example of a switch circuit 100F according to the fourth embodiment of the present invention, and FIG. 8 is a diagram illustrating a configuration example of a switch circuit 100G according to a modification of the fourth embodiment of the present invention. It is. In the switch circuit 100F, capacitive elements 53 (1) to 53 (N) are provided between the gate and source of each FET 30, and capacitive elements 54 (1) to 54 (N) are provided between the gate and drain. In the switching circuit 100G, capacitive elements 55 (1) to 55 (N) are provided between the bulk and the source of each FET 30, and capacitive elements 56 (1) to 56 (N) are provided between the bulk and the drain. Yes. As described above, the connection position of the elements provided in order to uniformly distribute the voltage between the source and drain of each FET 30 is not limited between the source and drain of each FET, but between the gate and source and between the gate and drain, or It may be between the bulk and the source and between the bulk and the drain. Even with such a configuration, the

switch circuits

100F and 100G can improve the withstand voltage by adjusting the length of the gate length of each FET 30 similarly to the switch circuit 100A. In addition, the

switch circuits

100F and 100G can further increase the allowable input voltage as compared with the switch circuit 100A, similarly to the switch circuit 100B.

FIG. 9 is a diagram illustrating a configuration example of a switch circuit 100H according to the fifth embodiment of the present invention, and FIG. 10 is a diagram illustrating a configuration example of a switch circuit 100I according to a modification of the fifth embodiment of the present invention. FIG. 11 is a diagram illustrating a configuration example of a switch circuit 100J according to another modification of the fifth embodiment of the present invention. In the switch circuits 100H to 100J, elements are provided between the gate and the source of the FET 30 (1) (that is, the FET closest to the input terminal 10) and between the gates of the adjacent FETs.

Specifically, in the switch circuit 100H, a capacitive element 57 (1) (first element) is provided between the gate and the source (that is, the electrode on the input terminal side) of the FET 30 (1), and adjacent FETs. Capacitance elements 57 (2) to 57 (N) (second element) are provided between the gates. Further, the switch circuit 100I is provided with a capacitive element 58 and a resistive element 42 (1) (first element) connected in series between the gate and source of the FET 30 (1), and the gates of the FETs adjacent to each other. Resistance elements 42 (2) to 42 (N) (second element) are provided between the two. Further, the switch circuit 100J is provided with a capacitive element 59 (1) and a resistance element 43 (1) (first element) connected in series between the gate and source of the FET 30 (1), and adjacent FETs. Capacitance elements 59 (2) to 59 (N) and resistance elements 43 (2) to 43 (N) (second element) connected in series with each other are provided between the gates.

As described above, the connection position of the elements provided in order to uniformly distribute the voltage between the source and drain of each FET 30 may be between the gates of the adjacent FETs. Even with such a configuration, the switch circuits 100H to 100J can improve the withstand voltage by adjusting the gate length of each FET 30 in the same manner as the switch circuit 100A. In addition, the switch circuits 100H to 100J can further increase the allowable input voltage as compared with the switch circuit 100A, similarly to the switch circuit 100B.

FIG. 12 is a diagram showing a configuration example of a switch circuit 100K according to the sixth embodiment of the present invention, and FIG. 13 is a diagram showing a configuration example of a switch circuit 100L according to a modification of the sixth embodiment of the present invention. FIG. 14 is a diagram illustrating a configuration example of a switch circuit 100M according to another modification of the sixth embodiment of the present invention. In the switch circuits 100K to 100M, elements are provided between the bulk sources of the FET 30 (1) (that is, the FET closest to the input terminal 10) and between the bulks of the adjacent FETs.

Specifically, in the switch circuit 100K, a capacitive element 60 (1) (third element) is provided between the bulk of the FET 30 (1) and the source (that is, the electrode on the input terminal side), and adjacent FETs. Capacitance elements 60 (2) to 60 (N) (fourth element) are provided between the bulks. In addition, the switch circuit 100L includes a capacitive element 61 and a resistive element 44 (1) (third element) connected in series between the bulk and the source of the FET 30 (1), and the bulks of the FETs adjacent to each other. Resistance elements 44 (2) to 44 (N) (fourth element) are provided between the two. Further, the switch circuit 100M includes a capacitive element 62 (1) and a resistive element 45 (1) (third element) connected in series between the bulk and the source of the FET 30 (1), and adjacent FETs. Capacitance elements 62 (2) to 62 (N) and resistance elements 45 (2) to 45 (N) (fourth element) connected in series with each other are provided between the bulks.

As described above, the connection position of the elements provided in order to evenly distribute the source-drain voltage of each FET 30 may be between the bulks of the adjacent FETs. Even with such a configuration, the switch circuits 100K to 100M can improve the withstand voltage by adjusting the gate length of each FET 30 in the same manner as the switch circuit 100A. In addition, the switch circuits 100K to 100M can further increase the allowable input voltage as compared with the switch circuit 100A, similarly to the switch circuit 100B.

FIG. 15 is a diagram illustrating a configuration example of a switch circuit 100N according to the seventh embodiment of the present invention, and FIG. 16 is a diagram illustrating a configuration example of a switch circuit 100P according to a modification of the seventh embodiment of the present invention. It is. In the

switch circuits

100N and 100P, a bias voltage is supplied to the bulk of each FET 30.

Specifically, in the switch circuit 100N, diode elements 70 (1) to 70 (N) are provided between the gate and bulk of each FET 30. Each diode element 70 has an anode connected to the bulk of each FET 30 and a cathode connected to the gate of each FET 30. The switch circuit 100P is provided with resistance elements 46 (1) to 46 (N) connected in series to the bulk of each FET 30. A bias voltage Vbias is supplied to the bulk of each FET 30 via each resistance element 46.

With the above configuration, in the

switch circuits

100N and 100P, a bias voltage can be supplied to the bulk of each FET. Even with such a configuration, the

switch circuits

100N and 100P can improve the withstand voltage by adjusting the length of the gate length of each FET 30 similarly to the switch circuit 100A. In the switch circuits 100A to 100M, a bias voltage can be supplied to the bulk of each FET 30 similarly to the

switch circuits

100N and 100P, and the same effect can be obtained.

FIG. 17 is a graph showing an example of a simulation result of the source-drain voltage in the switch circuit and the comparative example according to the first and second embodiments of the present invention. In the simulation, in each of the switch circuits in which 12 stages of FETs are connected in multiple stages, when the power of the input signal is increased and the source-drain voltage of any FET reaches the withstand voltage, The drain-to-drain voltage is shown. For convenience of explanation, reference numerals 1 to 12 are used in order from the FET closest to the input terminal. In the first embodiment, as an example of the switch circuit 100A, the gate length of the FET 30 (1) is 0.32 μm, the gate length of the FET 30 (2) is 0.28 μm, and the gates of the FETs 30 (3) to 30 (12). The length is 0.24 μm. In the second embodiment, the gate length is the same as that of the first embodiment. As an example of the switch circuit 100B, the capacitive elements 50 (1) to 50 (1) to 50 (1) to 30 (4) are arranged between the sources and drains of the four-stage FETs. 50 (4) is provided. In the comparative example, the gate lengths of the FETs 30 (1) to 30 (12) are all 0.24 μm. In the graph shown in FIG. 17, the vertical axis indicates the source-drain voltage (V) in each FET, and the horizontal axis indicates the sign of the FETs attached in order from the input terminal. Moreover, the three horizontal lines in the graph shown in FIG. 17 indicate the withstand voltage according to the gate length of each FET.

As shown in FIG. 17, in the comparative example, the higher the voltage between the source and the drain is applied to the FET closer to the input terminal, the maximum input power (38.5 dBm) when the FET 30 (1) reaches the withstand voltage. Is supplied. On the other hand, in the first embodiment, since the withstand voltage of the FET 30 (1) and the FET 30 (2) is improved, the maximum input power (40.3 dBm) is supplied when the FET 30 (3) reaches the withstand voltage. . Further, in the second embodiment, by adjusting the capacitance value of the capacitive element provided between the source and drain of the FETs 30 (1) to 30 (4), the voltage between the source and drain of each FET is set to a withstand voltage. You can get closer. Therefore, in the second embodiment, the maximum input power (42 dBm) is supplied when all of the FETs 30 (1) to 30 (4) reach the withstand voltage.

FIG. 18 is a graph showing an example of simulation results of withstand voltage and on-resistance in the switch circuit and the comparative example according to the first and second embodiments of the present invention. In the graph shown in FIG. 18, the left side of the vertical axis represents the withstand voltage (V) of the switch circuit, and the right side of the vertical axis represents the on-resistance × off-capacitance (fsec) of the switch circuit. The conditions in the graph are the same as the conditions in FIG.

As shown in FIG. 18, the withstand voltage of the first embodiment is improved by about 6V compared to the comparative example. Further, the withstand voltage of the second embodiment is improved by about 7V compared to the first embodiment. On the other hand, it can be seen that the on-resistance × off-capacitance is deteriorated as compared with the comparative example, particularly in the second embodiment in which the capacitive element is provided. That is, the length of the gate, the presence / absence of addition of a capacitor element, the number of elements to be added, or the like may be adjusted according to the required specifications of the switch circuit.

The exemplary embodiments of the present invention have been described above. The switch circuits 100A to 100P include a plurality of FETs connected in multiple stages, and an FET closer to the input terminal 10 has a longer gate length than an FET farther from the input terminal 10 than the FET. As a result, the withstand voltage of the FET close to the input terminal 10 is improved as compared with the configuration having a uniform gate length, and the input allowable voltage can be increased. Therefore, the switch circuits 100A to 100P can realize an increase in input power while suppressing an increase in circuit area. Further, the resistance value of the on-resistance is lowered and the insertion loss of the switch circuit is reduced as compared with the configuration in which the gate lengths of all the FETs are increased.

Further, the configuration of the length of the gate length of the FET is not particularly limited. For example, the gate length may be increased in order from the FET closer to the input terminal 10.

In the switch circuit 100B, each capacitive element 50 is provided between the source and drain of each FET 30. Thereby, equal distribution of the source-drain voltage of each FET 30 can be achieved. Alternatively, a voltage close to the withstand voltage can be applied to all FETs. Therefore, the input allowable voltage of the switch circuit can be further increased as compared with the switch circuit 100A.

In the switching circuit 100C, each capacitive element 51 is provided between the source of the FET 30 (1) closest to the input terminal 10 among the FETs 30 and the drain of each FET 30. Thereby, equal distribution of the source-drain voltage of each FET 30 can be achieved. Alternatively, a voltage close to the withstand voltage can be applied to all FETs. Therefore, the input allowable voltage of the switch circuit can be further increased as compared with the switch circuit 100A. Further, since the required capacitance value of each capacitive element 51 becomes smaller as the switch circuit 100C is farther from the input terminal 10, an increase in circuit area can be suppressed compared to the switch circuit 100B.

In the switch circuit 100F, the

capacitive elements

53 and 54 are provided between the gate and the source of each FET 30 and between the gate and the drain. Thereby, equal distribution of the source-drain voltage of each FET 30 can be achieved. Alternatively, a voltage close to the withstand voltage can be applied to all FETs. Therefore, the input allowable voltage of the switch circuit can be further increased as compared with the switch circuit 100A.

In the switch circuit 100G, the

capacitive elements

55 and 56 are provided between the bulk and the source of the FET 30 and between the bulk and the drain. Thereby, equal distribution of the source-drain voltage of each FET 30 can be achieved. Alternatively, a voltage close to the withstand voltage can be applied to all FETs. Therefore, the input allowable voltage of the switch circuit can be further increased as compared with the switch circuit 100A.

In addition, the switch circuits 100H to 100J include a capacitance element, a resistance element, or a series connection between the gate and the source of the FET 30 (1) closest to the input terminal 10 among the FETs 30 and between the gates of the adjacent FETs. Either a connected capacitive element or resistive element is provided. Thereby, equal distribution of the source-drain voltage of each FET 30 can be achieved. Alternatively, a voltage close to the withstand voltage can be applied to all FETs. Therefore, the input allowable voltage of the switch circuit can be further increased as compared with the switch circuit 100A.

Further, the switch circuits 100K to 100P include a capacitance element, a resistance element, or a series connection between the bulk sources of the FET 30 (1) closest to the input terminal 10 among the FETs 30 and between the bulks of adjacent FETs. Either a connected capacitive element or resistive element is provided. Thereby, equal distribution of the source-drain voltage of each FET 30 can be achieved. Alternatively, a voltage close to the withstand voltage can be applied to all FETs. Therefore, the input allowable voltage of the switch circuit can be further increased as compared with the switch circuit 100A.

Further, as shown in the switch circuit 100N, a diode element 70 may be provided between the gate and bulk of each FET 30, and a bias voltage may be supplied to the bulk of each FET 30. Alternatively, as shown in the switch circuit 100P, a bias voltage may be supplied to the bulk of each FET 30 via each resistance element 46.

In the switch circuit 100E, each resistance element 41 is provided between the source and drain of each FET 30. This stabilizes the DC voltage at the source and drain of each FET 30 when the switch circuit is off.

Further, in the switch circuits 100A to 100P, the FET closer to the input terminal 10 among the FETs 30 may have a wider gate width than the FET farther from the input terminal 10 than the FET. Thereby, equal distribution of the source-drain voltage of each FET 30 can be achieved. Alternatively, a voltage close to the withstand voltage can be applied to all FETs. Therefore, the input allowable voltage of the switch circuit can be further increased as compared with the configuration in which the gate width is uniform.

In each of the above-described embodiments, in each FET 30, an example in which the electrode on the input terminal side is the source and the electrode on the output terminal side is the drain is shown, but instead of this, the electrode on the input terminal side is The drain and the electrode on the output terminal side may be the source.

Each embodiment described above is for facilitating the understanding of the present invention, and is not intended to limit the present invention. The present invention can be changed or improved without departing from the gist thereof, and the present invention includes equivalents thereof. In other words, those obtained by appropriately modifying the design of each embodiment by those skilled in the art are also included in the scope of the present invention as long as they include the features of the present invention. For example, each element included in each embodiment and its arrangement, material, condition, shape, size, and the like are not limited to those illustrated, and can be changed as appropriate. In addition, each element included in each embodiment can be combined as much as technically possible, and combinations thereof are included in the scope of the present invention as long as they include the features of the present invention.

DESCRIPTION OF SYMBOLS 10 ... Input terminal, 20 ... Output terminal, 30 ... FET, 40-46 ... Resistance element, 50-62 ... Capacitance element, 70 ... Diode element, 100A-100P ... Switch circuit

Claims

An input terminal to which a signal is input;
An output terminal from which the signal is output;
A plurality of FETs connected in multiple stages between the input terminal and the output terminal, the plurality of FETs being controlled to be turned on and off according to a control voltage supplied to each gate;
With
The plurality of FETs includes a first FET and a second FET provided at a position farther from the input terminal than the first FET,
The gate length of the first FET is longer than the gate length of the second FET,
Switch circuit.
The plurality of FETs further includes a third FET provided at a position farther from the input terminal than the second FET,
The gate length of the second FET is longer than the gate length of the third FET.
The switch circuit according to claim 1.
The plurality of FETs includes N (N is an integer of 2 or more) FETs connected in series,
When the gate length of the i-th FET (i is an integer from 1 to N) counted from the input terminal is L (i),
L (1)> L (2) ≧ ... ≧ L (N−1) ≧ L (N)
Is established,
The switch circuit according to claim 1 or 2.
The switch circuit is
A capacitive element is provided between the source and drain of each of the plurality of FETs.
The switch circuit according to any one of claims 1 to 3.
The switch circuit is
Among the plurality of FETs, a capacitance between the electrode on the input terminal side of the source or drain of the FET closest to the input terminal and the electrode on the output terminal side among the sources or drains of the plurality of FETs Each element was provided,
The switch circuit according to any one of claims 1 to 3.
The switch circuit is
Capacitance elements are provided between the gate and source of each of the plurality of FETs and between the gate and drain.
The switch circuit according to any one of claims 1 to 3.
The switch circuit is
Capacitance elements are provided between the bulk and the source and between the bulk and the drain of each of the plurality of FETs.
The switch circuit according to any one of claims 1 to 3.
The switch circuit is
Among the plurality of FETs, a first element is provided between the gate of the FET closest to the input terminal and the electrode on the input terminal side of the source or drain of the FET,
Among the plurality of FETs, a second element is provided between the gates of adjacent FETs.
The switch circuit according to any one of claims 1 to 3.
Each of the first and second elements is either a capacitive element, a resistive element, or a capacitive element and a resistive element connected in series with each other.
The switch circuit according to claim 8.
The switch circuit is
A third element is provided between the bulk of the FET closest to the input terminal of the plurality of FETs and the electrode on the input terminal side of the source or drain of the FET,
Of the plurality of FETs, a fourth element is provided between the bulks of the adjacent FETs.
The switch circuit according to any one of claims 1 to 3.
Each of the third and fourth elements is either a capacitive element, a resistive element, or a capacitive element and a resistive element connected in series with each other.
The switch circuit according to claim 10.
The switch circuit is
A diode element is provided between the gate and bulk of each of the plurality of FETs,
The anode of the diode element is connected to the bulk, and the cathode of the diode element is connected to the gate;
The switch circuit according to any one of claims 1 to 11.
The switch circuit is
A resistive element is connected in series to the bulk of each of the plurality of FETs,
A bias voltage is supplied to the bulk via the resistance element.
The switch circuit according to any one of claims 1 to 11.
The switch circuit is
A resistance element is provided between the source and drain of each of the plurality of FETs.
The switch circuit according to any one of claims 1 to 13.
The gate width of the first FET is wider than the gate width of the second FET,
The switch circuit according to any one of claims 1 to 14.