WO2018137446A1 - 一种编译码方法和终端 - Google Patents

一种编译码方法和终端 Download PDF

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Publication number
WO2018137446A1
WO2018137446A1 PCT/CN2017/117571 CN2017117571W WO2018137446A1 WO 2018137446 A1 WO2018137446 A1 WO 2018137446A1 CN 2017117571 W CN2017117571 W CN 2017117571W WO 2018137446 A1 WO2018137446 A1 WO 2018137446A1
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Prior art keywords
information
bit
bits
cyclic redundancy
subchannel
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PCT/CN2017/117571
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English (en)
French (fr)
Inventor
周悦
李榕
罗禾佳
张华滋
陈莹
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to BR112019015057-9A priority Critical patent/BR112019015057A2/pt
Priority to EP17894234.8A priority patent/EP3573262B1/en
Publication of WO2018137446A1 publication Critical patent/WO2018137446A1/zh
Priority to US16/521,391 priority patent/US10700705B2/en
Priority to US16/914,775 priority patent/US11303298B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/098—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit using single parity bit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H04L1/0063—Single parity check
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching

Definitions

  • the present application relates to the field of communications, and in particular, to a coding and decoding method and a terminal.
  • the information uses a polarization coding scheme.
  • an outer code having a check capability can be cascaded outside the Polar.
  • the cascading outer code is divided into a Cyclic Redundancy Check (CRC) code and a Parity-Check (PC) code.
  • CRC Cyclic Redundancy Check
  • PC Parity-Check
  • CA CRC-assisted Polar
  • PC-Polar the scheme of using the PC code as an outer code.
  • the CA-Polar scheme is to determine the subchannels of the frozen bits and the subchannels of the information bits on the encoding side, and determine the bits to be transmitted on the subchannels of the Frozen bits and the subchannels of the information bits, and then perform all the bits.
  • Polar code The bits transmitted by the subchannels of the Frozen bits may be 0 bits or convention bits, and the bits transmitted on the subchannels of the information bits may include information bits and CRC bits.
  • the decoding result of the multiple paths of the decoder is CRC, and the path through the CRC is used as the decoding output result.
  • the PC-Polar scheme is to determine the subchannel of the Frozen bit, the subchannel of the PC-Frozen bit, and the subchannel of the information bit on the encoding side, and determine the subchannel of the Frozen bit, the subchannel of the PC-Frozen bit, and the information bit.
  • the bits that need to be passed on the subchannel are then Polar encoded for all bits.
  • the bit transmitted by the subchannel of the Frozen bit may be 0 bit or a reserved bit, the bit transmitted by the subchannel of the PC-Frozen bit is a PC-Frozen bit, and the bit transmitted on the subchannel of the information bit is an information bit.
  • the PC bits are distributed among the information bits, and the intermediate stage of decoding can provide early stop by using the PC bit, that is, in any path, if a decoding error occurs during the execution of the decoding process, the translation of the path is performed.
  • the code process interrupts and deletes the path, thereby determining the path decoded by the PC in the multiple paths of the decoder.
  • a simplified PC-Polar solution called Simplified PC-Polar (Sim-PC)
  • the Sim-PC solution utilizes the quasi-periodic nature of channel polarization, with each cycle as a segment.
  • the PC-Polar construction complexity is simplified by pre-selecting PC-Frozen bits in each segment.
  • the comparison between the Block Error Rate (BLER) performance of the Sim-PC and the PC-Polar (referred to as PC in FIG. 1) when the information bit size is 120 is included in FIG. 1 .
  • BLER Block Error Rate
  • PC PC-Polar
  • the block error rate curve decreases with the increase of signal-to-noise ratio (the higher the slope), indicating that the method can achieve higher transmission reliability faster with the increase of signal-to-noise ratio.
  • Sim-PC has a slight loss in the performance of the high signal to noise ratio interval at the decoding end.
  • the embodiment of the present application provides a coding and decoding method and a terminal, which can improve the decoding performance of a polarization code.
  • an embodiment of the present application provides an encoding method, including: performing, by a transmitting end, cyclic redundancy check on a coded information to obtain first coded information; and sending, by a transmitting end, parity coding of the first coded information to obtain a second Encoding information; the transmitting end performs polarization encoding on the second encoded information to obtain third encoded information and output the same to the receiving end.
  • the transmitting end performs both cyclic redundancy check and parity check before performing polarization coding, so that on the decoding side, the receiving end will pass parity coding and cyclic redundancy.
  • the decoded result output is verified.
  • the embodiment performs two-pass coding and two-fold verification, that is, CRC-assisted PC-Polar coding, and only performs CRC coding before PC-Polar coding, which can improve decoding error detection capability and improve polarization code decoding. performance.
  • the transmitting end performs cyclic redundancy check on the coded information
  • the first coded information includes: adding, by the transmitting end, the cyclic redundancy check bit to the information bits of the coded information, to obtain the first coded information, and looping
  • the redundancy check bit includes a first cyclic redundancy check bit and a second cyclic redundancy check bit, the first cyclic redundancy check bit is obtained according to the information bit, and the second cyclic redundancy check bit is based on the information
  • the first cyclic redundancy check bit is used to check information bits and the second cyclic redundancy check bit is used for auxiliary decoding.
  • the first cyclic redundancy check bit can be used to check whether there is an error in the information bit, and the second cyclic redundancy check bit can be used for auxiliary decoding to ensure that the missed detection probability of the output decoded value is sufficient. low.
  • the transmitting end performs parity encoding on the first encoded information
  • obtaining the second encoded information includes: the transmitting end sets the information bits of the first encoded information and the check frozen bit according to the reliability of each subchannel. And the frozen bits are allocated to the respective subchannels to obtain the second coding information.
  • the information bits and the check freeze bits in the second coding information are allocated in the subchannel with high reliability, and the frozen bits are allocated in the subchannel with low reliability. In this way, the information bits and the check frozen bits are allocated in the subchannel with high reliability, and the frozen bits are allocated in the subchannel with low reliability, which ensures that the transmission performance of the more important information bits and the check frozen bits is higher than that. Freeze bit transmission performance.
  • the parity check is performed after performing the cyclic redundancy check on the encoding side, that is, the transmitting end, and the BLER performance of the decoded value outputted on the decoding side of the decoding side is compared with the existing
  • the technique is only performing parity check coding on the coding side, and comparing the BLER performance of the decoded value outputted on the decoding side
  • FIG. 1a includes the information of the application (PC-CA) and the prior art (PC) in the to-be-coded information.
  • the number of information bits is 120
  • the number of encoded bits is the BLER performance of the decoded values of 240, 360, and 720, respectively.
  • the block error rate illustrates the transmission reliability of the encoding method
  • the codec method of the present application has a lower block error rate under the same SNR value than the prior art codec method, and The increase in signal-to-noise ratio is slower and the block rate is faster, so it has better coding performance.
  • the transmitting end performs parity coding on the first encoded information
  • obtaining the second encoded information includes: the transmitting end sets the information bits and the check of the first encoded information according to the quasi-periodic characteristic of the subchannel polarization. Freeze bits to And the frozen bits are allocated to the respective subchannels to obtain the second encoded information.
  • the transmitting end can allocate the information bits of the first coding information, the check freeze bits, and the freeze bits to the respective subchannels according to the quasi-periodic characteristics of the subchannel polarization, thereby obtaining the second coded information.
  • FIG. 1b includes information of the information to be encoded in the present application and the prior art. When the number of bits is 120, the number of encoded bits is the BLER performance of the decoded values of 240, 360, and 720, respectively.
  • the block error rate illustrates the transmission reliability of the encoding method
  • the codec (Sim-PC CA) method of the present application has the same signal-to-noise ratio value as compared with the prior art (Sim-PC) codec method.
  • the block error rate is greatly reduced, and the block error rate decreases more rapidly with the increase of the signal-to-noise ratio, so that the coding performance is greatly improved.
  • the transmitting end allocates information bits, check freeze bits and freeze bits of the first coding information to each subchannel according to the quasi-periodic characteristic of the subchannel polarization, including: the sender acquires each subchannel. a reliability sequence, and obtaining a subchannel corresponding to the punctured bit or the truncated bit by a polarization code rate matching method; the transmitting end acquires a subchannel segment point set according to a quasi-period of the subchannel polarization for each subchannel, to The sub-channel is segmented; the transmitting end determines a sequence number corresponding to the sub-channel corresponding to the sub-channel or the truncated bit corresponding to the sub-channel corresponding to the punctured bit and the sub-channel corresponding to the check frozen bit in each segment; the transmitting end
  • the sub-channels other than the sub-channels corresponding to the information bits, the check freeze bits, and the punctured bits in each sub-channel are determined as sub-channels of the frozen bits
  • Subchannels other than the corresponding subchannel are determined as subchannels of frozen bits.
  • the transmitting end can allocate the information bits of the first coding information, the check freeze bits, and the freeze bits to the respective subchannels according to the quasi-periodic characteristics of the subchannel polarization, thereby obtaining the second coded information.
  • the sending end may acquire segment points in the
  • the sub-channel corresponding to the first P fg sequence number in the sequence number set of each segment, the sub-channel corresponding to the subsequent P fg sequence numbers, or the sub-channel corresponding to the intermediate P fg sequence numbers are check freeze bits.
  • g is the segment number
  • P fg is a non-negative integer
  • g is a positive integer greater than or equal to 1.
  • the transmitting end may use the sub-channel corresponding to the pre-P fg sequence number of the sub-channel corresponding to the information bit and the check-and-freeze bit in each segment, and the sub-channel or the intermediate P fg corresponding to the subsequent P fg sequence numbers.
  • the subchannel corresponding to the sequence number is determined to be a subchannel corresponding to the check freeze bit.
  • the embodiment of the present application provides a sending apparatus, including: a checking unit, configured to perform cyclic redundancy check on a coded information to obtain first coded information, and a coding unit, configured to perform parity on the first coded information.
  • the encoding unit obtains the second encoding information, and the encoding unit is further configured to perform polarization encoding on the second encoding information to obtain the third encoding information and output the third encoding information to the receiving end.
  • the check unit is configured to: add a cyclic redundancy check bit to the information bits of the coded information to obtain first coded information, and the cyclic redundancy check bit includes the first cyclic redundancy check bit and Second cycle redundancy school
  • the first cyclic redundancy check bit is obtained according to the information bit
  • the second cyclic redundancy check bit is obtained according to the information bit and the first cyclic redundancy check bit, and the first cyclic redundancy check bit is obtained.
  • the second cyclic redundancy check bits are used for auxiliary decoding.
  • the coding unit is configured to: allocate information bits of the first coding information, check freeze bits, and freeze bits to each subchannel according to reliability of each subchannel, to obtain second coding information, The information bits and the check freeze bits in the two-coded information are allocated in the subchannel with high reliability, and the freeze bits are allocated in the subchannel with low reliability.
  • the coding unit is configured to: allocate information bits of the first coding information, check freeze bits, and freeze bits to each subchannel according to a quasi-periodic characteristic of the subchannel polarization, to obtain second coding information. .
  • the coding unit includes: an acquisition subunit, configured to acquire a reliability sequence of each subchannel, and obtain a subchannel corresponding to the punctured bit or the truncated bit by using a polarization code rate matching manner; a unit, configured to acquire, according to a quasi-period of subchannel polarization of each subchannel, a subchannel segment point set to segment each subchannel; and determine a subunit, configured to determine, in each segment, a corresponding punch bit a sub-channel or a truncated bit corresponding to the sub-channel other than the sub-channel corresponding to the sub-channel corresponding to the sub-channel corresponding to the sequence set; the determining sub-unit is further configured to: the information bits, check freeze bits and perforation in each sub-channel The subchannels other than the subchannels corresponding to the bits are determined as subchannels of the frozen bits; or the subchannels other than the subchannels corresponding to the information bits, the check freeze bits, and the trunc
  • the sub-channel corresponding to the first P fg sequence number in the sequence number set of each segment, the sub-channel corresponding to the subsequent P fg sequence numbers, or the sub-channel corresponding to the intermediate P fg sequence numbers are check freeze bits.
  • g is the segment number
  • P fg is a non-negative integer
  • g is a positive integer greater than or equal to 1.
  • an embodiment of the present application provides a sending apparatus, including: a processor, configured to perform cyclic redundancy check on a coded information to obtain first coded information, and a processor, configured to perform parity on the first coded information. Checking the code to obtain the second coded information; the processor is further configured to perform polarization coding on the second coded information to obtain the third coded information and output the same to the receiving end.
  • the processor is configured to: add a cyclic redundancy check bit to the information bits of the coded information to obtain first coded information, where the cyclic redundancy check bit includes the first cyclic redundancy check bit and the second Cyclic redundancy check bit, the first cyclic redundancy check bit is obtained according to the information bit, and the second cyclic redundancy check bit is obtained according to the information bit and the first cyclic redundancy check bit, the first cyclic redundancy The remainder check bits are used to verify the information bits and the second cyclic redundancy check bits are used to assist in decoding.
  • the processor is configured to: allocate information bits of the first coding information, check freeze bits, and freeze bits to each subchannel according to reliability of each subchannel, to obtain second coded information, and second The information bits and the check freeze bits in the coded information are allocated in a subchannel with high reliability, and the freeze bits are allocated in a sub-reliability sub-channel. In the channel.
  • the processor is configured to: allocate information bits of the first coding information, check freeze bits, and freeze bits to each subchannel according to a quasi-periodic characteristic of the subchannel polarization to obtain second coded information.
  • the processor is further configured to obtain a reliability sequence of each subchannel, and obtain a subchannel corresponding to the punctured bit or the truncated bit by using a polarization code rate matching manner; and subchannels for each subchannel.
  • the subchannels other than the subchannel corresponding to the bit, the check freeze bit, and the truncated bit are determined as subchannels of the freeze bit.
  • the sub-channel corresponding to the first P fg sequence number in the sequence number set of each segment, the sub-channel corresponding to the subsequent P fg sequence numbers, or the sub-channel corresponding to the intermediate P fg sequence numbers are check freeze bits.
  • g is the segment number
  • P fg is a non-negative integer
  • g is a positive integer greater than or equal to 1.
  • an embodiment of the present invention provides a device, which is in the form of a product of a chip.
  • the device includes a processor and a memory, and the memory is coupled to the processor to save necessary program instructions of the device. And data for executing the program instructions stored in the memory such that the apparatus performs the functions of the transmitting apparatus in the above method.
  • an embodiment of the present invention provides a sending apparatus, where the sending apparatus can implement the functions performed by the sending apparatus in the foregoing method embodiment, and the functions can be implemented by using hardware or by executing corresponding software by hardware.
  • the hardware or software includes one or more modules corresponding to the above functions.
  • the structure of the transmitting device includes a processor and a communication interface configured to support the transmitting device to perform a corresponding function in the above method.
  • the communication interface is used to support communication between the transmitting device and other network elements.
  • the transmitting device can also include a memory for coupling with the processor that holds the program instructions and data necessary for the transmitting device.
  • an embodiment of the present invention provides a computer readable storage medium, comprising instructions, when executed on a computer, causing a computer to perform any one of the methods provided by the first aspect.
  • an embodiment of the present invention provides a computer program product comprising instructions that, when run on a computer, cause the computer to perform any of the methods provided by the first aspect.
  • the embodiment of the present application provides a decoding method, including: receiving, by a receiving end, a PC-Successive cancellation list (PC-SCL) decoder to obtain each path after decoding the information to be decoded. Decoding value; the receiving end performs cyclic redundancy check on each path to obtain information bits of the path through the cyclic redundancy check. In this way, the receiving end can compare the information of the path through the cyclic redundancy check in the decoded value of each path of the PC-SCL. The output of the first path of the PC-SCL is outputted, and the decoded value of the first path may be incorrect.
  • the PC-SCL decoding and the CRC provided by the embodiments of the present application are provided. The verification can further reduce the probability of the decoding value error, thereby improving the decoding performance of the polarization code.
  • the decoded value of the path includes information bits of information to be decoded and cyclic redundancy check bits
  • the cyclic redundancy check bits include the first cyclic redundancy a remainder check bit and a second cyclic redundancy check bit
  • the first cyclic redundancy check bit is obtained according to the information bit
  • the second cyclic redundancy check bit is based on the information bit and the first cyclic redundancy check bit
  • the first cyclic redundancy check bit is used to check information bits
  • the second cyclic redundancy check bit is used for auxiliary decoding.
  • the first cyclic redundancy check bit can be used to check whether there is an error in the information bit, and the second cyclic redundancy check bit can be used for auxiliary decoding to ensure that the missed detection probability of the output decoded value is sufficient. low.
  • the receiving end performs cyclic redundancy check on each path, and the information bits of the path obtained by the cyclic redundancy check include: the receiving end assists the PC-SCL translation through the second cyclic redundancy check bit.
  • the coder selects any path, checks the information bits of any path by the first cyclic redundancy check bit in any path, and determines the information bits when the information bits of any path are correct is determined by cyclic redundancy. The information bits of the checked path.
  • the receiving end can determine which of the PC-SCL decoders to decode the decoded value according to the first cyclic redundancy check bit and the first cyclic redundancy check bit, compared to the prior art PC-
  • the decoded value of the first path of the SCL is output, and the decoded value of the first path may have an error.
  • the coding and decoding method provided by the embodiment of the present application can reduce the probability of the error of the decoded value, thereby improving the translation of the polarization code. Code performance.
  • a ninth aspect, the embodiment of the present invention provides a receiving apparatus, including: an acquiring unit, configured to acquire, by using a PC-SCL decoder, a decoding value of each path after decoding the information to be decoded; It is used to perform cyclic redundancy check on each path to obtain information bits of the path through the cyclic redundancy check.
  • the decoded value of the path includes information bits of information to be decoded and cyclic redundancy check bits
  • the cyclic redundancy check bits include the first cyclic redundancy a remainder check bit and a second cyclic redundancy check bit
  • the first cyclic redundancy check bit is obtained according to the information bit
  • the second cyclic redundancy check bit is based on the information bit and the first cyclic redundancy check bit
  • the first cyclic redundancy check bit is used to check information bits
  • the second cyclic redundancy check bit is used for auxiliary decoding.
  • the check unit is configured to select any path by the second cyclic redundancy check bit to assist the PC-SCL decoder to pass the first cyclic redundancy check bit check in any path.
  • the information bits of any path determine the information bits when the information bits of any of the paths are correct as the information bits of the path through the cyclic redundancy check.
  • the embodiment of the present application provides a receiving apparatus, including: a processor, configured to acquire, by using a PC-SCL decoder, a decoding value of each path after decoding information to be decoded; a processor, It is also used to perform cyclic redundancy check on each path to obtain information bits of the path through the cyclic redundancy check.
  • the decoded value of the path includes information bits of information to be decoded and cyclic redundancy check bits
  • the cyclic redundancy check bits include the first cyclic redundancy a remainder check bit and a second cyclic redundancy check bit
  • the first cyclic redundancy check bit is obtained according to the information bit
  • the second cyclic redundancy check bit is based on the information bit and the first cyclic redundancy check bit
  • the first cyclic redundancy check bit is used to check information bits
  • the second cyclic redundancy check bit is used for auxiliary decoding.
  • the processor is configured to select any path by the second cyclic redundancy check bit-assisted PC-SCL decoder, and verify any of the first cyclic redundancy check bits in either path. The information bits of the path will be verified The information bits when the information bits of any of the paths are correct are determined as the information bits of the path through the cyclic redundancy check.
  • an embodiment of the present invention provides a device, which is in the form of a product of a chip.
  • the device includes a processor and a memory, and the memory is coupled to the processor to save the necessary program of the device.
  • the instructions and data are used by the processor to execute program instructions stored in the memory such that the apparatus performs the functions of the receiving means in the method described above.
  • the embodiment of the present invention provides a receiving device, which can implement the functions performed by the receiving device in the foregoing method embodiment, and the function can be implemented by using hardware or by executing corresponding software through hardware.
  • the hardware or software includes one or more modules corresponding to the above functions.
  • the receiving device includes a processor and a communication interface configured to support the receiving device to perform a corresponding function in the above method.
  • the communication interface is used to support communication between the receiving device and other network elements.
  • the receiving device can also include a memory for coupling with the processor that retains the program instructions and data necessary for the receiving device.
  • an embodiment of the present invention provides a computer readable storage medium, including instructions, when executed on a computer, causing a computer to perform any one of the methods provided in the eighth aspect.
  • an embodiment of the present invention provides a computer program product comprising instructions, which when executed on a computer, cause the computer to perform any of the methods provided by the eighth aspect.
  • the transmitting end performs both the cyclic redundancy check and the parity check before performing the polarization coding.
  • the receiving end passes the parity check and the cyclic redundancy check. The result of the decoding is output.
  • the embodiment performs two-pass encoding and two-checking, that is, CRC-assisted PC-Polar encoding, performing CRC encoding only before PC-Polar encoding, and translating only in PC-SCL through CRC-assisted PC-Polar decoding.
  • the operation of adding the CRC selection path after the code can improve the error detection capability of the decoding and improve the decoding performance of the polarization code.
  • FIG. 1 is a schematic diagram of the performance of a prior art Sim-PC and PC-Polar
  • 1a is a schematic diagram of performance of an output decoding value of a PC and a PC CA according to an embodiment of the present application;
  • FIG. 1b is a schematic diagram of performance of an output decoding value of a Sim-PC and a Sim-PC CA according to an embodiment of the present application;
  • FIG. 2 is a schematic structural diagram of a system according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of an internal structure of a transmitting end according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of an internal structure of a receiving end according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic flowchart of a method for encoding and decoding according to an embodiment of the present application
  • FIG. 6 is a schematic diagram of reliability of each subchannel according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of allocation of a subchannel according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of reliability of each subchannel according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of reliability of each subchannel corresponding to a reliability sequence Q according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of reliability of each subchannel according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a sending apparatus according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a sending apparatus according to an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a receiving apparatus according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a receiving apparatus according to an embodiment of the present application.
  • the embodiment of the present application can be applied to a scenario in which the information bits are poli-coded and decoded, for example, a scenario in which the eMBB uplink control information and the downlink control information are subjected to Polar encoding and decoding, and can also be applied to other scenarios, such as applications.
  • the channel coding (VC) of the communication standard 36.212, the uplink control information, the downlink control information, and the channel coding part of the Sidelink channel are not limited in this embodiment.
  • the system of the embodiment of the present application may include a transmitting end and a receiving end, as shown in FIG. 2, which is a schematic diagram of a system architecture of a transmitting end and a receiving end.
  • the transmitting end is an encoding side, and can be used for encoding and outputting encoded information, and the encoded information is transmitted to the decoding side on the channel;
  • the receiving end is a decoding side, which can be used to receive the encoded information sent by the transmitting end, and the encoding is performed.
  • Information decoding may be a terminal, a server, a base station, or other device that can compile a code, which is not limited in this application.
  • the terminal can be a personal computer (PC), a mobile phone, a tablet, a smart learning machine, a smart game machine, a smart TV, a smart glasses or a smart watch.
  • FIG. 3 is a schematic diagram of an internal structure of a transmitting end according to the present invention.
  • the transmitting end may include a processing module 301, a communication module 302, and a storage module 303.
  • the processing module 301 is configured to control various parts of the hardware device and application software of the transmitting end
  • the communication module 302 is configured to receive the commands sent by other devices by using a wireless Fidelity (WiFi) communication manner, or may send the same.
  • WiFi wireless Fidelity
  • the data of the terminal is sent to other devices;
  • the storage module 303 is configured to perform storage of the software program at the transmitting end, storage of data, operation of the software, and the like.
  • the receiving end may include a processing module 401, a communication module 402, and a storage module 403.
  • the processing module 401 is configured to control each part of the hardware device and the application software of the receiving end
  • the communication module 402 is configured to receive the command sent by the other device by using a communication mode such as wifi, or send the data of the receiving end to other devices
  • the module 403 is configured to execute storage of a software program at the receiving end, storage of data, operation of software, and the like.
  • the embodiment of the present application provides a method for encoding and decoding.
  • the basic idea is that: on the encoding side, the transmitting end performs cyclic redundancy check on the coded information to obtain first coded information, and then performs parity check on the first coded information to obtain The second encoding information is then subjected to polarization encoding of the second encoding information to obtain third encoding information and output to the receiving end.
  • the receiving end acquires the decoded value of the third encoded information on each path through the decoder, and then performs cyclic redundancy check on the decoded values of the respective paths to obtain the path through the cyclic redundancy check.
  • the information bit which is the decoded result of the final output.
  • the embodiment of the present application provides a method for encoding and decoding, as shown in FIG. 5, including:
  • the transmitting end adds a cyclic redundancy check bit to the information bits of the coded information to obtain the first coded information, and then performs step 502 or step 503.
  • the length of the information bits of the first encoded information is 136 bits, that is, the information bits of the first encoded information.
  • Information bits including coded information and cyclic redundancy check bits are included.
  • the cyclic redundancy check bit may include a first cyclic redundancy check bit and a second cyclic redundancy check bit, where the first cyclic redundancy check bit is obtained according to the information bit, and the second cyclic redundancy check is performed. Bit is based on information ratio And the first cyclic redundancy check bit is used to check information bits, and the second cyclic redundancy check bit is used for auxiliary decoding, and the first cyclic redundancy check bit is obtained.
  • the length (order) may be greater than the second cyclic redundancy check bit.
  • the specific form of the CRC polynomial of the first cyclic redundancy check bit and the second cyclic redundancy check bit and the bit length are different, and the check capability of the first cyclic redundancy check bit and the second cyclic redundancy check ratio Different, therefore, the above cyclic redundancy check bits in the embodiment of the present application include the first cyclic redundancy check bit and the second cyclic redundancy check bit, and only one type of calibration is compared with the conventional cyclic redundancy check bit. The bit check can guarantee a lower false alarm probability and/or missed detection probability.
  • the transmitting end can perform two-fold CRC encoding when encoding on the encoding side, assuming that the information bit of the first encoding information is Info+CRC1+CRC2; Info is the information bit of the information to be encoded, and CRC1 is the first cyclic redundancy school.
  • the bit is checked, CRC1 can be calculated according to info;
  • CRC2 is the second cyclic redundancy check bit, which can be calculated according to Info+CRC1; and the length of CRC1 can be greater than CRC2.
  • the receiving end can decode the information bits and cyclic redundancy bits in each path through the PC-SCL decoder on the decoding side.
  • the decoder can decode info+CRC1+CRC2 of each path, and the PC-SCL decoder checks the correctness of Info+CRC1 through the CRC2 of each path, so as to select one of them.
  • the path outputs info+CRC1, and the receiving end detects whether there is an error in the info in the path according to the CRC1 of the path, and feeds back the error information to the upper layer of the physical layer.
  • the transmitting end may not add the second cyclic redundancy check bit on the encoding side.
  • the receiving end translates the information bits and the first cyclic redundant bits in each path by the SCL decoder on the decoding side. Thereafter, the information bits of the first path and the first cyclic redundancy bit may be directly output, and the information bit is determined to be erroneous by the first cyclic redundancy bit.
  • the transmitting end allocates information bits, check freeze bits, and frozen bits of the first coding information to each subchannel according to reliability of each subchannel, to obtain second coding information, and then performs step 504.
  • the information bits and the check freeze bits in the second coded information may be allocated in a subchannel with high reliability, and the freeze bits may be allocated in a subchannel with low reliability.
  • the check freeze bit can be a PC-Frozen bit.
  • the reliability of a subchannel is from low to high.
  • the reliability of the subchannel set for placing frozen bits is the lowest;
  • the subchannel set of information bits for placing the second coded information has the highest reliability, and the reliability of the subchannel for placing the PC-Frozen bit is located in the reliability of the subchannel of the allocated bit allocation and the subchannel of the information bit allocation. between. It should be noted that it is also possible that some PC-Frozen bits are placed in a subchannel with higher reliability than the subchannel in which the information bits are placed, and the reliability of the subchannel set in which the frozen bits are placed is always the lowest.
  • the information bits of the second encoded information at the transmitting end, the PC-Frozen bit, and the subchannel allocated by the Frozen bit may be a subchannel PC-Frozen allocated as an information bit as shown in FIG. 7.
  • the transmitting end may acquire PC-Frozen bits corresponding to different information bits according to different information bits and a PC-function, and a plurality of different information bit sets may correspond to one PC-Frozen bit, and therefore, at the receiving end It is possible to check whether the corresponding information bits are correct according to different PC-Frozen bits and PC-function.
  • the transmitting end allocates information bits, check freeze bits, and freeze bits of the first coding information to each subchannel according to a quasi-periodic characteristic of the subchannel polarization, to obtain second coding information.
  • the quasi-periodic characteristic of the subchannel polarization is embodied by the fact that the reliability of the subchannel exhibits periodic characteristics as the subchannel number changes. For example, as shown in Figure 8, the reliability of 256 subchannels is shown. The small squares in the figure represent each subletter. The reliability of the road. From different cycle scales, the reliability of subchannels varies from small to large. For example, in the figure, 32 subchannels are used as a period, and periodic intervals are marked with dashed lines. In each period, the subchannel reliability is generally increased from small to large. For example, if 8 subchannels are used as the cycle, the reliability of every 8 subchannels tends to increase from small to large, and the average reliability of each cycle is improved relative to the average reliability of the previous cycle.
  • the basic idea of the step 503 is: the transmitting end acquires the reliability sequence of each subchannel, and obtains the Punch bit or the subchannel corresponding to the short bit by the Polar code rate matching method;
  • the subchannel acquires a set of subchannel segment points according to a quasi-period of subchannel polarization to segment each subchannel;
  • the transmitting end determines a subchannel or a truncated bit corresponding to each of the segments corresponding to the punctured bits.
  • the transmitting end determines the information bits in the respective subchannels, the PC-Frozen bit, and the subchannels other than the subchannel corresponding to the Puncture bit as A subchannel of the Frozen bit, or a transmitting end determines a subchannel other than the subchannel of the subchannel corresponding to the information bit, the PC-Frozen bit, and the Shorten bit in each subchannel as a subchannel of the Frozen bit.
  • Step 1.1 The sender acquires the reliability sequence Q of each subchannel.
  • the sender can acquire Q through Gaussian Approximation (GA), Density Evolution (DE), Polar Weight (PW), or other methods.
  • GA Gaussian Approximation
  • DE Density Evolution
  • PW Polar Weight
  • the information in Q may include the reliability value of each subchannel or the relative relationship (sorting) of the reliability of each subchannel.
  • the reliability value of each subchannel can be described by the error probability value of each subchannel, so Q can be a set of error probability values for each subchannel.
  • the length of Q may be equal to the number of bits (size/length) K of the information bits of the first coded information, the number of bits of the PC-Frozen bit PF, the number of bits F of the Frozen bit, and the number of Puncture bits P, that is, the length of Q is equal to K+PF+F+P; or the length of Q may be equal to the difference between K+PF+F and the Shorten bit number S, that is, the length of Q is equal to K+PF+FS.
  • S or P can be determined according to the number of bits of K, PF and F and M, as shown in formulas 1-1 and 1-2:
  • M represents the length after encoding
  • the length of Q may be equal to the length of the mother code, since the mother code may be equal to the sum of the information bit length of the first encoded information, the PC-Frozen bit length, the Frozen bit length, and the Puncture bit length; or the mother code may be equal to the first The sum of the information bit length of the encoded information, the PC-Frozen bit length, the Frozen bit length, and the Shorten bit length.
  • Step 1.2 The transmitting end acquires a subchannel allocated by the punching bit or the truncated bit on the subchannel corresponding to the Q.
  • the transmitting end may use a puncturing scheme to obtain a subchannel allocated by the punctured bit or the truncated bit on the subchannel corresponding to the Q.
  • the puncturing scheme may employ a Bit Index Reverse (BIV) scheme or other Shortening/puncturing Puncturing rate matching scheme.
  • BIV Bit Index Reverse
  • the embodiment of the present application is described by taking an example of obtaining a subchannel allocated by puncturing bits. According to the example 1, it is assumed that the 112-bit punctured bits obtained by the transmitting end using the BIV Shortening scheme are allocated on the subchannels corresponding to the Q.
  • the serial number can be: [7 11 1519 23 27 31 39 43 47 51 55 59 63 71 75 79 83 87 91 95 103 107 111 115 119 123 127 135 139 143 147 151 155 159 167 171 175 179 183 187 191 199 203 207 211 215 219 223 231 235 239 243 247 275 279 263 287 295 299 303 307 311 315 319 327 331 335 339 343 347 351 359 363 367 371 375 379 383 391 395 399 403 407 411 415 423 427 431 435 439 443 447 455 459 463 467 471 475 479 487 491 495 499 503 507 511].
  • Step 1.3 The transmitting end acquires the information bit of the first coding information and the sequence number of the subchannel allocated by the subchannel corresponding to the check frozen bit.
  • each subchannel corresponding to Q except for the subchannel occupied by the Puncture bit, the information bits of the first coding information and the PC-Frozen bit occupy a portion of the subchannel with high reliability, and the Punch bit and the Frozen bit occupy low reliability. Part of the subchannel. As shown in FIG. 9, it is a sequence of reliability of subchannels occupied by bits other than the Puncture bit in each subchannel corresponding to Q.
  • the process of acquiring the information bits of the first coding information and the sub-channels allocated by the PC-Frozen bits may be divided into four steps a, b, c, and d.
  • the first coded information bits included in each segment and the sequence number of the subchannel occupied by the PC-Frozen bit are less than or equal to the segmentation point and do not belong to the previous segment.
  • the points in the figure represent the reliability of each sub-channel, and the information bits of the first encoding and the reliability of the sub-channel occupied by the PC-Frozen bits, the first encoding, are shown in FIG.
  • sequence numbers of the subchannels occupied by the bits may be: [252 253 254
  • the sub-channel or the intermediate Pf g sequence number corresponding to the sub-channel or the subsequent Pf g sequence numbers corresponding to the first Pf g sequence numbers in the sub-channel sequence number set of the PC-Frozen bit allocation may be the first coded information bits of each segment.
  • the corresponding subchannel is a subchannel corresponding to the PC-Frozen bit.
  • g is a segment number
  • Pf g is a non-negative integer
  • g is a positive integer greater than or equal to 1.
  • the first Pf g bits in the subchannel allocated by the Frozen bit is [252 366 373 414 429 430 468 472 461 481 482 484 496 497 504 508].
  • the transmitting end may determine the information bits of the first coding information, the PC-Frozen bit, and the subchannels other than the subchannel corresponding to the Puncture bit in each subchannel as the subchannel of the Frozen bit allocation; or the transmitting end shall be the first in each subchannel.
  • the information bits of the coded information, the PC-Frozen bit, and the subchannels other than the subchannel corresponding to the Shorten bit are determined as subchannels of the freeze bits.
  • the transmitting end determines the information bits of the first encoding information, the PC-Frozen bit, the Puncture bit, and the sub-channel allocated by the Frozen bit
  • the information bits of the first encoding information, the PC-Frozen bit, the Puncture bit, and the Frozen bit may be added to In each subchannel, the second encoded information is obtained.
  • the receiving end and the transmitting end may default to a bit value of 0 on the subchannel allocated by the Frozen bit.
  • the transmitting end performs polarization coding on the second encoded information to obtain third encoded information, and outputs the third encoded information to the receiving end.
  • the transmitting end may perform polarization code encoding on the second encoded information by using a Polar encoder, and remove the Puncture bit or the Shorten bit from the result of the polarization code encoding to obtain the third encoded information, and then output the third encoded information to the receiving end. .
  • the receiving end acquires, by using a PC-SCL decoder, a decoded value of each path after decoding the information to be decoded.
  • the information to be decoded is the third encoded information sent by the transmitting end.
  • the receiving end selects any path by using a second cyclic redundancy check bit to assist the PC-SCL decoder.
  • the second cyclic redundancy check bit in the decoded value of each path may be used to assist the PC-SCL decoder to select any path, and then step 507 Check the path.
  • the receiving end checks information bits of any path by using a first cyclic redundancy check bit in any path, and determines information bits when the information bits of any path are correct to be determined by cyclic redundancy check. The information bits of the path.
  • the receiving end checks the information bits of the path according to the first cyclic redundancy check bit in the decoding result of the path selected in step 506, if the information bit of the path can pass the first in the path.
  • the check of the cyclic redundancy check bit determines the information bit as the information bit of the path through the cyclic redundancy check, that is, the information bit finally output.
  • the transmitting end performs both cyclic redundancy check and PC-Frozen coding before performing polarization coding.
  • the receiver will pass the translation of PC-Frozen and cyclic redundancy check. Code result output.
  • the transmitting end and the receiving end include corresponding hardware structures and/or software modules for performing respective functions.
  • the present application can be implemented in a combination of hardware or hardware and computer software in conjunction with the algorithm steps described in the embodiments disclosed herein. Whether a function is implemented in hardware or computer software to drive hardware depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present application.
  • the embodiment of the present application may divide the function module by the sending end and the receiving end according to the foregoing method example.
  • each function module may be divided according to each function, or two or more functions may be integrated into one processing module.
  • the above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of the module in the embodiment of the present application is schematic, and is only a logical function division, and the actual implementation may have another division manner.
  • FIG. 12 is a schematic diagram showing a possible structure of the transmitting device 12 involved in the foregoing embodiment.
  • the transmitting device includes a check unit 1201 and an encoding unit 1202.
  • the verification unit 1201 is configured to support the transmitting device to perform the process 501 in FIG. 5;
  • the encoding unit 1202 is configured to support the transmitting device to perform the processes 502, 503, and 504 in FIG. All the related content of the steps involved in the foregoing method embodiments may be referred to the functional descriptions of the corresponding functional modules, and details are not described herein again.
  • FIG. 3 shows a possible structural diagram of the terminal involved in the above embodiment.
  • the processing module 301 can be a processor or a controller, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), and an application-specific integrated circuit (Application-Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic device, transistor logic device, hardware component, or any combination thereof. It is possible to implement or carry out the various illustrative logical blocks, modules and circuits described in connection with the present disclosure.
  • CPU central processing unit
  • DSP digital signal processor
  • ASIC Application-Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • the processor may also be a combination of computing functions, for example, including one or more microprocessor combinations, a combination of a DSP and a microprocessor, and the like.
  • the communication module 302 can be a transceiver, a transceiver circuit, a communication interface, or the like.
  • the storage module 303 can be a memory.
  • the transmitting device When the processing module 301 is a processor, the communication module 302 is a transceiver, and the storage module 303 is a memory, the transmitting device according to the embodiment of the present application may be the transmitting device shown in FIG.
  • the transmitting device 13 includes a processor 1301, a transceiver 1302, a memory 1303, and a bus 1304.
  • the transceiver 1302, the processor 1301, and the memory 1303 are mutually connected by a bus 1304.
  • the bus 1304 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. Wait.
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • the bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in FIG. 13, but it does not mean that there is only one bus or one type of bus.
  • FIG. 14 is a schematic diagram showing a possible structure of the receiving device 14 involved in the foregoing embodiment, and the receiving device includes: an obtaining unit 1401 and a checking unit 1402.
  • the obtaining unit 1401 is configured to support the receiving device to perform the process 505 in FIG. 5;
  • the checking unit 1402 is configured to support the receiving device to perform the processes 506 and 507 in FIG. 5. All the related content of the steps involved in the foregoing method embodiments may be referred to the functional descriptions of the corresponding functional modules, and details are not described herein again.
  • FIG. 4 shows a possible structural diagram of the terminal involved in the above embodiment.
  • the processing module 401 can be a processor or a controller, such as a CPU, a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. It is possible to implement or carry out the various illustrative logical blocks, modules and circuits described in connection with the present disclosure.
  • the processor may also be a combination of computing functions, for example, including one or more microprocessor combinations, a combination of a DSP and a microprocessor, and the like.
  • the communication module 402 can be a transceiver, a transceiver circuit, a communication interface, or the like.
  • the storage module 403 can be a memory.
  • the processing module 401 is a processor
  • the communication module 402 is a transceiver
  • the storage module 403 is a memory
  • the receiving device according to the embodiment of the present application may be the receiving device shown in FIG.
  • the receiving device 15 includes a processor 1501, a transceiver 1502, a memory 1503, and a bus 1504.
  • the transceiver 1502, the processor 1501, and the memory 1503 are connected to each other through a bus 1504.
  • the bus 1504 may be a PCI bus or an EISA bus.
  • the bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 15, but it does not mean that there is only one bus or one type of bus.
  • the steps of a method or algorithm described in connection with the present disclosure may be implemented in a hardware or may be implemented by a processor executing software instructions.
  • the software instructions may be composed of corresponding software modules, which may be stored in a random access memory (RAM), a flash memory, a read only memory (ROM), an erasable programmable read only memory ( Erasable Programmable ROM (EPROM), electrically erasable programmable read only memory (EEPROM), registers, hard disk, removable hard disk, compact disk read only (CD-ROM) or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor to enable the processor to read information from, and write information to, the storage medium.
  • the storage medium can also be an integral part of the processor.
  • the processor and the storage medium can be located in an ASIC. Additionally, the ASIC can be located in a core network interface device.
  • the processor and the storage medium may also exist as discrete components in the core network interface device.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a general purpose or special purpose computer.

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Abstract

本申请实施例提供一种编译码方法和终端，涉及通信领域，能够提高极化码的译码性能。其方法为：发送端对待编码信息进行循环冗余校验，得到第一编码信息；发送端对第一编码信息进行奇偶校验编码，得到第二编码信息；发送端对第二编码信息进行极化编码，得到第三编码信息并输出给接收端。本申请实施例应用于对信息比特进行Polar编码和译码的场景。

Description

一种编译码方法和终端
本申请要求于2017年01月25日提交中国专利局、申请号为201710064225.7、申请名称为“一种编译码方法和终端”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，尤其涉及一种编译码方法和终端。
背景技术
在第三代合作伙伴计划(3rd Generation Partnership Project，3GPP)无线接入网1(Radio Access Network1，RAN1)#87次会议上确定增强型移动互联网(Enhanced Mobile Broad Band，eMBB)的上行和下行控制信息都采用极化码(Polar)编码方案。为提高Polar译码性能，可以在Polar外级联具有校验能力的外码。目前，级联的外码分为循环冗余校验(Cyclic Redundancy Check，CRC)码和奇偶校验(Parity-Check，PC)码，将CRC码作为外码的方案称为CRC辅助Polar(CA(CRC-Aided)-Polar)，将PC码作为外码的方案称为PC-Polar。
CA-Polar的方案是，在编码侧确定冻结(Frozen)比特的子信道和信息比特的子信道，并确定Frozen比特的子信道和信息比特的子信道上需要传递的比特，然后对所有比特进行Polar编码。其中Frozen比特的子信道传递的比特可以为0比特或约定比特，信息比特的子信道上传递的比特可以包括信息比特和CRC比特。在译码侧，对译码器的多条路径的译码结果进行CRC，将通过CRC的路径作为译码输出结果。PC-Polar的方案是，在编码侧确定Frozen比特的子信道、PC-Frozen比特的子信道以及信息比特的子信道，并确定Frozen比特的子信道、PC-Frozen比特的子信道以及信息比特的子信道上需要传递的比特，然后对所有比特进行Polar编码。其中Frozen比特的子信道传递的比特可以为0比特或约定比特，PC-Frozen比特的子信道传递的比特为PC-Frozen比特，信息比特的子信道上传递的比特为信息比特。在译码侧，PC比特分布在信息比特之中，译码中间阶段可以利用PC比特提供早停，即任一路径中，在译码进程执行时若出现译码错误，则将该路径的译码过程中断并删除该路径，从而确定出译码器的多条路径中通过PC译码的路径。目前还提出了一种简化的PC-Polar方案，称为简化PC(Simplified PC-Polar，Sim-PC)，Sim-PC的方案利用信道极化的准周期特性，每个周期作为一个分段，通过在各个分段中预先选择PC-Frozen的比特以达到简化PC-Polar的构造复杂度。
但是，由于CA-Polar中，CRC比特级联在信息比特的末端，因此校验的执行发生在信息比特译码之后，从而CA-Polar在译码时不具有早停判断的能力。而且，CRC比特总是占据可靠度最高的子信道，没有给编码优化留出充分的空间，使得编码侧性能低。PC-Polar的构造方法相对复杂，且默认输出第一条路径的译码结果，但是第一条路径的译码结果可能会出现错误，使得译码侧性能低。Sim-PC与PC-Polar的性能相近 似，如图1所示，为Sim-PC与PC-Polar(图1中简称为PC)在信息比特大小为120时的误块率(Block Error Rate，BLER)性能对比，图1中同时包含了编码后长度为720(120/720)、240(120/240)及360(120/360)的情况，在某一信噪比下，误块率越低，表示该方法在信噪比下传输可靠度越高。对于某一方法的误块率曲线随信噪比的升高，下降得越快(斜率越高)，说明该方法能随信噪比的升高，更快得达到更高的传输可靠度。可见，Sim-PC在译码端的高信噪比区间性能上会有轻微的损失。
发明内容
本申请实施例提供一种编译码方法和终端，能够提高极化码的译码性能。
第一方面，本申请实施例提供一种编码方法，包括：发送端对待编码信息进行循环冗余校验，得到第一编码信息；发送端对第一编码信息进行奇偶校验编码，得到第二编码信息；发送端对第二编码信息进行极化编码，得到第三编码信息并输出给接收端。这样一来，在编码侧，发送端进行极化编码之前既进行循环冗余校验，又进行奇偶校验编码，以便于在译码侧，接收端将通过奇偶校验编码和循环冗余校验的译码结果输出。相比现有技术，在编码侧仅进行循环冗余校验或仅进行奇偶校验编码，在译码侧，将仅通过奇偶校验编码或循环冗余校验的译码结果输出，本申请实施例进行了两重编码和两重校验，即通过CRC辅助PC-Polar编码，仅在PC-Polar编码前进行一次CRC编码，能够提高译码的错误检测能力，提高极化码的译码性能。
在一种可能的设计中，发送端对待编码信息进行循环冗余校验，得到第一编码信息包括：发送端对待编码信息的信息比特添加循环冗余校验比特，得到第一编码信息，循环冗余校验比特包括第一循环冗余校验比特和第二循环冗余校验比特，第一循环冗余校验比特是根据信息比特获得的，第二循环冗余校验比特是根据信息比特以及第一循环冗余校验比特获取的，第一循环冗余校验比特用于校验信息比特，第二循环冗余校验比特用于辅助译码。这样一来，第一循环冗余校验比特可以用于校验信息比特是否存在错误，第二循环冗余校验比特可以用于辅助译码，以保证输出的译码值的漏检概率足够低。
在一种可能的设计中，发送端对第一编码信息进行奇偶校验编码，得到第二编码信息包括：发送端根据各个子信道的可靠度将第一编码信息的信息比特、校验冻结比特以及冻结比特分配至各个子信道中，得到第二编码信息，第二编码信息中信息比特和校验冻结比特分配在可靠度高的子信道中，冻结比特分配在可靠度低的子信道中。这样一来，信息比特和校验冻结比特分配在可靠度高的子信道中，冻结比特分配在可靠度低的子信道中，保证了比较重要的信息比特和校验冻结比特的传输性能高于冻结比特的传输性能。另外，如图1a所示，为本申请中在编码侧即发送端进行循环冗余校验后再进行奇偶校验编码，在译码侧接收端输出的译码值的BLER性能，与现有技术在编码侧仅进行奇偶校验编码，在译码侧输出的译码值的BLER性能的对比示意图，图1a中包括本申请(PC-CA)和现有技术(PC)在待编码信息的信息比特数量为120时，编码后的比特数量分别为240、360和720的译码值的BLER性能。由于误块率说明了编码方法的传输可靠度，由图1a可见，本申请的编译码方法相较现有技术的编译码方法在相同信噪比值下，误块率更低，且随着信噪比的升高误块率下降的更快，因此拥有更优的编码性能。
在一种可能的设计中，发送端对第一编码信息进行奇偶校验编码，得到第二编码信息包括：发送端根据子信道极化的准周期特性将第一编码信息的信息比特、校验冻结比特以 及冻结比特分配至各个子信道中，得到第二编码信息。这样一来，发送端可以根据子信道极化的准周期特性将第一编码信息的信息比特、校验冻结比特以及冻结比特分配至各个子信道中，从而得到第二编码信息。另外，如图1b所示，为本申请中在编码侧发送端进行循环冗余校验后再根据信道极化的准周期特性进行奇偶校验编码，在译码侧接收端输出的译码值的BLER性能，与现有技术在编码侧仅进行奇偶校验编码，在译码侧输出的译码值的BLER性能的对比示意图，图1b中包括本申请和现有技术在待编码信息的信息比特数量为120时，编码后的比特数量分别为240、360和720的译码值的BLER性能。由于误块率说明了编码方法的传输可靠度，由图1b可见，本申请的编译码(Sim-PC CA)方法相较现有技术(Sim-PC)的编译码方法在相同信噪比值下，误块率大幅度降低，且随制信噪比的升高误块率下降的更为迅速，因此拥有大幅度的编码性能提升。
在一种可能的设计中，发送端根据子信道极化的准周期特性将第一编码信息的信息比特、校验冻结比特以及冻结比特分配至各个子信道中包括：发送端获取各个子信道的可靠度序列，并通过极化码速率匹配方式获取打孔比特或截短比特对应的子信道；发送端对各个子信道按照子信道极化的准周期获取子信道分段点集合，以对各个子信道进行分段；发送端确定每个分段中除打孔比特对应的子信道或截短比特对应的子信道以外信息比特和校验冻结比特对应的子信道对应的序号集合；发送端将各个子信道中信息比特、校验冻结比特以及打孔比特对应的子信道以外的子信道确定为冻结比特的子信道；或发送端将各个子信道中信息比特、校验冻结比特以及截短比特对应的子信道以外的子信道确定为冻结比特的子信道。这样一来，发送端可以根据子信道极化的准周期特性将第一编码信息的信息比特、校验冻结比特以及冻结比特分配至各个子信道中，从而得到第二编码信息。
在一种可能的设计中，若可靠度序列的最小值为0，最大值为N-1，则N＝16，分段点集合为[7 11]；或者N＝32，分段点集合为[15 23 27]；或者N＝64，分段点集合为[31 47 55 59]；或者N＝128，分段点集合为[63 95 111 119 123]；或者N＝256，分段点集合为[127 191 223 239 247 251]；或者N＝512，分段点集合为[255 383 447 479 495 503 507]；或者N＝1024，分段点集合为[511 767 895 959 991 1007 1015 1019]；或者N＝2048，分段点集合为[1023 1535 1791 1919 1983 2015 2031 2039 2043]；或者N＝4096，分段点集合为[2047 3071 3583 3839 3967 4031 4065 4079 4087 4091]。其中，发送端可以根据移位寄存器获取不同N值对应的分段点集合中的分段点，当N值越大时，分段点集合中的分段点越多。
在一种可能的设计中，每个分段的序号集合中前Pfg个序号对应的子信道、后Pfg个序号对应的子信道或中间Pfg个序号对应的子信道为校验冻结比特对应的子信道,g为分段序号，Pfg为非负整数，g为大于或等于1的正整数。这样一来，发送端可以将每个分段中信息比特和校验冻结比特共同对应的子信道的前Pfg个序号对应的子信道、后Pfg个序号对应的子信道或中间Pfg个序号对应的子信道确定为校验冻结比特对应的子信道。
第二方面，本申请实施例提供一种发送装置，包括：校验单元，用于对待编码信息进行循环冗余校验，得到第一编码信息；编码单元，用于对第一编码信息进行奇偶校验编码，得到第二编码信息；编码单元还用于对第二编码信息进行极化编码，得到第三编码信息并输出给接收端。
在一种可能的设计中，校验单元用于：对待编码信息的信息比特添加循环冗余校验比特，得到第一编码信息，循环冗余校验比特包括第一循环冗余校验比特和第二循环冗余校 验比特，第一循环冗余校验比特是根据信息比特获得的，第二循环冗余校验比特是根据信息比特以及第一循环冗余校验比特获取的，第一循环冗余校验比特用于校验信息比特，第二循环冗余校验比特用于辅助译码。
在一种可能的设计中，编码单元用于：根据各个子信道的可靠度将第一编码信息的信息比特、校验冻结比特以及冻结比特分配至各个子信道中，得到第二编码信息，第二编码信息中信息比特和校验冻结比特分配在可靠度高的子信道中，冻结比特分配在可靠度低的子信道中。
在一种可能的设计中，编码单元用于：根据子信道极化的准周期特性将第一编码信息的信息比特、校验冻结比特以及冻结比特分配至各个子信道中，得到第二编码信息。
在一种可能的设计中，编码单元包括：获取子单元，用于获取各个子信道的可靠度序列，并通过极化码速率匹配方式获取打孔比特或截短比特对应的子信道；分段子单元，用于对各个子信道按照子信道极化的准周期获取子信道分段点集合，以对各个子信道进行分段；确定子单元，用于确定每个分段中除打孔比特对应的子信道或截短比特对应的子信道以外信息比特和校验冻结比特对应的子信道对应的序号集合；确定子单元还用于，将各个子信道中信息比特、校验冻结比特以及打孔比特对应的子信道以外的子信道确定为冻结比特的子信道；或将各个子信道中信息比特、校验冻结比特以及截短比特对应的子信道以外的子信道确定为冻结比特的子信道。
在一种可能的设计中，若可靠度序列的最小值为0，最大值为N-1，则N＝16，分段点集合为[7 11]；或者N＝32，分段点集合为[15 23 27]；或者N＝64，分段点集合为[31 47 55 59]；或者N＝128，分段点集合为[63 95 111 119 123]；或者N＝256，分段点集合为[127 191 223 239 247 251]；或者N＝512，分段点集合为[255 383 447 479 495 503 507]；或者N＝1024，分段点集合为[511 767 895 959 991 1007 1015 1019]；或者N＝2048，分段点集合为[1023 1535 1791 1919 1983 2015 2031 2039 2043]；或者N＝4096，分段点集合为[2047 3071 3583 3839 3967 4031 4065 4079 4087 4091]。
在一种可能的设计中，每个分段的序号集合中前Pfg个序号对应的子信道、后Pfg个序号对应的子信道或中间Pfg个序号对应的子信道为校验冻结比特对应的子信道,g为分段序号，Pfg为非负整数，g为大于或等于1的正整数。
第三方面，本申请实施例提供一种发送装置，包括：处理器，用于对待编码信息进行循环冗余校验，得到第一编码信息；处理器，还用于对第一编码信息进行奇偶校验编码，得到第二编码信息；处理器还用于对第二编码信息进行极化编码，得到第三编码信息并输出给接收端。
在一种可能的设计中，处理器用于：对待编码信息的信息比特添加循环冗余校验比特，得到第一编码信息，循环冗余校验比特包括第一循环冗余校验比特和第二循环冗余校验比特，第一循环冗余校验比特是根据信息比特获得的，第二循环冗余校验比特是根据信息比特以及第一循环冗余校验比特获取的，第一循环冗余校验比特用于校验信息比特，第二循环冗余校验比特用于辅助译码。
在一种可能的设计中，处理器用于：根据各个子信道的可靠度将第一编码信息的信息比特、校验冻结比特以及冻结比特分配至各个子信道中，得到第二编码信息，第二编码信息中信息比特和校验冻结比特分配在可靠度高的子信道中，冻结比特分配在可靠度低的子 信道中。
在一种可能的设计中，处理器用于：根据子信道极化的准周期特性将第一编码信息的信息比特、校验冻结比特以及冻结比特分配至各个子信道中，得到第二编码信息。
在一种可能的设计中，处理器还用于获取各个子信道的可靠度序列，并通过极化码速率匹配方式获取打孔比特或截短比特对应的子信道；对各个子信道按照子信道极化的准周期获取子信道分段点集合，以对各个子信道进行分段；确定每个分段中除打孔比特对应的子信道或截短比特对应的子信道以外信息比特和校验冻结比特对应的子信道对应的序号集合；将各个子信道中信息比特、校验冻结比特以及打孔比特对应的子信道以外的子信道确定为冻结比特的子信道；或将各个子信道中信息比特、校验冻结比特以及截短比特对应的子信道以外的子信道确定为冻结比特的子信道。
在一种可能的设计中，若可靠度序列的最小值为0，最大值为N-1，则N＝16，分段点集合为[7 11]；或者N＝32，分段点集合为[15 23 27]；或者N＝64，分段点集合为[31 47 55 59]；或者N＝128，分段点集合为[63 95 111 119 123]；或者N＝256，分段点集合为[127 191 223 239 247 251]；或者N＝512，分段点集合为[255 383 447 479 495 503 507]；或者N＝1024，分段点集合为[511 767 895 959 991 1007 1015 1019]；或者N＝2048，分段点集合为[1023 1535 1791 1919 1983 2015 2031 2039 2043]；或者N＝4096，分段点集合为[2047 3071 3583 3839 3967 4031 4065 4079 4087 4091]。
在一种可能的设计中，每个分段的序号集合中前Pfg个序号对应的子信道、后Pfg个序号对应的子信道或中间Pfg个序号对应的子信道为校验冻结比特对应的子信道,g为分段序号，Pfg为非负整数，g为大于或等于1的正整数。
第四方面，本发明实施例提供了一种装置，该装置以芯片的产品形态存在，该装置的结构中包括处理器和存储器，该存储器用于与处理器耦合，保存该装置必要的程序指令和数据，该处理器用于执行存储器中存储的程序指令，使得该装置执行上述方法中发送装置的功能。
第五方面，本发明实施例提供了一种发送装置，该发送装置可以实现上述方法实施例中发送装置所执行的功能，所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个上述功能相应的模块。
在一种可能的设计中，该发送装置的结构中包括处理器和通信接口，该处理器被配置为支持该发送装置执行上述方法中相应的功能。该通信接口用于支持该发送装置与其他网元之间的通信。该发送装置还可以包括存储器，该存储器用于与处理器耦合，其保存该发送装置必要的程序指令和数据。
第六方面，本发明实施例提供一种计算机可读存储介质，包括指令，当其在计算机上运行时，使得计算机执行第一方面提供的任意一种方法。
第七方面，本发明实施例提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行第一方面提供的任意一种方法。
第八方面，本申请实施例提供一种译码方法，包括：接收端通过奇偶校验连续抵消列表(PC-successive cancelation list，PC-SCL)译码器获取待译码信息译码后各个路径的译码值；接收端对各个路径进行循环冗余校验，获取通过循环冗余校验的路径的信息比特。这样一来，接收端可以将PC-SCL的各个路径的译码值中通过循环冗余校验的路径的信息比 特输出，相比现有技术将PC-SCL的第一条路径的译码值输出，而第一条路径的译码值可能存在错误，本申请实施例提供的PC-SCL译码和和CRC校验能够进一步降低译码值出错的概率，从而提高极化码的译码性能。
在一种可能的设计中，对于各个路径中的每个路径，该路径的译码值包括待译码信息的信息比特和循环冗余校验比特，循环冗余校验比特包括第一循环冗余校验比特和第二循环冗余校验比特，第一循环冗余校验比特是根据信息比特获得的，第二循环冗余校验比特是根据信息比特以及第一循环冗余校验比特获取的，第一循环冗余校验比特用于校验信息比特，第二循环冗余校验比特用于辅助译码。这样一来，第一循环冗余校验比特可以用于校验信息比特是否存在错误，第二循环冗余校验比特可以用于辅助译码，以保证输出的译码值的漏检概率足够低。
在一种可能的设计中，接收端对各个路径进行循环冗余校验，获取通过循环冗余校验的路径的信息比特包括：接收端通过第二循环冗余校验比特辅助PC-SCL译码器选取任一路径，通过任一路径中的第一循环冗余校验比特校验任一路径的信息比特，将校验任一路径的信息比特正确时的信息比特确定为通过循环冗余校验的路径的信息比特。这样一来，接收端可以根据第一循环冗余校验比特和第一循环冗余校验比特确定输出哪条PC-SCL译码器的路径的译码值，相比现有技术将PC-SCL的第一条路径的译码值输出，而第一条路径的译码值可能存在错误，本申请实施例提供的编译码方法能够降低译码值出错的概率，从而提高极化码的译码性能。
第九方面，本申请实施例提供一种接收装置，其特征在于，包括：获取单元，用于通过PC-SCL译码器获取待译码信息译码后各个路径的译码值；校验单元，用于对各个路径进行循环冗余校验，获取通过循环冗余校验的路径的信息比特。
在一种可能的设计中，对于各个路径中的每个路径，该路径的译码值包括待译码信息的信息比特和循环冗余校验比特，循环冗余校验比特包括第一循环冗余校验比特和第二循环冗余校验比特，第一循环冗余校验比特是根据信息比特获得的，第二循环冗余校验比特是根据信息比特以及第一循环冗余校验比特获取的，第一循环冗余校验比特用于校验信息比特，第二循环冗余校验比特用于辅助译码。
在一种可能的设计中，校验单元用于通过第二循环冗余校验比特辅助PC-SCL译码器选取任一路径，通过任一路径中的第一循环冗余校验比特校验任一路径的信息比特，将校验任一路径的信息比特正确时的信息比特确定为通过循环冗余校验的路径的信息比特。
第十方面，本申请实施例提供一种接收装置，其特征在于，包括：处理器，用于通过PC-SCL译码器获取待译码信息译码后各个路径的译码值；处理器，还用于对各个路径进行循环冗余校验，获取通过循环冗余校验的路径的信息比特。
在一种可能的设计中，对于各个路径中的每个路径，该路径的译码值包括待译码信息的信息比特和循环冗余校验比特，循环冗余校验比特包括第一循环冗余校验比特和第二循环冗余校验比特，第一循环冗余校验比特是根据信息比特获得的，第二循环冗余校验比特是根据信息比特以及第一循环冗余校验比特获取的，第一循环冗余校验比特用于校验信息比特，第二循环冗余校验比特用于辅助译码。
在一种可能的设计中，处理器用于通过第二循环冗余校验比特辅助PC-SCL译码器选取任一路径，通过任一路径中的第一循环冗余校验比特校验任一路径的信息比特，将校验 任一路径的信息比特正确时的信息比特确定为通过循环冗余校验的路径的信息比特。
第十一方面，本发明实施例提供了一种装置，该装置以芯片的产品形态存在，该装置的结构中包括处理器和存储器，该存储器用于与处理器耦合，保存该装置必要的程序指令和数据，该处理器用于执行存储器中存储的程序指令，使得该装置执行上述方法中接收装置的功能。
第十二方面，本发明实施例提供了一种接收装置，该接收装置可以实现上述方法实施例中接收装置所执行的功能，所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个上述功能相应的模块。
在一种可能的设计中，该接收装置的结构中包括处理器和通信接口，该处理器被配置为支持该接收装置执行上述方法中相应的功能。该通信接口用于支持该接收装置与其他网元之间的通信。该接收装置还可以包括存储器，该存储器用于与处理器耦合，其保存该接收装置必要的程序指令和数据。
第十三方面，本发明实施例提供一种计算机可读存储介质，包括指令，当其在计算机上运行时，使得计算机执行第八方面提供的任意一种方法。
第十四方面，本发明实施例提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行第八方面提供的任意一种方法。
这样一来，在编码侧，发送端进行极化编码之前既进行循环冗余校验，又进行奇偶校验编码，在译码侧，接收端将通过奇偶校验编码和循环冗余校验的译码结果输出。相比现有技术，在编码侧仅进行循环冗余校验或仅进行奇偶校验编码，在译码侧，将仅通过奇偶校验编码或循环冗余校验的译码结果输出，本申请实施例进行了两重编码和两重校验，即通过CRC辅助PC-Polar编码，仅在PC-Polar编码前进行一次CRC编码，且通过CRC辅助PC-Polar译码，仅在PC-SCL译码后增加CRC选择路径的操作，能够提高译码的错误检测能力，提高极化码的译码性能。
附图说明
图1为现有技术的一种Sim-PC与PC-Polar的性能示意图；
图1a为本申请实施例提供的一种PC与PC CA的输出译码值的性能示意图；
图1b为本申请实施例提供的一种Sim-PC与Sim-PC CA的输出译码值的性能示意图；
图2为本申请实施例提供的一种系统架构示意图；
图3为本申请实施例提供的一种发送端的内部结构示意图；
图4为本申请实施例提供的一种接收端的内部结构示意图；
图5为本申请实施例提供的一种编译码方法的流程示意图；
图6为本申请实施例提供的一种各子信道的可靠度情况示意图；
图7为本申请实施例提供的一种子信道的分配示意图；
图8为本申请实施例提供的一种各子信道的可靠度示意图；
图9为本申请实施例提供的一种可靠度序列Q对应的各子信道的可靠度情况示意图；
图10为本申请实施例提供的一种移位寄存器的示意图；
图11为本申请实施例提供的一种各子信道的可靠度示意图；
图12为本申请实施例提供的一种发送装置的结构示意图；
图13为本申请实施例提供的一种发送装置的结构示意图；
图14为本申请实施例提供的一种接收装置的结构示意图；
图15为本申请实施例提供的一种接收装置的结构示意图。
具体实施方式
本申请实施例可以应用于对信息比特进行Polar编码和译码的场景，例如可以应用于对eMBB上行控制信息和下行控制信息进行Polar编码和译码的场景，也可应用于其他场景，例如应用于通信标准36.212的5.1.3的信道编码(Channel Coding)、上行控制信息、下行控制信息以及Sidelink信道的信道编码部分，本申请实施例不做限定。
本申请实施例的系统可以包括发送端和接收端，如图2所示，为一种发送端和接收端的系统架构示意图。其中，发送端为编码侧，可以用于编码和输出编码信息，编码信息在信道上传输至译码侧；接收端为译码侧，可以用于接收发送端发送的编码信息，并对该编码信息译码。发送端和接收端可以是终端、服务器、基站或其他可以编译码的设备，本申请不做限制。终端可以为个人计算机(Personal Computer，PC)、手机、平板电脑(pad)、智能学习机、智能游戏机、智能电视、智能眼镜或智能手表等。
图3为本发明的发送端的一种内部结构示意图，在本发明中，发送端可以包括处理模块301、通讯模块302、存储模块303。其中，处理模块301用于控制发送端的各部分硬件装置和应用程序软件等；通讯模块302用于可使用无线保真(Wireless Fidelity，wifi)等通讯方式接收其它设备发送的指令，也可以将发送端的数据发送给其它设备；存储模块303用于执行发送端的软件程序的存储、数据的存储和软件的运行等。
图4为本发明的接收端的一种内部结构示意图，在本发明中，接收端可以包括处理模块401、通讯模块402、存储模块403。其中，处理模块401用于控制接收端的各部分硬件装置和应用程序软件等；通讯模块402用于可使用wifi等通讯方式接收其它设备发送的指令，也可以将接收端的数据发送给其它设备；存储模块403用于执行接收端的软件程序的存储、数据的存储和软件的运行等。
本申请实施例提供一种编译码方法，其基本思想是：在编码侧，发送端对待编码信息进行循环冗余校验得到第一编码信息，再对第一编码信息进行奇偶校验编码，得到第二编码信息，而后对第二编码信息进行极化编码，得到第三编码信息并输出给接收端。在译码侧，接收端通过译码器获取各个路径上对第三编码信息的译码值，而后对各个路径的译码值进行循环冗余校验，获取通过循环冗余校验的路径的信息比特，即最终输出的译码结果。
本申请实施例提供一种编译码方法，如图5所示，包括:
501、发送端对待编码信息的信息比特添加循环冗余校验比特，得到第一编码信息，而后执行步骤502或步骤503。
举例来说，假设待编码信息的信息比特长度为120位，循环冗余校验比特的长度为16位，则第一编码信息的信息比特的长度为136位，即第一编码信息的信息比特包括编码信息的信息比特和循环冗余校验比特。
其中，循环冗余校验比特可以包括第一循环冗余校验比特和第二循环冗余校验比特，第一循环冗余校验比特是根据信息比特获得的，第二循环冗余校验比特是根据信息比 特以及第一循环冗余校验比特获取的，第一循环冗余校验比特用于校验信息比特，第二循环冗余校验比特用于辅助译码，第一循环冗余校验比特的长度(阶数)可以大于第二循环冗余校验比特。通常第一循环冗余校验比特和第二循环冗余校验比特的CRC多项式的具体形式以及比特长度不同，第一循环冗余校验比特和第二循环冗余校验比的校验能力不同，因此本申请实施例中的上述循环冗余校验比特包括第一循环冗余校验比特和第二循环冗余校验比特相较于传统的循环冗余校验比特仅包括一种校验比特，可以保证更低的虚警概率和/或漏检概率。
也就是说，发送端在编码侧编码时可以进行两重CRC编码，假设第一编码信息的信息比特为Info+CRC1+CRC2；Info为待编码信息的信息比特，CRC1为第一循环冗余校验比特，CRC1可以根据info计算得出；CRC2为第二循环冗余校验比特，可以根据Info+CRC1计算得出；且CRC1长度可以大于CRC2。接收端在译码侧可以通过PC-SCL译码器将每一条路径中的信息比特和循环冗余比特译出来。根据本段中上述举例，译码器可以译出每条路径的info+CRC1+CRC2，PC-SCL译码器通过每条路径的CRC2来校验Info+CRC1的正确性，从而挑选出其中一条路径并输出info+CRC1，而后接收端根据该条路径的CRC1检测该条路径中的info是否存在错误，并将对错信息反馈给物理层的上层。
当然，发送端在编码侧也可以不添加第二循环冗余校验比特，此时，接收端在译码侧通过SCL译码器将每一条路径中信息比特和第一循环冗余比特译出来后，可以直接将第一条路径的信息比特和第一循环冗余比特输出，并通过该第一循环冗余比特判断该信息比特是否有错误。
502、发送端根据各个子信道的可靠度将第一编码信息的信息比特、校验冻结比特以及冻结(Frozen)比特分配至各个子信道中，得到第二编码信息，而后执行步骤504。
其中，第二编码信息中信息比特和校验冻结比特可以分配在可靠度高的子信道中，冻结比特可以分配在可靠度低的子信道中。校验冻结比特可以为PC-Frozen比特。
举例来说，如图6所示，为一种子信道的可靠度由低到高的排布方式，平均来看，其中用于放置冻结比特的子信道集合的可靠度最低；剩余信道平均来看，用于放置第二编码信息的信息比特的子信道集合的可靠度最高，用于放置PC-Frozen比特的子信道的可靠度位于Frozen比特分配的子信道和信息比特分配的子信道的可靠度之间。需要说明的是，也可能有部分PC-Frozen比特放置在比信息比特放置的子信道可靠度高的子信道中，且放置冻结比特的子信道集合的可靠度总是最低的。
按照上述子信道的排布方式，发送端的第二编码信息的信息比特、PC-Frozen比特以及Frozen比特所分配的子信道可以如图7所示，为一种信息比特分配的子信道PC-Frozen比特分配的子信道以及Frozen比特分配的子信道的排布方式。发送端可以根据不同的信息比特以及校验方程(PC-function)获取不同的信息比特对应的PC-Frozen比特，且多个不同的信息比特集合可以对应一个PC-Frozen比特，因此，在接收端，可以根据不同的PC-Frozen比特和PC-function校验相应的信息比特是否正确。
503、发送端根据子信道极化的准周期特性将第一编码信息的信息比特、校验冻结比特以及冻结比特分配至各个子信道中，得到第二编码信息。
子信道极化的准周期特性具体表现为子信道的可靠度随子信道序号的变化呈现周期特性。举例来说，如图8所示，展示了256个子信道的可靠度，图中小方块代表每个子信 道的可靠度。从不同的周期尺度来看，子信道的可靠度均存在从小到大的变化周期。例如，图中以32个子信道为周期，周期间隔用虚线标记，在每一个周期内，子信道可靠度总体由小变大。再比如，若以8个子信道为周期，则每8个子信道的可靠度也存在从小变大的趋势，并且每一个周期的平均可靠度相对于上一周期的平均可靠度有所提升。
步骤503的基本思想是：发送端获取各个子信道的可靠度序列，并通过Polar码速率匹配方式获取打孔(Puncture)比特或截短(Shorten)比特对应的子信道；然后，发送端对各个子信道按照子信道极化的准周期获取子信道分段点集合，以对各个子信道进行分段；发送端确定每个分段中除打孔比特对应的子信道或截短比特对应的子信道以外第一编码信息的信息比特和PC-Frozen比特对应的子信道对应的序号集合；发送端将各个子信道中信息比特、PC-Frozen比特以及Puncture比特对应的子信道以外的子信道确定为Frozen比特的子信道，或发送端将各个子信道中信息比特、PC-Frozen比特以及Shorten比特对应的子信道以外的子信道确定为Frozen比特的子信道。
具体地：Step 1.1、发送端获取各个子信道的可靠度序列Q。
发送端可以通过高斯近似(Gaussian Approximation，GA)、密度演进(Density Evolution，DE)、极化权重(Polar Weight，PW)或其它方法获取Q。
Q中的信息可以包括各个子信道的可靠度值或各个子信道可靠度的相对关系(排序)。各个子信道的可靠度值可以用各个子信道的错误概率值来描述，因此Q可以为各子信道的错误概率值集合。Q的长度可以等于第一编码信息的信息比特的位数(大小/长度)K、PC-Frozen比特位数PF、Frozen比特的位数F以及Puncture比特位数P的和，即Q的长度等于K+PF+F+P；或Q的长度可以等于K+PF+F与Shorten比特位数S的差，即Q的长度等于K+PF+F-S。其中，S或P可以根据K、PF以及F的位数和M确定，如公式1-1和1-2所示:
Figure PCTCN2017117571-appb-000001
Figure PCTCN2017117571-appb-000002
其中，M表示编码后的长度。
举例来说(记为举例1)，假设K＝40、PF＝16、M＝400，则根据公式(1-1)可得
Figure PCTCN2017117571-appb-000003
则Puncture比特有112位，因此Q的位数有400+112＝512位。
另外，Q的长度可以等于母码的长度，这是由于母码可以等于第一编码信息的信息比特长度、PC-Frozen比特长度、Frozen比特长度和Puncture比特长度的和；或母码可以等于第一编码信息的信息比特长度、PC-Frozen比特长度、Frozen比特长度的和再减去Shorten比特长度。
Step 1.2、发送端获取打孔比特或截短比特在Q对应的子信道上分配的子信道。
发送端可以采用打孔方案获取打孔比特或截短比特在Q对应的子信道上分配的子信道。打孔方案可以采用比特序号翻转(Bit Index Reverse，BIV)方案或其它Shortening/打孔Puncturing速率匹配方案。
本申请实施例以获取打孔比特分配的子信道为例进行说明。根据举例1，假设发送端采用BIV Shortening方案获取的112位打孔比特在Q对应的子信道上分配的子信道的 序号可以是：【7 11 1519 23 27 31 39 43 47 51 55 59 63 71 75 79 83 87 91 95 103 107 111 115 119 123 127 135 139 143 147 151 155 159 167 171 175 179 183 187 191 199 203 207 211 215 219 223 231 235 239 243 247 251 255 263 267 271 275 279 283 287 295 299 303 307 311 315 319 327 331 335 339 343 347 351 359 363 367 371 375 379 383 391 395 399 403 407 411 415 423 427 431 435 439 443 447 455 459 463 467 471 475 479 487 491 495 499 503 507 511】。
Step 1.3、发送端获取第一编码信息的信息比特和校验冻结比特在Q对应的子信道分配的子信道的序号。
Q所对应的各子信道中，除去Puncture比特所占据的子信道外，第一编码信息的信息比特和PC-Frozen比特占据可靠度高的部分子信道，Puncture比特和Frozen比特占据可靠性低的部分子信道。如图9所示，为一种Q对应的各子信道中除了Puncture比特外的其他比特所占子信道的可靠性的高低顺序。其中，获取第一编码信息的信息比特和PC-Frozen比特分配的子信道的过程可以分为a、b、c和d四步。
a)对Q对应的各个子信道进行分段。
按照子信道的分段算法，若Q所对应的子信道的序号的最大值为N，则：
N＝16，分段点集合为[7 11]；或者N＝32，分段点集合为[15 23 27]；或者N＝64，分段点集合为[31 47 55 59]；或者N＝128，分段点集合为[63 95 111 119 123]；或者N＝256，分段点集合为[127 191 223 239 247 251]；或者N＝512，分段点集合为[255 383 447 479 495 503 507]；或者N＝1024，分段点集合为[511 767 895 959 991 1007 1015 1019]；或者N＝2048，分段点集合为[1023 1535 1791 1919 1983 2015 2031 2039 2043]；或者N＝4096，分段点集合为[2047 3071 3583 3839 3967 4031 4065 4079 4087 4091]。
上述分段点集合可以是发送端采用长度n＝log2(N)的移位寄存器来产生的；也可以是直接以表格形式存放在发送端的。若以移位寄存器产生分段点集合，举例来说，如图10所示，可以初始化移位寄存器第一位为0其余位为1，此时寄存器内所存储的二进制数为第一分段点。其余分段点可以通过将寄存器中的二进制数依次按图中箭头方向循环移动一位产生。移位寄存器最多移动n-2次。
如图11所示，为各子信道可靠度分布，其中虚线表示分段点。根据举例1，当N＝512时，可以产生7个分段点，其中按照移位寄存器产生的各分段点分别是：第一分段点B1＝(011111111)二进制(Binary，BIN)＝(255)十进制(Decimal，DEC)；第二分段点B2＝(101111111)BIN＝(383)DEC；第三分段点B3＝(110111111)BIN＝(447)DEC；第四分段点B4＝(111011111)BIN＝(479)DEC；第五分段点B5＝(111101111)BIN＝(495)DEC；第六分段点B6＝(111110111)BIN＝(503)DEC；第七分段点B7＝(111111011)BIN＝(507)DEC。
b)确定第一编码的信息比特和PC-Frozen比特分配的子信道的序号。
每个分段中包含的第一编码的信息比特和PC-Frozen比特所占据的子信道的序号小于等于分段点，且不属于前面的分段。
根据举例1，如图11所示，图中的点代表各子信道可靠度，图11中示出了第一编码的信息比特和PC-Frozen比特所占据的子信道的可靠度，第一编码的信息比特和PC-Frozen 比特所占据的子信道的序号可以分别为：[252 253 254|366 373 374 377 378 380 381 382|414 429 430 437 438 441 442 444 445 446|461 462 468 469 470 472 473 474 476 477 478|481 482 483 484 485 486 488 489 490 492 493 494|496 497 498 500 501 502|504 505 506 |508 509 510]。
可知，各段中第一编码的信息比特和PC-Frozen比特分配的子信道的数量Gg分别为：G1＝3；G2＝8；G3＝10；G4＝11；G5＝12；G6＝6；G7＝3；G8＝3。
c)确定PC-Frozen比特分配的子信道的序号。
可以将每个分段的第一编码的信息比特和PC-Frozen比特分配的子信道序号集合中前Pfg个序号对应的子信道或后Pfg个序号对应的子信道或中间Pfg个序号对应的子信道为PC-Frozen比特对应的子信道。其中，g为分段序号，Pfg为非负整数,g为大于或等于1的正整数。
根据举例1，假设各段中第一编码的信息比特和PC-Frozen比特分配的子信道中PC-Frozen比特分配的子信道的数量Pfg分别为Pf1＝1，Pf2＝2，Pf3＝3，Pf4＝3，Pf5＝3，Pf6＝2，Pf7＝1，Pf8＝1；且PC-Frozen比特分配的子信道为各段中第一编码的信息比特和PC-Frozen比特分配的子信道中的前Pfg个比特，那么PC-Frozen比特分配的子信道的序号为[252 366 373 414 429 430 468 472 461 481 482 484 496 497 504 508]。
d)确定冻结比特分配的子信道。
发送端可以将各个子信道中第一编码信息的信息比特、PC-Frozen比特以及Puncture比特对应的子信道以外的子信道确定为Frozen比特分配的子信道；或发送端将各个子信道中第一编码信息的信息比特、PC-Frozen比特以及Shorten比特对应的子信道以外的子信道确定为冻结比特的子信道。
发送端确定出第一编码信息的信息比特、PC-Frozen比特、Puncture比特以及Frozen比特分配的子信道后，可以将第一编码信息的信息比特、PC-Frozen比特、Puncture比特以及Frozen比特添加至各子信道中，以得到第二编码信息。其中，接收端和发送端可以默认Frozen比特分配的子信道上的比特值为0。
504、发送端对第二编码信息进行极化编码，得到第三编码信息并输出给接收端。
发送端可以通过Polar编码器对第二编码信息进行极化码编码，并从极化码编码的结果中除去Puncture比特或Shorten比特以得到第三编码信息，而后将第三编码信息输出给接收端。
505、接收端通过PC-SCL译码器获取待译码信息译码后各个路径的译码值。
其中，待译码信息即发送端发送的第三编码信息。
PC-SCL译码器可以获取L个路径的译码值，L的值可以等于正整数n。举例来说，若L＝8，则接收端可以通过PC-SCL译码器获取8个路径的译码值，每个路径的译码值包括信息比特和循环冗余校验比特，信息比特即待编码信息的信息比特，循环冗余校验比特可以包括第一循环冗余校验比特和第二循环冗余校验比特。
506、接收端通过第二循环冗余校验比特辅助PC-SCL译码器选取任一路径。
当接收端对各个路径的译码值进行校验时，可以通过各路径的译码值中的第二循环冗余校验比特辅助PC-SCL译码器选取任一路径，而后通过步骤507校验该路径。
507、接收端通过任一路径中的第一循环冗余校验比特校验任一路径的信息比特，将校验任一路径的信息比特正确时的信息比特确定为通过循环冗余校验的路径的信息比特。
也就是说，接收端根据步骤506中选出的路径的译码结果中的第一循环冗余校验比特校验该路径的信息比特，若该路径的信息比特能通过该路径中的第一循环冗余校验比特的校验，则将该信息比特确定为通过循环冗余校验的路径的信息比特，也就是最终输出的信息比特。
这样一来，在编码侧，发送端进行极化编码之前既进行循环冗余校验，又进行PC-Frozen编码，在译码侧，接收端将通过PC-Frozen和循环冗余校验的译码结果输出。相比现有技术，在编码侧仅进行循环冗余校验或仅进行PC-Frozen编码，在译码侧，将仅通过PC-Frozen或循环冗余校验的译码结果输出，本申请实施例进行了两重编码和两重校验，即通过CRC辅助PC-Polar编码，仅在PC-Polar编码前进行一次CRC编码，且通过CRC辅助PC-Polar译码，仅在PC-SCL译码后增加CRC选择路径的操作，能够提高译码的错误检测能力，提高极化码的编译码性能。
上述主要从发送端和接收端的角度对本申请实施例提供的方案进行了介绍。可以理解的是，发送端和接收端为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的算法步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本申请实施例可以根据上述方法示例对发送端和接收端进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
在采用对应各个功能划分各个功能模块的情况下，图12示出了上述实施例中所涉及的发送装置12的一种可能的结构示意图，发送装置包括：校验单元1201和编码单元1202。校验单元1201用于支持发送装置执行图5中的过程501；编码单元1202用于支持发送装置执行图5中的过程502、503和504。其中，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
在采用集成的单元的情况下，图3示出了上述实施例中所涉及的终端的一种可能的结构示意图。其中，处理模块301可以是处理器或控制器，例如可以是中央处理器(Central Processing Unit，CPU)，通用处理器，数字信号处理器(Digital Signal Processor，DSP)，专用集成电路(Application-Specific Integrated Circuit，ASIC)，现场可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。其可以实现或执行结合本申请公开内容所描述的各种示例性的逻辑方框，模块和电路。所述处理器也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，DSP和微处理器的组合等等。通信模块302可以是收发器、收发电路或通信接口等。存储模块303可以是存储器。
当处理模块301为处理器，通信模块302为收发器，存储模块303为存储器时，本申请实施例所涉及的发送装置可以为图13所示的发送装置。
参阅图13所示，该发送装置13包括：处理器1301、收发器1302、存储器1303以及总线1304。其中，收发器1302、处理器1301以及存储器1303通过总线1304相互连接；总线1304可以是外设部件互连标准(Peripheral Component Interconnect，PCI)总线或扩展工业标准结构(Extended Industry Standard Architecture，EISA)总线等。所述总线可以分为地址总线、数据总线、控制总线等。为便于表示，图13中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
在采用对应各个功能划分各个功能模块的情况下，图14示出了上述实施例中所涉及的接收装置14的一种可能的结构示意图，接收装置包括：获取单元1401和校验单元1402。获取单元1401用于支持接收装置执行图5中的过程505；校验单元1402用于支持接收装置执行图5中的过程506和507。其中，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
在采用集成的单元的情况下，图4示出了上述实施例中所涉及的终端的一种可能的结构示意图。其中，处理模块401可以是处理器或控制器，例如可以是CPU，通用处理器，DSP，ASIC，FPGA或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。其可以实现或执行结合本申请公开内容所描述的各种示例性的逻辑方框，模块和电路。所述处理器也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，DSP和微处理器的组合等等。通信模块402可以是收发器、收发电路或通信接口等。存储模块403可以是存储器。
当处理模块401为处理器，通信模块402为收发器，存储模块403为存储器时，本申请实施例所涉及的接收装置可以为图15所示的接收装置。
参阅图15所示，该接收装置15包括：处理器1501、收发器1502、存储器1503以及总线1504。其中，收发器1502、处理器1501以及存储器1503通过总线1504相互连接；总线1504可以是PCI总线或EISA总线等。所述总线可以分为地址总线、数据总线、控制总线等。为便于表示，图15中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
结合本申请公开内容所描述的方法或者算法的步骤可以硬件的方式来实现，也可以是由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器(Random Access Memory，RAM)、闪存、只读存储器(Read Only Memory，ROM)、可擦除可编程只读存储器(Erasable Programmable ROM，EPROM)、电可擦可编程只读存储器(Electrically EPROM，EEPROM)、寄存器、硬盘、移动硬盘、只读光盘(CD-ROM)或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于核心网接口设备中。当然，处理器和存储介质也可以作为分立组件存在于核心网接口设备中。
本领域技术人员应该可以意识到，在上述一个或多个示例中，本申请所描述的功能可以用硬件、软件、固件或它们的任意组合来实现。当使用软件实现时，可以将这些功能存 储在计算机可读介质中或者作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是通用或专用计算机能够存取的任何可用介质。
以上所述的具体实施方式，对本申请的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本申请的具体实施方式而已，并不用于限定本申请的保护范围，凡在本申请的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本申请的保护范围之内。

Claims (25)

  1. 一种编码方法，其特征在于，包括：
    发送端对待编码信息进行循环冗余校验，得到第一编码信息；
    所述发送端对所述第一编码信息进行奇偶校验编码，得到第二编码信息；
    所述发送端对所述第二编码信息进行极化编码，得到第三编码信息并输出给接收端。
  2. 根据权利要求1所述的方法，其特征在于，所述发送端对待编码信息进行循环冗余校验，得到第一编码信息包括：
    所述发送端对所述待编码信息的信息比特添加循环冗余校验比特，得到所述第一编码信息，所述循环冗余校验比特包括第一循环冗余校验比特和第二循环冗余校验比特，所述第一循环冗余校验比特是根据所述信息比特获得的，所述第二循环冗余校验比特是根据所述信息比特以及所述第一循环冗余校验比特获取的，所述第一循环冗余校验比特用于校验所述信息比特，所述第二循环冗余校验比特用于辅助译码。
  3. 根据权利要求1或2所述的方法，其特征在于，所述发送端对所述第一编码信息进行奇偶校验编码，得到第二编码信息包括：
    所述发送端根据各个子信道的可靠度将所述第一编码信息的信息比特、校验冻结比特以及冻结比特分配至所述各个子信道中，得到所述第二编码信息，所述第二编码信息中所述信息比特和所述校验冻结比特分配在可靠度高的子信道中，所述冻结比特分配在可靠度低的子信道中。
  4. 根据权利要求1或2所述的方法，其特征在于，所述发送端对所述第一编码信息进行奇偶校验编码，得到第二编码信息包括：
    所述发送端根据子信道极化的准周期特性将所述第一编码信息的信息比特、校验冻结比特以及冻结比特分配至所述各个子信道中，得到所述第二编码信息。
  5. 根据权利要求4所述的方法，其特征在于，所述发送端根据子信道极化的准周期特性将所述第一编码信息的信息比特、校验冻结比特以及冻结比特分配至所述各个子信道中包括：
    所述发送端获取各个子信道的可靠度序列，并通过极化码速率匹配方式获取打孔比特或截短比特对应的子信道；
    所述发送端对所述各个子信道按照子信道极化的准周期获取子信道分段点集合，以对所述各个子信道进行分段；
    所述发送端确定每个分段中除所述打孔比特对应的子信道或所述截短比特对应的子信道以外所述信息比特和所述校验冻结比特对应的子信道对应的序号集合；
    所述发送端将所述各个子信道中所述信息比特、所述校验冻结比特以及所述打孔比特对应的子信道以外的子信道确定为所述冻结比特的子信道；或所述发送端将所述各个子信道中所述信息比特、所述校验冻结比特以及所述截短比特对应的子信道以外的子信道确定为所述冻结比特的子信道。
  6. 根据权利要求5所述的方法，其特征在于，若所述可靠度序列的最小值为0，最大值为N-1，则：
    N＝16，所述分段点集合为[7 11]；或者
    N＝32，所述分段点集合为[15 23 27]；或者
    N＝64，所述分段点集合为[31 47 55 59]；或者
    N＝128，所述分段点集合为[63 95 111 119 123]；或者
    N＝256，所述分段点集合为[127 191 223 239 247 251]；或者
    N＝512，所述分段点集合为[255 383 447 479 495 503 507]；或者
    N＝1024，所述分段点集合为[511 767 895 959 991 1007 1015 1019]；或者
    N＝2048，所述分段点集合为[1023 1535 1791 1919 1983 2015 2031 2039 2043]；或者
    N＝4096，所述分段点集合为[2047 3071 3583 3839 3967 4031 4065 4079 4087 4091]。
  7. 根据权利要求5所述的方法，其特征在于，所述每个分段的序号集合中前Pfg个序号对应的子信道或后Pfg个序号对应的子信道为所述校验冻结比特对应的子信道,g为分段序号，Pfg为非负整数,g为大于或等于1的正整数。
  8. 一种译码方法，其特征在于，包括：
    接收端通过奇偶校验连续抵消列表PC-SCL译码器获取待译码信息译码后各个路径的译码值；
    所述接收端对所述各个路径进行循环冗余校验，获取通过所述循环冗余校验的路径的信息比特。
  9. 根据权利要求8所述的方法，其特征在于，对于所述各个路径中的每个路径，该路径的译码值包括所述待译码信息的信息比特和循环冗余校验比特，所述循环冗余校验比特包括第一循环冗余校验比特和第二循环冗余校验比特，所述第一循环冗余校验比特是根据所述信息比特获得的，所述第二循环冗余校验比特是根据所述信息比特以及所述第一循环冗余校验比特获取的，所述第一循环冗余校验比特用于校验所述信息比特，所述第二循环冗余校验比特用于辅助译码。
  10. 根据权利要求9所述的方法，其特征在于，所述接收端对所述各个路径进行循环冗余校验，获取通过所述循环冗余校验的路径的信息比特包括：
    所述接收端通过所述第二循环冗余校验比特辅助所述PC-SCL译码器选取任一路径，通过所述任一路径中的所述第一循环冗余校验比特校验所述任一路径的信息比特，将校验所述任一路径的信息比特正确时的信息比特确定为通过所述循环冗余校验的路径的信息比特。
  11. 一种发送装置，其特征在于，包括：
    校验单元，用于对待编码信息进行循环冗余校验，得到第一编码信息；
    编码单元，用于对所述第一编码信息进行奇偶校验编码，得到第二编码信息；
    所述编码单元还用于对所述第二编码信息进行极化编码，得到第三编码信息并输出给接收端。
  12. 根据权利要求11所述的发送装置，其特征在于，所述校验单元用于：
    对所述待编码信息的信息比特添加循环冗余校验比特，得到所述第一编码信息，所述循环冗余校验比特包括第一循环冗余校验比特和第二循环冗余校验比特，所述第一循环冗余校验比特是根据所述信息比特获得的，所述第二循环冗余校验比特是根据所述信息比特以及所述第一循环冗余校验比特获取的，所述第一循环冗余校验比特用于校验所述信息比特，所述第二循环冗余校验比特用于辅助译码。
  13. 根据权利要求11或12所述的发送装置，其特征在于，所述编码单元用于：
    根据各个子信道的可靠度将所述第一编码信息的信息比特、校验冻结比特以及冻结比特分配至所述各个子信道中，得到所述第二编码信息，所述第二编码信息中所述信息比特和所述校验冻结比特分配在可靠度高的子信道中，所述冻结比特分配在可靠度低的子信道中。
  14. 根据权利要求11或12所述的发送装置，其特征在于，所述编码单元用于：
    根据子信道极化的准周期特性将所述第一编码信息的信息比特、校验冻结比特以 及冻结比特分配至所述各个子信道中，得到所述第二编码信息。
  15. 根据权利要求14所述的发送装置，其特征在于，所述编码单元包括：
    获取子单元，用于获取各个子信道的可靠度序列，并通过极化码速率匹配方式获取打孔比特或截短比特对应的子信道；
    分段子单元，用于对所述各个子信道按照子信道极化的准周期获取子信道分段点集合，以对所述各个子信道进行分段；
    确定子单元，用于确定每个分段中除所述打孔比特对应的子信道或所述截短比特对应的子信道以外所述信息比特和所述校验冻结比特对应的子信道对应的序号集合；
    所述确定子单元还用于，将所述各个子信道中所述信息比特、所述校验冻结比特以及所述打孔比特对应的子信道以外的子信道确定为所述冻结比特的子信道；或将所述各个子信道中所述信息比特、所述校验冻结比特以及所述截短比特对应的子信道以外的子信道确定为所述冻结比特的子信道。
  16. 根据权利要求15所述的发送装置，其特征在于，若所述可靠度序列的最小值为0，最大值为N-1，则：
    N＝16，所述分段点集合为[7 11]；或者
    N＝32，所述分段点集合为[15 23 27]；或者
    N＝64，所述分段点集合为[31 47 55 59]；或者
    N＝128，所述分段点集合为[63 95 111 119 123]；或者
    N＝256，所述分段点集合为[127 191 223 239 247 251]；或者
    N＝512，所述分段点集合为[255 383 447 479 495 503 507]；或者
    N＝1024，所述分段点集合为[511 767 895 959 991 1007 1015 1019]；或者
    N＝2048，所述分段点集合为[1023 1535 1791 1919 1983 2015 2031 2039 2043]；或者
    N＝4096，所述分段点集合为[2047 3071 3583 3839 3967 4031 4065 4079 4087 4091]。
  17. 根据权利要求15所述的发送装置，其特征在于，所述每个分段的序号集合中前Pfg个序号对应的子信道、后Pfg个序号对应的子信道或中间Pfg个序号对应的子信道为所述校验冻结比特对应的子信道,g为分段序号，Pfg为非负整数，g为大于或等于1的正整数。
  18. 一种接收装置，其特征在于，包括：
    获取单元，用于通过奇偶校验连续抵消列表PC-SCL译码器获取待译码信息译码后各个路径的译码值；
    校验单元，用于对所述各个路径进行循环冗余校验，获取通过所述循环冗余校验的路径的信息比特。
  19. 根据权利要求18所述的接收装置，其特征在于，对于所述各个路径中的每个路径，该路径的译码值包括所述待译码信息的信息比特和循环冗余校验比特，所述循环冗余校验比特包括第一循环冗余校验比特和第二循环冗余校验比特，所述第一循环冗余校验比特是根据所述信息比特获得的，所述第二循环冗余校验比特是根据所述信息比特以及所述第一循环冗余校验比特获取的，所述第一循环冗余校验比特用于校验所述信息比特，所述第二循环冗余校验比特用于辅助译码。
  20. 根据权利要求19所述的接收装置，其特征在于，所述校验单元用于：
    通过所述第二循环冗余校验比特辅助所述PC-SCL译码器选取任一路径，通过所述任一路径中的所述第一循环冗余校验比特校验所述任一路径的信息比特，将校验所述任一路径的信息比特正确时的信息比特确定为通过所述循环冗余校验的路径的信息 比特。
  21. 一种发送装置，其特征在于，包括：处理器、存储器和通信接口；
    所述存储器用于存储计算机执行指令，当所述发送装置运行时，所述处理器执行所述存储器存储的所述计算机执行指令，以使所述发送装置执行如权利要求1-7中任意一项所述的编码方法。
  22. 一种接收装置，其特征在于，包括：处理器、存储器和通信接口；
    所述存储器用于存储计算机执行指令，当所述接收装置运行时，所述处理器执行所述存储器存储的所述计算机执行指令，以使所述接收装置执行如权利要求8-10中任意一项所述的译码方法。
  23. 一种包含指令的计算机程序产品，其特征在于，当其在计算机上运行时，使得计算机执行如权利要求1-7中任意一项所述的编码方法，或权利要求8-10中任意一项所述的译码方法。
  24. 一种计算机可读存储介质，其特征在于，包括计算机指令，当其在计算机上运行时，使得计算机执行如权利要求1-7中任意一项所述的编码方法，或权利要求8-10中任意一项所述的译码方法。
  25. 一种芯片，其特征在于，包括：处理器和存储器；
    所述存储器，用于与所述处理器耦合，保存所述芯片的程序指令和数据；
    所述处理器，用于执行所述存储器中存储的程序指令，使得所述芯片执行如权利要求1-7中任意一项所述的编码方法，或权利要求8-10中任意一项所述的译码方法。
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110113132B (zh) * 2017-01-25 2020-07-07 华为技术有限公司 一种编译码方法和终端
CN108365914B (zh) * 2017-01-26 2023-04-18 华为技术有限公司 Polar码编译码方法及装置
WO2018201404A1 (en) * 2017-05-04 2018-11-08 Qualcomm Incorporated Polar codes for uplink control information
CN109391353B (zh) * 2017-08-11 2021-09-14 华为技术有限公司 一种速率匹配的方法和装置
CN109361401B (zh) * 2018-08-30 2021-11-02 中国地质大学（武汉） 一种用于随钻测量传输系统的极化信道编码方法
WO2020042089A1 (zh) * 2018-08-30 2020-03-05 华为技术有限公司 Scl并行译码方法、装置及设备
CN111200439B (zh) 2018-11-16 2022-05-06 华为技术有限公司 译码方法、装置及设备
CN109361495B (zh) * 2018-12-07 2020-05-08 北京邮电大学 一种极化码构造方法、装置、电子设备及可读存储介质
CN112118074B (zh) * 2019-06-21 2021-12-03 华为技术有限公司 一种通信方法及装置
CN111130566B (zh) * 2019-12-18 2021-05-11 清华大学 Polar码译码器中寻找L个最大路径度量值的电路实现方法
CN111614439B (zh) * 2020-05-20 2021-04-20 北京邮电大学 一种信息传输方法、系统、装置及电子设备
CN112953560B (zh) * 2021-03-11 2022-12-23 中山大学 一种基于关键集的极化码连续消除列表翻转译码方法
CN113067584A (zh) * 2021-03-23 2021-07-02 重庆邮电大学 一种crc码与pc码共同辅助极化码的编码方法
CN113114274A (zh) * 2021-04-16 2021-07-13 中国计量大学 一种基于分段关键集合的简化极化码连续消除列表译码器
CN113641531A (zh) * 2021-07-27 2021-11-12 东莞理工学院 Star码的编码方法及其解码方法
US20230077219A1 (en) * 2021-09-08 2023-03-09 Qualcomm Incorporated Securing polar codes
CN114448448B (zh) * 2022-01-24 2023-07-28 电子科技大学 一种基于ca-scl的极化码编译码方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104219019A (zh) * 2013-05-31 2014-12-17 华为技术有限公司 编码方法及编码设备
CN105227189A (zh) * 2015-09-24 2016-01-06 电子科技大学 分段crc辅助的极化码编译码方法
CN105680883A (zh) * 2015-12-23 2016-06-15 华中科技大学 一种极化码和多比特偶校验码级联的纠错编码方法
CN106230555A (zh) * 2016-07-29 2016-12-14 西安电子科技大学 极化码的分段循环冗余校验方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8184726B2 (en) * 2007-09-10 2012-05-22 Industrial Technology Research Institute Method and apparatus for multi-rate control in a multi-channel communication system
CN103281166B (zh) * 2013-05-15 2016-05-25 北京邮电大学 一种基于极化码的混合自动重传请求传输方法
US9722651B2 (en) * 2015-01-09 2017-08-01 Qualcomm Incorporated Adaptive channel coding using polarization
US10461779B2 (en) * 2015-08-12 2019-10-29 Telefonaktiebolaget Lm Ericsson (Publ) Rate-compatible polar codes
CN105743621B (zh) * 2016-02-02 2019-03-26 北京邮电大学 基于极化码的harq信号发送、接收方法及装置
US10432234B2 (en) * 2016-07-19 2019-10-01 Mediatek Inc. Low complexity rate matching for polar codes
CN110113132B (zh) * 2017-01-25 2020-07-07 华为技术有限公司 一种编译码方法和终端

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104219019A (zh) * 2013-05-31 2014-12-17 华为技术有限公司 编码方法及编码设备
CN105227189A (zh) * 2015-09-24 2016-01-06 电子科技大学 分段crc辅助的极化码编译码方法
CN105680883A (zh) * 2015-12-23 2016-06-15 华中科技大学 一种极化码和多比特偶校验码级联的纠错编码方法
CN106230555A (zh) * 2016-07-29 2016-12-14 西安电子科技大学 极化码的分段循环冗余校验方法

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