WO2018134999A1 - Variable gain amplifier - Google Patents

Variable gain amplifier Download PDF

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Publication number
WO2018134999A1
WO2018134999A1 PCT/JP2017/002134 JP2017002134W WO2018134999A1 WO 2018134999 A1 WO2018134999 A1 WO 2018134999A1 JP 2017002134 W JP2017002134 W JP 2017002134W WO 2018134999 A1 WO2018134999 A1 WO 2018134999A1
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Prior art keywords
transistor
gain control
terminal
impedance
terminals
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PCT/JP2017/002134
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French (fr)
Japanese (ja)
Inventor
孝信 藤原
下沢　充弘
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三菱電機株式会社
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Priority to JP2018538798A priority Critical patent/JP6411006B1/en
Priority to PCT/JP2017/002134 priority patent/WO2018134999A1/en
Publication of WO2018134999A1 publication Critical patent/WO2018134999A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/02—Manually-operated control
    • H03G3/04—Manually-operated control in untuned amplifiers
    • H03G3/10—Manually-operated control in untuned amplifiers having semiconductor devices

Definitions

  • the present invention relates to a variable gain amplifier capable of changing a gain.
  • variable gain amplifier a digitally controlled current steering type variable gain amplifier is widely used as a method capable of realizing high gain control accuracy (see, for example, Patent Document 1).
  • a variable gain amplifier includes an amplification stage transistor connected to a signal input end and a plurality of cascode stage transistors connected in cascade to the output end of the amplification stage transistor.
  • the plurality of cascode stage transistors constitute a unit cell circuit, and the variable gain amplifier includes a plurality of these unit cell circuits, and the amplification factor is obtained by controlling the conduction state and the cutoff state of each unit cell circuit by the control circuit. Is variable.
  • the current steering type variable gain amplifier can be regarded as a cascode amplifier using a common base transistor when viewed as one amplifier.
  • One important factor in designing the variable gain amplifier is that the input current is transmitted to the output terminal without being released to the base terminal side. Therefore, it is necessary to match the base terminal of the grounded base transistor, which is a cascode device, to the short point. That is, the impedance when the control circuit side that controls the transistor is viewed from the base terminal of the transistor needs to be sufficiently low at the operating frequency. When this impedance is high, an input signal from the emitter terminal leaks to the base terminal side, resulting in a decrease in gain. Therefore, conventionally, a stabilization capacitor has been arranged at the base terminal.
  • variable gain amplifier since it is necessary to arrange a capacitive element at the base terminal of the common base transistor, the area of the unit cell circuit becomes large. Therefore, when the unit cell circuits are arranged in an array, The wiring area of a transistor for transmitting a high frequency signal is increased. As a result, there has been a problem that high frequency characteristics are lowered in terms of operating band, gain and noise as a variable gain amplifier due to an increase in parasitic capacitance and inductance.
  • the present invention has been made to solve such a problem, and an object of the present invention is to provide a variable gain amplifier capable of suppressing deterioration of high frequency characteristics.
  • the variable gain amplifier includes a grounded base type first transistor and a second transistor, a conductive state in which a signal from the input terminal is conducted to the output terminal through the first transistor, and from the input terminal
  • the first gain control terminal for controlling the respective bases of the first and second transistors and the second gain control are realized by releasing a signal from the first transistor to the terminals other than the output terminal via the second transistor.
  • a plurality of unit cell circuits having a plurality of unit terminals, wherein the input terminals and the output terminals of the plurality of unit cell circuits are connected in parallel and connected to the first and second gain control terminals. Are provided between the base of the first and second transistors and the first and second gain control terminals, and is set in the control circuit unit.
  • a switch circuit for realizing a conductive state and a cut-off state and an impedance transformer having a set value as an impedance when the first and second gain control terminals are viewed from the bases of the first and second transistors. It is a thing.
  • the first gain control terminal and the second transistor are provided between the first transistor and the second transistor and the switching transistor between the first transistor and the base of the second transistor.
  • An impedance transformer having an impedance as viewed from the gain control terminal side as a set value is provided.
  • FIG. 1A and 1B are configuration diagrams of a variable gain amplifier according to Embodiment 1 of the present invention. It is explanatory drawing which shows the layout image of the variable gain amplifier of Embodiment 1 of this invention. It is a perspective view which shows an example of the impedance transformer in the variable gain amplifier of Embodiment 1 of this invention. It is explanatory drawing which shows the locus
  • FIG. 1A and 1B are configuration diagrams of a variable gain amplifier according to the present embodiment.
  • the variable gain amplifier according to the present embodiment is a current steering type variable gain amplifier as shown in the figure.
  • a plurality of unit cell circuits 100a to 100n are connected in parallel, and the number is N.
  • Each of the unit cell circuits 100a to 100n includes a first transistor 101, a second transistor 102, a switching transistor 103, and an impedance transformer 104.
  • the emitters of the first transistor 101 and the second transistor 102 are connected to the emitter input terminals 105a to 105n of the unit cell circuits 100a to 100n.
  • the collector of the first transistor 101 is connected to the collector output terminals 106a to 106n of the unit cell circuits 100a to 100n.
  • the collector of the second transistor 102 is connected to the power source.
  • the bases of the first transistor 101 and the second transistor 102 are connected to the drain terminal of a switching transistor 103 made of an NMOS transistor via an impedance transformer 104, respectively.
  • the source of the switching transistor 103 is connected to the base bias terminals 107a to 107n of the unit cell circuits 100a to 100n.
  • the gate of the switching transistor 103 is connected to the first gain control terminals 108a to 108n and the second gain control terminals 109a to 109n in the unit cell circuits 100a to 100n.
  • the emitter input terminals 105a to 105n of the unit cell circuits 100a to 100n are connected to the source of the transistor 110.
  • the drain of the transistor 110 is grounded, and the gate is connected to the voltage input terminal 111.
  • the collector output terminals 106a to 106n of the unit cell circuits 100a to 100n are connected to the power supply via the load inductance 112 and also to the output terminal 113.
  • FIG. 1B shows the control circuit unit 114.
  • the control circuit unit 114 includes a base current source 115 and a logic generation circuit 116.
  • the base current source 115 is a power source for supplying base currents of the first transistor 101 and the second transistor 102 via the base bias terminals 107a to 107n.
  • the logic generation circuit 116 is a circuit that generates a control signal for controlling the gain as the variable gain amplifier, and is connected via the first gain control terminals 108a to 108n and the second gain control terminals 109a to 109n.
  • the switch transistor 103 is controlled.
  • the impedance when the base bias terminals 107a to 107n are viewed from the bases of the first transistor 101 and the second transistor 102 is the base current source 115 in the control circuit unit 114.
  • the on-resistance of the switching transistor 103, and the impedance transformer 104 Generally, the output impedance of a circuit that functions as a current source is high, the output impedance of the base current source 115 is high, and the on-resistance of the NMOS transistor also has a finite resistance value of several tens to several hundreds ⁇ depending on the transistor size. .
  • the base bias terminals 107a to 107n are viewed from the bases of the first transistor 101 and the second transistor 102.
  • the impedance at the time can be transformed near the short point.
  • the first transistor 101 and the second transistor 102 can operate as a cascode circuit, and the current gain from the emitter input terminals 105a to 105n to the collector output terminals 106a to 106n can be maintained at a high value. .
  • An input signal from the voltage input terminal 111 is converted into a current signal 117 by the transistor 110.
  • the current signal 117 is distributed N and is input to the emitter input terminals 105a to 105n of the unit cell circuits 100a to 100n.
  • Each of the unit cell circuits 100a to 100n controls the first gain control terminals 108a to 108n and the second gain control terminals 109a to 109n from the control circuit unit 114 and supplies power to the base bias terminals 107a to 107n.
  • the gain is controlled by controlling the amount of current transmitted to the output terminal 113 by the current signal 117.
  • the control circuit unit 114 generates a reference current for biasing the bases of the first transistor 101 and the second transistor 102 by the base current source 115, and passes through the base bias terminals 107 a to 107 n and the switching transistor 103. Supply power.
  • the N unit cell circuits 100a to 100n are connected to the switching transistor 103 by a control signal from the control circuit unit 114 supplied to the first gain control terminals 108a to 108n and the second gain control terminals 109a to 109n. ON / OFF is controlled.
  • the conduction state of the first transistor 101 and the cutoff state of the second transistor 102 are controlled, and the two operations of releasing the current from the emitter input terminals 105a to 105n to the power source or transmitting the current to the output terminal 113 are performed.
  • control is performed so that only Nsel is transmitted to the output terminal 113, and the remainder is controlled so as to release current to the power supply, and the current gain G is expressed by the following equation.
  • G Nsel / N
  • FIG. 2 shows a layout image of the variable gain amplifier according to the first embodiment.
  • the element circuits in the unit cell circuits 100a to 100n in FIG. 1 are divided into a high-frequency signal block 204 and a bias block 205 and arranged in an N-array, and these two blocks are used as impedance transformation transmission lines.
  • 203 is connected.
  • the layout group 201 is N high frequency signal blocks 204, and the layout group 202 is N bias blocks 205.
  • the transmission line 203 is the impedance transformer 104 in FIG. 1A, and is mounted as a 1/4 wavelength transmission line at a desired frequency.
  • the high-frequency signal block 204 includes the first transistor 101 and the second transistor 102 in FIG. 1, and has a configuration in which only a circuit that passes a high-frequency signal is separated.
  • the bias block 205 includes a switch transistor 103.
  • the impedance transformer 104 is a 1/4 wavelength transmission line 203 at a desired frequency and has a physical length. By using this length, the bias block 205 can be arranged at a distance from the high-frequency signal block 204. In addition, as long as the bias block 205 can accurately transmit a bias current, which is a low-frequency signal, the sensitivity of characteristic changes to parasitic capacitance and inductance due to layout is low. Therefore, the chip area can be arranged in an arbitrary area that does not affect the high-frequency signal path, and the chip area can be effectively used.
  • the high-frequency signal block 204 can be densely laid out.
  • the high-frequency signal block 204 is a group of layouts 201 arranged together, and the wiring area of the emitter input terminals 105a to 105n and the collector output terminals 106a to 106n in FIG. 1 is reduced to reduce parasitic capacitance and inductance. Make it possible to do. By suppressing the parasitic components of these terminals, matching with impedance that optimizes high-frequency characteristics is facilitated, so that high-frequency performance improvement effects such as higher gain, wider bandwidth, and lower noise can be obtained.
  • FIG. 3 shows an implementation example of the transmission line 203 shown in FIG. 2 in the microstrip line system as an example of the impedance transformer 104.
  • the impedance transformer 104 (transmission line 203) desirably has a low characteristic impedance, and is compatible with a silicon process that can easily realize multilayer wiring.
  • the layout group 201 can be further downsized.
  • the layout group 303 (layout group 201 in FIG. 2) composed of high frequency blocks and the layout group 304 (layout group 202 in FIG. 2) composed of bias blocks are connected to optimize the high frequency characteristics. Impedance transformation is realized.
  • the layout example shown in FIGS. 2 and 3 is an example of layout design of the circuit configuration of the variable gain amplifier according to the present embodiment.
  • the layout example shown in FIG. 2 has a one-dimensional array arrangement. It is not limited. The same applies to a two-dimensional array arrangement.
  • the method of determining the array arrangement is one of the design items that should be optimized by minimizing the parasitic components on the path of the high-frequency signal, effectively using the chip area, and the parameters of the transistors of the high-frequency signal block 204. It is.
  • the impedance of the base current source 115 and the switching transistor 103 in FIG. 1 will be described as pure resistance, and an impedance transformer 104 using an ideal quarter wavelength line will be used. explained.
  • reactance components due to parasitic capacitance and inductance always exist, and after including these reactance components, the impedance viewed from the bases of the first transistor 101 and the second transistor 102 is brought close to the short point.
  • adjustment of the impedance transformer 104 is one of the design matters.
  • the case where bipolar transistors are used for the first transistor 101 and the second transistor 102 used in the high frequency block has been described.
  • the high frequency is used. The effect of improving the characteristics can be obtained.
  • the gate grounding type is used, and the impedance transformer 104 is disposed between the gate and the switching transistor 103.
  • the base-grounded first transistor and the second transistor are included, and the signal from the input terminal is output to the output terminal via the first transistor.
  • a plurality of unit cell circuits each having a control terminal and a second gain control terminal are provided, input terminals and output terminals of the plurality of unit cell circuits are connected in parallel, and the first and second gain control terminals are provided.
  • a control circuit unit that is connected to a terminal and sets a conduction state or a cutoff state for each unit cell circuit, and between the bases of the first and second transistors and the first and second gain control terminals.
  • the switch circuit that realizes the conduction state and the cutoff state by the setting of the control circuit unit, and the impedance when the first and second gain control terminal sides are viewed from the bases of the first and second transistors are set values.
  • the impedance transformer when the base bias terminal side is viewed from the base of the first transistor and the second transistor can be impedance-transformed near the short point, and the high frequency characteristics are deteriorated. Can be suppressed.
  • the impedance transformer has a characteristic impedance that is smaller than the total impedance of the switch circuit impedance and the control circuit unit impedance, and has a set operating frequency. In this case, the chip area can be effectively used when the semiconductor device is realized.
  • variable gain amplifier includes a grounded-gate first field effect transistor and a second field effect transistor, and outputs a signal from the input terminal via the first field effect transistor.
  • a conduction state for conducting to the terminal, and a blocking state for releasing a signal from the input terminal to a terminal other than the output terminal via the second field effect transistor, and the gates of the first and second field effect transistors are connected to each other.
  • a plurality of unit cell circuits each having a first gain control terminal and a second gain control terminal to be controlled; the input terminals and the output terminals of the plurality of unit cell circuits are connected in parallel; and A control circuit unit which is connected to the second gain control terminal and sets either a conduction state or a cutoff state for each unit cell circuit; and gates of the first and second field effect transistors; A switching circuit that is provided between the first and second gain control terminals and realizes a conductive state and a cut-off state according to the setting of the control circuit unit, and the first and second gates of the first and second field effect transistors And an impedance transformer whose setting value is an impedance when the gain control terminal side is viewed from the base of the first field effect transistor and the second field effect transistor. Impedance can be transformed near the short point, and deterioration of high frequency characteristics can be suppressed.
  • FIG. 3 when the impedance transformer is realized as a transmission line, the effect of this configuration can be increased by designing the layout so that the characteristic impedance becomes a sufficiently low value.
  • the impedance of the base current source 115 in FIG. 1 is R1 [ohm]
  • the on-resistance of the switching transistor 103 is R2 [ohm]
  • the characteristic impedance of the transmission lines 301a to 301n is In the case of Zo [ohm]
  • FIG. 4 is an explanatory diagram showing the impedance transformation locus using a Smith chart.
  • an impedance 401 when the control circuit unit 114 is viewed from the bases of the first transistor 101 and the second transistor 102 an impedance 402 when the control circuit unit 114 is viewed from the base bias terminals 107a to 107n, and an impedance transformer.
  • a locus 403 on the Smith chart according to 104 is shown.
  • variable gain amplifier relates to a configuration in which the gain can be changed by controlling the conduction state and the cutoff state for each of the plurality of unit cell circuits, and is used for a radio receiver or the like.
  • 100a to 100n unit cell circuit 101 first transistor, 102 second transistor, 103 switch transistor, 104 impedance transformer, 105a to 105n emitter input terminal, 106a to 106n collector output terminal, 107a to 107n base bias terminal, 108a to 108n, first gain control terminal, 109a to 109n, second gain control terminal, 110 transistor, 111 voltage input terminal, 112 load inductance, 113 output terminal, 114 control circuit section, 115 base current source, 116 logic Generator circuit, 117 current signal, 201, 202 layout group, 203, 301a to 301n transmission line, 204 high frequency signal block, 205 bias block, 302 group Command layer, 303 and 304 layout group.

Abstract

A control circuit (114) determines a conductive state and a cut-off state for unit cell circuits (100a-100n) by executing control via first gain control terminals (108a-108n) and second gain control terminals (109a-109n). Between a first transistor (101) and a switch transistor (103), and between a second transistor (102) and the switch transistor (103), in each of the unit cell circuits (100a-100n), impedance transformers (104) are provided, in which impedances viewed from the bases of the first transistor (101) and the second transistor (102) to the corresponding first gain control terminal (108a-108n) and the corresponding second gain control terminal (109a-109n), respectively, are set as setting values.

Description

可変利得増幅器Variable gain amplifier
　本発明は、利得を変更可能な可変利得増幅器に関する。 The present invention relates to a variable gain amplifier capable of changing a gain.
　可変利得増幅器において、高い利得制御精度を実現することが可能な方式として、デジタル制御方式のカレントステアリング型の可変利得増幅器が広く用いられている（例えば、特許文献１参照）。このような可変利得増幅器は、信号入力端に接続された増幅段トランジスタと、この増幅段トランジスタの出力端にカスコード接続された複数のカスコード段トランジスタを含むものである。複数のカスコード段トランジスタは単位セル回路を構成しており、可変利得増幅器は、これら単位セル回路を複数備え、それぞれの単位セル回路の導通状態と遮断状態とを制御回路で制御することにより増幅率を可変としている。 In a variable gain amplifier, a digitally controlled current steering type variable gain amplifier is widely used as a method capable of realizing high gain control accuracy (see, for example, Patent Document 1). Such a variable gain amplifier includes an amplification stage transistor connected to a signal input end and a plurality of cascode stage transistors connected in cascade to the output end of the amplification stage transistor. The plurality of cascode stage transistors constitute a unit cell circuit, and the variable gain amplifier includes a plurality of these unit cell circuits, and the amplification factor is obtained by controlling the conduction state and the cutoff state of each unit cell circuit by the control circuit. Is variable.
　カレントステアリング型の可変利得増幅器は、一つのアンプと見たときにベース接地トランジスタを用いたカスコードアンプとみなすことができる。可変利得増幅器を設計する上で重要なことの一つとして、入力電流をベース端子側に逃がすことなく出力端子に伝える点がある。従って、カスコードデバイスであるベース接地トランジスタのベース端子はショート点に整合を取ることが必要となる。つまり、トランジスタのベース端子から、このトランジスタを制御する制御回路側を見たときのインピーダンスが、動作周波数において十分に低い必要がある。このインピーダンスが高いと、エミッタ端子からの入力信号がベース端子側に漏れるために利得低下を招く。そのために、従来、ベース端子には、安定化容量を配置していた。 The current steering type variable gain amplifier can be regarded as a cascode amplifier using a common base transistor when viewed as one amplifier. One important factor in designing the variable gain amplifier is that the input current is transmitted to the output terminal without being released to the base terminal side. Therefore, it is necessary to match the base terminal of the grounded base transistor, which is a cascode device, to the short point. That is, the impedance when the control circuit side that controls the transistor is viewed from the base terminal of the transistor needs to be sufficiently low at the operating frequency. When this impedance is high, an input signal from the emitter terminal leaks to the base terminal side, resulting in a decrease in gain. Therefore, conventionally, a stabilization capacitor has been arranged at the base terminal.
特開２００７－２５９２９７号公報JP 2007-259297 A
　しかしながら、従来の可変利得増幅器では、ベース接地トランジスタのベース端子に容量素子を配置する必要があるために、単位セル回路の面積が大きくなり、従って、単位セル回路をアレイ状に配置した場合には高周波信号を伝えるためのトランジスタの配線面積が大きくなる。その結果、寄生容量やインダクタンスの増加により、可変利得増幅器としての動作帯域、利得及び雑音などの点で高周波特性を低下させるという問題点を有していた。 However, in the conventional variable gain amplifier, since it is necessary to arrange a capacitive element at the base terminal of the common base transistor, the area of the unit cell circuit becomes large. Therefore, when the unit cell circuits are arranged in an array, The wiring area of a transistor for transmitting a high frequency signal is increased. As a result, there has been a problem that high frequency characteristics are lowered in terms of operating band, gain and noise as a variable gain amplifier due to an increase in parasitic capacitance and inductance.
　この発明は、かかる問題を解決するためになされたもので、高周波特性の劣化を抑えることが可能な可変利得増幅器を提供することを目的とする。 The present invention has been made to solve such a problem, and an object of the present invention is to provide a variable gain amplifier capable of suppressing deterioration of high frequency characteristics.
　この発明に係る可変利得増幅器は、ベース接地型の第１のトランジスタと第２のトランジスタを含み、入力端子からの信号を第１のトランジスタを介して出力端子へ導通させる導通状態と、入力端子からの信号を第２のトランジスタを介して出力端子以外の端子に逃がす遮断状態を実現し、第１及び第２のトランジスタのそれぞれのベースを制御する第１の利得制御用端子と第２の利得制御用端子とを有する単位セル回路を複数備えると共に、複数の単位セル回路の入力端子と出力端子とを並列接続し、かつ、第１及び第２の利得制御用端子に接続され、単位セル回路毎に、導通状態か遮断状態のいずれかを設定する制御回路部と、第１及び第２のトランジスタのベースと第１及び第２の利得制御用端子の間に設けられ、制御回路部の設定により、導通状態と遮断状態を実現するスイッチ回路と、第１及び第２のトランジスタのベースから第１及び第２の利得制御用端子側を見たインピーダンスを設定値とするインピーダンス変成器とを備えたものである。 The variable gain amplifier according to the present invention includes a grounded base type first transistor and a second transistor, a conductive state in which a signal from the input terminal is conducted to the output terminal through the first transistor, and from the input terminal The first gain control terminal for controlling the respective bases of the first and second transistors and the second gain control are realized by releasing a signal from the first transistor to the terminals other than the output terminal via the second transistor. A plurality of unit cell circuits having a plurality of unit terminals, wherein the input terminals and the output terminals of the plurality of unit cell circuits are connected in parallel and connected to the first and second gain control terminals. Are provided between the base of the first and second transistors and the first and second gain control terminals, and is set in the control circuit unit. And a switch circuit for realizing a conductive state and a cut-off state, and an impedance transformer having a set value as an impedance when the first and second gain control terminals are viewed from the bases of the first and second transistors. It is a thing.
　この発明に係る可変利得増幅器は、第１のトランジスタ及び第２のトランジスタとスイッチ用トランジスタとの間に、第１のトランジスタ及び第２のトランジスタのベースから第１の利得制御用端子及び第２の利得制御用端子側を見たインピーダンスを設定値とするインピーダンス変成器を設けるようにしたものである。これにより、第１のトランジスタ及び第２のトランジスタのベースからベースバイアス端子側を見た時のインピーダンスをショート点付近にインピーダンス変成することができ、その結果、高周波特性の劣化を抑えることができる。 In the variable gain amplifier according to the present invention, the first gain control terminal and the second transistor are provided between the first transistor and the second transistor and the switching transistor between the first transistor and the base of the second transistor. An impedance transformer having an impedance as viewed from the gain control terminal side as a set value is provided. Thereby, the impedance when the base bias terminal side is seen from the bases of the first transistor and the second transistor can be transformed near the short point, and as a result, deterioration of the high frequency characteristics can be suppressed.
図１Ａ及び図１Ｂは、この発明の実施の形態１による可変利得増幅器の構成図である。1A and 1B are configuration diagrams of a variable gain amplifier according to Embodiment 1 of the present invention. この発明の実施の形態１の可変利得増幅器のレイアウトイメージを示す説明図である。It is explanatory drawing which shows the layout image of the variable gain amplifier of Embodiment 1 of this invention. この発明の実施の形態１の可変利得増幅器におけるインピーダンス変成器の一例を示す斜視図である。It is a perspective view which shows an example of the impedance transformer in the variable gain amplifier of Embodiment 1 of this invention. この発明の実施の形態２の可変利得増幅器におけるインピーダンス変成の軌跡をスミスチャートを用いて示す説明図である。It is explanatory drawing which shows the locus | trajectory of impedance transformation in the variable gain amplifier of Embodiment 2 of this invention using a Smith chart.
　以下、この発明をより詳細に説明するために、この発明を実施するための形態について、添付の図面に従って説明する。
実施の形態１．
　図１Ａ及び図１Ｂは、本実施の形態による可変利得増幅器の構成図である。
　本実施の形態による可変利得増幅器は、図示のように、カレントステアリング型の可変利得増幅器である。単位セル回路１００ａ～１００ｎは複数個並列に接続されており、個数はＮ個とする。単位セル回路１００ａ～１００ｎは、それぞれ第１のトランジスタ１０１、第２のトランジスタ１０２、スイッチ用トランジスタ１０３、インピーダンス変成器１０４を備えている。 Hereinafter, in order to explain the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.
Embodiment 1 FIG.
1A and 1B are configuration diagrams of a variable gain amplifier according to the present embodiment.
The variable gain amplifier according to the present embodiment is a current steering type variable gain amplifier as shown in the figure. A plurality of unit cell circuits 100a to 100n are connected in parallel, and the number is N. Each of the unit cell circuits 100a to 100n includes a first transistor 101, a second transistor 102, a switching transistor 103, and an impedance transformer 104.
　第１のトランジスタ１０１と第２のトランジスタ１０２のエミッタは、単位セル回路１００ａ～１００ｎのエミッタ入力端子１０５ａ～１０５ｎに接続されている。第１のトランジスタ１０１のコレクタは、単位セル回路１００ａ～１００ｎのコレクタ出力端子１０６ａ～１０６ｎに接続されている。第２のトランジスタ１０２のコレクタは電源に接続されている。第１のトランジスタ１０１及び第２のトランジスタ１０２のベースは、それぞれインピーダンス変成器１０４を介して、ＮＭＯＳトランジスタからなるスイッチ用トランジスタ１０３のドレイン端子に接続されている。 The emitters of the first transistor 101 and the second transistor 102 are connected to the emitter input terminals 105a to 105n of the unit cell circuits 100a to 100n. The collector of the first transistor 101 is connected to the collector output terminals 106a to 106n of the unit cell circuits 100a to 100n. The collector of the second transistor 102 is connected to the power source. The bases of the first transistor 101 and the second transistor 102 are connected to the drain terminal of a switching transistor 103 made of an NMOS transistor via an impedance transformer 104, respectively.
　スイッチ用トランジスタ１０３のソースは、単位セル回路１００ａ～１００ｎのベースバイアス端子１０７ａ～１０７ｎに接続されている。スイッチ用トランジスタ１０３のゲートは、単位セル回路１００ａ～１００ｎにおける第１の利得制御用端子１０８ａ～１０８ｎ及び第２の利得制御用端子１０９ａ～１０９ｎに接続されている。単位セル回路１００ａ～１００ｎのエミッタ入力端子１０５ａ～１０５ｎは、トランジスタ１１０のソースに接続されている。トランジスタ１１０のドレインは接地され、ゲートは電圧入力端子１１１に接続されている。単位セル回路１００ａ～１００ｎのコレクタ出力端子１０６ａ～１０６ｎは、負荷インダクタンス１１２を介して電源に接続されていると共に、出力端子１１３に接続されている。 The source of the switching transistor 103 is connected to the base bias terminals 107a to 107n of the unit cell circuits 100a to 100n. The gate of the switching transistor 103 is connected to the first gain control terminals 108a to 108n and the second gain control terminals 109a to 109n in the unit cell circuits 100a to 100n. The emitter input terminals 105a to 105n of the unit cell circuits 100a to 100n are connected to the source of the transistor 110. The drain of the transistor 110 is grounded, and the gate is connected to the voltage input terminal 111. The collector output terminals 106a to 106n of the unit cell circuits 100a to 100n are connected to the power supply via the load inductance 112 and also to the output terminal 113.
　図１Ｂは制御回路部１１４を示している。制御回路部１１４はベース電流源１１５とロジック生成回路１１６を備える。ベース電流源１１５は、ベースバイアス端子１０７ａ～１０７ｎを介して、第１のトランジスタ１０１及び第２のトランジスタ１０２のベース電流を供給するための電源である。ロジック生成回路１１６は、可変利得増幅器としての利得を制御するための制御信号を生成する回路であり、第１の利得制御用端子１０８ａ～１０８ｎ及び第２の利得制御用端子１０９ａ～１０９ｎを介してのスイッチ用トランジスタ１０３の制御を行うよう構成されている。 FIG. 1B shows the control circuit unit 114. The control circuit unit 114 includes a base current source 115 and a logic generation circuit 116. The base current source 115 is a power source for supplying base currents of the first transistor 101 and the second transistor 102 via the base bias terminals 107a to 107n. The logic generation circuit 116 is a circuit that generates a control signal for controlling the gain as the variable gain amplifier, and is connected via the first gain control terminals 108a to 108n and the second gain control terminals 109a to 109n. The switch transistor 103 is controlled.
　このように構成された可変利得増幅器において、第１のトランジスタ１０１及び第２のトランジスタ１０２のベースからベースバイアス端子１０７ａ～１０７ｎ側を見たときのインピーダンスは、制御回路部１１４内のベース電流源１１５のインピーダンスと、スイッチ用トランジスタ１０３のオン抵抗と、インピーダンス変成器１０４によって決定される。一般に電流源として機能する回路の出力インピーダンスは高く、ベース電流源１１５の出力インピーダンスは高く、さらにＮＭＯＳトランジスタのオン抵抗もトランジスタサイズにもよるが数十Ωから数百Ωと有限の抵抗値を有する。従って、インピーダンス変成器１０４の特性インピーダンスをこれらの合成インピーダンスよりも十分に低い値に設計することで、第１のトランジスタ１０１及び第２のトランジスタ１０２のベースからベースバイアス端子１０７ａ～１０７ｎ側を見た時のインピーダンスをショート点付近にインピーダンス変成することができる。結果として、第１のトランジスタ１０１及び第２のトランジスタ１０２がカスコード回路として動作することが可能となり、エミッタ入力端子１０５ａ～１０５ｎからコレクタ出力端子１０６ａ～１０６ｎへの電流利得を高い値に保つことができる。 In the variable gain amplifier configured as described above, the impedance when the base bias terminals 107a to 107n are viewed from the bases of the first transistor 101 and the second transistor 102 is the base current source 115 in the control circuit unit 114. , The on-resistance of the switching transistor 103, and the impedance transformer 104. Generally, the output impedance of a circuit that functions as a current source is high, the output impedance of the base current source 115 is high, and the on-resistance of the NMOS transistor also has a finite resistance value of several tens to several hundreds Ω depending on the transistor size. . Accordingly, by designing the characteristic impedance of the impedance transformer 104 to a value sufficiently lower than these combined impedances, the base bias terminals 107a to 107n are viewed from the bases of the first transistor 101 and the second transistor 102. The impedance at the time can be transformed near the short point. As a result, the first transistor 101 and the second transistor 102 can operate as a cascode circuit, and the current gain from the emitter input terminals 105a to 105n to the collector output terminals 106a to 106n can be maintained at a high value. .
　次に、実施の形態１の動作について説明する。
　電圧入力端子１１１からの入力信号は、トランジスタ１１０により電流信号１１７に変換される。電流信号１１７はＮ分配されて、単位セル回路１００ａ～１００ｎのエミッタ入力端子１０５ａ～１０５ｎに入力される。それぞれの単位セル回路１００ａ～１００ｎは、制御回路部１１４からの第１の利得制御用端子１０８ａ～１０８ｎ及び第２の利得制御用端子１０９ａ～１０９ｎの制御及びベースバイアス端子１０７ａ～１０７ｎへの電源供給によって、電流信号１１７が出力端子１１３へと伝わる電流量を制御することで、利得が制御される。 Next, the operation of the first embodiment will be described.
An input signal from the voltage input terminal 111 is converted into a current signal 117 by the transistor 110. The current signal 117 is distributed N and is input to the emitter input terminals 105a to 105n of the unit cell circuits 100a to 100n. Each of the unit cell circuits 100a to 100n controls the first gain control terminals 108a to 108n and the second gain control terminals 109a to 109n from the control circuit unit 114 and supplies power to the base bias terminals 107a to 107n. Thus, the gain is controlled by controlling the amount of current transmitted to the output terminal 113 by the current signal 117.
　制御回路部１１４は、ベース電流源１１５によって、第１のトランジスタ１０１及び第２のトランジスタ１０２のベースをバイアスするための基準電流を生成し、ベースバイアス端子１０７ａ～１０７ｎ及びスイッチ用トランジスタ１０３を介して電源を供給する。
　Ｎ個の単位セル回路１００ａ～１００ｎは、第１の利得制御用端子１０８ａ～１０８ｎと第２の利得制御用端子１０９ａ～１０９ｎとに与えられる制御回路部１１４からの制御信号によってスイッチ用トランジスタ１０３のオンオフが制御される。これにより、第１のトランジスタ１０１導通状態と第２のトランジスタ１０２の遮断状態が制御され、エミッタ入力端子１０５ａ～１０５ｎからの電流を電源に逃がすか、出力端子１１３へと伝えるかの二つの動作が可能である。例えば、単位セル回路１００ａ～１００ｎのうちで、Ｎsel個だけを出力端子１１３に伝わるよう制御し、残りは電流を電源に逃がすように制御した場合の電流利得Ｇは下式の通りとなる。
　　Ｇ＝Ｎsel／Ｎ The control circuit unit 114 generates a reference current for biasing the bases of the first transistor 101 and the second transistor 102 by the base current source 115, and passes through the base bias terminals 107 a to 107 n and the switching transistor 103. Supply power.
The N unit cell circuits 100a to 100n are connected to the switching transistor 103 by a control signal from the control circuit unit 114 supplied to the first gain control terminals 108a to 108n and the second gain control terminals 109a to 109n. ON / OFF is controlled. As a result, the conduction state of the first transistor 101 and the cutoff state of the second transistor 102 are controlled, and the two operations of releasing the current from the emitter input terminals 105a to 105n to the power source or transmitting the current to the output terminal 113 are performed. Is possible. For example, among the unit cell circuits 100a to 100n, control is performed so that only Nsel is transmitted to the output terminal 113, and the remainder is controlled so as to release current to the power supply, and the current gain G is expressed by the following equation.
G = Nsel / N
　本構成は、半導体デバイスとして実現するために回路図をマスクパターンへとレイアウト設計する際に、従来の回路よりも優れた効果を有している。図２に、実施の形態１の可変利得増幅器のレイアウトイメージを示す。図１中の単位セル回路１００ａ～１００ｎ中の要素回路を、高周波信号用ブロック２０４とバイアス用ブロック２０５に分割して、Ｎ個アレイ状に配置し、これら二つのブロックをインピーダンス変成用の伝送線路２０３により接続している。レイアウト群２０１がＮ個の高周波信号用ブロック２０４であり、レイアウト群２０２がＮ個のバイアス用ブロック２０５を示している。伝送線路２０３は、図１Ａ中のインピーダンス変成器１０４であり、所望周波数における１／４波長の伝送線路として実装されている。高周波信号用ブロック２０４は、図１中の第１のトランジスタ１０１及び第２のトランジスタ１０２が含まれ、高周波信号を通す回路のみが分離された構成である。バイアス用ブロック２０５にはスイッチ用トランジスタ１０３が含まれる。 This configuration has an effect superior to that of a conventional circuit when designing a layout of a circuit diagram into a mask pattern for realization as a semiconductor device. FIG. 2 shows a layout image of the variable gain amplifier according to the first embodiment. The element circuits in the unit cell circuits 100a to 100n in FIG. 1 are divided into a high-frequency signal block 204 and a bias block 205 and arranged in an N-array, and these two blocks are used as impedance transformation transmission lines. 203 is connected. The layout group 201 is N high frequency signal blocks 204, and the layout group 202 is N bias blocks 205. The transmission line 203 is the impedance transformer 104 in FIG. 1A, and is mounted as a 1/4 wavelength transmission line at a desired frequency. The high-frequency signal block 204 includes the first transistor 101 and the second transistor 102 in FIG. 1, and has a configuration in which only a circuit that passes a high-frequency signal is separated. The bias block 205 includes a switch transistor 103.
　インピーダンス変成器１０４は、所望周波数における１／４波長の伝送線路２０３であって、物理的な長さを有する。この長さを利用することでバイアス用ブロック２０５を高周波信号用ブロック２０４から距離を離して配置することができる。また、バイアス用ブロック２０５は低周波信号であるバイアス電流を正確に伝えることさえできれば、レイアウトによる寄生容量やインダクタンスに対する特性変化の感度は低い。従って、高周波信号経路に影響を与えないような、チップ面積の余った任意の領域に配置することができて、チップ面積の有効活用を可能とする。 The impedance transformer 104 is a 1/4 wavelength transmission line 203 at a desired frequency and has a physical length. By using this length, the bias block 205 can be arranged at a distance from the high-frequency signal block 204. In addition, as long as the bias block 205 can accurately transmit a bias current, which is a low-frequency signal, the sensitivity of characteristic changes to parasitic capacitance and inductance due to layout is low. Therefore, the chip area can be arranged in an arbitrary area that does not affect the high-frequency signal path, and the chip area can be effectively used.
　もっとも大きな効果は、高周波信号用ブロック２０４を、密集してレイアウトできる点にある。高周波信号用ブロック２０４はＮ個まとめて配置されたレイアウト群２０１となり、図１中のエミッタ入力端子１０５ａ～１０５ｎとコレクタ出力端子１０６ａ～１０６ｎの配線面積を小さくして、寄生の容量やインダクタンスを小さくすることを可能にする。これらの端子の寄生成分を抑えることで、高周波特性を最適化するインピーダンスへの整合を容易にするため、高利得化や広帯域化、低雑音化といった高周波性能の改善効果が得られる。 The greatest effect is that the high-frequency signal block 204 can be densely laid out. The high-frequency signal block 204 is a group of layouts 201 arranged together, and the wiring area of the emitter input terminals 105a to 105n and the collector output terminals 106a to 106n in FIG. 1 is reduced to reduce parasitic capacitance and inductance. Make it possible to do. By suppressing the parasitic components of these terminals, matching with impedance that optimizes high-frequency characteristics is facilitated, so that high-frequency performance improvement effects such as higher gain, wider bandwidth, and lower noise can be obtained.
　図３には、インピーダンス変成器１０４の一例として、図２に示した伝送線路２０３のマイクロストリップ線路方式での実現例を示す。本発明の回路構成では、インピーダンス変成器１０４（伝送線路２０３）の特性インピーダンスは低い方が望ましく、多層配線を容易に実現可能なシリコンプロセスとの相性が良い。伝送線路３０１ａ，…，３０１ｍ、３０１ｎと、グランド層３０２との距離を近づけることで線路幅の短い伝送線路を実現でき、レイアウト群２０１をさらに小型化することもできる。伝送線路のパターンは、高周波用ブロックからなるレイアウト群３０３（図２中のレイアウト群２０１）とバイアス用ブロックからなるレイアウト群３０４（図２中のレイアウト群２０２）を接続して、高周波特性を最適化するようなインピーダンス変成を実現している。 FIG. 3 shows an implementation example of the transmission line 203 shown in FIG. 2 in the microstrip line system as an example of the impedance transformer 104. In the circuit configuration of the present invention, the impedance transformer 104 (transmission line 203) desirably has a low characteristic impedance, and is compatible with a silicon process that can easily realize multilayer wiring. By shortening the distance between the transmission lines 301a,..., 301m, 301n and the ground layer 302, a transmission line with a short line width can be realized, and the layout group 201 can be further downsized. For the transmission line pattern, the layout group 303 (layout group 201 in FIG. 2) composed of high frequency blocks and the layout group 304 (layout group 202 in FIG. 2) composed of bias blocks are connected to optimize the high frequency characteristics. Impedance transformation is realized.
　なお、図２及び図３に示したレイアウト例は、本実施の形態の可変利得増幅器の回路構成をレイアウト設計する場合の一例であって、例えば図２に示したような１次元のアレイ配置に限定するものではない。２次元のアレイ配置でも同様に有効である。アレイ配置の決め方は、高周波信号の経路につく寄生成分を最小化することや、チップ面積の有効活用観点や、高周波信号用ブロック２０４のトランジスタのパラメータなどによって最適化されるべき設計事項の一つである。 The layout example shown in FIGS. 2 and 3 is an example of layout design of the circuit configuration of the variable gain amplifier according to the present embodiment. For example, the layout example shown in FIG. 2 has a one-dimensional array arrangement. It is not limited. The same applies to a two-dimensional array arrangement. The method of determining the array arrangement is one of the design items that should be optimized by minimizing the parasitic components on the path of the high-frequency signal, effectively using the chip area, and the parameters of the transistors of the high-frequency signal block 204. It is.
　また、説明を簡略化するために、図１中のベース電流源１１５やスイッチ用トランジスタ１０３のインピーダンスを純粋な抵抗性として説明し、理想的な１／４波長線路によるインピーダンス変成器１０４を用いて説明した。しかしながら、厳密には寄生の容量やインダクタンスによるリアクタンス成分が必ず存在し、これらのリアクタンス成分を含めた上で、第１のトランジスタ１０１及び第２のトランジスタ１０２のベースから見たインピーダンスをショート点に近づけるインピーダンス変成器１０４の調整（例えば線路長の調整）が設計事項の一つであることは言うまでもない。 In order to simplify the description, the impedance of the base current source 115 and the switching transistor 103 in FIG. 1 will be described as pure resistance, and an impedance transformer 104 using an ideal quarter wavelength line will be used. explained. However, strictly speaking, reactance components due to parasitic capacitance and inductance always exist, and after including these reactance components, the impedance viewed from the bases of the first transistor 101 and the second transistor 102 is brought close to the short point. Needless to say, adjustment of the impedance transformer 104 (for example, adjustment of the line length) is one of the design matters.
　なお、上記例では、高周波用ブロックに用いる第１のトランジスタ１０１及び第２のトランジスタ１０２に対して、バイポーラトランジスタを用いた場合について説明したが、これらのトランジスタとして電界効果トランジスタを用いても、高周波特性の改善効果は得られる。電界効果トランジスタを用いた場合は、ゲート接地型となり、ゲートとスイッチ用トランジスタ１０３との間にインピーダンス変成器１０４を配設することになる。 In the above example, the case where bipolar transistors are used for the first transistor 101 and the second transistor 102 used in the high frequency block has been described. However, even if field effect transistors are used as these transistors, the high frequency is used. The effect of improving the characteristics can be obtained. When a field effect transistor is used, the gate grounding type is used, and the impedance transformer 104 is disposed between the gate and the switching transistor 103.
　以上説明したように、実施の形態１の可変利得増幅器によれば、ベース接地型の第１のトランジスタと第２のトランジスタを含み、入力端子からの信号を第１のトランジスタを介して出力端子へ導通させる導通状態と、入力端子からの信号を第２のトランジスタを介して出力端子以外の端子に逃がす遮断状態を実現し、第１及び第２のトランジスタのそれぞれのベースを制御する第１の利得制御用端子と第２の利得制御用端子とを有する単位セル回路を複数備えると共に、複数の単位セル回路の入力端子と出力端子とを並列接続し、かつ、第１及び第２の利得制御用端子に接続され、単位セル回路毎に、導通状態か遮断状態のいずれかを設定する制御回路部と、第１及び第２のトランジスタのベースと第１及び第２の利得制御用端子の間に設けられ、制御回路部の設定により、導通状態と遮断状態を実現するスイッチ回路と、第１及び第２のトランジスタのベースから第１及び第２の利得制御用端子側を見たインピーダンスを設定値とするインピーダンス変成器とを備えたので、第１のトランジスタ及び第２のトランジスタのベースからベースバイアス端子側を見た時のインピーダンスをショート点付近にインピーダンス変成することができ、高周波特性の劣化を抑えることができる。 As described above, according to the variable gain amplifier of the first embodiment, the base-grounded first transistor and the second transistor are included, and the signal from the input terminal is output to the output terminal via the first transistor. A first gain for controlling a base of each of the first and second transistors by realizing a conduction state for conducting and a cutoff state for allowing a signal from the input terminal to escape to a terminal other than the output terminal through the second transistor. A plurality of unit cell circuits each having a control terminal and a second gain control terminal are provided, input terminals and output terminals of the plurality of unit cell circuits are connected in parallel, and the first and second gain control terminals are provided. A control circuit unit that is connected to a terminal and sets a conduction state or a cutoff state for each unit cell circuit, and between the bases of the first and second transistors and the first and second gain control terminals. The switch circuit that realizes the conduction state and the cutoff state by the setting of the control circuit unit, and the impedance when the first and second gain control terminal sides are viewed from the bases of the first and second transistors are set values. The impedance transformer when the base bias terminal side is viewed from the base of the first transistor and the second transistor can be impedance-transformed near the short point, and the high frequency characteristics are deteriorated. Can be suppressed.
　また、実施の形態１の可変利得増幅器によれば、インピーダンス変成器は、スイッチ回路のインピーダンスと制御回路部のインピーダンスを合計したインピーダンスよりも、小さい値の特性インピーダンスを有し、設定された動作周波数における波長の１／４の線路長を有するようにしたので、半導体デバイスとして実現する場合にチップ面積を有効活用することができる。 Further, according to the variable gain amplifier of the first embodiment, the impedance transformer has a characteristic impedance that is smaller than the total impedance of the switch circuit impedance and the control circuit unit impedance, and has a set operating frequency. In this case, the chip area can be effectively used when the semiconductor device is realized.
　また、実施の形態１の可変利得増幅器によれば、ゲート接地型の第１の電界効果トランジスタと第２の電界効果トランジスタを含み、入力端子からの信号を第１の電界効果トランジスタを介して出力端子へ導通させる導通状態と、入力端子からの信号を第２の電界効果トランジスタを介して出力端子以外の端子に逃がす遮断状態を実現し、第１及び第２の電界効果トランジスタのそれぞれのゲートを制御する第１の利得制御用端子と第２の利得制御用端子とを有する単位セル回路を複数備えると共に、複数の単位セル回路の入力端子と出力端子とを並列接続し、かつ、第１及び第２の利得制御用端子に接続され、単位セル回路毎に、導通状態か遮断状態のいずれかを設定する制御回路部と、第１及び第２の電界効果トランジスタのゲートと第１及び第２の利得制御用端子の間に設けられ、制御回路部の設定により、導通状態と遮断状態を実現するスイッチ回路と、第１及び第２の電界効果トランジスタのゲートから第１及び第２の利得制御用端子側を見たインピーダンスを設定値とするインピーダンス変成器とを備えたので、第１の電界効果トランジスタ及び第２の電界効果トランジスタのベースからベースバイアス端子側を見た時のインピーダンスをショート点付近にインピーダンス変成することができ、高周波特性の劣化を抑えることができる。 In addition, the variable gain amplifier according to the first embodiment includes a grounded-gate first field effect transistor and a second field effect transistor, and outputs a signal from the input terminal via the first field effect transistor. A conduction state for conducting to the terminal, and a blocking state for releasing a signal from the input terminal to a terminal other than the output terminal via the second field effect transistor, and the gates of the first and second field effect transistors are connected to each other. A plurality of unit cell circuits each having a first gain control terminal and a second gain control terminal to be controlled; the input terminals and the output terminals of the plurality of unit cell circuits are connected in parallel; and A control circuit unit which is connected to the second gain control terminal and sets either a conduction state or a cutoff state for each unit cell circuit; and gates of the first and second field effect transistors; A switching circuit that is provided between the first and second gain control terminals and realizes a conductive state and a cut-off state according to the setting of the control circuit unit, and the first and second gates of the first and second field effect transistors And an impedance transformer whose setting value is an impedance when the gain control terminal side is viewed from the base of the first field effect transistor and the second field effect transistor. Impedance can be transformed near the short point, and deterioration of high frequency characteristics can be suppressed.
実施の形態２．
　図３に示したように、インピーダンス変成器を伝送線路として実現した場合、その特性インピーダンスを十分に低い値となるようにレイアウト設計することで、本構成の効果を大きくすることができる。具体的には、図１中のベース電流源１１５のインピーダンスをＲ１［ｏｈｍ］とし、スイッチ用トランジスタ１０３のオン抵抗をＲ２［ｏｈｍ］、伝送線路３０１ａ～３０１ｎ（インピーダンス変成器１０４）の特性インピーダンスをＺｏ［ｏｈｍ］とした場合に、以下の関係を満たすことが望ましい。
　　Ｚｏ＜＜（Ｒ１＋Ｒ２）
　図４は、インピーダンス変成の軌跡をスミスチャートを用いて示す説明図である。図では、第１のトランジスタ１０１及び第２のトランジスタ１０２のベースから制御回路部１１４側を見たインピーダンス４０１、ベースバイアス端子１０７ａ～１０７ｎから制御回路部１１４側を見たインピーダンス４０２、及びインピーダンス変成器１０４によるスミスチャート上の軌跡４０３を図示している。 Embodiment 2. FIG.
As shown in FIG. 3, when the impedance transformer is realized as a transmission line, the effect of this configuration can be increased by designing the layout so that the characteristic impedance becomes a sufficiently low value. Specifically, the impedance of the base current source 115 in FIG. 1 is R1 [ohm], the on-resistance of the switching transistor 103 is R2 [ohm], and the characteristic impedance of the transmission lines 301a to 301n (impedance transformer 104) is In the case of Zo [ohm], it is desirable to satisfy the following relationship.
Zo << (R1 + R2)
FIG. 4 is an explanatory diagram showing the impedance transformation locus using a Smith chart. In the figure, an impedance 401 when the control circuit unit 114 is viewed from the bases of the first transistor 101 and the second transistor 102, an impedance 402 when the control circuit unit 114 is viewed from the base bias terminals 107a to 107n, and an impedance transformer. A locus 403 on the Smith chart according to 104 is shown.
　なお、本願発明はその発明の範囲内において、各実施の形態の自由な組み合わせ、あるいは各実施の形態の任意の構成要素の変形、もしくは各実施の形態において任意の構成要素の省略が可能である。 In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .
　以上のように、この発明に係る可変利得増幅器は、複数の単位セル回路毎に導通状態と遮断状態とを制御することで利得を変更可能とする構成に関するものであり、無線受信機などに用いるのに適している。 As described above, the variable gain amplifier according to the present invention relates to a configuration in which the gain can be changed by controlling the conduction state and the cutoff state for each of the plurality of unit cell circuits, and is used for a radio receiver or the like. Suitable for
　１００ａ～１００ｎ　単位セル回路、１０１　第１のトランジスタ、１０２　第２のトランジスタ、１０３　スイッチ用トランジスタ、１０４　インピーダンス変成器、１０５ａ～１０５ｎ　エミッタ入力端子、１０６ａ～１０６ｎ　コレクタ出力端子、１０７ａ～１０７ｎ　ベースバイアス端子、１０８ａ～１０８ｎ　第１の利得制御用端子、１０９ａ～１０９ｎ　第２の利得制御用端子、１１０　トランジスタ、１１１　電圧入力端子、１１２　負荷インダクタンス、１１３　出力端子、１１４　制御回路部、１１５　ベース電流源、１１６　ロジック生成回路、１１７　電流信号、２０１，２０２　レイアウト群、２０３，３０１ａ～３０１ｎ　伝送線路、２０４　高周波信号用ブロック、２０５　バイアス用ブロック、３０２　グランド層、３０３，３０４　レイアウト群。 100a to 100n unit cell circuit, 101 first transistor, 102 second transistor, 103 switch transistor, 104 impedance transformer, 105a to 105n emitter input terminal, 106a to 106n collector output terminal, 107a to 107n base bias terminal, 108a to 108n, first gain control terminal, 109a to 109n, second gain control terminal, 110 transistor, 111 voltage input terminal, 112 load inductance, 113 output terminal, 114 control circuit section, 115 base current source, 116 logic Generator circuit, 117 current signal, 201, 202 layout group, 203, 301a to 301n transmission line, 204 high frequency signal block, 205 bias block, 302 group Command layer, 303 and 304 layout group.

Claims (3)

  1. 　ベース接地型の第１のトランジスタと第２のトランジスタを含み、入力端子からの信号を前記第１のトランジスタを介して出力端子へ導通させる導通状態と、前記入力端子からの信号を前記第２のトランジスタを介して前記出力端子以外の端子に逃がす遮断状態を実現し、前記第１及び第２のトランジスタのそれぞれのベースを制御する第１の利得制御用端子と第２の利得制御用端子とを有する単位セル回路を複数備えると共に、当該複数の単位セル回路の前記入力端子と前記出力端子とを並列接続し、かつ、
    　前記第１及び第２の利得制御用端子に接続され、前記単位セル回路毎に、前記導通状態か前記遮断状態のいずれかを設定する制御回路部と、
    　前記第１及び第２のトランジスタの前記ベースと前記第１及び第２の利得制御用端子の間に設けられ、前記制御回路部の設定により、前記導通状態と前記遮断状態を実現するスイッチ回路と、
    　前記第１及び第２のトランジスタの前記ベースから前記第１及び第２の利得制御用端子側を見たインピーダンスを設定値とするインピーダンス変成器とを備えたことを特徴とする可変利得増幅器。     A grounded base type first transistor and a second transistor, a conduction state for conducting a signal from an input terminal to the output terminal via the first transistor; and a signal from the input terminal for the second A first gain control terminal and a second gain control terminal for controlling a base of each of the first and second transistors by realizing a cut-off state that escapes to a terminal other than the output terminal through a transistor. A plurality of unit cell circuits, and the input terminals and the output terminals of the plurality of unit cell circuits connected in parallel; and
    A control circuit unit which is connected to the first and second gain control terminals and sets either the conduction state or the cutoff state for each unit cell circuit;
    A switch circuit provided between the bases of the first and second transistors and the first and second gain control terminals, and configured to realize the conduction state and the cutoff state according to the setting of the control circuit unit; ,
    A variable gain amplifier comprising: an impedance transformer having a set value as an impedance when the first and second gain control terminals are viewed from the bases of the first and second transistors.
  2. 　前記インピーダンス変成器は、前記スイッチ回路のインピーダンスと前記制御回路部のインピーダンスを合計したインピーダンスよりも、小さい値の特性インピーダンスを有し、設定された動作周波数における波長の１／４の線路長を有することを特徴とする請求項１記載の可変利得増幅器。 The impedance transformer has a characteristic impedance that is smaller than the total impedance of the switch circuit and the control circuit, and has a line length that is ¼ of the wavelength at the set operating frequency. The variable gain amplifier according to claim 1.
  3. 　ゲート接地型の第１の電界効果トランジスタと第２の電界効果トランジスタを含み、入力端子からの信号を前記第１の電界効果トランジスタを介して出力端子へ導通させる導通状態と、前記入力端子からの信号を前記第２の電界効果トランジスタを介して前記出力端子以外の端子に逃がす遮断状態を実現し、前記第１及び第２の電界効果トランジスタのそれぞれのゲートを制御する第１の利得制御用端子と第２の利得制御用端子とを有する単位セル回路を複数備えると共に、当該複数の単位セル回路の前記入力端子と前記出力端子とを並列接続し、かつ、
    　前記第１及び第２の利得制御用端子に接続され、前記単位セル回路毎に、前記導通状態か前記遮断状態のいずれかを設定する制御回路部と、
    　前記第１及び第２の電界効果トランジスタの前記ゲートと前記第１及び第２の利得制御用端子の間に設けられ、前記制御回路部の設定により、前記導通状態と前記遮断状態を実現するスイッチ回路と、
    　前記第１及び第２の電界効果トランジスタの前記ゲートから前記第１及び第２の利得制御用端子側を見たインピーダンスを設定値とするインピーダンス変成器とを備えたことを特徴とする可変利得増幅器。     A grounded gate type first field effect transistor and a second field effect transistor, a conduction state for conducting a signal from the input terminal to the output terminal via the first field effect transistor; A first gain control terminal for controlling a gate of each of the first and second field effect transistors by realizing a cut-off state in which a signal is released to a terminal other than the output terminal via the second field effect transistor. And a plurality of unit cell circuits each having a second gain control terminal, the input terminal and the output terminal of the plurality of unit cell circuits are connected in parallel, and
    A control circuit unit which is connected to the first and second gain control terminals and sets either the conduction state or the cutoff state for each unit cell circuit;
    A switch that is provided between the gates of the first and second field effect transistors and the first and second gain control terminals, and realizes the conduction state and the cutoff state by setting the control circuit unit. Circuit,
    A variable gain amplifier comprising: an impedance transformer having a set value as an impedance when the first and second gain control terminals are viewed from the gates of the first and second field effect transistors. .
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002359530A (en) * 2001-03-28 2002-12-13 Sharp Corp High-frequency amplifier
JP2003188665A (en) * 2002-10-29 2003-07-04 Mitsubishi Electric Corp Microwave high-power amplifier
JP2007259297A (en) * 2006-03-24 2007-10-04 Sharp Corp Variable gain amplifier and communication equipment provided with the variable gain amplifier
US20120056681A1 (en) * 2010-09-06 2012-03-08 Chih-Hung Lee Signal amplification circuits for receiving/transmitting signals according to input signal
JP2013183412A (en) * 2012-03-05 2013-09-12 Renesas Electronics Corp High frequency amplifier

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002359530A (en) * 2001-03-28 2002-12-13 Sharp Corp High-frequency amplifier
JP2003188665A (en) * 2002-10-29 2003-07-04 Mitsubishi Electric Corp Microwave high-power amplifier
JP2007259297A (en) * 2006-03-24 2007-10-04 Sharp Corp Variable gain amplifier and communication equipment provided with the variable gain amplifier
US20120056681A1 (en) * 2010-09-06 2012-03-08 Chih-Hung Lee Signal amplification circuits for receiving/transmitting signals according to input signal
JP2013183412A (en) * 2012-03-05 2013-09-12 Renesas Electronics Corp High frequency amplifier

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