WO2018133409A1 - 一种电源管理电路、电子设备及电子设备控制方法 - Google Patents

一种电源管理电路、电子设备及电子设备控制方法 Download PDF

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Publication number
WO2018133409A1
WO2018133409A1 PCT/CN2017/098602 CN2017098602W WO2018133409A1 WO 2018133409 A1 WO2018133409 A1 WO 2018133409A1 CN 2017098602 W CN2017098602 W CN 2017098602W WO 2018133409 A1 WO2018133409 A1 WO 2018133409A1
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Prior art keywords
power
pin
power management
interface
type
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PCT/CN2017/098602
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English (en)
French (fr)
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刘海强
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深圳市金立通信设备有限公司
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Publication of WO2018133409A1 publication Critical patent/WO2018133409A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection

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  • the present invention relates to the field of power management technologies, and in particular, to a power management circuit, an electronic device, and an electronic device control method.
  • the power management circuit of the electronic device generally includes a power management chip and an interface detection chip for connecting to the TYPE_C interface.
  • the power management chip detects the power input and controls the electronic device to be powered on.
  • the power management chip may be triggered, causing the electronic device to be powered on.
  • the embodiment of the invention provides a power management circuit, an electronic device and an electronic device control method, which solves the problem that the electronic device is accidentally turned on when the TYPE_C cable of the unconnected power device is inserted into the interface detection chip.
  • Embodiments of the present invention provide a power management circuit including a TYPE_C interface, an interface detection chip, a power management chip, and a potential pull-down circuit.
  • the interface detection chip includes a power detection pin
  • the TYPE_C interface includes a power pin electrically connected to the power management chip, the power pin is electrically connected to the power detection pin and forms a node, and the potential pull-down circuit is electrically connected to the node. Between the power detection pin and the power supply.
  • Embodiments of the present invention also provide an electronic device including a power management circuit.
  • the power management circuit is as described above.
  • An embodiment of the present invention provides a method for controlling an electronic device, including:
  • the TYPE_C device When the electronic device is in the power-off state, the TYPE_C device is inserted through the TYPE_C interface, and the TYPE_C interface includes a power pin electrically connected to the power management chip, and the power pin is electrically connected to the power detection pin and forms a node;
  • the detection voltage is pulled down by the potential pull-down circuit, and the potential pull-down circuit is electrically connected between the power detection pin and the node.
  • the embodiment of the invention includes a potential pull-down circuit.
  • the potential pull-down circuit can pull down the voltage input to the power management chip, which is far lower than the triggering power-on voltage of the power management chip. , solved the problem of misbooting.
  • FIG. 1 is a block diagram showing the structure of a power management circuit according to a first embodiment of the present invention
  • Figure 2 is a circuit diagram of Figure 1;
  • Figure 3 is a schematic diagram of a circuit that causes a false boot
  • FIG. 4 is a circuit diagram of a power management circuit according to a second embodiment of the present invention.
  • FIG. 5 is a schematic flowchart of a method for controlling an electronic device according to a first embodiment of the present invention
  • FIG. 6 is a schematic flow chart of a method for controlling an electronic device according to a second embodiment of the present invention.
  • the term “if” can be interpreted as “when” or “on” or “in response to determining” or “in response to detecting” depending on the context. .
  • the phrase “if determined” or “if detected [condition or event described]” may be interpreted in context to mean “once determined” or “in response to determining” or “once detected [condition or event described] ] or “in response to detecting [conditions or events described]”.
  • FIG. 1 is a structural block diagram of a power management circuit according to a first embodiment of the present invention.
  • the power management circuit is applied to an electronic device such as a mobile terminal.
  • the power management circuit can include:
  • a filter circuit 10 configured to connect to a power source; wherein the power source is used to provide power to the power management circuit;
  • the central processing unit 11 is configured to send a low level signal
  • TYPE_C interface 13 connected to the power management chip 12;
  • the interface detecting chip 14 is connected to the filter circuit 10, the central processing unit 11 and the connection TYPE_C interface 13;
  • the potential pull-down circuit 15 is connected to the interface detecting chip 14 and the power management chip 12 for pulling down the detection voltage input to the power management chip 12.
  • the filter circuit 10 includes a first capacitor C1 and a second capacitor C2.
  • the first capacitor C1 and the second capacitor C2 are connected in parallel, and one end connected in parallel is connected to a power source VPH_PWR for supplying power to the entire power management circuit.
  • the interface detects the chip 12, and the other end connected in parallel is grounded.
  • the TYPE_C interface 13 is electrically connected to the interface detection chip 14 and the power management chip 12, and includes a power supply pin (ie, pin 1).
  • the interface detection chip 14 includes a pin 1, a pin 2, a pin 4, a pin 10, a pin 11, and a pin 12.
  • Pin 1 and pin 2 are a first configuration channel pin CC1 and a second configuration channel pin CC2, respectively, for connecting to the TYPE_C interface 13, and the TYPE_C device passes the TYPE_C interface 13
  • the access interface detects the chip 14; the pin 4 is the power detection pin VBUSDET, and is used for electrically connecting to the power management chip 12 and the power pin of the TYPE_C interface 13 (ie, pin 1), and the pin 4 and the power management chip A resistor R1 is connected in series between 12, and further, a node A is formed between the power pin (ie, pin 1) and the power detecting pin VBUSDET; pin 10 is a ground pin GND; pin 11 is an enable pin.
  • the pin ENB is electrically connected to the central processing unit 11 to receive the low level signal sent by the central processing unit 11 to enable the interface detecting chip 14; the pin 12 is the power input pin VDD for electrically connecting to The first capacitor C1, the second capacitor C2, and the power source VPH_PWR of the filter circuit 10.
  • the potential pull-down circuit 15 is electrically connected between the node A and the power detection pin VBUSDET.
  • the potential pull-down circuit 15 includes a first resistor R1 (resistance value is 1M) and a second resistor R2 (resistance value is 20K ⁇ ).
  • One end of the first resistor R1 is connected to the node A, and the other end is connected to the power source.
  • the pin VBUSDET (and pin 4) is detected, and one end of the second resistor R2 is connected to the node A, and the other end is grounded.
  • the central processor 21 transmits a low level signal and transmits it to the interface detecting chip 24 through the enable pin (ie, pin 11) of the interface detecting chip 24 to enable the interface detecting chip 24.
  • the electronic device is automatically shut down due to power exhaustion, if the TYPE_C interface 23 is connected to the unpowered device through the TYPE_C cable (that is, the pure TYPE_C cable is inserted through the TYPE_C interface), since the pure TYPE_C cable has a default 5.1K inside.
  • Resistor R3 which is specified by the standard TYPE_C protocol), which divides the power supply VPH_PWR with the internal resistor R4 of the interface detection chip 24.
  • the internal resistor R4 has one end connected to the power input pin VDD (ie, pin 12), and the other end connected to the power detecting pin VBUSDET (ie, pin 4) and the first configuration channel pin CC1 (ie, pin 1). At this time, it is detected that the voltage at the power supply detecting pin VBUSDET (ie, pin 4) is about 0.9V. The voltage of about 0.9V will be reversed to the power management chip 22, and since the power management chip 22 triggers the voltage of the electronic device to be turned on too low, the voltage of about 0.9V triggers the power-on, which causes a false boot.
  • an embodiment of the present invention provides a potential pull-down circuit 15 as shown in FIG.
  • the output of the power detecting pin VBUSDET (ie, pin 4) of the interface detecting chip 14 is about 0.9V.
  • the voltage, after the potential pull-down circuit, will be pulled down to about 0.3V (ie, the voltage at node A is about 0.3V).
  • the voltage is input to the power management chip 12, it is much lower than the power management chip 12 triggers the power-on. Voltage (about 0.9V), which solves the problem that the power is not connected
  • the problem that the TYPE_C cable of the device is inserted into the interface detection chip causes the power to be triggered by mistake.
  • FIG. 4 is a circuit diagram of a second embodiment of the power-on detection circuit of the present invention.
  • the potential pull-down circuit 35 includes a first diode D1 in series with the first resistor R5, and the cathode of the first diode D1 is coupled to the first resistor R5.
  • the anode of the first diode D1 is connected to the node B, and the first resistor R1 is connected to the power supply detecting pin VBUSDET (ie, pin 4).
  • the on-voltage of the first diode D1 is about 0.7V.
  • the potential pull-down circuit 35 in this embodiment further includes a second resistor R6 and a second diode D2.
  • One end of the second resistor R6 is connected to the power detecting pin VBUSDET (ie, pin 4) and the first resistor R5.
  • the other end is connected to the anode of the second diode D2
  • the cathode of the second diode D2 is connected to the anode of the first diode D1
  • the cathode of the second diode D2 is connected to the anode of the first diode D1 and the node B.
  • the first resistor R5 and the first diode D1 form a first path
  • the second resistor R6 and the second diode D2 form a second path.
  • the TYPE_C device When the TYPE_C device is inserted into the interface detecting chip, the first path or the second path is turned on. .
  • the TYPE_C device includes a TYPE_C cable that is not connected to the power device and a TYPE_C cable that connects the power device.
  • the power detection pin VBUSDET ie, pin 4
  • the first resistor R5 and the first path formed by the first diode D1 are turned on, and the second resistor R6 and the second diode D2 are simultaneously turned on.
  • the formed second via is turned off by the reverse diode D2 and is non-conducting.
  • the voltage that triggers the power-on (about 0.9V) solves the problem that the TYPE_C cable that is not connected to the power device is inserted into the interface detection chip, causing a false trigger.
  • the power supply device outputs a charging voltage through the pin 1 of the TYPE_C interface, for example, a charging voltage such as 5V, 12V, etc., to the node B, and the charging voltage is output to the power management.
  • the chip 32 turns on the electronic device normally, and simultaneously turns on the second path formed by the second resistor R6 and the second diode D2, and the first path formed by the first resistor R5 and the first diode D1 is reversed diode D1 is cut off and is not conductive. Therefore, the interface detecting chip 34 can normally recognize the inserted TYPE_C device, thereby completing normal charging.
  • the component symbols, the connection relationship, and the working process of the filter circuit 30, the central processing unit 31, the power management chip 32, the TYPE_C interface 33, and the interface detection chip 34 in FIG. 4 are the same as the filter circuit 10 in FIG.
  • the central processing unit 11, the power management chip 12, the TYPE_C interface 13, and the interface detection chip 14 are similar, and are not described here.
  • an embodiment of the present invention further provides an electronic device.
  • the electronic device includes a power management circuit.
  • the electronic device includes a power management circuit.
  • the control circuit of the power management circuit controls the interface to detect that the chip is in the off state. Therefore, if the TYPE_C cable that is not connected to the power device is inserted into the interface detection chip at this time, the power management chip is not triggered to be turned on, thereby solving the problem that the TYPE_C cable inserted into the unconnected power device is turned off and the electronic device is turned on by mistake.
  • FIG. 5 it is a schematic flowchart of a method for controlling an electronic device according to a first embodiment of the present invention. As shown in the figure, the method may include:
  • the TYPE_C interface when the electronic device is in a shutdown state, receiving the insertion of the TYPE_C device through the TYPE_C interface, the TYPE_C interface includes a power pin electrically connected to the power management chip, and the power pin is electrically connected to the power detection pin and forms a node;
  • the detection voltage is pulled down by a potential pull-down circuit, and the potential pull-down circuit is electrically connected between the power detection pin and the node.
  • the method in this embodiment is implemented by using the circuit shown in FIG. 2. Therefore, for the specific working process of the method in this embodiment, refer to the foregoing description of the circuit shown in FIG. 2, and details are not described herein again.
  • the voltage input to the power management chip will be pulled down to about 0.3V, which is much lower than the power management.
  • the chip triggers the voltage of the boot (about 0.9V), which solves the problem that the TYPE_C cable that is not connected to the power device is inserted into the interface detection chip, causing the trigger to be triggered by mistake.
  • FIG. 6 is a schematic flowchart of a method for controlling an electronic device according to a second embodiment of the present invention. As shown, the method can include:
  • the TYPE_C interface when the electronic device is in a shutdown state, receiving the insertion of the TYPE_C device through the TYPE_C interface, the TYPE_C interface includes a power pin electrically connected to the power management chip, and the power pin is electrically connected to the power detection pin and forms a node;
  • the first path is turned on, the second path is turned off, and the detection voltage is pulled down by the potential pull-down circuit; when the TYPE_C cable connected to the power supply device is inserted, the conduction is performed.
  • the second path simultaneously closes the first path, and the interface detection chip performs normal recognition on the inserted TYPE_C device to complete normal charging.
  • the method in this embodiment is implemented by using the circuit shown in FIG. 2. Therefore, for the specific working process of the method in this embodiment, refer to the foregoing description of the circuit shown in FIG. 4, and details are not described herein again.
  • the voltage input to the power management chip will be pulled down to about 0.2V, which is much lower than the power management.
  • the chip triggers the voltage of the boot (about 0.9V), which solves the problem that the TYPE_C cable that is not connected to the power device is inserted into the interface detection chip, causing the trigger to be triggered by mistake.
  • the disclosed terminal and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division, and may be implemented in actual implementation. Additional ways of dividing, such as multiple units or components, may be combined or integrated into another system, or some features may be omitted or not performed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the units in the terminal in the embodiment of the present invention may be combined, divided, and deleted according to actual needs.

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Abstract

一种电源管理电路、电子设备及电子设备控制方法，电源管理电路包括TYPE_C接口(13)、接口检测芯片(14)、电源管理芯片(12)及电位下拉电路(15)。其中，接口检测芯片(14)包括电源检测引脚VBUSDET，TYPE_C接口(13)包括电性连接至电源管理芯片(12)的电源引脚，电源引脚电性连接至电源检测引脚VBUSDET并形成一节点，电位下拉电路(15)电性连接至节点与电源检测引脚VBUSDET之间。电位下拉电路(15)当未连接电源设备的TYPE_C线缆插入接口检测芯片(14)时，电位下拉电路(15)可拉低输入至电源管理芯片(12)的电压，使其远低于电源管理芯片(12)的触发开机电压，解决了误开机的问题。

Description

一种电源管理电路、电子设备及电子设备控制方法 技术领域
本发明涉及电源管理技术领域，尤其涉及一种电源管理电路、电子设备及电子设备控制方法。
背景技术
随着技术的发展，TYPE_C接口已成为高端电子设备的标配。相应地，该电子设备的电源管理电路一般包括电源管理芯片及用于连接TYPE_C接口的接口检测芯片。当电子设备由于电力耗尽自动关机后，若该TYPE_C接口通过TYPE_C线缆连接至电源设备，例如充电器或者电脑时，该电源管理芯片检测到电源输入则会控制电子设备开机。但是，若该TYPE_C线缆并未连接电源设备时，也可能会触发电源管理芯片，导致电子设备误开机。
发明内容
本发明实施例提供一种电源管理电路、电子设备及电子设备控制方法，以解决未连接电源设备的TYPE_C线缆插入接口检测芯片时导致电子设备误开机的问题
本发明实施例提供了一种电源管理电路，包括TYPE_C接口、接口检测芯片、电源管理芯片及电位下拉电路。其中，接口检测芯片包括电源检测引脚，TYPE_C接口包括电性连接至电源管理芯片的电源引脚，电源引脚电性连接至电源检测引脚并形成一节点，电位下拉电路电性连接至节点与电源检测引脚之间。
本发明实施例还提供了一种电子设备，包括电源管理电路。其中，该电源管理电路如前所述。
本发明实施例提供了一种电子设备控制方法，包括：
当电子设备处于关机状态时，通过TYPE_C接口接收TYPE_C设备的插入，TYPE_C接口包括电性连接至电源管理芯片的电源引脚，电源引脚电性连接至电源检测引脚并形成一节点；
根据TYPE_C设备的插入产生一检测电压，并通过接口检测芯片的电源检测引脚向电源管理芯片输入检测电压；
通过电位下拉电路拉低检测电压，电位下拉电路电性连接至电源检测引脚与节点之间。
本发明实施例包括电位下拉电路，当未连接电源设备的TYPE_C线缆插入接口检测芯片时，电位下拉电路可拉低输入至电源管理芯片的电压，使其远低于电源管理芯片的触发开机电压，解决了误开机的问题。
附图说明
为了更清楚地说明本发明实施例技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明第一实施例提供的电源管理电路的结构框图；
图2是图1的电路图；
图3是导致误开机的电路原理图；
图4是本发明第二实施例提供的电源管理电路的电路图；
图5是本发明第一实施例提供的电子设备控制方法的示意流程图；
图6是本发明第二实施例提供的电子设备控制方法的示意流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
应当理解，当在本说明书和所附权利要求书中使用时，术语“包括”和“包含”指示所描述特征、整体、步骤、操作、元素和/或组件的存在，但并不排除一个或多个其它特征、整体、步骤、操作、元素、组件和/或其集合的存在或添加。
还应当理解，在此本发明说明书中所使用的术语仅仅是出于描述特定实施 例的目的而并不意在限制本发明。如在本发明说明书和所附权利要求书中所使用的那样，除非上下文清楚地指明其它情况，否则单数形式的“一”、“一个”及“该”意在包括复数形式。
还应当进一步理解，在本发明说明书和所附权利要求书中使用的术语“和/或”是指相关联列出的项中的一个或多个的任何组合以及所有可能组合，并且包括这些组合。
如在本说明书和所附权利要求书中所使用的那样，术语“如果”可以依据上下文被解释为“当...时”或“一旦”或“响应于确定”或“响应于检测到”。类似地，短语“如果确定”或“如果检测到[所描述条件或事件]”可以依据上下文被解释为意指“一旦确定”或“响应于确定”或“一旦检测到[所描述条件或事件]”或“响应于检测到[所描述条件或事件]”。
请参考图1，是本发明第一实施例提供一种电源管理电路的结构框图。该电源管理电路应用于移动终端等电子设备。如图所示，该电源管理电路可包括：
滤波电路10，用于连接电源；其中，该电源用于为电源管理电路提供电力；
中央处理器11，用于发送低电平信号；
电源管理芯片12；
TYPE_C接口13，连接电源管理芯片12；
接口检测芯片14，连接滤波电路10、中央处理器11及连接TYPE_C接口13；
电位下拉电路15，连接接口检测芯片14及电源管理芯片12，用于拉低输入至电源管理芯片12的检测电压。
进一步地，请参考图2，滤波电路10包括第一电容C1及第二电容C2，第一电容C1及第二电容C2并联，且并联后的一端连接为整个电源管理电路提供电力的电源VPH_PWR以及接口检测芯片12，并联后的另一端则接地。
TYPE_C接口13电性连接至接口检测芯片14及电源管理芯片12，且包括一电源引脚(即引脚1)。
接口检测芯片14包括引脚1、引脚2、引脚4、引脚10、引脚11及引脚12。其中，引脚1和引脚2分别为第一配置通道引脚CC1和第二配置通道引脚CC2，用于连接TYPE_C接口13，TYPE_C设备通过该TYPE_C接口13 接入接口检测芯片14；引脚4为电源检测引脚VBUSDET，用于电性连接至电源管理芯片12及TYPE_C接口13的电源引脚(即引脚1)，且引脚4与电源管理芯片12之间串接有一电阻R1，进一步地，电源引脚(即引脚1)与电源检测引脚VBUSDET之间形成一节点A；引脚10为接地引脚GND；引脚11为使能引脚ENB，用于电性连接至中央处理器11，以接收中央处理器11发送的低电平信号而使能接口检测芯片14；引脚12为电源输入引脚VDD，用于电性连接至滤波电路10的第一电容C1、第二电容C2及电源VPH_PWR。
电位下拉电路15电性连接至节点A与电源检测引脚VBUSDET之间。具体地，如图2所示，电位下拉电路15包括第一电阻R1(阻值为1M)及第二电阻R2(阻值为20KΩ)，第一电阻R1的一端连接节点A，另一端连接电源检测引脚VBUSDET(及引脚4)，第二电阻R2的一端连接节点A，另一端接地。
如图3所示，中央处理器21发送低电平信号，并通过接口检测芯片24的使能引脚(即引脚11)输送至接口检测芯片24，以使能该接口检测芯片24。当电子设备因电力耗尽自动关机后，若TYPE_C接口23通过TYPE_C线缆连接至未带电源的设备(即通过TYPE_C接口插入纯TYPE_C线缆)，由于纯TYPE_C线缆内部有个默认5.1K的电阻R3(该电阻阻值是标准TYPE_C协议规定的)，该电阻R3将与接口检测芯片24的内部电阻R4对电源VPH_PWR进行分压。其中，该内部电阻R4的一端连接电源输入引脚VDD(即引脚12)，另一端连接电源检测引脚VBUSDET(即引脚4)和第一配置通道引脚CC1(即引脚1)。此时，检测出电源检测引脚VBUSDET(即引脚4)处的电压为0.9V左右。该0.9V左右的电压将会反灌至电源管理芯片22，又由于电源管理芯片22触发电子设备开机的电压过低，因此，0.9V左右的电压便触发开机，从而导致了误开机。
基于此，本发明实施例提供了如图2所示电位下拉电路15。当TYPE_C接口13通过TYPE_C线缆连接至未带电源的设备(即通过TYPE_C接口插入纯TYPE_C线缆)，从接口检测芯片14的电源检测引脚VBUSDET(即引脚4)输出的0.9V左右的电压，经过电位下拉电路后，将会被下拉至0.3V左右(即节点A处的电压为0.3V左右)，该电压再输入电源管理芯片12时，其远低于电源管理芯片12触发开机的电压(大概0.9V左右)，从而解决了未连接电源 设备的TYPE_C线缆插入接口检测芯片导致误触发开机的问题。
请参考图4，是本发明开机检测电路第二实施例的电路图。如图所示，电位下拉电路35包括第一二极管D1，其与第一电阻R5串联，且第一二极管D1的阴极连接第一电阻R5。且第一二极管D1的阳极连接节点B，第一电阻R1的连接电源检测引脚VBUSDET(即引脚4)。其中，该第一二极管D1的导通电压为0.7V左右。
进一步地，本实施例中的电位下拉电路35还包括第二电阻R6及第二二极管D2，第二电阻R6的一端连接电源检测引脚VBUSDET(即引脚4)及第一电阻R5，另一端连接第二二极管D2的阳极，第二二极管D2的阴极连接第一二极管D1的阳极，第二二极管D2的阴极连接第一二极管D1的阳极及节点B。第一电阻R5及第一二极管D1形成第一通路，第二电阻R6及第二二极管D2形成第二通路，当TYPE_C设备插入接口检测芯片时，第一通路或第二通路导通。其中，TYPE_C设备包括未连接电源设备的TYPE_C线缆和连接电源设备的TYPE_C线缆。
具体地，电子设备因电力耗尽自动关机后，若TYPE_C接口33通过TYPE_C线缆连接至未带电源的设备(即通过TYPE_C接口插入纯TYPE_C线缆)，如前所述，电源检测引脚VBUSDET(即引脚4)会向外输出0.9V左右的检测电压，此时第一电阻R5及第一二极管D1形成的第一通路导通，同时第二电阻R6及第二二极管D2形成的第二通路被反向二极管D2截止，是不导通的。因此，0.9V左右的电压经过第一通路后，节点B处的电压会降低至0.9-0.7＝0.2V左右，0.2V左右的电压再输入电源管理芯片32时，其远低于电源管理芯片32触发开机的电压(大概0.9V左右)，从而解决了未连接电源设备的TYPE_C线缆插入接口检测芯片导致误触发开机的问题。
相应地，若TYPE_C接口33通过TYPE_C线缆连接至带电源的设备，该电源设备通过TYPE_C接口的引脚1输出充电电压，例如5V、12V等充电电压至节点B，该充电电压输出至电源管理芯片32使电子设备正常开机，同时使第二电阻R6及第二二极管D2形成的第二通路导通，且第一电阻R5及第一二极管D1形成的第一通路被反向二极管D1截止，是不导通的。因此，接口检测芯片34可对插入的TYPE_C设备进行正常识别，从而完成正常的充电。
需要说明的是，图4中的滤波电路30、中央处理器31、电源管理芯片32、TYPE_C接口33及接口检测芯片34的元器件符号、连接关系及工作过程与图2中的滤波电路10、中央处理器11、电源管理芯片12、TYPE_C接口13及接口检测芯片14类似，在此不再赘述。
相应地，本发明实施例还提供了一种电子设备。该电子设备包括电源管理电路。具体地，该电源管理电路的内部结构及相应功能请参考前述对图1及图2的描述，在此不再赘述。
本发明实施例中，当电子设备关机时，电源管理电路的控制电路控制接口检测芯片处于关闭状态。因此，若此时未连接电源设备的TYPE_C线缆插入接口检测芯片，也不会触发电源管理芯片开机，从而解决了关机时插入未连接电源设备的TYPE_C线缆导致电子设备误开机的问题。
请参考图5，是本发明第一实施例提供一种电子设备控制方法的示意流程图，如图所示，该方法可以包括：
S101，当电子设备处于关机状态时，通过TYPE_C接口接收TYPE_C设备的插入，TYPE_C接口包括电性连接至电源管理芯片的电源引脚，电源引脚电性连接至电源检测引脚并形成一节点；
S102，根据TYPE_C设备的插入产生一检测电压，并通过接口检测芯片的电源检测引脚向电源管理芯片输入检测电压；
S103，通过电位下拉电路拉低检测电压，该电位下拉电路电性连接至电源检测引脚与节点之间。
需要说明的是，本实施例中的方法是采用如图2所示的电路实现的。故，本实施例中方法的具体工作流程请参考前述对图2所示电路的描述，在此不再赘述。本实施例中，当TYPE_C线缆连接至未带电源的设备插入接口检测芯片时，经过电位下拉电路后，输入至电源管理芯片的电压将会被下拉至0.3V左右，其远低于电源管理芯片触发开机的电压(大概0.9V左右)，从而解决了未连接电源设备的TYPE_C线缆插入接口检测芯片导致误触发开机的问题。
请参考图6，是本发明第二实施例提供一种电子设备控制方法的示意流程 图，如图所示，该方法可以包括：
S201，当电子设备处于关机状态时，通过TYPE_C接口接收TYPE_C设备的插入，TYPE_C接口包括电性连接至电源管理芯片的电源引脚，电源引脚电性连接至电源检测引脚并形成一节点；
S202，根据TYPE_C设备的插入产生一检测电压，并通过接口检测芯片的电源检测引脚向电源管理芯片输入检测电压；
S203，根据TYPE_C设备的插入选择性地导通第一通路或第二通路；
S204，当第一通路导通时，通过电位下拉电路拉低检测电压，该电位下拉电路电性连接至电源检测引脚与节点之间。
具体地，当未连接电源设备的TYPE_C线缆插入时，导通第一通路，同时关闭第二通路，并通过电位下拉电路拉低检测电压；当连接电源设备的TYPE_C线缆插入时，导通第二通路，同时关闭第一通路，接口检测芯片对插入的TYPE_C设备进行正常识别，完成正常的充电。
需要说明的是，本实施例中的方法是采用如图2所示的电路实现的。故，本实施例中方法的具体工作流程请参考前述对图4所示电路的描述，在此不再赘述。本实施例中，当TYPE_C线缆连接至未带电源的设备插入接口检测芯片时，经过电位下拉电路后，输入至电源管理芯片的电压将会被下拉至0.2V左右，其远低于电源管理芯片触发开机的电压(大概0.9V左右)，从而解决了未连接电源设备的TYPE_C线缆插入接口检测芯片导致误触发开机的问题。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
此外，在本申请所提供的几个实施例中，应该理解到，所揭露的、终端和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有 另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本发明实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
本发明实施例方法中的步骤可以根据实际需要进行顺序调整、合并和删减。
本发明实施例终端中的单元可以根据实际需要进行合并、划分和删减。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求的保护范围为准。

Claims (9)

  1. 一种电源管理电路，包括TYPE_C接口、接口检测芯片及电源管理芯片，所述接口检测芯片包括电源检测引脚，所述TYPE_C接口包括电性连接至所述电源管理芯片的电源引脚，所述电源引脚电性连接至所述电源检测引脚并形成一节点；其特征在于，所述电源管理电路还包括电位下拉电路，所述电位下拉电路电性连接至所述节点与所述电源检测引脚之间。
  2. 如权利要求1所述的电源管理电路，其特征在于，所述电位下拉电路包括第一电阻及第二电阻，所述第一电阻的一端连接所述节点，另一端连接所述电源检测引脚，所述第二电阻的一端连接所述节点，另一端接地。
  3. 如权利要求1所述的电源管理电路，其特征在于，所述电位下拉电路包括第一电阻及第一二极管，所述第一二极管与所述第一电阻串联，所述第一二极管的阴极连接所述第一电阻，所述第一二极管的阳极连接所述节点，所述第一电阻的连接所述电源检测引脚。
  4. 如权利要求3所述的电源管理电路，其特征在于，所述电位下拉电路还包括第二电阻及第二二极管，所述第二电阻的一端连接所述电源检测引脚及所述第一电阻，所述第二电阻的另一端连接所述第二二极管的阳极，所述第二二极管的阴极连接所述第一二极管的阳极及所述节点。
  5. 如权利要求1-4任一项所述的电源管理电路，其特征在于，所述接口检测芯片包括电源输入引脚，所述电源管理电路还包括电性连接至一电源及所述电源输入引脚之间的滤波电路，所述滤波电路包括第一电容及第二电容，所述第一电容及第二电容并联，且并联后的一端连接所述电源和所述接口检测芯片，并联后的另一端接地。
  6. 一种电子设备，包括电源管理电路，其特征在于，所述电源管理电路如权利要求1-5任一项所述。
  7. 一种电子设备控制方法，其特征在于，包括：
    当电子设备处于关机状态时，通过TYPE_C接口接收TYPE_C设备的插入，所述TYPE_C接口包括电性连接至所述电源管理芯片的电源引脚，所述电源引脚电性连接至所述电源检测引脚并形成一节点；
    根据所述TYPE_C设备的插入产生一检测电压，并通过接口检测芯片的电源检测引脚向电源管理芯片输入所述检测电压；
    通过电位下拉电路拉低所述检测电压，所述电位下拉电路电性连接至所述电源检测引脚与所述节点之间。
  8. 如权利要求7所述的电子设备控制方法，其特征在于，所述电位下拉电路包括第一通路及第二通路，所述方法还包括：
    根据所述TYPE_C设备的插入选择性地导通所述第一通路或第二通路。
  9. 如权利要求8所述的电子设备控制方法，其特征在于，根据所述插入信号选择性地导通所述第一通路或第二通路具体包括：
    当未连接电源设备的TYPE_C线缆插入时，导通所述第一通路，同时关闭所述第二通路；
    当连接电源设备的TYPE_C线缆插入时，导通所述第二通路，同时关闭所述第一通路。
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