WO2018126490A1 - 电容检测电路及电子装置 - Google Patents

电容检测电路及电子装置 Download PDF

Info

Publication number
WO2018126490A1
WO2018126490A1 PCT/CN2017/070683 CN2017070683W WO2018126490A1 WO 2018126490 A1 WO2018126490 A1 WO 2018126490A1 CN 2017070683 W CN2017070683 W CN 2017070683W WO 2018126490 A1 WO2018126490 A1 WO 2018126490A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrodes
row
detecting circuit
capacitance detecting
differential
Prior art date
Application number
PCT/CN2017/070683
Other languages
English (en)
French (fr)
Inventor
文亚南
梁颖思
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2017/070683 priority Critical patent/WO2018126490A1/zh
Priority to CN201780000032.3A priority patent/CN108700976B/zh
Publication of WO2018126490A1 publication Critical patent/WO2018126490A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means

Definitions

  • the present application relates to a capacitance detecting circuit and an electronic device, and more particularly to a capacitance detecting circuit and an electronic device capable of avoiding noise accumulation.
  • the operational interfaces of various electronic products have gradually become more humanized in recent years.
  • the user can directly operate on the screen with a finger or a stylus, input a message/text/pattern, and save the trouble of using an input device such as a keyboard or a button.
  • the touch screen usually consists of a sensing panel and a display disposed behind the sensing panel.
  • the electronic device judges the meaning of the touch according to the position touched by the user on the sensing panel and the picture presented by the display at the time, and executes the corresponding operation result.
  • the receiving electrodes on the touch screen are affected by common mode noise, which has approximately the same effect on all receiving electrodes in the touch screen.
  • SNR signal-to-noise ratio
  • the touch signal will be submerged in the common mode noise, and the position where the touch occurs cannot be determined.
  • the prior art has developed the use of a differential circuit to eliminate common mode noise.
  • the existing differential circuit has the disadvantage of noise accumulation.
  • FIG. 4 is a schematic diagram of a conventional differential circuit 40 .
  • the differential circuit 40 includes electrodes RX0-RX3, amplifiers OP_0-OP_2, and a recovery module 420.
  • the amplifiers OP_0-OP_2 are coupled to the electrodes RX0-RX3 for receiving the electrode signals R_0-R_3 and generating a difference.
  • the output signals Vo_0 to Vo_2 are divided, and the recovery module 420 generates the recovery signals R_1' to R_3' corresponding to the electrode signals R_0 to R_3 based on the differential output signals Vo_0 to Vo_2.
  • the reply module 420 accumulates noises n0, n1, and n2 according to the manner in which the differential output signals Vo_0 to Vo_2 generate the reply signals R_1' to R_3'.
  • the reply module 420 is based on the differential output.
  • the noises n1, n2 are accumulated in the reply signals R_2', R_3', and the overall performance is lowered.
  • the present application provides a capacitance detecting circuit including a plurality of electrodes for transmitting a plurality of electrode signals, wherein the plurality of electrodes have an electrode number; at least one differential amplifier coupled to the a plurality of electrodes for generating a plurality of differential output signals, wherein each differential amplifier has a first input and a second input, and the at least one differential amplifier has an amplifier And a reply module coupled to the at least one differential amplifier for generating a plurality of return signals corresponding to the plurality of electrode signals according to the plurality of differential output signals, wherein the plurality of return signals are related a capacitance of the plurality of electrodes; wherein the first input end of a differential amplifier of the at least one differential amplifier is coupled to the plurality of first electrodes of the plurality of electrodes, the first of the differential amplifiers The two input ends are coupled to the plurality of second electrodes of the plurality of electrodes.
  • the plurality of first electrodes are electrodes of one half of the plurality of electrodes
  • the plurality of second electrodes are electrodes of the other half of the plurality of electrodes.
  • the first input of each of the at least one differential amplifier is coupled to one of the plurality of electrodes, and the second input of each of the differential amplifiers is coupled to the An electrode of the other half of the plurality of electrodes.
  • one of the plurality of electrodes is coupled to all of the differential amplifiers of the at least one differential amplifier.
  • the electrode is coupled to the first input of a differential amplifier of a portion of the at least one differential amplifier.
  • the electrode is coupled to the second input of a differential amplifier of another portion of the at least one differential amplifier.
  • each of the plurality of electrodes is coupled to all of the differential amplifiers of the at least one differential amplifier.
  • the correspondence between the plurality of differential output signals and the plurality of electrode signals is related to a first matrix operation
  • the first matrix operation is related to a first coding matrix
  • the coding matrix has multiple Element, each element has a value of +1 or -1.
  • the encoding matrix has a plurality of rows, and one row of the plurality of rows has a plurality of row elements,
  • the plurality of row elements include a plurality of first row elements and a plurality of second row elements, the plurality of first row elements having a value of +1, and the plurality of second row elements having a value of -1,
  • a first number of the plurality of first row elements is equal to a second number of the plurality of second row elements.
  • the reply module calculates an addition result of a first differential output signal and a second differential output signal of the plurality of differential output signals, and calculates one of the plurality of reply signals according to the addition result.
  • First reply signal the reply module calculates an addition result of a first differential output signal and a second differential output signal of the plurality of differential output signals, and calculates one of the plurality of reply signals according to the addition result.
  • the reply module multiplies the addition result by a specific value, and obtains the first reply signal according to a result of multiplying the addition result and the specific value.
  • the reply module performs a second matrix operation on a second vector including the plurality of differential output signals, the second matrix operation is related to a second decoding matrix, and the second decoding matrix has multiple a row, the row of the plurality of rows having a plurality of row elements, wherein the plurality of row elements in the row includes a first row element, a second row element, and a third row element, the first row element And the value of the second row element is -0.5, and the value of the third row element is 1, the plurality of row elements except the first row element, the second row element, and the third row Outside the element, the remaining row elements have a value of 0.
  • the reply module calculates a subtraction result of a third differential output signal and a fourth differential output signal of the plurality of differential output signals, and calculates one of the plurality of reply signals according to the subtraction result. Reply signal.
  • the reply module multiplies the subtraction result by a specific value, and obtains the reply signal according to a multiplication result of the subtraction result and the specific value.
  • the specific value is 0.5.
  • the reply module performs a third matrix operation on a third vector including the plurality of differential output signals, the third matrix operation being related to a third decoding matrix, the third decoding matrix Having a plurality of rows, the row of the plurality of rows having a plurality of row elements, wherein the plurality of row elements in the row includes a fourth row element, a fifth row element, and a sixth row element, the fourth The value of the row element is -0.5, the value of the fifth row element is +0.5, and the value of the sixth row element is 1, except for the fourth row element and the fifth row element among the plurality of row elements. And the other row elements have a value of 0 other than the sixth row element.
  • the capacitance detecting circuit further includes a reference voltage generator and a reference amplifier, the reference voltage generator is coupled to the reference amplifier, and the reference voltage generator is coupled to the at least one differential amplifier.
  • the reference amplifier is coupled to the plurality of electrodes.
  • the number of electrodes is a multiple of two.
  • the number of amplifiers is one less than the number of electrodes.
  • the number of amplifiers is equal to the number of electrodes.
  • the present application further provides an electronic device, including a capacitance detecting circuit, including a plurality of electrodes for transmitting a plurality of electrode signals, wherein the plurality of electrodes have an electrode number; at least one differential amplifier coupled to the The plurality of electrodes are configured to generate a plurality of differential output signals, wherein each of the differential amplifiers has a first input end and a second input end, the at least one differential amplifier has an amplifier number; and a return module coupled And the at least one differential amplifier is configured to generate, according to the plurality of differential output signals, a plurality of return signals corresponding to the plurality of electrode signals, wherein the plurality of return signals are related to a capacitance of the plurality of electrodes
  • the first input end of a differential amplifier of the at least one differential amplifier is coupled to the plurality of first electrodes of the plurality of electrodes, and the second input end of the differential amplifier is coupled to the plurality of electrodes a plurality of second electrodes; and a determining circuit coupled to the capacitance
  • FIG. 1 is a schematic diagram of an electronic device according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a capacitance detecting circuit according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a capacitance detecting circuit according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a conventional differential circuit.
  • FIG. 5 is a schematic diagram of a capacitance detecting circuit according to an embodiment of the present application.
  • the present application utilizes a plurality of differential amplifiers and a connection manner between a plurality of differential amplifiers and a plurality of electrodes to implement a specific coding matrix, and generates a plurality of reply signals by using a decoding matrix corresponding to the specific coding matrix to avoid multiple The problem of noise accumulation in the reply signal.
  • FIG. 1 is a schematic diagram of an electronic device 10 according to an embodiment of the present application.
  • the electronic device 10 can be an electronic device capable of performing touch operation or fingerprint recognition, such as a smart phone or a tablet computer.
  • the electronic device 10 includes a capacitance detecting circuit 12 and a determining circuit 14.
  • the capacitance detecting circuit 12 includes electrodes Rx_0 to Rx_3, differential amplifiers Amp_0 to Amp_2, and a reply module 120.
  • the electrodes Rx_0 to Rx_3 are used to transmit the electrode signals R 0 to R 3 corresponding to the electrodes Rx_0 to Rx_3 ; the differential amplifiers Amp_0 to Amp_2 are coupled to the electrodes Rx_0 to Rx_3 for generating the differential output signals Out 0 to Out 2 ; The differential amplifiers Amp_0 to Amp_2 are coupled to generate a recovery signal (Recovery Signal) R 1 ' to R 3 ' corresponding to the electrode signals R 1 to R 3 according to the differential output signals Out 0 to Out 2 ;
  • the response module 120 is configured to determine the capacitance corresponding to the electrodes Rx_1 - Rx_3 according to the reply signals R 1 ' to R 3 '. Further, in the electronic device 10, the number of amplifiers of the differential amplifiers Amp_0 to Amp_2 is one minus the number of electrodes of the electrodes Rx_0 to Rx_3.
  • the reply module 120 can be implemented by using an RTL circuit
  • any of the differential amplifiers Amp_0 to Amp_2 has a positive input terminal (labeled with a "+” sign) and a negative input terminal (with a "-” sign).
  • the positive input terminal of the differential amplifier Amp_k is coupled.
  • the plurality of first electrodes are connected to the electrodes Rx_0 to Rx_3, and the negative input terminals of the differential amplifiers Amp_k are coupled to the plurality of second electrodes of the electrodes Rx_0 to Rx_3.
  • the number of the plurality of first electrodes is the same as the number of the plurality of second electrodes, and the number of the plurality of first electrodes (or the number of the plurality of second electrodes) is the number of electrodes of the electrodes Rx_0 to Rx_3 Half of it.
  • the negative input terminal of the differential amplifier Amp_k is coupled to one of the electrodes Rx_0 to Rx_3, and the positive input terminal of the differential amplifier Amp_k is coupled to the electrode of the other half of the electrodes Rx_0 to Rx_3.
  • the negative input terminal of the differential amplifier Amp_0 can be coupled to the electrodes Rx_0, Rx_1, and the positive input terminal of the differential amplifier Amp_0 can be coupled to the electrodes Rx_2, Rx_3.
  • the electrode Rx_0 Rx_1 (corresponding to a plurality of first electrodes) is an electrode of one half of the electrodes Rx_0 to Rx_3, and electrodes Rx_2 and Rx_3 (corresponding to a plurality of second electrodes) are electrodes of the other half of the electrodes Rx_0 to Rx_3.
  • the negative input of the differential amplifier Amp_1 can be coupled to the electrodes Rx_0, Rx_2, and the positive input of the differential amplifier Amp_1 can be Coupling to the electrodes Rx_1 and Rx_3, in this case, the electrodes Rx_0, Rx_2 (corresponding to the plurality of first electrodes) are the electrodes of one of the electrodes Rx_0 to Rx_3, and the electrodes Rx_1, Rx_3 (corresponding to the plurality of second electrodes) It is the electrode of the other half of the electrodes Rx_0 to Rx_3.
  • the negative input terminal of the differential amplifier Amp_2 can be coupled to the electrodes Rx_0 and Rx_3, and the positive input terminal of the differential amplifier Amp_2 can be coupled to the electrodes Rx_1 and Rx_2.
  • the electrodes Rx_0 and Rx_3 (corresponding to the plurality of One electrode is an electrode of one half of the electrodes Rx_0 to Rx_3, and the electrodes Rx_1 and Rx_2 (corresponding to a plurality of second electrodes) are electrodes of the other half of the electrodes Rx_0 to Rx_3.
  • one of the electrodes Rx_0 to Rx_3 is coupled to all of the differential amplifiers Amp_0 to Amp_2.
  • the electrode Rx_j can be coupled to the negative input of a part of the differential amplifiers Amp_0 to Amp_2. And coupled to the positive input terminal of another differential amplifier of the differential amplifiers Amp_0 to Amp_2.
  • the electrode Rx_1 can be coupled to the negative input terminal of the differential amplifier Amp_0 and coupled to the positive input terminals of the differential amplifiers Amp_1 and Amp_2.
  • the differential amplifier Amp_0 can be regarded as a differential amplifier.
  • the differential amplifiers of some of Amp_0 to Amp_2, and the differential amplifiers Amp_1 and Amp_2 can be regarded as differential amplifiers of the other part of the differential amplifiers Amp_0 to Amp_2.
  • the electrode Rx_2 can be coupled to the negative input terminal of the differential amplifier Amp_1 and coupled to the positive input terminals of the differential amplifiers Amp_0 and Amp_2.
  • the differential amplifier Amp_1 can be regarded as a differential amplifier of a part of the differential amplifiers Amp_0 to Amp_2, and
  • the differential amplifiers Amp_0 and Amp_2 can be regarded as differential amplifiers of the other part of the differential amplifiers Amp_0 to Amp_2.
  • the electrode Rx_3 can be coupled to the negative input terminal of the differential amplifier Amp_2 and coupled to the positive input terminals of the differential amplifiers Amp_0 and Amp_1.
  • the differential amplifier Amp_2 can be regarded as a differential of a part of the differential amplifiers Amp_0 to Amp_2.
  • Amplifier the differential amplifiers Amp_0 and Amp_1 can be regarded as differential amplifiers of the other part of the differential amplifiers Amp_0 to Amp_2.
  • the electrode Rx_0 can be coupled to the negative input terminals of the differential amplifiers Amp_0 to Amp_2. That is, each of the electrodes Rx_0 to Rx_3 is coupled to all of the differential amplifiers Amp_0 to Amp_2.
  • the correspondence between the differential output signals Out 0 to Out 2 and the electrode signals R 0 to R 3 can be described by an encoding matrix (Encoding Matrix) D 1 .
  • the differential output signal Out 1 can be expressed as Out.
  • a v represents the gain of the differential amplifiers Amp_0 to Amp_2 (for simplicity, the gain Av can be assumed to be 1)
  • n 0 , n 1 , and n 2 represent the noise inside the differential amplifiers Amp_0, Amp_1, and Amp_2, respectively (and eliminate common mode). Residual noise after noise).
  • Equation 1 the correspondence relationship between the differential output signals Out 0 to Out 2 and the electrode signals R 0 to R 3 can be expressed as Equation 1, wherein the encoding matrix D 1 can be expressed as Equation 2 (shown below).
  • Equation 2 the encoding matrix D 1
  • the value of each element (Entry) in the coding matrix D 1 is +1 or -1, and further, in each row (Row) of the coding matrix D 1 , a plurality of rows whose value is +1
  • the number of elements (Row Entry) is equal to the number of multiple row elements whose value is -1.
  • each row in the encoding matrix D 1 contains a plurality of row elements, and the plurality of row elements includes a plurality of first rows.
  • An element and a plurality of second row elements the plurality of first row elements representing a row element having a value of +1, the plurality of second row elements representing a row element having a value of -1, and the plurality of first row elements and the plurality of The number of elements in the second row is equal, that is, the number of elements in the first row is equal to the number of elements in the second row.
  • the reply module 120 can generate the reply signals R 1 ' to R 3 ' based on the differential output signals Out 0 to Out 2 .
  • the correspondence between the differential output signals Out 0 to Out 2 and the electrode signals R 0- and the reply signals R 1 ' to R 3 ' can utilize a decoding matrix corresponding to the encoding matrix D 1 (Decoding Matrix). Described as D 1 -1 , as shown in Equation 3, in which the decoding matrix D 1 -1 can be expressed as Equation 4. It should be noted that the k-th row of the decoding matrix D 1 -1 contains a row element whose value is 1 and two row elements whose value is -0.5, in addition to the k-th row of the decoding matrix D 1 -1 The remaining row elements have a value of 0, where k is an integer from 1 to 3.
  • the kth row of the decoding matrix D 1 -1 includes a first row element, a second row element, and a third row element, and the value of the first row element and the second row element is -0.5, and the third The row element has a value of 1, and the remaining row elements of the kth row of the decoding matrix D 1 -1 have a value of 0.
  • the position of the third row element in the kth row corresponds to the vector in Equation 3 [Out 0 Out 1 Out 2 R 0 ] The position of R 0 in T.
  • the noises n 0 , n 1 , and n 2 are not accumulated in a specific reply signal.
  • the degree to which the reply signals R 1 ', R 2 ', and R 3 ' are affected by noise is equivalent.
  • the capacitance detecting circuit 12 eliminates the common mode noise in the electrodes Rx_0 to Rx_3 by using the differential amplifiers Amp_0 to Amp_2 and the connection between the differential amplifiers Amp_0 to Amp_2 and the electrodes Rx_0 to Rx_3 (that is, using the encoding matrix D 1 ). Further, the capacitance detecting circuit 12 uses the decoding matrix D 1 -1 to prevent the noises n 0 , n 1 , n 2 from accumulating in a certain reply signal, and solves the problem of noise accumulation in the prior art.
  • the reply signals R 1 ', R 2 ', R 3 ' are still affected by noise.
  • the coding matrix and the decoding matrix can be appropriately designed, so that the reply module can cancel the noises in the process of generating the reply signal/decoding, further reducing the noise. The effect on the reply signal.
  • FIG. 2 is a schematic diagram of a capacitance detecting circuit 22 according to an embodiment of the present application.
  • the capacitance detecting circuit 22 is similar to the capacitance detecting circuit 12, so the same components follow the same symbols.
  • the capacitance detecting circuit 22 includes a differential amplifier Amp_3 and a recovery module 220 (the number of amplifiers of the differential amplifiers Amp_0 to Amp_3 is the same as the number of electrodes of the electrodes Rx_0 to Rx_3), and the capacitance detecting circuit
  • the connection relationship between the middle electrode and the differential amplifier of 22 is different from the connection relationship between the electrode and the differential amplifier in the capacitance detecting circuit 12.
  • the negative input terminal of the differential amplifier Amp_2 is coupled to the electrodes Rx_1 and Rx_2, the positive input terminal of the differential amplifier Amp_2 is coupled to the electrodes Rx_0 and Rx_3, and the negative input terminal of the differential amplifier Amp_3 is coupled to the electrodes Rx_1 and Rx_3.
  • the positive input terminal of the amplifier Amp_3 is coupled to the electrodes Rx_0 and Rx_2.
  • the negative input terminal of any one of the differential amplifiers Amp_0 to Amp_3 is coupled to one of the electrodes Rx_0 to Rx_3, and the positive input terminal of the differential amplifier Amp_k is coupled to the other half of the electrodes Rx_0 to Rx_3. .
  • any one of the electrodes Rx_0 to Rx_3 is coupled to a negative input terminal of a differential amplifier of the differential amplifiers Amp_0 to Amp_3, and is coupled to another differential portion of the differential amplifiers Amp_0 to Amp_3.
  • the positive input of the amplifier can be coupled to the negative input terminals of the differential amplifiers Amp_0 and Amp_1 and coupled to the positive input terminals of the differential amplifiers Amp_2 and Amp_3, and the electrode Rx_1.
  • the negative input terminal of the differential amplifiers Amp_0, Amp_2, and Amp_3 can be coupled to the positive input terminal of the differential amplifier Amp_1, and the electrode Rx_2 can be coupled to the negative input terminal of the differential amplifiers Amp_1 and Amp_2 and coupled to the differential amplifier Amp_0.
  • the positive input terminal of the Amp_3, the electrode Rx_3 can be coupled to the negative input terminal of the differential amplifier Amp_3 and coupled to the positive input terminals of the differential amplifiers Amp_0, Amp_1, and Amp_2.
  • each of the electrodes Rx_0 to Rx_3 is coupled to all of the differential amplifiers Amp_0 to Amp_3.
  • an encoding matrix D 2 corresponding to the capacitance detecting circuit 22 is different from the encoding matrix D 1 corresponding to the capacitance detecting circuit 12, and the reply module 220 is used to generate a decoding matrix D 2 of the reply signals R 1 ' to R 3 ' -1 is also different from the decoding matrix D 1 -1 used by the reply module 120 to generate the reply signals R 1 '-R 3 '.
  • the correspondence between the differential output signals Out 0 to Out 3 and the electrode signals R 0 to R 3 can be expressed as Equation 8
  • the encoding matrix D2 can be expressed as Equation 9, the differential output signal.
  • Equation 10 The correspondence between Out 0 to Out 2 and the electrode signal R 0- and the reply signals R 1 ' to R 3 ' can be expressed as Equation 10, and the decoding matrix D 2 -1 can be expressed as Equation 11.
  • R 1 ' R 1 +0.5(n 2 -n 1 ) (Equation 12)
  • R 1 +0.5(n 2 -n 0 Equation 13)
  • R1+0.5(n 3 -n 0 ) Equation 14.
  • the noise in the reply signals R 1 ', R 2 ', R 3 ' can be further eliminated, thereby reducing the noise pair Respond to the effects of the signal and improve the signal to noise ratio.
  • the reply module is not limited to being implemented by an RTL circuit.
  • the reply module of the present application may also utilize a processor to generate/calculate a reply signal, that is, a function corresponding to the reply module may be implemented in a software manner.
  • the capacitance detecting circuit 12 and the capacitance detecting circuit 22 all include four electrodes, and the capacitor detecting circuit of the present application may include N electrodes and N differential amplifiers, as long as N is a multiple of 2, that is, the present application is satisfied. Demand.
  • the k-th row (k ⁇ 1) of the decoding matrix D 3 -1 and the decoding matrix D 4 -1 contains a row element having a value of -0.5, a row element having a value of 0.5, and a row element.
  • the row element has a value of 1, and the values of the remaining row elements of the k-th row of the decoding matrix D 3 -1 and the decoding matrix D 4 -1 are zero.
  • a person skilled in the art should implement the connection manner between multiple differential amplifiers and multiple electrodes in the capacitance detecting circuit of the present application according to the encoding matrix D 3 and the encoding matrix D 4 , and use the reply module to decode according to the decoding matrix D 3 -1 .
  • the matrix D 4 -1 produces a reply signal and falls within the scope of the present application.
  • FIG. 3 is a schematic diagram of a capacitance detecting circuit 32 according to an embodiment of the present application.
  • the capacitance detecting circuit 32 is similar to the capacitance detecting circuit 22, so the same components follow the same symbols.
  • the capacitance detecting circuit 32 further includes a reference voltage generator VGref and a reference amplifier Amp_4.
  • the reference voltage generator VGref is coupled to the negative input terminals of the differential amplifiers Amp_0 to Amp_3 and coupled to the reference amplifier.
  • the positive input terminal of Amp_4 in addition, the electrodes Rx_0 to Rx_3 are coupled to the negative input terminal of the reference amplifier Amp_4, which is also within the scope of the present application.
  • FIG. 5 is a schematic diagram of a capacitance detecting circuit 52 according to an embodiment of the present application.
  • the capacitance detecting circuit 52 includes electrodes Rx_0-Rx_N, differential amplifiers Amp_0-Amp_K, a switching unit 522, and a reply module 520.
  • the 522 is coupled to the electrodes Rx_0 to Rx_N and the differential amplifiers Amp_0 to Amp_K.
  • the switching unit 522 controls the connection relationship between the electrodes Rx_0 to Rx_N and the differential amplifiers Amp_0 to Amp_K by a control signal ctrl, as long as the positive input of the differential amplifier Amp_k
  • the terminal is coupled to the plurality of first electrodes of the electrodes Rx_0-Rx_N and the negative input terminal of the differential amplifier Amp_k is coupled to the plurality of second electrodes of the electrodes Rx_0-Rx_N, which meets the requirements of the present application and belongs to the scope of the present application.
  • the capacitance detecting circuit of the present application is not limited to include a plurality of differential amplifiers.
  • the capacitance detecting circuit of the present application may include only a single differential amplifier, as long as a specific electrode signal is transmitted to the differential amplifier through a switching unit at different times, that is, the difference. It is within the scope of the present application for the amplifier to sequentially output a plurality of differential output signals at different times, also satisfying the requirements of the present application.
  • the present application utilizes a plurality of differential amplifiers and a connection mode between a plurality of differential amplifiers and a plurality of electrodes (implementing a specific coding matrix) to eliminate common mode among the plurality of electrodes.
  • Noise, and using a decoding matrix corresponding to the particular coding matrix generates a plurality of reply signals corresponding to the plurality of electrode signals such that there is no problem of noise accumulation among the plurality of reply signals.
  • the present application can further eliminate noise in the reply signal, further improving the overall signal to noise ratio.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Amplifiers (AREA)
  • Position Input By Displaying (AREA)

Abstract

一种电容检测电路（12、22、32、52），包括多个电极（RX_0、RX_1、RX_2……RX_N），用来传递多个电极信号（R 0、R 1、R 2……R N）；至少一差分放大器（Amp_0、Amp_1、Amp_2……Amp_K），用来产生多个差分输出信号（Out 0、Out 1、Out 2……），其中每一差分放大器（Amp_0、Amp_1、Amp_2……Amp_K）具有一第一输入端及一第二输入端；以及一回复模块（120、220、320、520），用来根据该多个差分输出信号（Out 0、Out 1、Out 2……），产生对应于该多个电极信号（R 0、R 1、R 2……R N）的多个回复信号（R 0 '、R 1 '、R 2 '……R N '）；其中，该至少一差分放大器（Amp_0、Amp_1、Amp_2……Amp_K）中一差分放大器的该第一输入端耦接于多个电极（RX_0、RX_1、RX_2……RX_N）中多个第一电极，该差分放大器的该第二输入端耦接于多个电极（Amp_0、Amp_1、Amp_2……Amp_K）中多个第二电极。

Description

电容检测电路及电子装置 技术领域
本申请涉及一种电容检测电路及电子装置，尤其涉及一种可避免噪声累积的电容检测电路及电子装置。
背景技术
随着科技日益进步，近年来各种电子产品的操作接口逐渐人性化。举例而言，透过触控面板，使用者可直接以手指或触控笔在屏幕上操作、输入讯息/文字/图样，省去使用键盘或按键等输入设备的麻烦。实际上，触控屏通常由一感应面板及设置于感应面板后方的显示器组成。电子装置根据用户在感应面板上所触碰的位置，以及当时显示器所呈现的画面，来判断该次触碰的意涵，并执行相对应的操作结果。
详细来说，触控屏上的接收电极会受到共模噪声的影响，其中共模噪声对触控屏中所有接收电极造成大致相同的影响。在信噪比(Signal-to-Noise Ratio，SNR)很小的情况下，触控信号会淹没在共模噪声当中，而无法确的判断触控发生的位置。为了消除接收电极的共模噪声，现有技术已发展出利用差分电路来消除共模噪声，然而，现有差分电路具有噪声累积(Noise Accumulation)的缺点。
具体来说，请参考图4，图4为现有一差分电路40的示意图。差分电路40包含电极RX0～RX3、放大器OP_0～OP_2以及一回复模块420，放大器OP_0～OP_2耦接于电极RX0～RX3，用来接收电极信号R_0～R_3并产生差 分输出信号Vo_0～Vo_2，回复模块420根据差分输出信号Vo_0～Vo_2产生对应于电极信号R_0～R_3的回复信号R_1’～R_3’。然而，放大器OP_0～OP_2受到噪声的影响而差分输出信号Vo_0～Vo_2可表示为Vo_0＝R_0－R_1+n0(公式01)、Vo_1＝R_1－R_2+n1(公式02)以及Vo_2＝R_2－R_3+n2(公式03)，其中n0、n1、n2包括集成电路(Intergrated Circuit，IC)的内部噪声和差分接收無法消除的外部噪聲。现有技术中，回复模块420根据差分输出信号Vo_0～Vo_2产生回复信号R_1’～R_3’的方式会累积噪声n0、n1、n2，详细来说，于一实施例中，回复模块420根据差分输出信号Vo_0～Vo_2，计算回复信号R_1’～R_3’相对于R_0的值为R_1’＝R_0－Vo_0(公式04)、R_2’＝R_0－(Vo_0+Vo_1)(公式05)以及R_1’＝R_0－(Vo_0+Vo_1+Vo_2)(公式06)。根据公式01～公式06，回复信号R_1’～R_3’可表为R_1’＝R_1－n0、R_2’＝R_2－n0－n1以及R_3’＝R_3－n0－n1－n2。然而，噪声n1、n2会累积在回复信号R_2’、R_3’中，而使整体效能降低。
因此，如何解决噪声累积的问题，就成为业界所努力的目标之一。
发明内容
因此，本发明部分实施例主要目的即在于提供一种可避免噪声累积的电容检测电路及电子装置，以改善习知技术的缺点。
为了解决上述技术问题，本申请提供了一种电容检测电路，包括多个电极，用来传递多个电极信号，其中所述多个电极具有一电极个数；至少一差分放大器，耦接于所述多个电极，用来产生多个差分输出信号，其中每一差分放大器具有一第一输入端及一第二输入端，所述至少一差分放大器具有一放大器 个数；以及一回复模块，耦接于所述至少一差分放大器，用来根据所述多个差分输出信号，产生对应于所述多个电极信号的多个回复信号，其中多个回复信号相关于所述多个电极的电容大小；其中，所述至少一差分放大器中一差分放大器的所述第一输入端耦接于多个电极中多个第一电极，所述差分放大器的所述第二输入端耦接于多个电极中多个第二电极。
例如，所述多个第一电极为所述多个电极中一半的电极，所述多个第二电极为所述多个电极中另一半的电极。
例如，所述至少一差分放大器中每一差分放大器的所述第一输入端耦接于所述多个电极中一半的电极，所述每一差分放大器的所述第二输入端耦接于所述多个电极中另一半的电极。
例如，所述多个电极中一电极耦接于所述至少一差分放大器中所有的差分放大器。
例如，所述电极耦接于所述至少一差分放大器中一部分的差分放大器的所述第一输入端。
例如，所述电极耦接于所述至少一差分放大器中另一部分的差分放大器的所述第二输入端。
例如，所述多个电极中每一电极耦接于所述至少一差分放大器中所有的差分放大器。
例如，所述多个差分输出信号与所述多个电极信号之间的对应关系相关于一第一矩阵运算，所述第一矩阵运算相关于一第一编码矩阵，所述编码矩阵具有多个元素，每一元素的值为+1或－1。
例如，所述编码矩阵具有多个行，所述多个行的一行具有多个行元素， 所述多个行元素包含多个第一行元素以及多个第二行元素，所述多个第一行元素的值为+1，所述多个第二行元素的值为－1，所述多个第一行元素的一第一个数与所述多个第二行元素的一第二个数相等。
例如，所述回复模块计算所述多个差分输出信号中一第一差分输出信号与一第二差分输出信号的一相加结果，并根据所述相加结果计算所述多个回复信号中一第一回复信号。
例如，所述回复模块将所述相加结果乘以一特定值后，并根据所述相加结果与所述特定值的一相乘结果，取得所述第一回复信号。
例如，所述回复模块对包含所述多个差分输出信号的一第二向量进行一第二矩阵运算，所述第二矩阵运算相关于一第二解码矩阵，所述第二解碼矩阵具有多个行，所述多个行的一行具有多个行元素，所述行中所述多个行元素包含一第一行元素、一第二行元素以及一第三行元素，所述第一行元素及所述第二行元素的值为－0.5，所述第三行元素的值为1，所述多个行元素除了所述第一行元素、所述第二行元素以及所述第三行元素以外，其余行元素的值为0。
例如，所述回复模块计算所述多个差分输出信号中一第三差分输出信号与一第四差分输出信号的一相减结果，并根据所述相减结果计算所述多个回复信号中一回复信号。
例如，所述回复模块将所述相减结果乘以一特定值后，并根据所述相减结果与所述特定值的一相乘结果，取得所述回复信号。
例如，所述特定值为0.5。
例如，所述回复模块对包含所述多个差分输出信号的一第三向量进行一第三矩阵运算，所述第三矩阵运算相关于一第三解码矩阵，所述第三解碼矩阵 具有多个行，所述多个行的一行具有多个行元素，所述行中所述多个行元素包含一第四行元素、一第五行元素以及一第六行元素，所述第四行元素的值为－0.5，所述第五行元素的值为+0.5，所述第六行元素的值为1，所述多个行元素中除了所述第四行元素、所述第五行元素以及所述第六行元素以外，其余行元素的值为0。
例如，所述的电容检测电路另包括一参考电压产生器以及一参考放大器，所述参考电压产生器耦接于所述参考放大器，所述参考电压产生器耦接于所述至少一差分放大器，所述参考放大器耦接于所述多个电极。
例如，所述电极个数为2的倍数。
例如，所述放大器个数为所述电极个数减1。
例如，所述放大器个数等于所述电极个数。
本申请另提供了一种电子装置，包括一电容检测电路，包括多个电极，用来传递多个电极信号，其中所述多个电极具有一电极个数；至少一差分放大器，耦接于所述多个电极，用来产生多个差分输出信号，其中每一差分放大器具有一第一输入端及一第二输入端，所述至少一差分放大器具有一放大器个数；以及一回复模块，耦接于所述至少一差分放大器，用来根据所述多个差分输出信号，产生对应于所述多个电极信号的多个回复信号，其中多个回复信号相关于所述多个电极的电容大小；其中，所述至少一差分放大器中一差分放大器的所述第一输入端耦接于多个电极中多个第一电极，所述差分放大器的所述第二输入端耦接于多个电极中多个第二电极；以及一判断电路，耦接于所述电容检测电路，用来根据所述多个回复信号，判断对应于所述多个电极的电容大小。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为本申请实施例一电子装置的示意图。
图2为本申请实施例一电容检测电路的示意图。
图3为本申请实施例一电容检测电路的示意图。
图4为现有一差分电路的示意图。
图5为本申请实施例一电容检测电路的示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请利用多个差分放大器以及多个差分放大器与多个电极之间的连接方式，以实现特定编码矩阵，并利用对应于该特定编码矩阵的解码矩阵，产生多个回复信号，以避免多个回复信号中噪声累积的问题。
具体来说，请参考图1，图1为本申请实施例一电子装置10的示意图，电子装置10可为智能手机、平板计算机等可进行触控操作或指纹辨识的电子装置。电子装置10包括一电容检测电路12以及一判断电路14，电容检测电路12包括电极Rx_0～Rx_3、差分放大器Amp_0～Amp_2以及一回复模块120。电极Rx_0～Rx_3用来传递对应于电极Rx_0～Rx_3 的电极信号R0～R3；差分放大器Amp_0～Amp_2耦接于电极Rx_0～Rx_3，用来产生差分输出信号Out0～Out2；回复模块120耦接于差分放大器Amp_0～Amp_2，用来根据差分输出信号Out0～Out2，产生对应于电极信号R1～R3的回复信号(Recovery Signal)R1’～R3’；判断电路14耦接于回复模块120，用来根据回复信号R1’～R3’，判断对应于电极Rx_1～Rx_3的电容大小。另外，于电子装置10中，差分放大器Amp_0～Amp_2的放大器个数为电极Rx_0～Rx_3的电极个数减去1。其中，回复模块120可利用RTL电路来实现。
详细来说，差分放大器Amp_0～Amp_2中任一差分放大器Amp_k具有一正输入端(标示有「+」号)以及一负输入端(标示有「－」号)，差分放大器Amp_k的正输入端耦接于电极Rx_0～Rx_3中多个第一电极，而差分放大器Amp_k的负输入端耦接于电极Rx_0～Rx_3中多个第二电极。例如，多个第一电极的个数与多个第二电极的个数相同，且多个第一电极的个数(或多个第二电极的个数)为电极Rx_0～Rx_3的电极个数的一半。换句话说，差分放大器Amp_k的负输入端耦接于电极Rx_0～Rx_3中一半的电极，而差分放大器Amp_k的正输入端耦接于电极Rx_0～Rx_3中另一半的电极。举例来说，如图1所示，差分放大器Amp_0的负输入端可耦接于电极Rx_0、Rx_1，而差分放大器Amp_0的正输入端可耦接于电极Rx_2、Rx_3，在此情形下，电极Rx_0、Rx_1(对应多个第一电极)即为电极Rx_0～Rx_3中一半的电极，而电极Rx_2、Rx_3(对应多个第二电极)即为电极Rx_0～Rx_3中另一半的电极。差分放大器Amp_1的负输入端可耦接于电极Rx_0、Rx_2，而差分放大器Amp_1的正输入端可 耦接于电极Rx_1、Rx_3，在此情形下，电极Rx_0、Rx_2(对应多个第一电极)即为电极Rx_0～Rx_3中一半的电极，而电极Rx_1、Rx_3(对应多个第二电极)即为电极Rx_0～Rx_3中另一半的电极。同样地，差分放大器Amp_2的负输入端可耦接于电极Rx_0、Rx_3，而差分放大器Amp_2的正输入端可耦接于电极Rx_1、Rx_2，在此情形下，电极Rx_0、Rx_3(对应多个第一电极)即为电极Rx_0～Rx_3中一半的电极，其中电极Rx_1、Rx_2(对应多个第二电极)即为电极Rx_0～Rx_3中另一半的电极。
另一方面，电极Rx_0～Rx_3中一电极Rx_j皆耦接于差分放大器Amp_0～Amp_2中所有的差分放大器，更进一步地，电极Rx_j可耦接于差分放大器Amp_0～Amp_2中一部分差分放大器的负输入端，且耦接于差分放大器Amp_0～Amp_2中另一部分差分放大器的正输入端。举例来说，如图1所示，电极Rx_1可耦接于差分放大器Amp_0的负输入端且耦接于差分放大器Amp_1、Amp_2的正输入端，在此情形下，差分放大器Amp_0可视为差分放大器Amp_0～Amp_2中一部分的差分放大器，而差分放大器Amp_1、Amp_2可视为差分放大器Amp_0～Amp_2中另一部分的差分放大器。电极Rx_2可耦接于差分放大器Amp_1的负输入端且耦接于差分放大器Amp_0、Amp_2的正输入端，在此情形下，差分放大器Amp_1可视为差分放大器Amp_0～Amp_2中一部分的差分放大器，而差分放大器Amp_0、Amp_2可视为差分放大器Amp_0～Amp_2中另一部分的差分放大器。同样地，电极Rx_3可耦接于差分放大器Amp_2的负输入端且耦接于差分放大器Amp_0、Amp_1的正输入端，在此情形下，差分放大器Amp_2可视为差分放大器Amp_0～Amp_2中一部分的差分放大器， 而差分放大器Amp_0、Amp_1可视为差分放大器Amp_0～Amp_2中另一部分的差分放大器。另外，电极Rx_0可耦接于差分放大器Amp_0～Amp_2的负输入端。也就是说，电极Rx_0～Rx_3中每一电极皆耦接于差分放大器Amp_0～Amp_2中所有的差分放大器。
在此情形下，差分输出信号Out0～Out2与电极信号R0～R3之间的对应关系可以一编码矩阵(Encoding Matrix)D1来描述。详细来说，以图1所示的实施例为例，差分输出信号Out0可表示为Out0＝Av(R0+R1－R2－R3)+n0，差分输出信号Out1可表示为Out1＝Av(R0+R2－R1－R3)+n1，差分输出信号Out2可表示为Out2＝Av(R0+R3－R1－R2)+n2，其中Av代表差分放大器Amp_0～Amp_2的增益(为求简洁，增益Av可假设为1)，n0、n1、n2分别代表差分放大器Amp_0、Amp_1、Amp_2内部的噪声(以及消除共模噪声后的残存噪声)。换句话说，在假设增益Av为1的情况下，差分输出信号Out0～Out2与电极信号R0～R3之间的对应关系可表示为公式1，其中编码矩阵D1可表示为公式2(如下所示)。需注意的是，编码矩阵D1中每一个元素(Entry)的值为+1或－1，更进一步地，编码矩阵D1中每一行(Row)中，其值为+1的多个行元素(Row Entry)的个数与其值为－1的多个行元素的个数相等，换句话说，编码矩阵D1中每一行包含多个行元素，多个行元素包含多个第一行元素以及多个第二行元素，多个第一行元素代表其值为+1的行元素，多个第二行元素代表其值为－1的行元素，多个第一行元素与多个第二行元素个数相等，即多个第一行元素的个数等于多个第二行元素的个数。
Figure PCTCN2017070683-appb-000001
Figure PCTCN2017070683-appb-000002
另一方面，回复模块120可根据差分输出信号Out0～Out2，产生回复信号R1’～R3’。于一实施例中，回复模块120可以电极信号R0‐为一参考值，并计算回复信号R1’为R1’＝R0－0.5*(Out1+Out2)，即根据0.5*(Out1+Out2)取得回复信号R1’，回复信号R1’即代表/相关于电极信号R1相对于电极信号R0的值，同样地，回复模块120可计算回复信号R2’为R2’＝R0－0.5*(Out0+Out2)，并计算回复信号R3’为R3’＝R0－0.5*(Out0+Out1)，也就是说，回复模块120可根据0.5*(Out0+Out2)取得回复信号R2’，根据0.5*(Out0+Out1)取得回复信号R3’，其中回复信号R2’、R3’代表/相关于电极信号R2、R3相对于电极信号R0的值，换句话说，回复模块120可根据差分输出信号Out1、Out2取得回复信号R1’，根据差分输出信号Out0、Out2取得回复信号R2’，并根据差分输出信号Out0、Out1取得回复信号R3’。
在此情形下，差分输出信号Out0～Out2及电极信号R0‐与回复信号R1’～R3’之间的对应关系可利用对应于编码矩阵D1的一解码矩阵(Decoding Matrix)D1 -1来描述，如公式3所示，其中解码矩阵D1 -1可表示为公式4。需注意的是，解碼矩阵D1 -1的第k行包含一个其值为1的行 元素以及二个其值为－0.5的行元素，除此之外，解码矩阵D1 -1第k行的其余行元素的值为0，其中k为1至3的整数。换句话说，解碼矩阵D1 -1的第k行包含一第一行元素、一第二行元素以及一第三行元素，第一行元素及第二行元素的值为－0.5，第三行元素的值为1，而解碼矩阵D1 -1第k行的其余行元素的值为0，另外，第三行元素于第k行中的位置对应于公式3中向量[Out0 Out1 Out2 R0]T中R0的位置。如此一来，回复信号R1’、R2’、R3’可表示为R1’＝R1－0.5(n1+n2)(公式5)、R2’＝R2－0.5(n0+n2)(公式6)、R3’＝R3－0.5(n0+n1)(公式7)。由公式5～7可知，噪声n0、n1、n2不会累积在某个特定回复信号中。另外，在n0～n2能量相等的情况下，回复信号R1’、R2’、R3’受到噪声影响的程度是相当的。
Figure PCTCN2017070683-appb-000003
Figure PCTCN2017070683-appb-000004
简言之，电容检测电路12利用差分放大器Amp_0～Amp_2以及差分放大器Amp_0～Amp_2与电极Rx_0～Rx_3之间的连接方式(即利用编码矩阵D1)，消除电极Rx_0～Rx_3中的共模噪声，更进一步地，电容检测电路12利用解码矩阵D1 -1，避免噪声n0、n1、n2累积在某个特定回复信号中，而解决现有技术中噪声累积的问题。
然而，回复信号R1’、R2’、R3’仍然会受到噪声的影响。为了进一步提升信噪比(Signal-to-Noise Ratio，SNR)，可适当设计编码矩阵及解码矩阵，使得回复模块可在产生回复信号/译码的过程中，将噪声相互抵销，进一步降低噪声对回复信号的影响。
具体来说，请参考图2，图2为本申请实施例一电容检测电路22的示意图，电容检测电路22与电容检测电路12类似，故相同组件沿用相同符号。与电容检测电路12不同的是，电容检测电路22包含一差分放大器Amp_3以及一回复模块220(差分放大器Amp_0～Amp_3的放大器个数与电极Rx_0～Rx_3的电极个数相同)，另外，电容检测电路22中电极与差分放大器之间的连接关系与电容检测电路12中电极与差分放大器之间的连接关系不同。详细来说，差分放大器Amp_2的负输入端耦接于电极Rx_1、Rx_2，差分放大器Amp_2的正输入端耦接于电极Rx_0、Rx_3，差分放大器Amp_3的负输入端耦接于电极Rx_1、Rx_3，差分放大器Amp_3的正输入端耦接于电极Rx_0、Rx_2。同样地，差分放大器Amp_0～Amp_3中任一差分放大器Amp_k的负输入端耦接于电极Rx_0～Rx_3中一半的电极，而差分放大器Amp_k的正输入端耦接于电极Rx_0～Rx_3中另一半的电极。
另一方面，于电容检测电路22中，电极Rx_0～Rx_3中任一电极Rx_j耦接于差分放大器Amp_0～Amp_3中一部分差分放大器的负输入端，且耦接于差分放大器Amp_0～Amp_3中另一部分差分放大器的正输入端。举例来说，如图2所示，电极Rx_0可耦接于差分放大器Amp_0、Amp_1的负输入端且耦接于差分放大器Amp_2、Amp_3的正输入端，电极Rx_1 可耦接于差分放大器Amp_0、Amp_2、Amp_3的负输入端且耦接于差分放大器Amp_1的正输入端，电极Rx_2可耦接于差分放大器Amp_1、Amp_2的负输入端且耦接于差分放大器Amp_0、Amp_3的正输入端，电极Rx_3可耦接于差分放大器Amp_3的负输入端且耦接于差分放大器Amp_0、Amp_1、Amp_2的正输入端。换句话说，电极Rx_0～Rx_3中每一电极皆耦接于差分放大器Amp_0～Amp_3中所有的差分放大器。
另外，对应于电容检测电路22的一编码矩阵D2与对应于电容检测电路12的编码矩阵D1不同，且回复模块220用来产生回复信号R1’～R3’的一解码矩阵D2 -1与回复模块120用来产生回复信号R1’～R3’的解碼矩阵D1 -1亦不同。简单来说，于电容检测电路22中，差分输出信号Out0～Out3与电极信号R0～R3之间的对应关系可表示为公式8，编码矩阵D2可表示为公式9，差分输出信号Out0～Out2及电极信号R0‐与回复信号R1’～R3’之间的对应关系可表示为公式10，解码矩阵D2 -1可表示为公式11。如公式10所示，回复模块220可计算回复信号R1’为R1’＝R0+0.5*(Out2－Out1)，换句话说，回复模块220可先将差分输出信号Out2与差分输出信号Out1相减，将差分输出信号Out2与差分输出信号Out1‐的相减结果乘以0.5，並根據0.5倍的相减结果取得回复信号R1’，回复信号R1’即代表/相关于电极信号R1相对于电极信号R0的值，同样地，回复模块220可计算回复信号R2’为R2’＝R0+0.5*(Out2－Out0)，计算回复信号R3’为R3’＝R0+0.5*(Out3－Out0)，也就是说，回复模块220可根据0.5*(Out2－Out0)取得回复信号R2’，根据0.5*(Out3－Out0)取得回复信号R3’，其中回复信号R2’、R3’代表/相关于电极信号R2、R3相对于电 极信号R0的值，换句话说，回复模块220可根据差分输出信号Out1、Out2取得回复信号R1’，根据差分输出信号Out0、Out2取得回复信号R2’，并根据差分输出信号Out0、Out3取得回复信号R3’。
Figure PCTCN2017070683-appb-000005
Figure PCTCN2017070683-appb-000006
Figure PCTCN2017070683-appb-000007
Figure PCTCN2017070683-appb-000008
如此一来，回复信号R1’、R2’、R3’可表示为R1’＝R1+0.5(n2－n1)(公式12)、R1+0.5(n2－n0)(公式13)、R1+0.5(n3－n0)(公式14)。另外，在n0＝n1＝n2＝n的情况下，根据公式12～14，回复信号R1’、R2’、R3’中的噪声将可进一步被消除，因此可降低噪声对回复信号的影响，而提升信噪比。
需注意的是，前述实施例用以说明本申请之概念，本领域技术人员当可据以做不同之修饰，而不限于此。举例来说，回复模块不限于以RTL电路来实现，本申请的回复模块亦可利用一处理器来产生/计算回复信号，即可以软件的方式来实现对应于回复模块的功能。另外，电容检测电路12以及电容检测电路22皆包含4个电极，而不在此限，本申请的电容检测电路可包含N个电极以及N个差分放大器，只要N为2的倍数，即满足本申请的需求。更进一步地，当电容检测电路包含6个电极时(即N＝6)，对应于N＝6的一编码矩阵D3以及一解码矩阵D3 -1可表示为公式15及公式16；而当电容检测电路包含8个电极时(即N＝8)，对应于N＝8的一编码矩阵D4以及一解码矩阵D4 -1可表示为公式17及公式18。需注意的是，由公式15、17可知，编码矩阵D3及编码矩阵D4的每一行中其值为+1的行元素与其值为－1的行元素个数相等。由公式16、18可知，解碼矩阵D3 -1及解碼矩阵D4 -1的第k行(k≥1)包含一个其值为－0.5的行元素、一个其值为0.5的行元素以及一个其值为1的行元素，而解码矩阵D3 -1及解碼矩阵D4 -1的第k行其余行元素的值为0。本领域技术人员应可根据编码矩阵D3、编码矩阵D4实现本申请电容检测电路中多个差分放大器与多个电极之间的连接方式，利用回复模块并根据解码矩阵D3 -1、解码矩阵D4 -1产生回复信号，而属于本申请的范畴。
Figure PCTCN2017070683-appb-000009
Figure PCTCN2017070683-appb-000010
Figure PCTCN2017070683-appb-000011
Figure PCTCN2017070683-appb-000012
另外，请参考图3，图3为本申请实施例一电容检测电路32的示意图，电容检测电路32与电容检测电路22类似，故相同组件沿用相同符号。与电容检测电路22不同的是，电容检测电路32另包含一参考电压产生器VGref以及一参考放大器Amp_4，参考电压产生器VGref耦接于差分放大器Amp_0～Amp_3的负输入端且耦接于参考放大器Amp_4的正输入端，另外，电极Rx_0～Rx_3耦接于参考放大器Amp_4的负输入端，亦属于本申请的范畴。
另外，请参考图5，图5为本申请实施例一电容检测电路52的示意图，电容检测电路52包含电极Rx_0～Rx_N、差分放大器Amp_0～Amp_K、一切换单元522以及一回复模块520，切换单元522耦接于电极Rx_0～Rx_N与差分放大器Amp_0～Amp_K，切换单元522受控于一控制信号ctrl而切换电极Rx_0～Rx_N与差分放大器Amp_0～Amp_K之间的连接关系，只要差分放大器Amp_k的正输入端耦接于电极Rx_0～Rx_N中多个第一电极且差分放大器Amp_k的负输入端耦接于电极Rx_0～Rx_N中多个第二电极，即满足本申请的要求而属于本申请的范畴。
另外，本申请的电容检测电路不限于包括多个差分放大器，本申请的电容检测电路可仅包括单一个差分放大器，只要通过切换单元将特定电极信号于不同时间传递至该差分放大器，即该差分放大器于不同时间依序地(Sequentially)输出多个差分输出信号，亦满足本申请的要求而属于本申请的范畴。
由上述可知，本申请利用多个差分放大器以及多个差分放大器与多个电极之间的连接方式(实现特定编码矩阵)，以消除多个电极中的共模 噪声，并利用对应于该特定编码矩阵的解码矩阵，产生对应于多个电极信号的多个回复信号，使得多个回复信号中不会有噪声累积的问题。另外，本申请可进一步消除回复信号中的噪声，进一步提升整体信噪比。
以上所述仅为本申请的部分实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (22)

  1. 一种电容检测电路，所述电容检测电路包括：
    多个电极，用来传递多个电极信号，其中所述多个电极具有一电极个数；
    至少一差分放大器，耦接于所述多个电极，用来产生多个差分输出信号，其中每一差分放大器具有一第一输入端及一第二输入端，所述至少一差分放大器具有一放大器个数；以及
    一回复模块，耦接于所述至少一差分放大器，用来根据所述多个差分输出信号，产生对应于所述多个电极信号的多个回复信号，其中多个回复信号相关于所述多个电极的电容大小；
    其中，所述至少一差分放大器中一差分放大器的所述第一输入端耦接于多个电极中多个第一电极，所述差分放大器的所述第二输入端耦接于多个电极中多个第二电极。
  2. 如权利要求1所述的电容检测电路，其中，所述多个第一电极为所述多个电极中一半的电极，所述多个第二电极为所述多个电极中另一半的电极。
  3. 如权利要求1所述的电容检测电路，其中，所述至少一差分放大器中每一差分放大器的所述第一输入端耦接于所述多个电极中一半的电极，所述每一差分放大器的所述第二输入端耦接于所述多个电极中另一半的电极。
  4. 如权利要求1所述的电容检测电路，其中，所述多个电极中一电极耦接于所述至少一差分放大器中所有的差分放大器。
  5. 如权利要求4所述的电容检测电路，其中，所述电极耦接于所述至少一差分放大器中一部分的差分放大器的所述第一输入端。
  6. 如权利要求5所述的电容检测电路，其中，所述电极耦接于所述至少一差分 放大器中另一部分的差分放大器的所述第二输入端。
  7. 如权利要求1所述的电容检测电路，其中，所述多个电极中每一电极耦接于所述至少一差分放大器中所有的差分放大器。
  8. 如权利要求1所述的电容检测电路，其中，所述多个差分输出信号与所述多个电极信号之间的对应关系相关于一第一矩阵运算，所述第一矩阵运算相关于一第一编码矩阵，所述编码矩阵具有多个元素，每一元素的值为+1或－1。
  9. 如权利要求8所述的电容检测电路，其中，所述编码矩阵具有多个行，所述多个行的一行具有多个行元素，所述多个行元素包含多个第一行元素以及多个第二行元素，所述多个第一行元素的值为+1，所述多个第二行元素的值为－1，所述多个第一行元素的一第一个数与所述多个第二行元素的一第二个数相等。
  10. 如权利要求1所述的电容检测电路，其中，所述回复模块计算所述多个差分输出信号中一第一差分输出信号与一第二差分输出信号的一相加结果，并根据所述相加结果计算所述多个回复信号中一第一回复信号。
  11. 如权利要求10所述的电容检测电路，其中，所述回复模块将所述相加结果乘以一特定值后，并根据所述相加结果与所述特定值的一相乘结果，取得所述第一回复信号。
  12. 如权利要求11所述的电容检测电路，其中，所述特定值为0.5。
  13. 如权利要求1所述的电容检测电路，其中，所述回复模块对包含所述多个差分输出信号的一第二向量进行一第二矩阵运算，所述第二矩阵运算相关于一第二解码矩阵，所述第二解碼矩阵具有多个行，所述多个行的一行具有多个行元素，所述行中所述多个行元素包含一第一行元素、一第二行元素以及一第三行元素，所述第一行元素及所述第二行元素的值为－0.5，所述第三行元素的值 为1，所述多个行元素除了所述第一行元素、所述第二行元素以及所述第三行元素以外，其余行元素的值为0。
  14. 如权利要求1所述的电容检测电路，其中，所述回复模块计算所述多个差分输出信号中一第三差分输出信号与一第四差分输出信号的一相减结果，并根据所述相减结果计算所述多个回复信号中一回复信号。
  15. 如权利要求14所述的电容检测电路，其中，所述回复模块将所述相减结果乘以一特定值后，并根据所述相减结果与所述特定值的一相乘结果，取得所述回复信号。
  16. 如权利要求15所述的电容检测电路，其中，所述特定值为0.5。
  17. 如权利要求1所述的电容检测电路，其中，所述回复模块对包含所述多个差分输出信号的一第三向量进行一第三矩阵运算，所述第三矩阵运算相关于一第三解码矩阵，所述第三解碼矩阵具有多个行，所述多个行的一行具有多个行元素，所述行中所述多个行元素包含一第四行元素、一第五行元素以及一第六行元素，所述第四行元素的值为－0.5，所述第五行元素的值为+0.5，所述第六行元素的值为1，所述多个行元素中除了所述第四行元素、所述第五行元素以及所述第六行元素以外，其余行元素的值为0。
  18. 如权利要求1所述的电容检测电路，其中，另包括一参考电压产生器以及一参考放大器，所述参考电压产生器耦接于所述参考放大器以及所述至少一差分放大器，所述参考放大器耦接于所述多个电极。
  19. 如权利要求1所述的电容检测电路，其中，所述电极个数为2的倍数。
  20. 如权利要求1所述的电容检测电路，其中，所述放大器个数为所述电极个数减1。
  21. 如权利要求1所述的电容检测电路，其中，所述放大器个数等于所述电极个数。
  22. 一种电子装置，包括：
    一电容检测电路，所述电容检测电路为权利要求1-21中任意一项所述的电容检测电路；以及
    一判断电路，耦接于所述电容检测电路，用来根据所述多个回复信号，判断对应于所述多个电极的电容大小。
PCT/CN2017/070683 2017-01-09 2017-01-09 电容检测电路及电子装置 WO2018126490A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2017/070683 WO2018126490A1 (zh) 2017-01-09 2017-01-09 电容检测电路及电子装置
CN201780000032.3A CN108700976B (zh) 2017-01-09 2017-01-09 电容检测电路及电子装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2017/070683 WO2018126490A1 (zh) 2017-01-09 2017-01-09 电容检测电路及电子装置

Publications (1)

Publication Number Publication Date
WO2018126490A1 true WO2018126490A1 (zh) 2018-07-12

Family

ID=62788895

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/070683 WO2018126490A1 (zh) 2017-01-09 2017-01-09 电容检测电路及电子装置

Country Status (2)

Country Link
CN (1) CN108700976B (zh)
WO (1) WO2018126490A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110037708A1 (en) * 2009-08-11 2011-02-17 Yang jun-wei Touch panel device having high touch sensitivity and touch positioning method thereof
CN104750330A (zh) * 2013-12-31 2015-07-01 乐金显示有限公司 触摸感测系统
CN105283827A (zh) * 2013-09-27 2016-01-27 株式会社和冠 位置检测装置
CN106020559A (zh) * 2016-06-30 2016-10-12 华为技术有限公司 压力感应检测装置、电子设备与触摸显示屏

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102207193B1 (ko) * 2013-12-31 2021-01-26 엘지디스플레이 주식회사 터치 센싱 시스템

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110037708A1 (en) * 2009-08-11 2011-02-17 Yang jun-wei Touch panel device having high touch sensitivity and touch positioning method thereof
CN105283827A (zh) * 2013-09-27 2016-01-27 株式会社和冠 位置检测装置
CN104750330A (zh) * 2013-12-31 2015-07-01 乐金显示有限公司 触摸感测系统
CN106020559A (zh) * 2016-06-30 2016-10-12 华为技术有限公司 压力感应检测装置、电子设备与触摸显示屏

Also Published As

Publication number Publication date
CN108700976B (zh) 2021-06-15
CN108700976A (zh) 2018-10-23

Similar Documents

Publication Publication Date Title
US10949032B2 (en) Circuit, touch chip, and electronic device for capacitance detection
WO2018076343A1 (zh) 电容检测装置、方法和压力检测系统
Park et al. A pen-pressure-sensitive capacitive touch system using electrically coupled resonance pen
US10324573B2 (en) Sensing devices for sensing electrical characteristics
US20200210008A1 (en) Touch Sensing Device And Display Apparatus Including The Same
US10474291B2 (en) Driving device and device method
WO2024159907A1 (zh) 一种触控检测电路和方法、触控芯片及显示装置
CN111902801B (zh) 电容检测电路、触控芯片和电子设备
CN110347282B (zh) 噪声抑制电路
US11326907B2 (en) Circuit and method for capacitance detection, touch chip and electronic device
WO2021243532A1 (zh) 电容检测电路、触控芯片和电子设备
WO2018126490A1 (zh) 电容检测电路及电子装置
US20220261104A1 (en) Distributed analog display noise suppression circuit
US11216113B2 (en) Touch circuit
US11630540B2 (en) Analog front end circuit with noise cancellation
CN116155214A (zh) 信号放大电路、触控芯片和电子设备
US11429233B2 (en) Common mode noise suppression with restoration of common mode signal
CN111399704B (zh) 电容检测电路、触控芯片和电子设备
US10606409B2 (en) Method of processing sensing signals and related processor
US20170199613A1 (en) Touch screen controller
Seong et al. Alternating panel charge sharing technique for touch screen panel self‐capacitance sensing IC
US20200210020A1 (en) Touch sensing device and display apparatus including the same
CN107078705B (zh) 差分电路
WO2022188316A1 (zh) 触摸屏显示器的处理电路、数据处理方法和判断触摸事件的方法
US20230393693A1 (en) Capacitive sensing device and capacitive sensing method

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17890294

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17890294

Country of ref document: EP

Kind code of ref document: A1