WO2018126459A1 - Circuit de mesure de capacité et dispositif électronique - Google Patents

Circuit de mesure de capacité et dispositif électronique Download PDF

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Publication number
WO2018126459A1
WO2018126459A1 PCT/CN2017/070492 CN2017070492W WO2018126459A1 WO 2018126459 A1 WO2018126459 A1 WO 2018126459A1 CN 2017070492 W CN2017070492 W CN 2017070492W WO 2018126459 A1 WO2018126459 A1 WO 2018126459A1
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WO
WIPO (PCT)
Prior art keywords
detecting circuit
impedance
capacitance detecting
coupled
electrodes
Prior art date
Application number
PCT/CN2017/070492
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English (en)
Chinese (zh)
Inventor
陈圣凯
文亚南
杨富强
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2017/070492 priority Critical patent/WO2018126459A1/fr
Priority to CN201780000370.7A priority patent/CN109496290A/zh
Publication of WO2018126459A1 publication Critical patent/WO2018126459A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means

Definitions

  • the present application relates to a capacitance detecting circuit and an electronic device, and more particularly to a capacitance detecting circuit and an electronic device capable of canceling external impedance and eliminating common mode noise.
  • the operational interfaces of various electronic products have gradually become more humanized in recent years.
  • the user can directly operate on the screen with a finger or a stylus, input information/text/pattern, and save the trouble of using an input device such as a keyboard or a button.
  • the touch screen usually consists of a sensing panel and a display disposed behind the sensing panel.
  • the electronic device judges the meaning of the touch according to the position touched by the user on the sensing panel and the picture presented by the display at the time, and executes the corresponding operation result.
  • a primary object of some embodiments of the present invention is to provide a capacitance detecting circuit and an electronic device that can cancel external impedance and eliminate common mode noise to improve the disadvantages of the prior art.
  • the present application provides a capacitance detecting circuit coupled to a plurality of transmitting electrodes and a plurality of receiving electrodes, the capacitance detecting circuit including a driving circuit coupled to the plurality of transmitting electrodes, Generating a driving signal to the plurality of transmitting electrodes, wherein the plurality of transmitting electrodes and the plurality of receiving electrodes have a plurality of external impedances; an impedance unit coupled to the driving circuit for receiving Driving the signal and generating a plurality of dummy electrode signals, wherein the impedance unit is formed with a plurality of internal impedances, the plurality of virtual electrode signals are related to the plurality of internal impedances; and a plurality of first amplifiers, each The first amplifier has a first input end and a second input end, and the first input end of the plurality of first amplifiers is coupled to the plurality of receiving electrodes, the plurality of first amplifiers The second input end is coupled to the impedance unit, and the
  • the impedance unit includes at least one capacitor; and at least one resistor coupled to the at least one capacitor, the at least one capacitor and the at least one resistor forming the plurality of internal impedances.
  • the impedance unit further includes an adjusting unit coupled to the at least one resistor for adjusting a resistance value of the at least one resistor such that an external impedance of the plurality of external impedances and the plurality of internal portions An impedance difference of an internal impedance of the impedance is less than a specific value.
  • the specific value is 0.4 times the external impedance.
  • the adjustment unit includes a storage unit, the storage unit stores a plurality of impedance adjustment values, and the adjustment unit adjusts a resistance value of the at least one resistor according to the plurality of impedance adjustment values.
  • the capacitance detecting circuit further includes a control logic circuit coupled to the memory unit, and the control logic circuit is controlled by a control unit for outputting the plurality of impedance adjustment values.
  • the storage unit is a Non-Volatile Memory (NVM).
  • NVM Non-Volatile Memory
  • the storage unit is a Volotile Memory.
  • the capacitance detecting circuit further includes at least one second amplifier coupled to the plurality of first amplifiers for canceling a common mode noise received by the plurality of transmitting electrodes (Common Mode) Noise) to generate at least one second output signal; wherein the at least one second output signal is related to the plurality of capacitance sizes between the plurality of transmitting electrodes and the plurality of receiving electrodes.
  • at least one second amplifier coupled to the plurality of first amplifiers for canceling a common mode noise received by the plurality of transmitting electrodes (Common Mode) Noise) to generate at least one second output signal; wherein the at least one second output signal is related to the plurality of capacitance sizes between the plurality of transmitting electrodes and the plurality of receiving electrodes.
  • the at least one second amplifier is a Programmable Gain Amplifier.
  • the capacitance detecting circuit further includes a duplexer coupled between the plurality of first amplifiers and the at least one second amplifier.
  • the capacitance detecting circuit further includes a control logic circuit coupled to the reworker, the control logic circuit is controlled by a control unit for controlling the reworker to A portion of the first output signal of the output signal is passed to an input of the at least one second amplifier.
  • the drive signal is an alternating current (AC) signal.
  • AC alternating current
  • the present application further provides an electronic device including a plurality of transmitting electrodes, a plurality of receiving electrodes, and a capacitance detecting circuit coupled to the plurality of transmitting electrodes and the plurality of receiving electrodes, wherein the capacitance detecting circuit includes a driving circuit.
  • the plurality of transmitting electrodes are coupled to the plurality of transmitting electrodes for generating a driving signal to the plurality of transmitting electrodes, wherein the plurality of transmitting electrodes and the plurality of receiving electrodes have a plurality of external impedances; an impedance unit, And coupled to the driving circuit, configured to receive the driving signal, and generate a plurality of virtual electrode signals, wherein the impedance unit is formed with a plurality of internal impedances, and the plurality of virtual electrode signals are related to the plurality of internal electrodes And a plurality of first amplifiers, each of the first amplifiers having a first input end and a second input end, the first input end of the plurality of first amplifiers being coupled to the plurality of receiving electrodes The second input end of the plurality of first amplifiers is coupled to the impedance unit, and the plurality of first amplifiers generate a plurality of first output signals; wherein the plurality of first Signals associated with the plurality of electrodes between the plurality of transfer electrodes receiving the pluralit
  • FIG. 1 is a schematic top view of an electronic device according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a capacitance detecting circuit according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of an impedance unit according to an embodiment of the present application.
  • FIG. 1 is a schematic top view of an electronic device 10 according to an embodiment of the present disclosure.
  • the electronic device 10 can be a touch-operated electronic device such as a smart phone, a tablet computer, a smart wearable device, or an in-vehicle display device.
  • the electronic device 10 includes transmission electrodes (or driving electrodes) TX_1 to TX_N, receiving electrodes RX_1 to RX_M, a capacitance detecting circuit 12, a flexible display panel 14, and a control unit 16.
  • the control unit 16 can be a microcontroller/microcontroller unit (MCU).
  • the flexible display 14 is used to display a picture to be displayed by the electronic device 10, which has flexibility.
  • the transmitting electrodes TX_1-TX_N and the receiving electrodes RX_1-RX_M are disposed on/in the flexible display screen 14.
  • the capacitance detecting circuit 12 is coupled to the transmitting electrodes TX_1-TX_N and the receiving electrodes RX_1-RX_M for detecting the transmitting electrodes TX_1-TX_N.
  • the size of the plurality of capacitors between the receiving electrodes RX_1 and RX_M to determine the position at which the touch occurs.
  • the capacitances corresponding to the transmitting electrodes TX_1 to TX_N and the receiving electrodes RX_1 to RX_M are larger than those of the conventional Rigid Type Panel (usually larger than the hard screen). Nearly 10 times).
  • the present application uses the impedance unit of the capacitance detecting circuit 12 to form between the transmitting electrodes TX_1-TX_N and the receiving electrodes RX_1-RX_M.
  • a plurality of internal impedances for canceling a plurality of external impedances between the transmitting electrodes TX_1-TX_N and the receiving electrodes RX_1-RX_M, wherein the plurality of external impedances include the transmitting electrodes TX_1-TX_N and the receiving electrodes RX_1-RX_M with respect to a ground terminal capacitance.
  • FIG. 2 is a schematic functional block diagram of a capacitance detecting circuit 12 according to an embodiment of the present disclosure.
  • the capacitor detecting circuit 12 includes a driving circuit 120, an impedance unit 122, a reworker 124, and a logic control circuit.
  • Logic Control Circuit 126 a front end circuit 128, a determination circuit 130, and an amplifier Amp and preamplifiers Amp_pre_1 to Amp_pre_M.
  • the logic control circuit 126 is coupled to the impedance unit 122 and the duplexer 124 for controlling the impedance unit 122 and the duplexer 124 according to the indication of the control unit 16.
  • the driving circuit 120 (via the duplexer 124) is coupled to the transmitting electrodes TX_1-TX_N for generating the driving signals tx1 to txN to the transmitting electrodes TX_1-TX_N, and the driving signals tx1-txN may be alternating currents (AC) having the same waveform.
  • the signal may be an alternating current signal such as a square wave, a triangular wave, a sine wave, or a trapezoidal wave.
  • a plurality of external impedances Z_ex are formed between the transmitting electrodes TX_1 to TX_N and the receiving electrodes RX_1 to RX_M. For convenience of explanation, FIG.
  • the impedance unit 122 is coupled to the driving circuit 120 for generating a plurality of virtual electrode signals rx1' to rxM' according to the driving signals tx1 to txN.
  • the impedance unit 122 can form a plurality of internal impedances, where the internal impedance refers to It is an impedance formed within the capacitance detecting circuit 12, and the virtual electrode signals rx1' to rxM' are related to a plurality of internal impedances.
  • Each of the preamplifiers Amp_pre_1 to Amp_pre_M has a first input terminal and a second input terminal. The first input terminals of the preamplifiers Amp_pre_1 to Amp_pre_M are coupled to the receiving electrodes RX_1 RXX_M to receive the electrode signals rx1 r rxM.
  • the second input ends of the amplifiers Amp_pre_1 ⁇ Amp_pre_M are coupled to the impedance unit 122 to receive the virtual electrode signals rx1 ′ rxm′.
  • the preamplifiers Amp_pre_1 to Amp_pre_M may be differential amplifiers for subtracting the electrode signals rx1 to rxM from the virtual electrode signals rx1' to rxM', respectively, to generate output signals Vo_pre_1 to Vo_pre_M, in other words,
  • the impedance unit 122 may form a plurality of internal impedances to cancel a plurality of external impedances between the transmitting electrodes TX_1 to TX_N and the receiving electrodes RX_1 to RX_M.
  • the impedance equivalent to the transfer electrode TX_j and the receive electrode RX_i is only (Z_ij_ex-Z_ij_in), in other words, when the true external impedance Z_ij_ex is large.
  • the impedance unit 122 can be utilized to form the internal impedance Z_ij_in to cancel the true external impedance Z_ij_ex such that the impedance seen at the output of the preamplifier Amp_pre_m (and its back end circuit) is only (Z_ij_ex-Z_ij_in).
  • a difference between the external impedance Z_ij_ex and the internal impedance Z_ij_in is less than 0.4 times the external impedance Z_ij_ex, ie Z_ij_ex-Z_ij_in ⁇ 0.4*Z_ij_ex.
  • this multiple relationship is only for illustration, and can be set to other values.
  • the equivalent circuit of the external impedance Z_ij_ex is as shown in FIG. 2.
  • the external impedance Z_ij_ex includes capacitors Cij, Cdg, Csg and resistors Rd, Rs, wherein the capacitance Cij represents the mutual capacitance between the transmitting electrode TX_j and the receiving electrode RX_i (Mutual Capacitance)
  • the capacitor Cdg represents the capacitance of the transmitting electrode TX_j to the ground
  • the capacitor Csg receives the capacitance of the electrode RX_i to the ground
  • the resistor Rd represents the equivalent resistance corresponding to the transmitting electrode TX_j
  • the resistor Rs represents the equivalent resistance corresponding to the receiving electrode RX_i.
  • FIG. 3 is a schematic diagram of an impedance unit 122 according to an embodiment of the present application.
  • the impedance unit 122 can form an internal impedance Z_ij_in.
  • the impedance unit 122 can include capacitors Cij', Cdg', Csg', resistors Rd', Rs', and an adjustment unit 30,
  • the adjusting unit 30 can be coupled to the resistors Rd', Rs' for adjusting the resistance values of the resistors Rd', Rs' such that the internal impedance Z_ij_in formed by the impedance unit 122 satisfies Z_ij_ex-Z_ij_in ⁇ 0.4*Z_ij_ex or other relationship.
  • the adjustment unit 30 includes a storage unit 32, which stores The storage unit 32 stores impedance adjustment values corresponding to the resistors Rd' and Rs', and the adjustment unit 30 adjusts the resistance values of the resistors Rd' and Rs' based on the impedance adjustment value.
  • the storage unit 32 can be a Non-Volatile Memory (NVM), which can be an electrically erasable programmable read only memory (EEPROM), fast.
  • NVM Non-Volatile Memory
  • EEPROM electrically erasable programmable read only memory
  • the impedance adjustment value may be stored in the memory unit 32 in advance (via the logic control circuit 126) to adjust the resistances Rd', Rs' in the internal impedance Z_ij_in.
  • the storage unit 32 can be a volatile memory (Volatile Memory), which can be a Synchronous Dynamic Random Access Memory (SDRAM), and the impedance adjustment value can be controlled by the control unit. 16 is generated and stored in the memory unit 32 by the logic control circuit 126 to adjust the resistors Rd', Rs' in the internal impedance Z_ij_in.
  • the front end circuit 128 may include an anti-alias filter (AAF), a band pass filter (BPF), and an analog-to-digital converter (Analog-to-Digital).
  • AAF anti-alias filter
  • BPF band pass filter
  • ADC analog-to-digital converter
  • the converter circuit (ADC) determines the size of the plurality of capacitors between the transmitting electrodes TX_1 to TX_N and the receiving electrodes RX_1 to RX_M according to the output signal of the analog-to-digital converter to determine the position at which the touch occurs.
  • the amplifier Amp can be a Programmable Gain Amplifier (PGA), and the amplifier Amp can be used to eliminate the common mode noise received by the receiving electrodes RX_1 ⁇ RX_M, wherein the common mode noise can come from the display noise of the flexible display screen 14 ( Such as LCD noise).
  • the amplifier Amp is coupled to the preamplifiers Amp_pre_1 to Amp_pre_M through the duplexer 124, and the duplexer 124 can transmit the K output signals of the output signals Vo_pre_1 to Vo_pre_M to the amplifier Amp to eliminate the receiving electrodes RX_1 to RX_M.
  • Common mode noise, where K can be a multiple of two.
  • the duplexer 124 can be controlled by the logic control circuit 126 (and the logic control circuit 126 can be controlled by the control unit 16), and K output signals whose channel characteristics/noise characteristics are similar, and K The output signal is passed to the amplifier Amp.
  • the semaphore can effectively eliminate the common mode noise, so that the operational amplifier in the amplifier Amp does not enter the saturated state due to noise, and fully utilizes a dynamic range of the analog-to-digital converter and improves Signal-to-Noise Ratio (SNR).
  • SNR Signal-to-Noise Ratio
  • the capacitance detecting circuit is not limited to include only one programmable gain amplifier.
  • the capacitance detecting circuit of the present application may include a plurality of programmable gain amplifiers, as long as the input end (through the duplexer) is coupled to the output of the preamplifier,
  • the Parallel Processing method eliminates common mode noise and also satisfies the requirements of the present application and falls within the scope of the present application.
  • the present application utilizes an impedance unit to form a plurality of internal impedances and utilizes a preamplifier to cancel a true plurality of external impedances between the transmitting and receiving electrodes.
  • the present application utilizes a duplexer (and logic control circuit) to select an output signal with similar channel characteristics/noise characteristics, and uses a programmable gain amplifier to eliminate common mode noise and amplify the touch signal to improve the signal to noise ratio.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Amplifiers (AREA)
  • Position Input By Displaying (AREA)

Abstract

L'invention concerne un circuit de mesure de capacité (12) comprenant : un circuit d'attaque (120) couplé à de multiples électrodes de transmission (TX_1-TX _N) et servant à générer un signal d'attaque (tx1-txN) pour les multiples électrodes de transmission (TX_1-TX_N) ; une unité d'impédance (122) couplée au circuit d'attaque (120) et servant à recevoir le signal d'attaque (tx1-txN) et à générer de multiples signaux d'électrode virtuelle (rx1 '-rxM''), de multiples impédances internes (Z_ij_in) étant formées dans l'unité d'impédance (122), les multiples signaux d'électrode virtuelle (rx1 '-rxM'') étant associés aux multiples impédances internes (Z_ij_in) ; et de multiples premiers amplificateurs (Amp_pre_1-Amp_pre _M) couplés à de multiples électrodes de réception (RX_1 ~ RX_M) et à l'unité d'impédance (122), de multiples premiers signaux de sortie (Vo_pre_1-Vo_pre _M) délivrés en sortie par les multiples premiers amplificateurs (Amp_pre_1-Amp_pre_M) étant associés aux amplitudes de multiples capacités (Cij) entre les multiples électrodes de transmission (TX_1-TX_N) et les multiples électrodes de réception (RX_1-RX_M).
PCT/CN2017/070492 2017-01-06 2017-01-06 Circuit de mesure de capacité et dispositif électronique WO2018126459A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2017/070492 WO2018126459A1 (fr) 2017-01-06 2017-01-06 Circuit de mesure de capacité et dispositif électronique
CN201780000370.7A CN109496290A (zh) 2017-01-06 2017-01-06 电容检测电路及电子装置

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PCT/CN2017/070492 WO2018126459A1 (fr) 2017-01-06 2017-01-06 Circuit de mesure de capacité et dispositif électronique

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102681743A (zh) * 2011-01-31 2012-09-19 发明元素股份有限公司 微量阻抗变化检测装置
CN103049158A (zh) * 2012-12-31 2013-04-17 深圳市汇顶科技股份有限公司 一种电容式触摸屏的触摸检测方法及系统
CN103150055A (zh) * 2013-02-07 2013-06-12 友达光电股份有限公司 触控芯片及采用此触控芯片的触控装置
CN104238846A (zh) * 2013-06-20 2014-12-24 财团法人工业技术研究院 触控装置及感测补偿方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8279180B2 (en) * 2006-05-02 2012-10-02 Apple Inc. Multipoint touch surface controller
TWI447625B (zh) * 2009-09-14 2014-08-01 Au Optronics Corp 電容式觸控偵測系統及其偵測訊號接收及波形整形模組

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102681743A (zh) * 2011-01-31 2012-09-19 发明元素股份有限公司 微量阻抗变化检测装置
CN103049158A (zh) * 2012-12-31 2013-04-17 深圳市汇顶科技股份有限公司 一种电容式触摸屏的触摸检测方法及系统
CN103150055A (zh) * 2013-02-07 2013-06-12 友达光电股份有限公司 触控芯片及采用此触控芯片的触控装置
CN104238846A (zh) * 2013-06-20 2014-12-24 财团法人工业技术研究院 触控装置及感测补偿方法

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