WO2018125118A1

WO2018125118A1 - Back-end ferroelectric field-effect transistor devices

Info

Publication number: WO2018125118A1
Application number: PCT/US2016/069121
Authority: WO
Inventors: Brian S. Doyle; Kevin P. O'brien; Ricky J. TSENG; Kaan OGUZ
Original assignee: Intel Corporation
Priority date: 2016-12-29
Filing date: 2016-12-29
Publication date: 2018-07-05

Abstract

Techniques are disclosed for forming integrated circuit (IC) devices that include ferroelectric field-effect transistors (FE-FETs) formed in the back end of the IC structure. The disclosed back-end FE-FET devices may be implemented with various materials that exhibit ferroelectric properties when processed at temperatures within the thermal budget of the back-end, and in some cases, an alloy of doped or undoped transition metal oxides may be used as the ferroelectric material. The disclosed back-end FE-FET devices may be able to provide comparable or improved ferroelectric performance relative to FE-FET devices formed during front-end processing. Additionally, as will be appreciated in light of this disclosure, the disclosed back-end FE-FET devices may also free up floor space in the front-end, thereby providing space for additional devices in the front-end.

Description

BACK-END FERROELECTRIC FIELD-EFFECT TRANSISTOR DEVICES

BACKGROUND

A field-effect transistor (FET) is a semiconductor device that includes a gate, a source and a drain. A FET uses an electric field applied by the gate to control the electrical conductivity of a channel through which charge carriers (e.g., electrons or holes) flow from the source to the drain.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates a cross-section view of a front-end ferroelectric field-effect transistor (FE-FET) structure implemented with silicon semiconductor material.

Figure 2 illustrates an example methodology for producing back-end FE-FET devices, in accordance with one or more embodiments of the present disclosure.

Figures 3A-3C illustrate example integrated circuit structures that may be formed when carrying out the method of Figure 2, in accordance with various embodiments of the present disclosure.

Figures 4A-4D illustrate example back-end FE-FET configurations, in accordance with one or more embodiments of the present disclosure.

Figure 5 illustrates an example integrated circuit (IC) structure that includes multiple back-end FE-FET devices, in accordance with one or more embodiments of the present disclosure.

Figure 6 illustrates an example computing system implemented with one or more integrated circuit structures or devices formed using the techniques disclosed herein, in accordance with various embodiments of the present disclosure.

As will be appreciated, the figures are not necessarily drawn to scale or intended to limit the disclosure to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of a structure may have less than perfect straight lines, right angles, and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used. In short, the figures are provided merely to show example structures.

DETAILED DESCRIPTION

Integrated circuit (IC) fabrication primarily includes two portions: the front-end or front-end-of-line (FEOL) and the back-end or back-end-of-line (BEOL). The front-end is formed during the first portion of IC fabrication and includes formation of individual semiconductor devices (e.g., logic transistors) and all processes up to deposition of metal interconnect layers. The front-end thus includes the device layer of the IC. The back-end is formed over the device layer during the second portion of IC fabrication when or more interconnect layers are produced (such as interconnect layers Ml through M9). In general, interconnect layers operatively connect the individual semiconductor devices of the device layer (the front-end) to contacts and other parts of the IC. The back-end may include any number of metallization layers, depending on target application or end use. As the back-end of an IC includes metallized materials, back-end processing temperatures are often constrained by the maximum temperature that the metallized materials present in the back-end can experience without degradation or other structural changes. This maximum temperature is sometimes referred to as the "thermal budget" of the back-end.

Techniques are disclosed for forming integrated circuit structures having ferroelectric field-effect transistor (FE-FET) structures in the back-end. The disclosed back-end FE-FET devices may include a ferroelectric layer formed of one or more materials that exhibit ferroelectric properties when deposited, annealed, or otherwise processed at temperatures within the thermal budget of the back-end. For example, the ferroelectric layer of an example back-end FE-FET device may exhibit ferroelectric properties at processing temperatures of less than 400°C, less than 300°C, or less than 200°C, in some embodiments. In some particular embodiments, the ferroelectric layer of the disclosed back-end FE-FET devices may be implemented with a transition metal oxide or one more transition metal oxides, such as an alloy of hafnium oxide and zirconium oxide. In some cases where the ferroelectric material of the back-end FE-FET device is an alloy of hafnium oxide and zirconium oxide, the alloy may include approximately equal atomic percentages of hafnium oxide and zirconium oxide while in other cases, the atomic percentages of hafnium oxide and zirconium oxide may be unequal, with either a greater amount of hafnium oxide or zirconium oxide present.

The disclosed back-end FE-FET devices may be formed on a semiconductor substrate in the back-end of the integrated circuit (IC) (at some position above the device layer and/or a metallization line of the IC). In some embodiments, the semiconductor substrate of the back-end FE-FET device includes a material having a crystal structure that is not monocrystalline. For example, in some cases, the semiconductor substrate of a back-end FE-FET device is formed of polycrystalline or amorphous silicon. In other embodiments, the semiconductor substrate of a back-end FE-FET device is formed of indium gallium zinc oxide (IGZO), a group III-V material, indium tin oxide (ITO), a complex oxide, or a transition metal dichalcogenide.

The disclosed back-end FE-FET devices may provide numerous benefits as compared to other FE-FET devices that are located in the front-end. For example, a FE-FET device located in the back-end of a device as opposed to the front-end of the device provides for increased space in the front-end that may be utilized for additional devices. As described below in detail, techniques are described for stacking two or more back-end FE-FET devices on top of one another, thereby doubling or, in some cases, tripling or quadrupling the cell count. The techniques variously described herein can thus provide increased cell density and versatility for implementation. Numerous other configurations and variations will be apparent in light of this disclosure. General Overview

As previously described, IC fabrication customarily includes two portions: the front- end or front-end-of-line (FEOL) and the back-end or back-end-of-line (BEOL). A distinguishing factor between the front-end and back-end portions of an IC is that back-end processing generally begins when individual devices formed during front-end processing become interconnected or otherwise routed for a circuit with wiring or other electrical conductors. Interconnect features of the back-end are generally formed of one or more metallization layers, each layer having one or more metal conductors including vias and lines within a dielectric layer or structure. Some interconnect layers may include both metal conductors and dielectric material, while others may include only dielectric material or only metal. As the interconnect features of the back-end are sometimes implemented with metal, back-end processing can have a relatively low or limited thermal budget (e.g., the back-end processing temperature may be limited to less than 500°C, less than 475°C, less than 450°C, less than 425°C, less than 400°C, less than 350°C, or less than 300°C).

Ferroelectrics are dielectric materials that show spontaneous electric polarization.

When an external electric field is applied to a ferroelectric, the direction of polarization may be altered. When used in a transistor, ferroelectrics can provide both memory and logic functions. For example, in ferroelectric transistors (FE-FETs), the direction of spontaneous polarization can used to store information by either switching or not switching polarization direction when a voltage is applied to the gate of the transistor, to signify either a "0" or a "1."

Many ferroelectric materials require processing temperatures above the thermal budget of the back-end. Accordingly, ferroelectric transistors (FE-FETs) are generally formed during front-end processing. Figure 1 illustrates the structure of an example front-end FE-FET device formed on a crystalline silicon semiconductor substrate, where silicon is used as the channel. Previous FE-FET devices formed during front-end processing occupy valuable floor space that could be used for housing additional devices. It would thus be highly advantageous to include FE-FET devices in the back-end to provide space for additional logic and/or memory features in the front-end, thereby increasing the density and functionality of the chip.

Back-end FE-FET devices have not previously been built, at least in part, due to difficulties in fabricating the ferroelectric material at temperatures within the thermal budget of the back-end (e.g., temperatures less than 400°C). Previously known ferroelectric materials, including lead zirconate titanate (PZT), barium titanium oxide (BTO) and barium strontium titanate (BST), each require deposition temperatures of approximately 700°C, which is far above the thermal budget of many back-ends. Even other ferroelectric materials that may be deposited at lower temperatures, such as doped hafnium oxide (Hf0₂), doped or undoped strontium (Sr), aluminum (Al), silicon (Si) and yttrium (Y), for example, generally require annealing temperatures above 600°C to change from insulator to ferroelectric. The processing temperatures of these materials are thus also above the back-end thermal budget of most devices.

In contrast, and in accordance with embodiments of the present disclosure, a back-end FE-FET device is configured with a ferroelectric material that exhibits ferroelectric properties when processed at temperatures within the thermal budget of the back-end. In accordance with these and other embodiments of the subject disclosure, one or more FE-FET devices may be formed during back-end processing of integrated circuit (IC) structures. The disclosed back-end FE-FET devices may be able to provide comparable or improved ferroelectric performance relative to FE-FET devices formed during front-end processing. Additionally, as will be further appreciated in light of this disclosure, the disclosed back-end FE-FET devices may also free up floor space in the front-end, thereby providing space for additional devices in the front-end.

From a structural viewpoint, integrated circuit (IC) structures that include the disclosed back-end FE-FET devices as provided herein may include various cross-section profiles. For example, in some embodiments, a semiconductor substrate may be formed in the back-end of the IC structure, for example, on or over a metallization line of the device. The semiconductor substrate of the disclosed back-end FE-FET devices, may, in some cases, be formed of polycrystalline or amorphous silicon. In some particular embodiments, one or more back-end

FE-FET devices may be positioned on or over a back-end FE-FET device. Numerous configurations and variations will be apparent in light of the subject disclosure. As will be apparent, the disclosed techniques may, in some embodiments, provide additional floor space in the front-end of a device and may, in some cases, provide increased memory density of the device.

Use of the techniques and structures provided herein may be detectable in cross- sections of an integrated circuit using tools such as scanning electron microscopy (SEM) or transmission electron microscopy (TEM) that can show the various layers and structure of the device. Other methods, such as composition mapping, x-ray crystallography or diffraction (XRD), secondary ion mass spectrometry (SFMS), time-of-flight SFMS (ToF-SFMS), atom probe imaging, local electrode atom probe (LEAP) techniques, 3D tomography, or high resolution physical or chemical analysis, to name some suitable example analytical tools may also be used to detect the techniques and structures provided herein. In some embodiments, for instance, a SEM may indicate a back-end FE-FET device formed in the back-end of an IC (e.g., above a metallized line). In some cases, chemical analysis of the ferroelectric material of the back-end FE-FET device may also reveal that a particular IC structure includes a FE-FET device, as presently described.

The semiconductor structures variously described herein may be suitable for numerous applications, such as the personal computers (PC), tablet computers, smartphones, test equipment, power management and communication applications, as well as power conversion and automotive applications, to name a few examples. The structure may be included in an integrated circuit chip or chip set, such as a system-on-chip (SOC). Numerous configurations and variations will be apparent in light of this disclosure. Architecture and Methodology

Figure 2 illustrates a method 100 of forming integrated circuit (IC) structures including back-end FE-FET devices, in accordance with one or more embodiments of the present disclosure. Figures 3A-3C illustrate example structures that may be formed when carrying out method 100 of Figure 2, in accordance with some embodiments. As will be appreciated in light of this disclosure, the disclosed techniques may be used to form various types of back-end FE- FET devices, and in some cases may be used to form numerous different types of transistors, such as MOSFETS, tunnel-FETs (TFETs), high-electron-mobility transistors (HEMTs), or other appropriate transistor architectures, depending on end use or target application. Also, in some embodiments, the techniques can be used to form integrated circuits having p-channel and/or n- channel transistor devices, such as p-channel MOSFET (PMOS), n-channel MOSFET ( MOS), p-channel TFET (PTFET), n-channel TFET (NTFET), p-channel HEMP (PHEMT), and/or n- channel HEMT ( HEMT), to name some examples.

As shown in Figure 2, method 100 includes providing 102 a substrate 200 to produce a structure as shown in Figure 3 A, in accordance with an example embodiment. Substrate 200 may be formed of any suitable semiconductor material, including group rV semiconductor materials such as silicon (Si), silicon carbide (SiC), sapphire, germanium (Ge), or silicon germanium (SiGe). In some embodiments, substrate 200 may be an X on insulator (XOI) structure where X comprises Si, Ge, SiC, SiGe, or sapphire, and the insulator material may be an oxide material, a dielectric material, some other electrically insulating material, or a multilayer structure where the top layer comprises Si, Ge, SiC, SiGe, or sapphire. In some embodiments where substrate 200 is implemented with silicon, the silicon may be single crystal silicon and in some cases may be prepared to expose a particular plane of its crystal structure as defined by a Miller index number. For example, in some embodiments, substrate 200 may include Si 111, Si 110, Si 100 with an off cut of between 2 to 8 degrees toward 110, or equivalents thereof. Substrate 200 may have any suitable thickness, such as a thickness in the range of 100 to 950 microns, in the case of a bulk substrate.

Method 100 of Figure 2 continues with optionally completing 104 front-end processing of the substrate 200. Completing 104 front-end processing can include various features, such as wafer preparation, isolation, well formation, gate patterning, spacer formation, extension, S/D implantation, silicide formation, dual stress liner formation, and/or forming any desired integrated circuit structures on substrate 200 using any appropriate lithography technique. In some embodiments, completing 104 front-end processing can include forming one or more transistors, capacitors, and/or resistors, etc. An example IC that includes both front-end-of-line (FEOL) and back-end-of-line (BEOL) regions is shown in Figure 3 A. As shown in Figure 3 A, the example FEOL region includes a logic transistor having a source, drain, gate and gate dielectric (e.g., a high-k gate dielectric), among other possible features. Although Figure 3A illustrates a SOI structure, in other embodiments, a bulk substrate may be used. The FEOL region of the disclosed IC structures may also include any other device or structure. Although contact features of the devices shown in the FEOL region are positioned in the FEOL region of Figure 3A, it is to be understood that these contact features may, in some embodiments, be formed during BEOL processing or processing that occurs between FEOL processing and BEOL processing, sometimes referred to as middle-of-the-line (MOL) processing. As shown in Figure 3A and in accordance some embodiments, a seal layer (for example, comprising silicon carbide, SiC) may be formed to isolate desired components of the front-end. Throughout the subject disclosure, the FEOL and BEOL may each be referred to simply as "front-end" and "back-end," respectively, for ease of discussion.

Method 100 of Figure 2 continues with optionally depositing 106 S/D metal feature(s) 202 to form a structure as shown in Figure 3 A, in accordance with an example embodiment. S/D metal features 202 may, in some embodiments, include a metal layer that contacts a desired electrically conducting feature, such as, for example, a bitline, and/or via. However, in other examples, S/D metal feature 202 may itself be a bitline and/or via. Although S/D metal features 202 are positioned underneath a semiconductor layer in the Figure 3C, it is to be understood that in some embodiments S/D metal features 202 may alternatively be positioned above the semiconductor layer, as described with respect to Figure 4C. S/D metal feature(s) 202 may be formed using, for example, a silicidation process (generally, deposition of contact metal and subsequent annealing). Example materials that may be used to form S/D metal features 202 include but are not limited to titanium, titanium nitride, aluminum, tungsten, titanium, tantalum, copper, palladium, platinum, ruthenium, silver, gold, tantalum nitride (TaN), or various suitable metals or metal alloys, for example. Figure 3 A illustrates an example integrated circuit structure that includes S/D metal feature(s) 202 surrounded by inter layer dielectric (ILD) material 204. If present, ILD material 204 may be implemented with any dielectric material, including various oxides, such as silicon dioxide, silicon nitride, or other spin-on dielectrics. ILD material 204 may have any desired thickness, such as less than 300 nm, less than 200 nm, less than 150 nm, or less than 100 nm, in accordance with some example embodiments. Any suitable deposition technique may be used to deposit ILD material 204 and/or S/D metal feature(s) 202, including chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any other appropriate process.

Method 100 of Figure 2 continues with forming 108 a semiconductor layer 206 to produce a structure as shown in Figure 3B, in accordance with some example embodiments. Semiconductor layer 206 may be implemented with any desired semiconductor material. In some embodiments, semiconductor layer 206 may comprise one or more of the following materials: silicon, such as polycrystalline silicon or amorphous silicon, indium gallium zinc oxide (IGZO), one or more group III-V materials, including group III material -nitride (III-N) compounds, such as low temperature poly III-V materials, including but not limited to indium tin oxide (ITO), complex oxides (chemical compounds containing oxygen and at least two other elements or containing oxygen and one other element that is in at least two oxidation states), and/or transition metal dichalcogenides (e.g., MoS₂, WS₂, MoSe₂, WSe₂, MoTe₂). Semiconductor layer 206 may have any desired thickness and in some embodiments semiconductor layer 206 has a thickness of less than, more than, or approximately 100 nm.

Method 100 of Figure 2 continues with depositing 110 a ferroelectric layer 208 on semiconductor layer 206 to produce a structure as shown in Figure 3C, in accordance with an example embodiment. Ferroelectric layer 208 may be formed of any material that exhibits ferroelectric properties. In some embodiments, ferroelectric layer 208 comprises a ferroelectric material that may be deposited and/or annealed at temperatures within the thermal budget of the back-end. For example, in some particular embodiments, the ferroelectric material of the ferroelectric layer 208 may exhibit ferroelectric properties after processing (e.g., deposition and/or annealing) at a temperature of less than 500°C, 475°C, 450°C, 425°C, 400°C, 375°C, 350°C, 325°C, 300°C, 275°C, 250°C, 225°C, or 200°C. In some particular embodiments, the ferroelectric material of ferroelectric layer 208 may exhibit ferroelectric properties when processed at a temperature less than 400°C but above 200°C.

Ferroelectric layer 208 may comprise, in some embodiments, one or more doped or undoped transition metal oxides. For example, in some embodiments, ferroelectric layer 208 may include doped or undoped hafnium oxide (Hf0₂) or zirconium oxide (Zr0₂). Ferroelectric layer 208 may, in some embodiments, comprise an alloy of at least two transition metal oxides. For example, in some particular example embodiments, ferroelectric layer 208 may be implemented with an alloy of hafnium oxide and zirconium oxide (Hf0₂/Zr0₂). In some specific embodiments, ferroelectric layer 208 may comprise an alloy having approximately equal atomic percentages of Hf0₂ and Zr0₂. In other embodiments, however, ferroelectric layer 208 may comprise an alloy of Hf0₂ and Zr0₂ in atomic percentage ratios ranging from between 1 :2 to 2: 1 Hf0₂ to Zr0₂. In various embodiments, ferroelectric layer 208 may comprise hafnium zirconium oxide (Hf₀ 5Zro_.50₂). In embodiments where ferroelectric layer 208 includes one or more dopants, the total weight percentage of dopants used may be less than 10%, less than 8%, less than 5%, less than 4%, less than 3%, less than 2% or less than 1% of the weight of the ferroelectric layer. In embodiments where ferroelectric layer 208 includes one or more dopants, any suitable type of dopant may be used, such as aluminum, silicon, yttrium, gadolinium, lanthanum, boron, gallium, indium, and/or tin, in some example embodiments. Numerous configurations and variations will be apparent to one of skill in the art.

The thickness of ferroelectric layer 208 may vary based on the end use or desired application. For example, in some embodiments, ferroelectric layer 208 may have a thickness of between 1 and 2 microns. Ferroelectric layer 208 may be deposited by any appropriate deposition process, such as by atomic layer deposition (ALD) or by physical vapor deposition (PVD). In some embodiments, for example, where ferroelectric layer 208 is formed by PVD, the ferroelectric material may optionally be re-annealed after deposition.

In some select embodiments, S/D regions of semiconductor layer 206 may be formed, if necessary. In various embodiments, semiconductor layer 206 does not include discrete S/D regions and instead operates as a type of Schottky barrier with S/D metal features 202 (e.g., metal contacts, bitlines, vias, or other metal structures) on semiconductor layer 206 forming the potential energy barrier for electrons or carriers. Figure 3C illustrates an example back-end FE- FET device that includes S/D metal features 202. It should be noted that semiconductor layer 206 in Figure 3C may be doped or undoped. In some embodiments, semiconductor layer 206 may be doped or undoped throughout or doped in one or more regions to form discrete S/D regions. In embodiments where at least a portion or all of semiconductor layer 206 is doped, semiconductor layer 206 may be doped by any appropriate process. For example, in some cases, semiconductor layer 206 may be exposed to chemicals, including dopants, through a chemical bath. In various embodiments, S/D regions may be formed in semiconductor layer 206 through ion implantation. In some embodiments where semiconductor layer 206 includes discrete S/D regions, the S/D regions may be formed via molecular doping that does not exceed the back-end thermal budget (such as a thermal budget of 400°C). In some cases, molecular doping processes may involve adhering a self-assembled monolayer to the surface of semiconductor layer 206 and driving the dopant material into semiconductor layer 206 at desired locations via a relatively low temperature anneal to form S/D regions within semiconductor layer 206. In some embodiments, S/D regions may be formed by removing a portion of semiconductor layer 206 and replacing it with appropriate S/D material. If doped, S/D regions may be p-type doped or n-type doped using any suitable dopant. Material used to form S/D regions may be doped prior to deposition, during deposition (in situ), or after deposition (ion implantation) to provide the desired polarity of p- type or n-type, in some particular embodiments. The doping may be graded within the deposited S/D material, in some embodiments. In some specific embodiments, semiconductor layer 206 is implemented with polycrystalline or amorphous silicon and the S/D material of the S/D regions may be, for example, silicon doped to form n-type S/D regions.

Method 100 of Figure 2 continues with forming 112 gate electrode 210 to produce a back-end FE-FET device 300 as shown in Figure 3C, in accordance with an example embodiment. Gate electrode 210 (generally referred to as 'gate') may be implemented with any appropriate material, including titanium nitride (TiN), polysilicon, silicon nitride, silicon carbide, or various suitable metals or metal alloys, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), or tantalum nitride, for example. Although not shown in Figure 3C, spacers may also be formed on either side of gate 210, if desired. If present, spacers may be formed of any suitable spacer material, including silicon nitride or silicon dioxide, or any other gate spacer material. It will be understood that although depicted linearly in Figure 3C, the components of the disclosed back-end FE-FET device 300 (e.g., substrate 206, ferroelectric layer 208, gate 210 and/or S/D metal features 202) may be non-linear, in some embodiments.

Method 100 of Figure 2 continues with optionally completing 114 additional back-end processing, in accordance with some example embodiments. For example, in some embodiments, additional back-end processing may include contact formation, formation of one or more wordlines or bitlines, and/or formation of additional back-end FE-FET devices.

Numerous variations on method 100 will be apparent in light of the present disclosure.

Additional Embodiments

As will be understood, the disclosed back-end FE-FET structures may be attached to bitlines and wordlines as shown, for example, in Figure 4 A. Figure 4 A illustrates S/D metal features 202 contacting bitlines, however, in other embodiments, bitlines may directly contact semiconductor layer 206 and S/D metal feature 202 may not be included. While Figure 4A illustrates a particular back-end FE-FET configuration where the bitlines are under semiconductor layer 206 and the wordline is above semiconductor layer 206, it is to be understood that various other FE-FET configurations may be produced. For example, Figure 4B shows an example back-end FE-FET configuration where the bitlines are above semiconductor layer 206 and the wordline is under semiconductor layer 206. In some embodiments, bitlines and wordlines may be on opposite sides of semiconductor layer 206, while in other embodiments, bitlines and wordlines may be on the same side of semiconductor layer 206. For example, Figure 4C shows an example back-end FE-FET configuration where both bitlines and the wordline are above semiconductor layer 206. Similarly, Figure 4D shows an example back- end FE-FET configuration where both bitlines and the wordline are under semiconductor layer 206. As shown in Figures 4C and 4D, vias may be used to position the bitlines as needed to avoid contacting other metal features, such as the wordline. Numerous configurations and variations will be apparent.

In some particular embodiments, one or more additional back-end FE-FET devices may be formed over an existing back-end FE-FET device. An example structure showing a back-end FE-FET device 300a with an additional back-end FE-FET device 300b positioned over it is shown in Figure 5. Figure 5 also shows example bitlines and wordlines that may be connected to the back-end FE-FET devices (300a and 300b). As shown in Figure 5, bitlines may be positioned under a back-end FE-FET device 300a and a wordline may be positioned above back- end FE-FET device 300a, contacting gate 210. It is to be understood that the arrangement of bitlines and wordlines shown in Figure 5 is merely representative of some example embodiments. For example, in other embodiments, the stack order may be reversed (with bitlines positioned above an example back-end FE-FET device 300 and wordline(s) below an example back-end FE-FET device 300. However, in other embodiments, bitlines and wordlines may both be positioned either above or below a back-end FE-FET device 300. As previously described, in some such example embodiments, S/D metal features may be extended to position the bitlines farther away from the semiconductor layer than the wordline in an effort to avoid undesirable electrical contact between bitlines and wordline(s). Numerous configurations and variations will be apparent in light of the subject disclosure.

As will be understood, an IC substrate 200 may be positioned at some layer below the structure depicted in Figure 5. When a back-end FE-FET device is positioned over another back-end FE-FET device, the cell count density may be effectively doubled. In some embodiments, more than one back-end FE-FET device (e.g., two, three, four, five, six, seven, eight, nine, ten, or more FE-FET devices) may be positioned over a back-end FE-FET device to further increase cell density. When one or more back-end FE-FET devices are stacked, each FE- FET device may have its own periphery that is specific to that FE-FET, or multiple FE-FETs may share the same sense amplifier, depending on the number of cells included in the bitline and the leakage of the cell in the unselected state.

In some embodiments, one or more other integrated circuit (IC) devices, such as various diodes (e.g., light-emitting diodes (LEDs) or laser diodes), various transistors (e.g., metal-oxide field-effect transistors (MOSFETs) or tunnel FETs (TFETs)), various microelectromechanical systems (MEMS), various nanoelectromechanical systems (NEMS), various sensors, or any other suitable semiconductor or IC devices, may also be formed on substrate 200, depending on the end use or target application. Accordingly, in some embodiments, back-end FE-FET devices as described herein may be included in various system- on-chip (SoC) applications, as will be apparent in light of the present disclosure.

Upon analysis (e.g., using scanning/transmission electron microscopy (SEM/TEM), composition mapping, secondary ion mass spectrometry (SEVIS), atom probe imaging, 3D tomography, etc.), a structure or device configured in accordance with one or more embodiments will effectively show the components of the disclosed back-end FE FET structures (e.g., back- end FE-FET devices comprising material that exhibits ferroelectric properties at temperatures within the thermal budget of back-end processing, such as an alloy of Hf0₂ and Zr0₂, in some particular examples).

Example System

Figure 6 illustrates a computing system 1000 implemented with integrated circuit structures or devices formed using the techniques disclosed herein, in accordance with various embodiments of the present disclosure. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc.

Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. In some embodiments, the communication chip 1006 is implemented with or otherwise includes one or more back-end FE-FET devices as variously described herein.

The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices (e.g., back-end FE-FETs) formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. As will be appreciated in light of this disclosure, note that multi -standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing system 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.

Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example 1 is an integrated circuit device that includes a semiconductor substrate, a device layer over the substrate including one or more metal oxide semiconductor (MOS) logic transistors and a ferroelectric field-effect transistor (FE-FET) device above the device layer that includes a ferroelectric layer and a gate electrode.

Example 2 includes the subject matter of Example 1 and further includes a FE-FET semiconductor substrate under or above the ferroelectric layer. Example 3 includes the subject matter of Example 2, wherein the FE-FET semiconductor substrate includes a material having a structure that is polycrystalline or amorphous.

Example 4 includes the subject matter of Example 3, wherein the FE-FET semiconductor substrate is selected from the group consisting of: polycrystalline silicon, amorphous silicon, indium gallium zinc oxide (IGZO), group III-V materials and indium tin oxide (ITO), a complex oxide, and transition metal dichalcogenides.

Example 5 includes the subject matter of any of Examples 1-4, wherein the ferroelectric layer includes a material capable of exhibiting ferroelectric properties at processing temperatures of less than 500°C.

Example 6 includes the subject matter of any of Examples 1-5, wherein the ferroelectric layer includes a material capable of exhibiting ferroelectric properties at processing temperatures of less than 400°C.

Example 7 includes the subject matter of any of Examples 1-6, wherein the ferroelectric layer comprises a material capable of exhibiting ferroelectric properties at a processing temperature of between 200°C and 400°C.

Example 8 includes the subject matter of any of Examples 1-7, wherein the ferroelectric layer includes a material selected from the group consisting of hafnium oxide, zirconium oxide and an alloy of hafnium oxide and zirconium oxide.

Example 9 includes the subject matter of Example 8, wherein the ferroelectric layer includes an alloy having alloy of hafnium oxide and zirconium oxide in atomic percentage ratios ranging from between 1 :2 to 2: 1 hafnium oxide and zirconium oxide.

Example 10 includes the subject matter of Example 9, wherein the alloy has an approximately equal atomic percentage of hafnium oxide and zirconium oxide. Example 11 includes the subject matter of any of Examples 1-10 and further includes an additional ferroelectric field-effect transistor (FE-FET) device including a ferroelectric layer positioned above the FE-FET device.

Example 12 includes the subject matter of Example 11, wherein the additional FE-FET device includes a FE-FET substrate including a material selected from the group consisting of: polycrystalline silicon, amorphous silicon, indium gallium zinc oxide (IGZO), group III-V materials and indium tin oxide (ITO), a complex oxide, and transition metal dichalcogenides.

Example 13 includes the subject matter of any of Examples 11-12, wherein the ferroelectric layer of the additional FE-FET device includes a material capable of exhibiting ferroelectric properties at processing temperatures of less than 500°C.

Example 14 includes the subject matter of any of Examples 11-13, wherein the ferroelectric layer of the additional FE-FET device includes a material capable of exhibiting ferroelectric properties at processing temperatures of less than 400°C.

Example 15 includes the subject matter of any of Examples 11-14, wherein the ferroelectric layer of the additional FE-FET device includes a material selected from the group consisting of hafnium oxide, zirconium oxide and an alloy of hafnium oxide and zirconium oxide.

Example 16 includes the subject matter of any of Examples 11-15, wherein the ferroelectric layer of the additional FE-FET device includes an alloy having alloy of hafnium oxide and zirconium oxide in atomic percentage ratios ranging from between 1 :2 to 2: 1 hafnium oxide and zirconium oxide.

Example 17 includes the subject matter of Example 16, wherein the alloy has an approximately equal atomic percentage of hafnium oxide and zirconium oxide.

Example 18 is an integrated circuit device that includes a semiconductor substrate and a ferroelectric field-effect transistor (FE-FET) device including a gate electrode and a ferroelectric layer including an alloy of hafnium oxide and zirconium oxide. Example 19 includes the subject matter of Example 18 and further includes at least one metallization line positioned between the substrate and the FE-FET device.

Example 20 includes the subject matter of any of Examples 18-19 and further includes a FE-FET semiconductor substrate positioned under or above the ferroelectric layer.

Example 21 includes the subject matter of Example 20, wherein the FE-FET semiconductor substrate includes a material having a structure that is polycrystalline or amorphous.

Example 22 includes the subject matter of any of Examples 20-21, wherein the FE-FET semiconductor substrate is selected from the group consisting of: polycrystalline silicon, amorphous silicon, indium gallium zinc oxide (IGZO), group III-V materials and indium tin oxide (ITO), a complex oxide, and transition metal dichalcogenides.

Example 23 includes the subject matter of any of Examples 18-22, wherein the alloy includes hafnium oxide and zirconium oxide in atomic percentage ratios ranging from between 1 :2 to 2: 1 hafnium oxide and zirconium oxide.

Example 24 includes the subject matter of Example 23, wherein the alloy has an approximately equal atomic percentage of hafnium oxide and zirconium oxide.

Example 25 includes the subject matter of any of Examples 18-24 and further includes an additional ferroelectric field-effect transistor (FE-FET) device including a ferroelectric layer positioned above the FE-FET device.

Example 26 includes the subject matter of Example 25, wherein the additional FE-FET device includes a FE-FET substrate comprising a material selected from the group consisting of: polycrystalline silicon, amorphous silicon, indium gallium zinc oxide (IGZO), group III-V materials and indium tin oxide (ITO), a complex oxide, and transition metal dichalcogenides.

Example 27 includes the subject matter of any of Examples 25-26, wherein the ferroelectric layer of the additional FE-FET device includes a material capable of exhibiting ferroelectric properties at processing temperatures of less than 500°C. Example 28 includes the subject matter of any of Examples 25-27, wherein the ferroelectric layer of the additional FE-FET device includes a material capable of exhibiting ferroelectric properties at processing temperatures of less than 400°C.

Example 29 includes the subject matter of any of Examples 25-28, wherein the ferroelectric layer of the additional FE-FET device includes a material capable of exhibiting ferroelectric properties at a processing temperature of between 200°C and 400°C.

Example 30 includes the subject matter of any of Examples 25-29, wherein the ferroelectric layer of the additional FE-FET device includes a material selected from the group consisting of hafnium oxide, zirconium oxide and an alloy of hafnium oxide and zirconium oxide.

Example 31 includes the subject matter of Example 30, wherein the ferroelectric layer of the additional FE-FET device includes an alloy of hafnium oxide and zirconium oxide in atomic percentage ratios ranging from between 1 :2 to 2: 1 hafnium oxide and zirconium oxide.

Example 32 includes the subject matter of Example 31, wherein the alloy has an approximately equal atomic percentage of hafnium oxide and zirconium oxide.

Example 33 is a system-on-chip (SoC) that includes the integrated circuit device of any of Examples 1-32.

Example 34 is a mobile computing system that includes the integrated circuit device of any of Examples 1-32 or the SoC of Example 33.

Example 35 is a method of producing a back-end ferroelectric field-effect transistor

(FE-FET), the method including forming one or more metal features over a semiconductor substrate, forming a semiconductor layer over the one or more metal features, depositing a ferroelectric layer on the semiconductor layer and forming a gate on the ferroelectric layer.

Example 36 includes the subject matter of Example 35, wherein the ferroelectric layer includes a material selected from the group consisting of hafnium oxide, zirconium oxide and an alloy of hafnium oxide and zirconium oxide. Example 37 includes the subject matter of Example 36, wherein the ferroelectric layer includes an alloy of hafnium oxide and zirconium oxide having an approximately equal atomic percentage of hafnium oxide and zirconium oxide.

Example 38 includes the subject matter of any of Examples 35-37 and further includes forming an additional ferroelectric field-effect transistor (FE-FET) device above the gate.

The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit this disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of this disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.

Claims

CLAIMS What is claimed is:

1. An integrated circuit device, comprising:

a semiconductor substrate;

a device layer over the substrate and including one or more metal oxide semiconductor (MOS) logic transistors; and

a ferroelectric field-effect transistor (FE-FET) device above the device layer and including a ferroelectric layer and a gate electrode.

2. The integrated circuit device of claim 1 further comprising a FE-FET semiconductor substrate under or above the ferroelectric layer.

3. The integrated circuit device of claim 2, wherein the FE-FET semiconductor substrate comprises a material having a structure that is polycrystalline or amorphous.

4. The integrated circuit device of claim 3, wherein the FE-FET semiconductor substrate is selected from the group consisting of: polycrystalline silicon, amorphous silicon, indium gallium zinc oxide (IGZO), group III-V materials and indium tin oxide (ITO), a complex oxide, and transition metal dichalcogenides.

5. The integrated circuit device of claim 1, wherein the ferroelectric layer comprises a material capable of exhibiting ferroelectric properties at processing temperatures of less than 500°C.

6. The integrated circuit device of claim 1, wherein the ferroelectric layer comprises a material capable of exhibiting ferroelectric properties at processing temperatures of less than 400°C.

7. The integrated circuit device of claim 1, wherein the ferroelectric layer comprises a material capable of exhibiting ferroelectric properties at a processing temperature of between 200°C and 400°C.

8. The integrated circuit device of claim 1, wherein the ferroelectric layer comprises a material selected from the group consisting of hafnium oxide, zirconium oxide and an alloy of hafnium oxide and zirconium oxide.

9. The integrated circuit device of claim 8, wherein the ferroelectric layer comprises an alloy having alloy of hafnium oxide and zirconium oxide in atomic percentage ratios ranging from between 1 :2 to 2: 1 hafnium oxide and zirconium oxide.

10. The integrated circuit device of claim 9, wherein the alloy has an approximately equal atomic percentage of hafnium oxide and zirconium oxide.

11. The integrated circuit device of claim 1 further comprising an additional ferroelectric field-effect transistor (FE-FET) device including a ferroelectric layer positioned above the FE-FET device.

12. An integrated circuit device, comprising:

a semiconductor substrate; and

a ferroelectric field-effect transistor (FE-FET) device including a gate electrode and a ferroelectric layer including an alloy of hafnium oxide and zirconium oxide.

13. The integrated circuit device of claim 12 further comprising at least one metallization line positioned between the substrate and the FE-FET device.

14. The integrated circuit device of claim 12 further comprising a FE-FET semiconductor substrate positioned under or above the ferroelectric layer.

15. The integrated circuit device of claim 14, wherein the FE-FET semiconductor substrate comprises a material having a structure that is polycrystalline or amorphous.

16. The integrated circuit device of claim 14, wherein the FE-FET semiconductor substrate is selected from the group consisting of: polycrystalline silicon, amorphous silicon, indium gallium zinc oxide (IGZO), group III-V materials and indium tin oxide (ITO), a complex oxide, and transition metal dichalcogenides.

17. The integrated circuit device of claim 12, wherein the alloy includes hafnium oxide and zirconium oxide in atomic percentage ratios ranging from between 1 :2 to 2: 1 hafnium oxide and zirconium oxide.

18. The integrated circuit device of claim 17, wherein the alloy has an approximately equal atomic percentage of hafnium oxide and zirconium oxide.

19. The integrated circuit device of claim 12 further comprising an additional ferroelectric field-effect transistor (FE-FET) device including a ferroelectric layer positioned above the FE-FET device.

20. A system-on-chip (SoC) comprising the integrated circuit device of any of claims

1-19.

21. A mobile computing system comprising the integrated circuit device of any of claims 1-19 or the SoC of claim 20.

22. A method of producing a back-end ferroelectric field-effect transistor (FE-FET), the method comprising:

forming one or more interconnect features over a semiconductor substrate;

forming a semiconductor layer on the interconnect feature;

depositing a ferroelectric layer on the semiconductor layer; and

forming a gate on the ferroelectric layer.

23. The method of claim 22, wherein the ferroelectric layer comprises a material selected from the group consisting of hafnium oxide, zirconium oxide and an alloy of hafnium oxide and zirconium oxide.

24. The method of claim 23, wherein the ferroelectric layer comprises an alloy of hafnium oxide and zirconium oxide having an approximately equal atomic percentage of hafnium oxide and zirconium oxide.

25. The method of claim 22 further comprising forming an additional ferroelectric field-effect transistor (FE-FET) device above the gate.