WO2018004650A1

WO2018004650A1 - 1t-1r rram cell including group iii-n access transistor

Info

Publication number: WO2018004650A1
Application number: PCT/US2016/040682
Authority: WO
Inventors: Ravi Pillarisetty; Han Wui Then; Sansaptak DASGUPTA; Elijah V. KARPOV; Marko Radosavljevic
Original assignee: Intel Corporation
Priority date: 2016-07-01
Filing date: 2016-07-01
Publication date: 2018-01-04

Abstract

Techniques are disclosed for forming a one transistor, one resistor (1T-1R) resistive random-access memory (RRAM) cell including a group III-N access transistor, such as a gallium nitride (GaN) access transistor. Use of a group III-N access transistor in a 1T-1R RRAM cell enables relatively higher switching voltage and switching currents in a scaled RRAM cell as compared to conventional silicon (Si) access transistors. For example, for a given RRAM footprint, a 1T-1R configuration having a group III-N access transistor can achieve switching characteristics of almost double the amount of voltage and almost double the amount of current as compared to a 1T-1R configuration having a Si access transistor, with all else being the same. The relatively higher switching voltage/current at scaled dimensions enables the beneficial use of high voltage/high current switching film materials (e.g., tantalum oxide) for RRAM switching layers. Other embodiments may be described and/or disclosed.

Description

1 T-1 RRAM CELL INCLUDING GROUP III-N ACCESS TRANSISTOR

BACKGROUND

Resistive memory, such as resistive random-access memory (RRAM or ReRAM), generally includes a two-terminal device in which a comparatively insulating switching layer or medium is positioned between two conductive electrodes. RRAM devices typically consist of one transistor (IT) or one diode (ID) along with one resistor (1R), resulting in 1T-1R or 1D-1R configurations, where the transistor (IT) or diode (ID) is used as an access device for reading and/or writing operations, while the resistor (1R) acts as a memristor to store the memory state. RRAM can change between two different states: a high-resistance state (HRS), which may be representative of an off or 0 state; and a low-resistance state (LRS), which may be representative of an on or 1 state. Typically, a reset process is used to switch the RRAM device to the HRS using a reset voltage, and a set process is used to switch the RRAM device to the LRS using a set voltage. Filamentary RRAM requires an initial forming process whereby a high voltage stress (known as a forming voltage) is applied to the device. Interfacial RRAM does not require such an initial forming process.

A field-effect transistor (FET) is a semiconductor device that includes three terminals: a gate, a source, and a drain. A FET uses an electric field applied by the gate to control the electrical conductivity of a channel through which charge carriers (e.g., electrons or holes) flow from the source to the drain. In instances where the charge carriers are electrons, the FET is referred to as an n-channel device, and in instances where the charge carriers are holes, the FET is referred to as a p-channel device. Some FETs have a fourth terminal called, the body or substrate, which can be used to bias the transistor. In addition, for FETs, there are two major operation types known as depletion mode (D-mode) and enhancement mode (E-mode). D-mode transistors operate with zero (or near zero) gate-source voltage when the transistor is in an on- state, for example. E-mode transistors operate with zero (or near zero) gate-source voltage when the transistor is in an off-state, for example.

Integrated circuit (IC) fabrication primarily includes two portions: the front-end or front- end-of-line (FEOL) and the back-end or back-end-of-line (BEOL). The front-end or FEOL is the first portion of IC fabrication where individual semiconductor devices are formed, including all processes up to the deposition of metal interconnect layers. The back-end or BEOL, not to be confused with back-end chip fabrication, is the second portion of IC fabrication where the individual semiconductor devices get interconnected with metal wiring. BEOL may include any number of metallization layers, depending on the target application or end use.

BRIEF DESCRIPTION OF THE DRAWINGS

Figures 1A-B illustrate example resistive random-access-memory (RRAM) cells including a group III-N access transistor, in accordance with some embodiments of the present disclosure. Note that the structures shown in Figures 1A-B are cross-sectional views taken along an orthogonal-to-gate direction relative to the access transistor. Also note that, generally, the example structure of Figure 1 A utilizes a patterned shallow trench isolation (STI) layer for lateral epitaxial overgrowth (LEO) of the III-N layer for the III-N access transistor, whereas the example structure of Figure IB utilizes a buffer layer for growth of the III-N layer for the III-N access transistor.

Figures 2A-B illustrate the example RRAM cells of Figures 1A-B, respectively, including multiple variations, in accordance with some embodiments of the present disclosure.

Figure 3 illustrates a method of forming an IC structure including an RRAM cell including a group III-N access transistor, in accordance with some embodiments of the present disclosure.

Figure 4 illustrates an example computing system implemented with the integrated circuit structures and/or techniques disclosed herein, in accordance with some embodiments of the present disclosure.

These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. In short, the figures are provided merely to show example structures.

DETAILED DESCRIPTION

For one transistor, one resistor (or so-called, 1T-1R) resistive random-access memory (RRAM) cells, conventional access transistors (the IT portion of 1T-1R) are implemented with silicon (Si) and present numerous drawbacks and limitations. For instance, as 1T-1R RRAM is scaled, the Si access transistor scales as well and thereby supplies less switching voltage and switching current. In more detail, scaling the Si access transistor down to a gate length (Lg) of less than 100 nm yields access transistors with relatively low switching characteristics. Specifically, such scaled Si access transistors are limited to less than 1-1.5 V of switching voltage and less than 100 microamps of switching current. Even high voltage Si access transistors formed using a thick gate process have low drive currents (substantially less than 100 microamps of current). Therefore, as RRAM scales, the switching characteristics of Si access transistors become too restrictive and preclude the use of high voltage/high current switching film materials, such as tantalum oxide (TaO_x), zirconium oxide (ZiO_x), and hafnium oxide (HfO_x). As will be appreciated in light of this disclosure, such relatively higher voltage/current switching layer materials can provide a more stable bit for RRAM, leading to improved endurance and retention characteristics. Thus, techniques enabling the use of such higher voltage/current switching layer materials for RRAM applications are needed. Such techniques would be particularly useful in embedded non-volatile memory (eNVM) applications.

Thus, and in accordance with one or more embodiments of the present disclosure, techniques are provided for forming a 1T-1R memory cell including a group III-N access transistor. As used herein, group III-N material (or III-N material or III-N) includes a compound of one or more group III elements (e.g., aluminum, gallium, indium, boron, thallium), with nitrogen. Accordingly, III-N material as used herein includes, but is not limited to, gallium nitride (GaN), indium nitride (InN), aluminum nitride (AIN), aluminum indium nitride (AlInN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). A short-channel scaled III-N transistor (e.g., a GaN transistor) used as an access transistors in a 1T-1R RRAM cell enables relatively higher switching voltage and switching currents in a scaled RRAM cell as compared to conventional Si access transistors. For example, in the case of scaling the access transistor down to an Lg of approximately 20 nm, a III- N access transistor can provide greater than 200 microamps of switching current at 3 V of switching voltage. Therefore, for a given RRAM footprint, a 1T-1R configuration having a III-N access transistor can achieve switching characteristics of almost double the amount of voltage and almost double the amount of current as compared to a 1T-1R configuration having a Si access transistor, with all else being the same. The relatively higher switching voltage and switching currents at such scaled dimensions enables the use of high voltage/high current switching film materials (e.g., tantalum oxide, zirconium oxide, hafnium oxide) for RRAM switching layers. Use of the techniques and structures provided herein may be detectable using tools such as: electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDS); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF- SFMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. In particular, in some embodiments, such tools may indicate a 1T-1R RRAM cell including a group III-N semiconductor material access transistor. Further, in some embodiments, the III-N access transistor may include a gate length (Lg) of less than 100, 75, 50, 40, 30, 25, 20, 15, or 10 nm, or less than any other suitable maximum length, as will be apparent in light of this disclosure. In some such embodiments, the scaled-down 1T-1R RRAM cell may include high voltage/high current switching films, such as a film including tantalum oxide (TaO_x), zirconium oxide (ZiO_x), or hafnium oxide (HfO_x), to name a few examples. Numerous variations and configurations will be apparent in light of this disclosure.

Architecture and Methodology

Figures 1A-B illustrate an example resistive random-access-memory (RRAM) cell including a group III-N access transistor, in accordance with some embodiments of the present disclosure. Note that the structures shown in Figures 1 A-B are cross-sectional views taken along an orthogonal -to-gate direction relative to the access transistor 100. Generally, in these example embodiments, the integrated circuit (IC) structure including an RRAM cell has a one transistor, one resistor (1T-1R) configuration, where the access transistor is the IT portion of the cell. As shown in Figures 1A-B, the access transistor is indicated by 100, while the resistor or memristor stack is indicated by 200 and includes first electrode 211, switching layer 220, optional oxygen exchange layer (OEL) 230, and second electrode 212, as shown. The example structures of Figures 1 A-B are similar, with a primary difference being the techniques used to form III-N layer 120, as will be described in more detail herein. Generally, the example structure of Figure 1A utilizes a patterned shallow trench isolation (STI) layer 112 for lateral epitaxial overgrowth (LEO) of the III-N layer 120, whereas the example structure of Figure IB utilizes buffer layer 114 for growth of the III-N layer 120.

Note that the III-N access transistors 100 in the present disclosure are primarily described and depicted in the context of metal-oxide-semiconductor field-effect transistors (MOSFETs); however, the present disclosure is not intended to be so limited. For example, in some embodiments, the transistors may be tunnel field-effect transistors (TFETs) or any other suitable transistor configuration, as will be apparent in light of the present disclosure. Further, the access transistors in the present disclosure are primarily described and depicted in the context of planar transistor configurations. However, in some embodiments, the techniques can be used to form access transistors including a non-planar configuration, such as finned or finFET configurations (e.g., including a dual-gate or tri-gate configuration) or gate-all-around configurations (e.g., including one or more nanowires or nanoribbons). Further still, the memristor stacks in the present disclosure are primarily depicted and described herein in the context of a planar stack. However, in some embodiments, the techniques can be used to form memristor stacks including a non-planar configuration, such as a U-shaped configuration where one or more of the layers of the memristor stack generally have a U shape, to provide one example non-planar configuration. Note that the RRAM cell is primarily depicted and described herein in the context of a 1T-1R configuration including one III-N access transistor 100 and one memristor stack 200, for ease of description; however, the present disclosure is not intended to be limited to any quantity of transistors, memristor stacks, or RRAM cells, unless otherwise stated. For instance, in some embodiments, multiple RRAM cells as described herein may be used in a memory array, such as in a non-volatile ransom-access memory (NVRAM) array, for example. In some embodiments, the techniques may be used to benefit devices of varying scales, such as transistor devices having critical dimensions in the micrometer range or in the nanometer range (e.g., transistors formed at the 32, 22, 14, 10, 7, or 5 nm process nodes, or beyond).

Substrate 110, in some embodiments, may include: a bulk substrate including a group IV material, such as silicon (Si), germanium (Ge), SiGe, or silicon carbide (SiC), and/or at least one group III-V material and/or sapphire and/or any other suitable material(s) as will be apparent in light of this disclosure; an X on insulator (XOI) structure where X is one of the aforementioned materials (e.g., group IV and/or group III-V and/or sapphire) and the insulator material is an oxide material or dielectric material or some other electrically insulating material; or some other suitable multilayer structure where the top layer includes one of the aforementioned materials (e.g., group IV and/or group III-V and/or sapphire). Note that group IV material as used herein includes at least one group IV element (e.g., carbon, silicon, germanium, tin, lead), such as Si, Ge, SiGe, or SiC to name some examples. Note that group III-V material as used herein includes at least one group III element (e.g., aluminum, gallium, indium, boron, thallium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium nitride (GaN), gallium arsenide (GaAs), indium gallium nitride (InGaN), and indium gallium arsenide (InGaAs), to name some examples. In some embodiments, substrate 110 may include a surface crystalline orientation described by a Miller Index of <100>, <110>, or <111>, or its equivalents, as will be apparent in light of this disclosure. Although substrate 110, in this example embodiment, is shown as having a thickness (the dimension in the Y direction) similar to the other layers for ease of illustration, in some instances, substrate 110 may be much thicker than the other layers, such as having a thickness in the range of 50 to 950 microns, for example. In some embodiments, substrate 110 may be used for one or more other IC devices, such as various diodes (e.g., light-emitting diodes (LEDs) or laser diodes), various transistors (e.g., MOSFETs or TFETs), various capacitors (e.g., MOSCAPs), various microelectromechanical systems (MEMS), various nanoelectromechanical systems (NEMS), various sensors, or any other suitable semiconductor or IC devices, depending on the end use or target application. Accordingly, in some embodiments, the structures described herein may be included in a system-on-chip (SoC) application, as will be apparent in light of this disclosure.

III-N layer 120, in some embodiments, may include any suitable III-N material, such as GaN or InGaN, or any other suitable group III-N semiconductor material, as will be apparent in light of this disclosure. In some embodiments, formation of one or more of the layers in the structures shown in Figures 1A-B, such as III-N layer 120, may be performed using metal- organic chemical vapor deposition (MOCVD), molecular-beam epitaxy (MBE) chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and/or any other suitable process as will be apparent in light of this disclosure. As previously described, III- N material, as used herein, includes a compound of one or more group III elements (e.g., aluminum, gallium, and/or indium), with nitrogen. Accordingly, III-N materials as variously used herein include, but are not limited to, GaN, InN, AIN, AlInN, AlGaN, InGaN, and AlInGaN. In some embodiments, GaN may be particularly well-suited for III-N layer 120 because of its wide bandgap, high critical breakdown electric field, and high electron saturation, for example. For instance, embodiments employing GaN for the III-N layer 120 may be particularly well-suited for high-voltage applications, such as for an access transistor in an RRAM cell including a high voltage/high current switching material, for example. In some embodiments, III-N layer 120 may have a multilayer structure including multiple III-N materials. In some embodiments, III-N layer 120 may or may not include grading (e.g., increasing and/or decreasing) the content of one or more materials in at least a portion of the layer. In some embodiments, III-N layer 120 may be doped with another material, such as with one or more suitable p-type or n-type dopants, for example. In some embodiments, III-N layer 120 may be formed to have a thickness (the dimension in the Y direction) between 20 nm and 2 microns, or any other suitable thickness, as will be apparent in light of this disclosure. Note that the thickness of the III-N layer 120 may be measured as the thickness above substrate 110, above STI features 112, or above buffer layer 114, for example.

In the example structure of Figure 1A, III-N layer 120 is formed using lateral epitaxial overgrowth (LEO) processing. Such LEO processing may include, for example, forming and patterning shallow trench isolation (STI) layer on substrate 110 to form individual STI features 112 as shown and then growing the III-N layer 120 material on substrate 110 and from the openings in the STI features 112, such that defects that may be present bend or otherwise form over the STI features 1 12, leaving the remainder of the III-N layer 120 material suitable for transistor channel use. Such defects may be present due to the growth of the III-N layer 120 material (e.g., GaN) on the substrate 110 material (e.g., Si). In such embodiments, STI 112 may include any suitable material, such as any suitable dioxide (e.g., silicon dioxide) and/or any suitable nitride (e.g., silicon nitride), to name a few examples. In the example structure of Figure IB, III-N layer 120 is formed using buffer layer 114. In this example embodiment, buffer layer 114 may be used to assist with the formation of III-N layer 120 such that layer 120 can achieve device quality for transistor 100. As such, buffer layer 114 may include any suitable III-N material. For instance, in the case where III-N layer 120 is GaN and substrate 110 is Si, an AlGaN or InGaN buffer layer may be used below the GaN layer to assist with ensuring the GaN layer (to be used for the transistor 100 channel material) is of a sufficient device quality, for example. In some embodiments, buffer layer 114 may have any suitable thickness (the dimension in the Y direction) such as between 50 nm and 5 microns, or any other suitable thickness, as will be apparent in light of this disclosure. In some embodiments, an optional nucleation layer (not shown) may be present in the structure of Figure 1A and/or the structure of Figure IB, where such nucleation layer would be below III-N layer 120, such as in embodiments where III-N layer 120 is formed on a non-III-V material substrate (e.g., formed on a Si substrate). In such embodiments, the nucleation layer may be present to, for example, improve growth conditions and/or prevent the III-N layer 120 from reacting with the substrate material in an undesired manner. In some such embodiments, the nucleation layer, where present, may include a III-V or III-N material, such as A1N or a low temperature GaN layer (e.g., epitaxially grown at a temperature in the range of 700 to 950 degrees Celsius), for example. In some embodiments, the nucleation layer, where present, may have any suitable thickness (dimension in the Y direction), such as a thickness of 10 nm to 2 microns (e.g., 200nm to 1 micron), or any other suitable thickness as will be apparent in light of this disclosure.

Polarization charge inducing layer 130, in some embodiments, may be formed using any suitable techniques, as will be apparent in light of the present disclosure. In some embodiments, polarization charge inducing layer 130 may include any suitable materials, such as one or more III-V materials, and more specifically in some embodiments, one or more III-N materials, for example. In some embodiments, polarization charge inducing layer 130 may include aluminum, such that the layer includes at least one of A1N, AlGaN, InAIN, and InAlGaN, for instance. In some embodiments, polarization charge inducing layer 130 may increase carrier mobility in the transistor channel region (e.g., in III-N layer 120) and/or be used to form a two-dimensional electron gas (2DEG) configuration with underlying III-N layer 120, for example. Note that the 2DEG configuration is represented by dashed lines near the top of III-N layer 120, in the example structures of Figures 1A-B. In some such embodiments, polarization layer 130 may include material having a higher or larger energy gap or bandgap than the material of III-N layer 120, to form the 2DEG configuration, for example, and such a scheme may be referred to as polarization doping. For instance, in some embodiments, III-N layer 120 may include GaN (having a band gap of 3.4 eV) and polarization charge inducing layer 130 may include A1N and/or AlGaN, for example. In other embodiments, III-N layer 120 may include AlGaN and polarization charge inducing layer 130 may include GaN, A1N, and/or AlGaN, for example. In some embodiments, polarization charge inducing layer 130 may have a multilayer structure including multiple III-V materials. In some such embodiments, where the polarization layer 130 is a multilayer structure, one of the layers in the multilayer structure may be present to further increase carrier mobility in the transistor channel region and/or to improve compatibility (e.g., density of interface traps) between polarization charge inducing layer 130 and overlying layers (such as gate dielectric layer 154, in the structures of Figures 1A-B), for example. In some embodiments, polarization charge inducing layer 130 may or may not include grading (e.g., increasing and/or decreasing) the content of one or more materials in at least a portion of the layer. In some embodiments, polarization charge inducing layer 130 may have a thickness (the dimension in the Y direction) of 0.1 to 100 nm (e.g., 0.5 to 5 nm), or any other suitable thickness, as will be apparent in light of this disclosure.

Source/drain (S/D) regions 140, in some embodiments, may be formed using any suitable techniques, as will be apparent in light of the present disclosure. For example, in some embodiments, S/D regions 140 may be formed by any combination of optional patterning/masking/lithography/etching with depositing/growing/regrowing the S/D region 140 material(s), which may then be followed by a planarization and/or polish process, for instance. Note that although S/D regions 140 are shown as one continuous portion in Figures 1A-B, in some embodiments, the S/D regions 140 may include multiple portions, such as S/D material adjacent to the channel region (which is the top portion of III-N layer 120) and S/D contacts above the S/D material. However, in some embodiments, the first layer of interconnect 181 may be considered S/D contacts for S/D regions 140. Regardless of the configuration, in some embodiments, the S/D material (which will be in at least a portion of the S/D region 140) may be any suitable material, such as III-V material, III-N material, and/or any other suitable material(s), as will be apparent in light of this disclosure. In addition, in some embodiments, the S/D region 140 material may be doped in an n-type or p-type manner, for example, using any suitable doping techniques. In an example embodiment, S/D regions 140 may include indium and nitrogen (e.g., InN or InGaN) and be doped in an n-type manner using, e.g., Si, Ge, and/or Te, with doping amounts of around 2E20 atoms per cubic cm, for instance. In some embodiments, one or both of the S/D regions 140 of transistor 100 may have a multilayer structure including multiple materials. In some embodiments, one or both of the S/D regions 140 may or may not include grading (e.g., increasing and/or decreasing) the content of one or more materials in at least a portion of one or both of the regions.

As previously stated, in some embodiments, S/D regions 140 may include S/D contacts. In some such embodiments, S/D contacts may include any suitable material, such as a conductive metal or alloy (e.g., aluminum, tungsten, silver, titanium, nickel-platinum, or nickel-aluminum). In some embodiments, S/D contacts may include a resistance reducing metal and a contact plug metal, or just a contact plug, depending on the end use or target application. Example contact resistance reducing metals include silver, nickel, aluminum, titanium, gold, gold-germanium, nickel-platinum, or nickel aluminum, and/or other such resistance reducing metals or alloys. The contact plug metal may include, for instance, aluminum, silver, nickel, platinum, titanium, or tungsten, or alloys thereof, although any suitably conductive contact metal or alloy can be used, depending on the end use or target application. In some embodiments, additional layers may be present in the S/D contact regions 140, such as adhesion layers (e.g., titanium nitride) and/or liner or barrier layers (e.g., tantalum nitride), if so desired. Note that, in some embodiments, gate stack processing (including forming gate dielectric layer 154 and gate 152) may be performed prior to the formation of S/D regions 140, while in other embodiments, gate stack processing may be performed after the formation of S/D regions 140, for example. As can be seen in Figures 1A-B, the S/D region 140 in the center of the example structures shown is electrically connected to the right-most S/D region 240 of back-end transistor 200. Depending on the end use or target application, the source or drain of transistor 100 may be connected to the source or drain of transistor 200.

In the example structure of Figure IB, a selective wet etch process was used to form notches from which the S/D regions 140 were grown. As can be seen, the notches were formed above and in the ends of the polarization layer 130 and any suitable techniques may be used to form such notches, such as using a wet etch process that selectively removes material from the interface between polarization charge inducing layer 130 and gate dielectric layer 154, for example. For instance, in an example embodiment, the selective wet etch used to form notches may include an etchant of tetramethylammonium hydroxide (TMAH) and a lateral/horizontal etch direction (in the X direction) at the sides of the interface between polarization layer 130 and gate dielectric layer 154. In some such embodiments, the ledges of polarization charge inducing layer 130 exposed by the formation of the notches (e.g., exposed by performing the selective wet etch) may provide relatively high-quality surfaces from which to grow S/D region 140 material and thus result in S/D material having a relatively high-quality crystalline structure, for example. Numerous S/D configurations will be apparent in light of this disclosure and the present disclosure is not intended to be limited to any particular configuration unless otherwise stated.

Gate 152 and gate dielectric layer 154, in some embodiments, may be formed using any suitable techniques. As is also shown in Figures 1A-B, spacers 160 are adjacent to gate 152, in this example embodiment, and such spacers 160 may be formed using any suitable techniques. The processing of gate dielectric layer 154, gate 152, and spacers 160 may be achieved using any suitable techniques as will be apparent in light of this disclosure, such as any suitable wet and/or dry etch processes, any suitable deposition processes such as those described herein (e.g., MBE, CVD, PVD), any suitable planarization and/or polishing processes, and so forth. In some cases, gate 152 may be referred to as a gate electrode or metal gate (e.g., when gate 152 includes metal material), and generally, gate 152 and gate dielectric layer 154 may be referred to as a gate stack. Although gate dielectric layer 154 is shown located below and adjacent to spacers 160, in some embodiments, gate dielectric layer 154 material need not be present in those locations, and the material of gate dielectric layer 154 may only be located below gate 152 or be located below gate 152 and between gate 152 and spacers 160, for example. In some embodiments, gate dielectric layer 154 may be located over at least a portion of the S/D regions 140, such as is shown in Figure IB (where gate dielectric layer 154 is over the notch portion of S/D regions), for example. In some such embodiments, such a structure may occur as a result of a blanket deposition of the gate dielectric layer 154, for example.

In some embodiments, spacer material 160 may include any suitable material, such as dielectric material, oxide material (e.g., silicon oxide) and/or nitride material (e.g., silicon nitride), for example. In some embodiments, gate dielectric layer 154 may include silicon dioxide and/or high-k dielectric material, or any other suitable gate dielectric material. Example high-k dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to name some examples. In some embodiments, an annealing process may be carried out on the gate dielectric layer 154 to improve its quality when a high-k material is used, for example. In some embodiments, the material of gate 152 and/or the gate contact (which may be located behind or in front of the example structure shown in Figures 1A-B) may include any suitable material, such as polysilicon, silicon nitride, silicon carbide, or various suitable metals or metal alloys, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), titanium nitride (TiN), or tantalum nitride (TaN), for example. In some embodiments, one or more material layers may be formed between the gate dielectric layer 154 and the gate 152 to, for example, increase the interface quality between the two features and/or to improve the electrical properties between the two features. Such intervening layers may include one or more work- function material layers, for example. In some embodiments, gate dielectric layer 154 and/or gate 152 may include a multilayer structure of two or more material layers. In some embodiments, gate dielectric layer 154 and/or gate 152 may include grading (e.g., increasing and/or decreasing) the content of one or more materials in at least a portion of the layer(s). Numerous gate stack configurations will be apparent in light of this disclosure and the present disclosure is not intended to be limited to any particular configuration unless otherwise stated.

Note that, in the example structures of Figures 1A-B, the channel region of III-N transistor

100 may be defined by the gate stack (including gate dielectric layer 154 and gate 152), such that the transistor channel is located below the gate stack. Also note that, in this example embodiment, polarization charge inducing layer 130 located above III-N layer 120 forms a two- dimensional electron gas (2DEG) configuration when the transistor is in an on state (indicated with dashed lines near the top of III-N layer 120). As can be understood based on this disclosure, a 2DEG configuration includes a gas of carriers (e.g., electrons or holes) free to move in two dimensions but tightly confined in the third. Such a tight confinement can lead to quantized energy levels for motion in the third. Although 2DEG configurations include electron carriers and two-dimensional hole gas (2DHG) configurations include hole carriers, the term 2DEG will be used herein to generally refer to both carrier type configurations (both electron and hole carriers) for ease of description, unless otherwise stated. Therefore, in some instances, the 2DEG configuration locations may be considered a part of the channel region, as the 2DEG configurations (along with the channel located below the gate stack) allow charge carriers (e.g., electrons or holes) to flow from the source to the drain when the transistor is in an on state. In embodiments where access transistor 100 is an n-channel transistor, the carriers will be electrons and thus an actual 2DEG configuration will form. However, in some embodiments, III-N layer 120 material may be doped to achieve the proper transistor configuration, such as doping the III- N layer 120 material with a p-type dopant (e.g., using Mg) to achieve a p-channel transistor, for example.

In the example structures of Figures 1A-B, the gate length Lg is shown, which is the dimension in the X direction in these embodiments or, in other words, the length of the gate between S/D regions 140. As previously described, as 1T-1R RRAM cells are scaled down to improve on footprint and/or to improve cell density, the access transistors (the IT portion of 1T- 1R) are also scaled down. In some such embodiments, this translates to a reduced available area in the X dimension of the structures shown in Figures 1 A-B for the RRAM cells. Accordingly, in some embodiments, the gate length Lg may be less than 100, 75, 50, 40, 30, 25, 20, 15, or 10 nm, or less than any other suitable maximum length, as will be apparent in light of this disclosure. In some embodiments, for a given layout footprint, III-N access transistor 100 may be able to output at least 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, or 2 times the amount of voltage and/or current as a conventional Si access transistor. In some embodiments, the 1T-1R RRAM cell structures of Figures 1A-B may also include peripheral control circuitry using group IV transistors (e.g., Si, Ge, or SiGe transistors). In some such embodiments, the group IV transistors may be included elsewhere on a common substrate, such as in a system -on-chip (SOC) integration scheme

Continuing with the example RRAM cell structures of Figures 1A-B, after access transistor 100 has been formed, memristor stack 200 may be formed, as shown, such that access transistor 100 is in series with memristor stack 200. In these example embodiments, memristor stack 200 includes first electrode 211, switching layer 220, optional oxygen exchange layer (OEL) 230, and second electrode 212. The layers of memristor stack 200 may be formed using any suitable techniques. In some embodiments, the processing techniques may include a low thermal budget (e.g., less than 500, 450, 400, 350, or 300 °C), as the processing may occur during back-end processing in the interconnect stack. As shown, memristor stack 200 has been formed in the back-end or back-end-of-line (BEOL) portion of the integrated circuit (IC) structure processing, as compared to transistor 100 which was formed in the front-end or front-end-of-line (FEOL) portion of the IC structure processing. Such back-end processing, in these example embodiments, includes the formation of metallization layers above the transistor 100 as well as the formation of memristor stack 200 in the metallization layers. The metallization layers include interlayer dielectric (ILD) material (indicated by numbers in the 170s, specifically, 171- 174) and interconnect features (indicated by numbers in the 180s, specifically, 181-184). Note that each metallization layer is numbered with the last number of each feature representing the related metallization layer, such that metallization layer 1 (Ml) is represented by ILD layer 171 and interconnect features 181, metallization layer 2 (M2) is represented by ILD layer 172 and interconnect feature 182, and so forth. In some cases, a single metallization layer may include more than one layer shown in the example structures of Figures 1 A-B. For instance, in some such cases, metallization layer (Ml) may include a lower level of 171/181 and an upper level of 172/182, and so forth. As previously described, the first set of interconnects 181 (the set in physical contact with S/D regions 140) may be considered S/D contacts, in some instances, whereas in other instances, such S/D contacts may be included in S/D regions 140, for example. As can be understood based on this disclosure, the previous relevant discussion of S/D contacts is equally applicable to embodiments where features 181 are S/D contacts.

In some embodiments, ILD layers 171-174 may include any suitable material, such as dielectric material, oxide material (e.g., silicon oxide), nitride material (e.g., silicon nitride), and/or carbide material (e.g., silicon carbide), for example. In some embodiments, interconnect features 181-184 may include any suitable electrically conductive material, such as copper (Cu), cobalt (Co), molybdenum (Mo), rhodium (Rh), beryllium (Be), chromium (Cr), manganese (Mn), aluminum (Al), silver (Ag), gold (Au), titanium (Ti), indium (In), ruthenium (Ru), palladium (Pd), tungsten (W), nickel (Ni), and/or graphene to name a few examples. Formation of the ILD layers 171-174 and interconnect features 181-184 may be performed using any suitable techniques such as any suitable wet and/or dry etch processes, any suitable deposition processes such as those described herein (e.g., MBE, CVD, PVD), any suitable planarization and/or polishing processes, and so forth. Note that although the term interconnect is used to identify the metal features in the back-end portion (above device level 100) of the example IC structures shown in Figures 1A-B, the metal features need not connect two devices and may be included in the structure for other reasons (e.g., to generate a desired capacitance).

Memristor stack 200, is co-integrated in the interconnect stack, in these example embodiments. Specifically, as shown in the example structures of Figures 1A-B, memristor stack 200 has been formed in metallization layers two (M2) and three (M3); however, as can be understood based on this disclosure, memristor stack 200 could be formed in any metallization layer or in any location in the interconnect stack. In some embodiments, memristor stack 200 may be formed on a separate substrate, such as a transfer substrate, and added to the structure shown via bonding or layer stacking techniques. Note that although memristor stack 200 is shown as formed above the right S/D region 140 of the structures, and thereby makes use of a vertical co-integration scheme, the present disclosure is not intended to be so limited. For instance, in some embodiments, memristor stack 200 may be formed adjacent to access transistor 100 or to the side of access transistor 100, such that it is primarily formed during front-end processing, for example. However, vertical integration of memristor stack 200 with access transistor 100 (such that memristor stack 200 is above access transistor 100, whether directly above or generally in an area above substrate 110 that is higher in the Y direction than access transistor 100) can help decrease the overall footprint of the RRAM cell structure, as can be understood based on this disclosure. Regardless of the location or method of integrating memristor stack 200 with access transistor 100, in some embodiments, access transistor 100 and memristor stack 200 can be electrically connected in series to form a 1T-1R RRAM architecture. For example, in some such embodiments, the drain region (the right S/D region 140) of access transistor 100 may be electrically connected to the first electrode 211 of memristor stack 200, such as is shown in Figures 1 A-B. Numerous configurations for integrating access transistor 100 with memristor stack 200 will be apparent in light of the present disclosure.

In some embodiments, first and second electrodes 211 and 212 may each include at least one of: disulfur dinitride (S₂N₂); titanium nitride (TiN); tantalum nitride (TaN); copper (Cu); tungsten (W); titanium (Ti); one or more noble metals, such as ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), iridium (Ir), platinum (Pt), and gold (Au); and/or any other suitable material or combination of materials, as will be apparent in light of this disclosure. In some embodiments, first and second electrodes 211 and 212 may each have a thickness (the dimension in the Y direction) in the range of 5-100 nm, or any other suitable thickness, as will be apparent in light of this disclosure. In some embodiments, first and second electrodes 211 and 212 (and memristor stack 200 in general) may have a width (the dimension in the X direction) in the range of 10-300 nm (e.g., 20-200 nm), or any other suitable thickness, as will be apparent in light of this disclosure. Note that in some embodiments, the layers in memristor stack 200 need not have the same or similar widths. Further note that in the example structures of Figures 1 A-B, first electrode 211 may be considered a bottom electrode and second electrode 212 may be considered a top electrode; however, the present disclosure is not intended to be so limited. For instance, in an example embodiment where memristor stack 200 is integrated in a horizontal manner (as opposed to the vertical manner shown in Figures 1A-B), then first and second electrodes 211 and 212 may not be considered bottom and top electrodes (and may more-so be considered left and right electrodes, for example).

In some embodiments, switching layer 220 may include at least one of: a metal oxide, such as hafnium oxide (HfO_x), titanium oxide (TiO_x), nitrogen oxide (NiO_x), tungsten oxide (WO_x), tantalum oxide (TaO_x), zirconium oxide (ZiO_x), vanadium oxide (VO_x), copper oxide (CuO_X), aluminum oxide (A10_x); a metal alloy oxide; and/or any other suitable material, as will be apparent in light of this disclosure. In some embodiments, switching layer 220 may have a thickness (the dimension in the Y direction) in the range of 1-50 nm (e.g., 2-10 nm), or any other suitable thickness, as will be apparent in light of this disclosure. In some embodiments, optional oxygen exchange layer (OEL) 230, when present, may include at least one of: hafnium (Hf); titanium (Ti); tantalum (Ta); and/or any other suitable material or combination of materials. In some such embodiments, OEL 230 may be present in memristor stack 200 to, for example, increase flexibility in incorporating the other materials in the stack 200, as can be understood based on this disclosure. For instance, in some embodiments, OEL 230 may be present to affect the switching mechanism of memristor stack 200, such as to help provide a more stable switching mechanism or to provide a bipolar operation versus a unipolar operation, for example. In some embodiments, optional OEL 326, when present, may have a thickness in the range of 1- 50 nm (e.g., 2-10), or any other suitable thickness, as will be apparent in light of this disclosure. In some embodiments one or more of the layers of memristor stack 200 may have a multilayer structure. For instance, in some embodiments, switching layer 220 may include two material layers that may or may not include grading (e.g., increasing and/or decreasing) the content of at least one material throughout the multilayer structure.

Figures 2A-B illustrate the example RRAM cells of Figures 1A-B, respectively, including multiple variations, in accordance with some embodiments of the present disclosure. The primary variations between the two sets of structures includes that the example structures of Figures 1A-B include a depletion mode III-N transistor 100, while the example structures of Figures 2A-B include an enhancement mode III-N transistor 100, which is achieved using the multilayer polarization charge inducing layer (including polarization layer 1 131 and polarization layer 2 132), in these example embodiments. An enhancement-mode transistor configuration may be desired for various reasons, such as the enhancement-mode configuration not requiring a negative voltage to turn off the transistor and enhanced control of short channel effects of the transistor as a result of the thinner equivalent oxide thickness, just to provide a few example reasons. As a result of the change in the polarization layer configuration, the 2DEG scheme is also changed (as indicated by the dashed lines). For example, the 2DEG is present below the gate stack in the depletion mode configuration, while it is absent below the gate stack in the enhancement mode configuration, as shown in Figures 1 A-B and 2A-B, respectively. Also, as a result of the change in the polarization layer configuration, the gate 153 and gate dielectric 155 of the example structures of Figures 2A-B is also different from the gate 152 and gate dielectric 154 of the example stmctures of Figures 1A-B, as shown. Another primary variation between the two sets of structures includes that the optional OEL layer 230, when present, is below the switching layer 220 in the example structures of Figures 2A-B, as opposed to the optional OEL layer 230 being above the switching layer 220, when present, in the example structures of Figures 1A-B, for example. Further note that these and any other variations described in the present disclosure may be individually implemented or implemented in some combination, for example. The previous relevant description with respect to Figures 1 A-B is equally applicable to the example structures of Figures 2 A-B.

Note that the channel of the transistors 100 in Figures 1A-B and 2A-B may be approximately located below the gate stack (e.g., below the gate 152/153 and gate dielectric 154/155). Further note that the channel is indicated as 122 in Figures 2A-B, for illustrative purposes. In addition, the lengths (dimensions in the X direction) between the gate 153 and the S/D regions 140, indicated as lengths Lg-s/d and Lg-d/s, are shown in Figures 2A-B, and such lengths Lg-sd and Lg-ds may be in the range of 10 and 150 nm (e.g., 20 to 100 nm), or any other suitable length or length range as will be apparent in light of this disclosure. In this example embodiment, Lg-s/d and Lg-d/s are the same or approximately the same. However, in some embodiments, the gate-source spacing or length between the gate and the source (Lg-s) may be different than the gate-drain spacing or length between the gate and the drain (Lg-d), depending on the desired breakdown voltage of the III-N device. In some embodiments, Lg-s may be less than Lg-d, such that Lg-d is at least 10, 20, 30, 40, 50, 60, 70, 80, 90, or 100 nm greater than Lg- s, or some other suitable threshold difference as will be apparent in light of this disclosure. In some embodiments, Lg-s may be in the range of 10 to 50 nm (e.g., 20 to 40 nm), or some other suitable length or length range as will be apparent in light of this disclosure. In some embodiments, Lg-d may be in the range of 50 to 200 nm (e.g., 80 to 150 nm), or some other suitable length or length range as will be apparent in light of this disclosure. In some such embodiments, Lg-s and Lg-d may be selected to control the breakdown voltage, thereby making such a characteristic tunable, for example. Note that the description with respect to these gate to S/D regions (or gate to source and gate to drain) lengths is equally applicable to the example structures of Figures 1A-B.

As previously described, another primary variation between the example structures of

Figures 1 A-B and the example structures of Figures 2A-B is the polarization charge inducing layer configuration. In the example embodiments of Figures 2A-B, the polarization charge inducing layer is a multilayer structure, including a first polarization charge inducing layer 131 (also referred to as polarization layer 1) and a second polarization charge inducing layer 132 (also referred to as polarization layer 2), as shown. In some embodiments, the polarization layers 131, 132 may include III-N material and may also be formed using any suitable techniques. Note that polarization layer 1 131 is only formed on the top of III-N layer 120 in these example embodiments; however, the present disclosure is not intended to be so limited. Also note that in these example embodiments, the gate stack trench used to form the gate stack etched through polarization layer 2 132, such that the gate stack makes contact with polarization layer 1 131 as shown. This may be achieved by etching polarization layer 2 132 at the gate stack trench location prior to gate stack processing (e.g., prior to depositing gate dielectric layer 155), for instance. Accordingly, polarization layer 1 131 may act as an intermediary layer between the gate stack (e.g., gate dielectric layer 155) and the transistor channel 122, while polarization layer 2 132 may be used to form 2DEG in the access regions to the left and right of the transistor channel, for example. Note that polarization layer 1 131 may also assist in forming the 2DEG configurations, as that layer 131 is also present in those locations. In an example embodiment, polarization layer 1 131 may include A1N or Al_xGai_-xN (e.g., where 0 < x < 0.5) and polarization layer 2 132 may include Al_yIni_-yN (e.g., where 0.7 < y < 1), Al_zGai_-zN (e.g., where 0 < z < 0.5), or Al_pIn_qGai_-p-qN (e.g., where 0 < p < 0.5 and 0 < q < 0.5). As can be understood based on this disclosure, such a multilayer polarization layer configuration can be used to form an enhancement mode transistor. In some embodiments, polarization layer 1 131 may have a thickness (dimension in the Y direction) in the range of 0.5 to 20 nm (e.g., 1 to 5 nm), or some other suitable thickness or thickness range as will be apparent in light of this disclosure. In some embodiments, polarization layer 2 132 may have a thickness (dimension in the Y direction) in the range of 0.5 to 100 nm (e.g., 1 to 20 nm), or any other suitable thickness or thickness range as will be apparent in light of this disclosure. Note that enhancement-mode transistor configurations are not intended to be limited to being formed with a multilayer polarization charge inducing layer construct. For example, in some embodiments, a single polarization charge inducing layer may be used and the gate stack trench may remove a portion of that single layer to form a similar configuration as shown in Figures 2A-B, except that the distinct polarization layers 131, 132 would be one continuous material layer. Numerous variations and configurations will be apparent in light of the present disclosure.

Figure 3 illustrates a method 300 of forming an IC structure including an RRAM cell including a group III-N access transistor, in accordance with some embodiments of the present disclosure. Example method 300 includes providing 310 a substrate, such as substrate 110 depicted in Figures 1A-B and variously described herein, for instance. Example method 300 continues with forming 312 a transistor including a channel layer or region including group III-N material, such as a III-N transistor indicated by 100 in Figures 1A-B and variously described herein, for instance. Example method 300 continues with forming 314 a first electrode in electrical contact with the source or drain region of the III-N transistor, such as first electrode 211 depicted in Figures 1A-B and variously described herein. Example method 300 continues with forming 316 a switching layer at least one of above and on (or in physical contact with) the first electrode, such as switching layer 220 depicted in Figures 1A-B and variously described herein, for instance. Example method 300 continues with optionally forming 318 an oxygen exchange layer (OEL) above the first electrode, such as optional OEL 230 depicted in Figures 1 A-B and variously described herein, for instance. Note that in some embodiments, process 318, when performed, may be performed prior to process 316, such that the OEL, when present, is formed prior to forming the switching layer. Example method 300 continues with forming 320 a second electrode above the switching layer, such as second electrode 212 depicted in Figures 1 A-B and variously described herein, for instance. The example method may then continue with any additional suitable processing to form an RRAM cell including a group III-N access transistor, as will be apparent in light of this disclosure. Numerous variations and configurations will be apparent in light of this disclosure.

Example System

Figure 4 illustrates a computing system 1000 implemented with the integrated circuit structures and/or techniques disclosed herein, in accordance some embodiments of the present disclosure. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc.

Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM, RRAM, etc.), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices (e.g., one or more RRAM cells) formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices (e.g., one or more RRAM cells) formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices (e.g., one or more RRAM cells) formed using the disclosed techniques as variously described herein. As will be appreciated in light of this disclosure, note that multi- standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing device 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices (e.g., one or more RRAM cells) formed using the disclosed techniques, as variously described herein.

Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example 1 is a resistive random-access memory (RRAM) cell (or generally, an integrated circuit) including a transistor including and a multilayer stack. The transistor includes: a channel layer including group Ill-nitride (III-N) material; a gate above the channel layer; and source and drain regions adjacent to the channel layer. The multilayer stack includes: a first electrode in electrical contact with one of the source and drain regions of the transistor; a second electrode; and a switching layer between the first and second electrodes, wherein the switching layer includes one of a metal oxide and a metal alloy oxide.

Example 2 includes the subject matter of Example 1, wherein the channel layer includes gallium nitride (GaN).

Example 3 includes the subject matter of any of Examples 1-2, further including a polarization charge inducing layer between the channel layer and the gate, wherein the polarization charge inducing layer includes a group III-N material having a larger energy gap or bandgap than the group III-N material of the channel layer.

Example 4 includes the subject matter of any of Examples 1-3, further including a gate dielectric layer between the gate and the channel layer.

Example 5 includes the subject matter of any of Examples 1-4, wherein the gate has a length dimension between the source and drain regions that is less than 50 nm.

Example 6 includes the subject matter of any of Examples 1-5, wherein the switching layer can be set to multiple states. Example 7 includes the subject matter of any of Examples 1-6, wherein the switching layer includes one of tantalum oxide (TaO_x), zirconium oxide (ZiO_x), and hafnium oxide (HfO_x).

Example 8 includes the subject matter of any of Examples 1-7, wherein each of the first and second electrodes include at least one of disulfur dinitride (S₂N₂), titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), tungsten (W), titanium (Ti), and at least one noble metal.

Example 9 includes the subject matter of any of Examples 1-8, wherein each of the first and second electrodes have a thickness in the range of 5-100 nm.

Example 10 includes the subject matter of any of Examples 1-9, wherein the switching layer has a thickness between the first and second electrodes in the range of 2-10 nm.

Example 11 includes the subject matter of any of Examples 1-10, further including an oxygen exchange layer (OEL) between the switching layer and one of the first and second electrodes.

Example 12 includes the subject matter of Example 11, wherein the OEL includes at least one of hafnium (Hf), titanium (Ti), and tantalum (Ta).

Example 13 includes the subject matter of any of Examples 11-12, wherein the OEL has a thickness between the switching layer and the one of the first and second electrodes in the range of 2-10 nm.

Example 14 includes the subject matter of any of Examples 1-13, wherein the multilayer stack is above the transistor.

Example 15 is a computing system including the subject matter of any of Examples 1-14.

Example 16 is a resistive random-access memory (RRAM) cell including a one transistor, one resistor (1T-1R) configuration, the RRAM cell including an access transistor and a memristor stack. The access transistor includes: a channel layer including gallium nitride (GaN); a polarization charge inducing layer on the channel layer, wherein the polarization charge inducing layer includes a group Ill-nitride (III-N) material having a bandgap of greater than 3.4 eV; a gate above the channel layer; a gate dielectric layer between the polarization charge inducing layer and the gate; and source and drain regions adjacent to the channel layer. The memristor stack includes: a first electrode in electrical contact with the drain region of the access transistor; a second electrode; and a switching layer between the first and second electrodes.

Example 17 includes the subject matter of Example 16, wherein the access transistor can drive at least 200 microamps of current at 3 volts. Example 18 includes the subject matter of any of Examples 16-17, wherein the polarization charge inducing layer includes aluminum.

Example 19 includes the subject matter of any of Examples 16-18, wherein the gate has a length dimension between the source and drain regions that is less than 20 nm.

Example 20 includes the subject matter of any of Examples 16-19, wherein the switching layer includes one of a metal oxide and a metal alloy oxide.

Example 21 includes the subject matter of any of Examples 16-20, wherein the switching layer can be set to multiple states.

Example 22 includes the subject matter of any of Examples 16-21, wherein the switching layer includes one of tantalum oxide (TaO_x), zirconium oxide (ZiO_x), and hafnium oxide (HfO_x).

Example 23 includes the subject matter of any of Examples 16-22, wherein each of the first and second electrodes include at least one of disulfur dinitnde (S₂N₂), titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), tungsten (W), titanium (Ti), and at least one noble metal.

Example 24 includes the subject matter of any of Examples 16-23, wherein each the first and second electrodes have a thickness in the range of 5-100 nm.

Example 25 includes the subject matter of any of Examples 16-24, wherein the switching layer has a thickness between the first and second electrodes in the range of 2-10 nm.

Example 26 includes the subject matter of any of Examples 16-25, further including an oxygen exchange layer (OEL) between the switching layer and the second electrode.

Example 27 includes the subject matter of Example 26, wherein the OEL includes at least one of hafnium (Hf), titanium (Ti), and tantalum (Ta).

Example 28 includes the subject matter of any of Examples 26-27, wherein the OEL has a thickness between the switching layer and the second electrode in the range of 2-10 nm.

Example 29 includes the subject matter of any of Examples 16-28, wherein the memristor stack is above the transistor.

Example 30 is a computing system including the RRAM cell of any of Examples 16-29.

Example 31 is a method of forming a resistive random-access memory (RRAM) cell (or generally, an integrated circuit), the method including: forming a transistor including: a channel layer including group Ill-nitride (III-N) material; a gate above the channel layer; and source and drain regions adjacent to the channel layer; forming a first electrode in electrical contact with one of the source and drain regions of the transistor; forming a switching layer above the first electrode, wherein the switching layer includes one of a metal oxide and a metal ally oxide; and forming a second electrode above the switching layer.

Example 32 includes the subject matter of Example 31, wherein the channel layer is formed using lateral epitaxial overgrowth (LEO) processing.

Example 33 includes the subject matter of Example 31, wherein the channel layer is formed using an underlying buffer layer that includes group III-N material.

Example 34 includes the subject matter of any of Examples 31-33, wherein the channel layer includes gallium nitride (GaN).

Example 35 includes the subject matter of any of Examples 31-34, further including forming a polarization charge inducing layer above the channel layer, wherein the polarization charge inducing layer includes a group III-N material having a larger energy gap or bandgap than the group III-N material of the channel layer.

Example 36 includes the subject matter of any of Examples 31-35, further including forming a gate dielectric layer above the channel layer.

Example 37 includes the subject matter of any of Examples 31-36, wherein the gate has a length dimension between the source and drain regions that is less than 50 nm.

Example 38 includes the subject matter of any of Examples 31-37, wherein the switching layer can be set to multiple states.

Example 39 includes the subject matter of any of Examples 31-38, wherein the switching layer includes one of tantalum oxide (TaO_x), zirconium oxide (ZiO_x), and hafnium oxide (HfO_x).

Example 40 includes the subject matter of any of Examples 31-39, wherein each of the first and second electrodes include at least one of disulfur dinitride (S₂N₂), titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), tungsten (W), titanium (Ti), and at least one noble metal.

Example 41 includes the subject matter of any of Examples 31-40, wherein each of the first and second electrodes have a thickness in the range of 5-100 nm.

Example 42 includes the subject matter of any of Examples 31-41, wherein the switching layer has a thickness between the first and second electrodes in the range of 2-10 nm.

Example 43 includes the subject matter of any of Examples 31-42, further including forming an oxygen exchange layer (OEL) above the first electrode layer.

Example 44 includes the subject matter of Example 43, wherein the OEL includes at least one of hafnium (Hf), titanium (Ti), and tantalum (Ta). Example 45 includes the subject matter of any of Examples 43-44, wherein the OEL has a thickness between the switching layer and the one of the first and second electrodes in the range of 2-10 nm.

The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.

Claims

CLAIMS What is claimed is:

1. A resistive random-access memory (RRAM) cell comprising:

a transistor including:

a channel layer including group Ill-nitride (III-N) material;

a gate above the channel layer; and

source and drain regions adjacent to the channel layer; and

a multilayer stack including:

a first electrode in electrical contact with one of the source and drain regions of the transistor;

a second electrode; and

a switching layer between the first and second electrodes, wherein the switching layer includes one of a metal oxide and a metal alloy oxide.

2. The RRAM cell of claim 1, wherein the channel layer includes gallium nitride

(GaN).

3. The RRAM cell of claim 1, further comprising a polarization charge inducing layer between the channel layer and the gate, wherein the polarization charge inducing layer includes a group III-N material having a larger energy gap or bandgap than the group III-N material of the channel layer.

4. The RRAM cell of claim 1, further comprising a gate dielectric layer between the gate and the channel layer.

5. The RRAM cell of claim 1, wherein the gate has a length dimension between the source and drain regions that is less than 50 nm.

6. The RRAM cell of claim 1, wherein the switching layer can be set to multiple states.

7. The RRAM cell of claim 1, wherein the switching layer includes one of tantalum oxide (TaO_x), zirconium oxide (ZiO_x), and hafnium oxide (HfO_x).

8. The RRAM cell of claim 1, wherein each of the first and second electrodes include at least one of disulfur dinitride (S₂N₂), titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), tungsten (W), titanium (Ti), and at least one noble metal.

9. The RRAM cell of claim 1, wherein each of the first and second electrodes have a thickness in the range of 5-100 nm.

10. The RRAM cell of claim 1, wherein the switching layer has a thickness between the first and second electrodes in the range of 2-10 nm.

11. The RRAM cell of claim 1, further comprising an oxygen exchange layer (OEL) between the switching layer and one of the first and second electrodes.

12. The RRAM cell of claim 11, wherein the OEL includes at least one of hafnium (Hf), titanium (Ti), and tantalum (Ta).

13. The RRAM cell of claim 11, wherein the OEL has a thickness between the switching layer and the one of the first and second electrodes in the range of 2-10 nm.

14. The RRAM cell of claim 1, wherein the multilayer stack is above the transistor.

15. A computing system comprising the RRAM cell of any of claims 1-14.

16. A resistive random-access memory (RRAM) cell including a one transistor, one resistor (1T-1R) configuration, the RRAM cell comprising:

an access transistor including:

a channel layer including gallium nitride (GaN);

a polarization charge inducing layer on the channel layer, wherein the polarization charge inducing layer includes a group Ill-nitride (III-N) material having a bandgap of greater than 3.4 eV;

a gate above the channel layer;

a gate dielectric layer between the polarization charge inducing layer and the gate; and

source and drain regions adjacent to the channel layer; and

a memristor stack including:

a first electrode in electrical contact with the drain region of the access transistor; a second electrode; and

a switching layer between the first and second electrodes.

17. The RRAM cell of claim 16, wherein the access transistor can drive at least 200 microamps of current at 3 volts.

18. The RRAM cell of claim 16, wherein the polarization charge inducing layer includes aluminum.

19. The RRAM cell of claim 16, wherein the gate has a length dimension between the source and drain regions that is less than 20 nm.

20. The RRAM cell of claim 16, wherein the switching layer can be set to multiple states.

21. The RRAM cell of any of claims 16-20, wherein the switching layer includes one of tantalum oxide (TaO_x), zirconium oxide (ZiO_x), and hafnium oxide (HfO_x).

22. A method of forming a resistive random-access memory (RRAM) cell, the method comprising:

forming a transistor including:

a channel layer including group Ill-nitride (III-N) material;

a gate above the channel layer; and

source and drain regions adjacent to the channel layer;

forming a first electrode in electrical contact with one of the source and drain regions of the transistor;

forming a switching layer above the first electrode, wherein the switching layer includes one of a metal oxide and a metal ally oxide; and

forming a second electrode above the switching layer.

23. The method of claim 22, wherein the channel layer is formed using lateral epitaxial overgrowth (LEO) processing.

24. The method of claim 22, wherein the channel layer is formed using an underlying buffer layer that includes group III-N material.

25. The method of any of claims 22-24, further comprising forming an oxygen exchange layer (OEL) above the first electrode layer.